JP2019159151A - Method for forming wiring pattern, and printed circuit board, semiconductor package and electronic apparatus using the method - Google Patents

Abstract

To form a good wiring pattern by achieving sufficient adhesion of a resist.SOLUTION: A method for forming a wiring pattern in accordance with an embodiment of the present invention includes steps of: forming a conductor layer on an insulation base material; forming a molecular joint layer on a surface of the conductor layer so as to chemically bond the molecular joint layer to the surface of the conductor layer; forming a photosensitive resin layer on the molecular joint layer so as to chemically bond the photosensitive resin layer to the molecular joint layer; exposing the photosensitive resin layer and then developing for patterning; and etching the conductor layer via the photosensitive resin layer.SELECTED DRAWING: Figure 1G

Description

  FIELD Embodiments described herein relate generally to a wiring pattern forming method, a printed circuit board using the wiring pattern forming method, a semiconductor package, and an electronic apparatus.

  In printed wiring boards such as WLCSP (wafer level chip size package), FOWLP (fan out wafer level package), glass interposer, semiconductor package such as Si interposer, MEMS (micro electro mechanical system), liquid crystal, etc. Wiring is formed using film or liquid resist.

  In the subtractive method, which is one of the wiring pattern forming methods, a conductor is formed on an insulating material, and then a pretreatment is performed on the conductor and then a resist is formed. Such pretreatment is performed to clean the conductor and remove the oxide film, and to roughen the surface of the conductor to ensure adhesion of the resist. Examples of the roughening treatment include a mechanical method such as buffing, and a chemical method such as sulfuric acid-hydrogen peroxide, persulfate, or copper chloride microetching.

  In addition, in a method that is relatively easy to form a fine pattern, such as the semi-additive method, a seed layer of plating or ultra-thin copper foil is formed on an insulating material, and a resist is formed after pre-processing on the seed layer. To do. The pretreatment is performed in order to ensure adhesion of the resist by washing and removing the oxide film, and finely roughing the plating or seed layer. Since the seed layer is as thin as 0.5 μm to 3 μm, a mechanical method such as buffing is not used as a roughening method, and a sulfuric acid-hydrogen peroxide system, a persulfate system, and a copper chloride system are used. Alternatively, chemical methods such as organic acid microetching are used.

  Although such roughening treatment is effective for improving the adhesion to the resist, the wiring pattern is liable to be damaged when forming a fine pattern, and the unevenness on the surface of the wiring pattern causes an increase in transmission loss in high-speed transmission. In addition, the semi-additive method has a problem that it is difficult to perform a roughening process with a large roughness because the seed layer is thin.

  On the other hand, if the roughness of the roughening treatment is reduced, or if the fine pattern is formed, the contact area is reduced, so that the contact force may be insufficient. If the adhesion is low, the resist is peeled off, and a wiring failure such as disconnection occurs in the subtractive method and short circuit occurs in the semi-additive method.

  In addition, in the semi-additive method, if the pattern thickness is designed to be thicker than the pattern width, the aspect ratio of the resist opening becomes high, the resist tends to collapse, and a strong adhesion may be required. .

JP-A-11-177210

  An object of an embodiment of the present invention is to form a good wiring pattern by sufficiently adhering a resist.

The method for forming a wiring pattern according to the embodiment forms a conductor layer on an insulating substrate,
Forming a molecular bonding layer on the surface of the conductor layer, chemically bonding the molecular bonding layer to the surface of the conductor layer,
Forming a photosensitive resin layer on the molecular bonding layer, chemically bonding the photosensitive resin layer to the molecular bonding layer,
After exposing the photosensitive resin layer, developing and patterning,
Etching the conductor layer through the photosensitive resin layer.

It is a figure showing the manufacturing process of the wiring pattern concerning 1st Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 1st Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 1st Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 1st Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 1st Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 1st Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 1st Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 2nd Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 2nd Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 2nd Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 2nd Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 2nd Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 2nd Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 2nd Embodiment. It is a figure showing the manufacturing process of the wiring pattern concerning 2nd Embodiment. It is a perspective view showing the electronic device which concerns on 3rd Embodiment. It is a perspective view which shows SSD of FIG. It is sectional drawing which shows roughly an example of the semiconductor package concerning 4th Embodiment.

The method for forming a wiring pattern according to the first embodiment is as follows:
Forming a conductor layer on an insulating substrate;
Forming a molecular bonding layer on the surface of the conductor layer, chemically bonding the molecular bonding layer to the surface of the conductor layer,
Forming a photosensitive resin layer on the molecular bonding layer, chemically bonding the photosensitive resin layer to the molecular bonding layer,
After exposing the photosensitive resin layer, developing and patterning,
Etching the conductor layer through a photosensitive resin layer.

In addition, the method of forming a wiring pattern according to the second embodiment is as follows:
Forming a seed layer on an insulating substrate;
Forming a molecular bonding layer on the seed layer surface, chemically bonding the molecular bonding layer to the seed layer surface;
Forming a photosensitive resin layer on the molecular bonding layer, chemically bonding the photosensitive resin layer to the molecular bonding layer,
After exposing the photosensitive resin layer, developing and patterning,
Forming a conductor layer on the seed layer via the photosensitive resin layer.

  In the first and second embodiments, as a pretreatment of the step of patterning the photosensitive resin layer, a molecular bonding layer is formed and chemically bonded on the conductor layer or the seed layer, and a photosensitive resin layer is further formed. By chemically bonding with the molecular bonding layer, the photosensitive resin layer can be sufficiently adhered onto the conductor layer or the seed layer without roughening treatment, so that the resist peeling is reduced and the pattern is fine. Even if it is made, it is possible to form a wiring pattern with a good yield.

  As the conductor layer, copper, aluminum, cobalt, tungsten, or the like is used.

  As the seed layer, copper, aluminum, tantalum, titanium, cobalt, tungsten, or the like is used.

  The molecular bonding agent is a compound that can chemically bond to a metal or a resin.

  For the molecular bonding layer, for example, one solvent of water, methanol, ethanol or isopropyl alcohol is added to the molecular bonding agent to prepare a molecular bonding layer coating solution having a concentration of 0.05 to 5% by mass, for example. Then, it can be formed by applying to an object.

  Examples of the application method include methods such as dipping and spray coating.

  The molecular bonding layer has a portion chemically bonded to the conductor or seed layer and a portion chemically bonded to the photosensitive resin layer.

  After the molecular bonding layer is formed, the chemical bonding is promoted by leaving it still or applying energy such as heat and light.

  A triazine derivative can be used as the molecular bonding agent.

  The triazine derivative used in the embodiment can be represented by, for example, the following formula (1).

(In the formula, R represents a hydrocarbon group or a hydrocarbon group in which a hetero atom or a functional group may intervene, X represents a hydrogen atom or a hydrocarbon group, Y represents an alkoxy group, and Z represents , A thiol group, an amino group or an azide group which may form a salt, or a hydrocarbon group which may be intervened by a hetero atom or a functional group, n1 is an integer from 1 to 3, and n2 is (It is an integer from 1 to 2.)
In the above general formula (C1), R preferably represents a hydrocarbon group having 1 to 7 carbon atoms, or a group in which a nitrogen atom is interposed in the main chain. X shows a C1-C3 hydrocarbon group. Y shows a C1-C3 alkoxy group. n1 is preferably 3. n2 is preferably 2. Z represents a thiol group, an amino group, an azide group, an alkyl group, or a salt thereof. As an element of the cation forming the salt, an alkali metal is preferable, and Li, Na, K, or Cs is more preferable among them. In addition, when n2 is 2, it is preferable that at least 1 Z shows the thiol group, amino group, or azide group which forms the salt.

  The triazine derivative can be used alone or as a mixture with other compounds.

  For the formation of the photosensitive resin layer, a dry film or a liquid film can be used. As the photosensitive resin, a resin in which an alkali-soluble polymer and a monomer are blended and a photopolymerization initiator is added can be used.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1A to FIG. 1G are diagrams showing manufacturing steps of the wiring pattern according to the first embodiment.

  According to the first embodiment, when such a subtractive method is used, the wiring pattern is not roughened, so that transmission loss at high frequencies can be reduced. Further, when the photosensitive resin layer is removed using an alkali stripping solution, the triazine derivative can be left on the conductor layer, and the adhesion of the insulating resin prepreg or the solder resist can be improved.

  2A to 2H are views showing a manufacturing process of a wiring pattern according to the second embodiment.

  According to the second embodiment, when such a semi-additive method is used, since it is not necessary to roughen the seed layer, a thinner seed layer can be applied, and the photosensitive resin layer can be applied. Thus, it is possible to achieve a good pattern formation yield.

  The wiring pattern manufactured by the method according to the first and second embodiments is, for example, a printed circuit board, WLCSP (wafer level chip size package), FOWLP (fan out wafer level package), glass interposer, Si interposer, etc. It can be applied to electronic packages such as semiconductor packages, MEMS (micro electro mechanical system), and liquid crystal.

  The printed circuit board according to the third embodiment includes the wiring pattern according to the first or second embodiment.

  The semiconductor package according to the fourth embodiment includes the wiring pattern according to the first or second embodiment.

  The electronic device according to the fifth embodiment includes the wiring pattern according to the first or second embodiment.

  FIELD Embodiments described herein relate generally to a wiring pattern forming method, a printed circuit board using the wiring pattern forming method, a semiconductor package, and an electronic apparatus.

  The wiring pattern manufacturing method according to the first embodiment is a so-called subtractive method.

  First, as shown in FIG. 1A, the conductor 2 is formed on one main surface of the insulating material 1.

  Subsequently, pretreatment is performed on the surface of the conductor 2.

  As a pretreatment, a molecular bonding agent containing a triazine derivative represented by the formula (1) is applied on the conductor 2 to form a molecular bonding layer 3 of a monomolecular layer or a multimolecular layer as shown in FIG. 1B. And chemically bonded to the conductor 2.

  A triazine derivative represented by the formula (1) is dissolved in, for example, one of water, methanol, ethanol, or isopropyl alcohol to prepare a molecular bonding agent coating solution having a concentration of 0.05 to 5% by mass, A molecular bonding layer is formed by coating on the conductor 2 by a method such as dipping or spray coating. Furthermore, the triazine derivative and the conductor 2 surface are chemically bonded by heating at a temperature of 80 to 200 ° C. for 5 to 30 minutes.

  If necessary, the portion of the molecular bonding layer that is not chemically bonded is cleaned and dried using, for example, the above-mentioned solvent as a cleaning solution. The thickness of the molecular bonding layer can be adjusted by conditions such as the concentration of the molecular bonding agent coating solution, the coating amount, the cleaning time, and the number of times.

  Next, a photosensitive resin dry film is prepared, and the conductor 2 on which the molecular bonding layer 3 is formed and the dry film are bonded together via the molecular bonding layer 3 while peeling off the protective film provided on the dry film. The photosensitive resin layer 4 is formed by passing between hot rolls as shown in FIG. 1C. For example, the hot roll temperature can be set to 50 to 120 ° C., the roll pressure to 0.1 to 1 MPa / cm, and the laminating speed to 0.1 to 6 m / min.

  Next, a photomask is aligned on the photosensitive resin layer 4.

  Thereafter, as a light source, a high pressure mercury lamp, an ultra high pressure mercury lamp, an ultraviolet fluorescent lamp, a carbon arc lamp, or a xenon lamp is used, and exposure is performed to cure the photosensitive resin layer as shown in FIG. 1D. In order to obtain a finer pattern, a parallel light source can be used.

  In image exposure, a direct drawing type exposure method can be used without using a photomask. In the direct drawing type exposure method, exposure is performed directly on the photosensitive resin layer 4 by a drawing apparatus. As the light source, a semiconductor laser having a wavelength of 350 to 410 nm, an ultrahigh pressure mercury lamp, or the like is used.

  Subsequently, as shown in FIG. 1E, a pattern comprising a photosensitive resin layer developed with an alkaline developer, unexposed portions of the photosensitive resin layer dissolved or dispersed with the developer, and cured on the conductor 2 4a is formed. Examples of the aqueous alkali solution used for the alkali development include aqueous solutions of sodium carbonate, potassium carbonate, sodium hydroxide, potassium hydroxide, and the like. For example, a 0.2 to 2 mass% sodium carbonate aqueous solution can be used.

  Thereafter, as shown in FIG. 1F, the conductor 2 not covered with the photosensitive resin layer pattern 4a is etched from above the formed photosensitive resin layer pattern 4a using an etching solution such as iron chloride or cupric chloride. Then, the wiring pattern 2a and the molecular bonding layer pattern 3a are obtained.

  In FIG. 1G, the molecular bonding layer pattern 3a is removed together with the photosensitive resin layer pattern 4a. However, the molecular bonding layer 3 may remain on the wiring pattern 2a without being patterned. The molecular bonding layer 3 remaining on the wiring pattern 2a can have a function of improving the adhesion between the insulating resin prepreg and the solder resist.

  By removing the photosensitive resin layer 4a from the substrate using an alkali stripping solution, a wiring substrate 100 having a wiring pattern 2a as shown in FIG. 1G is obtained.

  The alkaline stripping solution used in the stripping step is more alkaline than the alkaline aqueous solution used in the development, and examples thereof include sodium hydroxide, potassium hydroxide, and organic amine compounds. Here, an aqueous solution of 1 to 5% by mass of sodium hydroxide or potassium hydroxide is used. The alkali stripping solution can be applied by spraying or dipping.

  The wiring pattern manufacturing method according to the second embodiment is a so-called semi-additive method.

  As shown in FIGS. 2A to 2E, the first layer is formed except that a seed layer 5 is formed instead of the conductor layer 2 and a photomask 6 having an inverted pattern of the photomask 5 is aligned instead of the photomask 5. In the same manner as in the embodiment, the photosensitive resin layer 4 is formed on the seed layer 5, and the photosensitive resin layer pattern 4a is formed by exposure and development. 2E shows that the molecular bonding layer pattern 3a is formed together with the photosensitive resin layer pattern 4a on the seed layer 5, but the molecular bonding layer 3 is not patterned at the time of development, and the photosensitive resin pattern 4a is not patterned. Since it may remain in the opening 7 and the molecular bonding layer is very thin, there is no resistance between the seed layer and the electroplating even if the electroplating in the subsequent process is performed, and a good electrical connection is possible It becomes.

Thereafter, as shown in FIG. 2F, a current is passed from the seed layer, and electrolytic plating is performed on the opening 7 that is not covered with the photosensitive resin layer pattern 4a to obtain a wiring pattern 8. The electrolytic plating is generally Cu, and a copper sulfate or copper pyrophosphate bath is used to form a wiring thickness necessary for a product. Current density, can be carried out in 3A / dm ² about 0.5.

  As shown in FIG. 2G, the photosensitive resin layer pattern 4a is removed from the substrate using an alkaline stripping solution. As the alkali stripping solution, an alkali stripping solution similar to the alkali stripping solution used in the manufacturing process of the wiring pattern according to the first embodiment can be used.

  Subsequently, as shown in FIG. 2H, by etching the seed layer with a sulfuric acid-hydrogen peroxide system or the like, the wiring substrate 200 having the wiring pattern 8 similar to the wiring pattern 2 of FIG. 1D can be formed. .

  As another example of the pattern forming method according to the second embodiment, a triazine derivative having a photoreactive functional group can be used as a molecular bonding agent.

  When the molecular bonding layer 3 is formed using such a molecular bonding agent, for example, when the photosensitive resin layer 4 is exposed as shown in FIG. 2D, the wavelength region of the irradiated light is cured and the photosensitive resin layer 4 is cured. The molecular bonding layer can be photoreacted and chemically bonded to the photosensitive resin layer 4.

  In addition, it is also possible to use the molecular bonding agent containing the triazine derivative which has a photoreactive functional group for the pattern formation method concerning 1st Embodiment.

  FIG. 3 is a perspective view illustrating an electronic apparatus according to the fifth embodiment.

  A portable computer 10 as illustrated may be an example of an electronic apparatus according to the fifth embodiment.

  The portable computer 10 includes a first housing 11, a second housing 12, and a display module 13. The first and second housings 11 and 12 may be referred to as a case, an outer shell, and a wall, for example.

  The first housing 11 has an upper surface 11a. A keyboard 15 and a touch pad 16 are provided on the upper surface 11a. The first housing 11 is, for example, a board such as a mother board on which a central processing unit (CPU) is mounted, a storage device such as a hard disk drive (HDD) or a solid state drive (SSD), and a battery. Various kinds of parts are accommodated. As shown by a broken line in FIG. 1, the SSD 18 is accommodated in the first housing 11. The SSD 18 may be an example of an electronic device, and may be referred to as, for example, a semiconductor device, a storage device, a board module, a module, and a component.

  The second housing 12 is rotatably attached to the first housing 11 by, for example, a hinge. For example, the second housing 12 can be rotated between a closed position that covers the upper surface 11 a of the first housing 11 and an open position that rises from the end of the first housing 11.

  The display module 13 is accommodated in the second housing 12. The display module 13 is exposed through a display opening 12 a provided in the second housing 12. The display module 13 displays an image on the screen exposed by the display opening 12a.

  FIG. 4 is a perspective view showing the SSD 18 of FIG.

  As shown in FIG. 4, the SSD 18 includes a circuit board 21, a plurality of storage modules 22, and a connector 23. The SSD 18 exposes various components such as the circuit board 21 and the storage module 22, but may have a housing that accommodates these components.

  In FIG. 4, an X axis, a Y axis, and a Z axis are defined. The X axis, the Y axis, and the Z axis are orthogonal to each other. The X axis runs along the length of the SSD 18. The Y axis is along the width of the SSD 18. The Z axis is along the thickness of the SSD 18.

  The circuit board 21 is an example of a printed circuit board according to the third embodiment, includes at least a wiring pattern according to the first or second embodiment, and may also be referred to as a mounting board and a board, for example. The circuit board 21 is, for example, a printed wiring board formed in a substantially rectangular shape (square shape). The circuit board 21 may be another board such as a flexible printed wiring board or may be formed in another shape. The circuit board 21 has a substantially flat mounting surface 21a.

  The connector 23 protrudes from one end face 21 b of the circuit board 21. The connector 23 is formed integrally with the circuit board 21, for example. The connector 23 is attached to, for example, a connector provided inside the first housing 11. As a result, signals can be transmitted between the SSD 18 and the portable computer 10 (host device) via the connector 23.

  The storage module 22 is, for example, a package called FOWLP (Fan Out Wafer Level Package), and is an example of a semiconductor package according to the fourth embodiment.

  FIG. 5 is a cross-sectional view schematically showing an example of a semiconductor package according to the fourth embodiment.

  The storage module 22 is mounted side by side on the mounting surface 21 a of the circuit board 21. The storage module 22 may be mounted on the other surface of the circuit board 21 or may be mounted in a distributed manner.

  In FIG. 5, the X axis and the Z axis are defined as in FIG. The X axis and the Z axis are orthogonal to each other. The X axis runs along the length of the SSD 18. The Z axis is along the thickness of the SSD 18.

  As illustrated in FIG. 5, the storage module 22 includes a substrate 31, a plurality of storage components 32, a controller 33, a sealing unit 34, and a plurality of bumps 35.

  The substrate 31 includes at least the wiring pattern according to the first or second embodiment, and is, for example, a printed wiring substrate, but may be another substrate. The substrate 31 has a mounting surface 31a and a connection surface 31b. Various components such as the storage component 32 and the controller 33 are mounted on the mounting surface 31a. The connection surface 31b is located on the opposite side of the mounting surface 31a.

  The memory component 32 is an example of a substrate, and may be referred to as, for example, a package including a through silicon via (Through-Silicon Via) and a component. The storage component 32 includes, for example, a memory element and can store information. The plurality of storage components 32 are mounted on the mounting surface 31a of the substrate 31 in a state where they are overlapped with each other and electrically connected. Another member may be interposed between the storage components 32 stacked on each other.

  The controller 33 controls the storage component 32. The function of the controller 33 can be realized by, for example, a processor or hardware that executes firmware stored in the storage component 32 or a read only memory (ROM) provided in the controller 33. For example, the controller 33 can read data from the storage component 32 and write data to the storage component 32 in accordance with a command from the host device.

  The sealing unit 34 covers the mounting surface 31 a of the substrate 31 on which components such as the memory component 32 and the controller 33 are mounted. Thereby, the memory component 32 and the controller 33 are covered with the sealing portion 34. For example, the sealing portion 34 is made of an insulating synthetic resin, but may be made of other materials.

  The bumps 35 are provided on the connection surface 31 b of the substrate 31. The bump 35 is, for example, a solder ball, and an electrical connection is established between the electrode of the storage module 22 formed on the connection surface 31 b of the substrate 31 and the electrode of the circuit substrate 21 formed on the mounting surface 21 a of the circuit substrate 21. Connect.

  Wiring formation of these printed wiring boards, substrates, FOWLPs, and TSVs can be performed, for example, by the subtractive method of FIGS. 1A to 1G or the semi-additive method of FIGS. 2A to 2H.

  Note that the storage module 22 may be another component such as a ball grid array (BGA) or a chip size package (CSP).

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Insulating material, 2 ... Conductor, 2a ... Wiring pattern, 3 ... Molecular bonding layer, 4 ... Photosensitive resin layer, 4a ... Photosensitive resin layer pattern, 5 ... Seed layer, 8 ... Wiring pattern, 18 ... SSD, 21 ... Circuit board, 22 ... Memory module, 100, 200 ... Wiring board

Claims (8)

Forming a conductor layer on an insulating substrate;
Forming a molecular bonding layer on the surface of the conductor layer, chemically bonding the molecular bonding layer to the surface of the conductor layer,
Forming a photosensitive resin layer on the molecular bonding layer, chemically bonding the photosensitive resin layer to the molecular bonding layer,
After exposing the photosensitive resin layer, developing and patterning,
A method for forming a wiring pattern, comprising etching the conductor layer through the photosensitive resin layer. Forming a seed layer on an insulating substrate;
Forming a molecular bonding layer on the seed layer surface, chemically bonding the molecular bonding layer to the seed layer surface;
Forming a photosensitive resin layer on the molecular bonding layer, chemically bonding the photosensitive resin layer to the molecular bonding layer,
After exposing the photosensitive resin layer, developing and patterning,
A wiring pattern forming method including forming a conductor layer on the seed layer via the photosensitive resin layer.   The method according to claim 1, wherein the molecular bonding layer includes a triazine derivative. The triazine derivative has a photoreactive functional group,
The method according to claim 3, wherein when the photosensitive resin layer is exposed, the photosensitive resin layer is cured and the molecular bonding layer is photoreacted to chemically bond with the photosensitive resin layer.   The method according to any one of claims 1 to 4, wherein the molecular bonding layer is a monomolecular layer or a multimolecular layer.   A printed circuit board comprising a wiring pattern manufactured by the method according to claim 1.   6. A semiconductor package comprising a wiring pattern manufactured by the method according to claim 1.   An electronic device comprising a wiring pattern manufactured by the method according to claim 1.

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