JP2019121850A - Circuit device, vibration device, electronic apparatus, and movable body - Google Patents

Abstract

To provide a circuit device which can efficiently layout a hybrid type A/D conversion circuit having a differential configuration in a viewpoint of a circuit area and signal transfer, and a vibration device, an electronic apparatus and a movable body.SOLUTION: A circuit device 100 includes: an A/D conversion circuit 20 performing A/D conversion by successive approximation using a charge-redistribution type D/A conversion circuit 21 having capacitor array circuits CAP and CAN; and a quantization error holding circuit 30 holding an electric charge corresponding to a quantization error in the A/D conversion. The quantization error holding circuit 30 has quantization error holding circuits QEHP and QEHN of which one ends are connected to sampling nodes NSP and NSN of the capacitor array circuits CAP and CAN. The quantization error holding circuits QEHP and QEHN are disposed at a side of a direction D2 orthogonal to a direction D1 of the capacitor array circuits CAP and CAN disposed in the direction D1.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a circuit device, a vibration device, an electronic device, a moving body, and the like.

  Conventionally, the voltage of the input signal is compared with the D / A converted voltage of the successive comparison data, the successive comparison data is updated based on the comparison result, and the comparison and update are repeatedly performed by a method such as binary search. There is known a successive approximation A / D conversion circuit that A / D converts an input signal. The successive approximation type A / D conversion circuit has low power consumption, but it is difficult to achieve high accuracy (for example, expansion of the number of effective bits) as compared with, for example, a delta sigma type A / D conversion circuit.

  As a technique for improving the accuracy of the successive approximation type A / D conversion circuit, for example, there is a technique disclosed in Patent Document 1. In Patent Document 1, a delta sigma type configuration is incorporated in a successive approximation type A / D conversion circuit to form a hybrid A / D conversion circuit, and quantization noise in a low frequency band is reduced by a noise shaping effect. To improve accuracy.

Unexamined-Japanese-Patent No. 11-4166

  The prior art does not disclose or suggest the layout of a hybrid A / D conversion circuit. For example, the A / D conversion circuit disclosed in Patent Document 1 has a single-ended configuration, and its layout is neither disclosed nor suggested. As a method of increasing the accuracy (for example, increasing the S / N ratio) of the A / D conversion circuit, a method of using a differential configuration can be considered. There is no disclosure or suggestion about the configuration and layout.

  The present invention has been made to solve at least a part of the above-described problems, and can be realized as the following forms or embodiments.

  One aspect of the present invention is an A / D conversion circuit having a charge redistribution type D / A conversion circuit, performing A / D conversion of an input voltage by successive comparison using the D / A conversion circuit, and And a quantization error holding circuit holding a charge corresponding to the quantization error in the A / D conversion of the input voltage, wherein the D / A conversion circuit includes a capacitor array circuit on the positive side and a capacitor array on the negative side. A first input node is connected to a positive side sampling node that is a sampling node of the capacitor array circuit on the positive side, and the A / D conversion circuit performs sampling of the negative electrode side capacitor array circuit A comparison circuit in which the second input node is connected to the negative side sampling node which is a node, and the quantization error holding circuit has one end in contact with the positive side sampling node A positive side quantization error holding circuit, and a negative side quantization error holding circuit whose one end is connected to the negative side sampling node, the positive side capacitor array circuit and the negative side capacitor The array circuit is disposed along a first direction, and when the direction orthogonal to the first direction is a second direction, the quantization error holding circuit on the positive side is a capacitor array circuit on the positive side. The quantization error holding circuit disposed on the second direction side of the negative side and the quantization error holding circuit on the negative side relates to a circuit device disposed on the second direction side of the capacitor array circuit on the negative side.

  According to one aspect of the present invention, capacitor array circuits on the positive electrode side and the negative electrode side are disposed along the first direction, and the quantization error holding circuit for the positive electrode side and the negative electrode side is arranged on the second direction side of each. By arranging, the circuit on the positive side (capacitor array circuit on the positive side, quantization error holding circuit on the positive side) and the circuit on the negative side (capacitor array circuit on the negative side, quantization error on the negative side) that are differential configurations And the holding circuit) can be arranged symmetrically. Further, by arranging the quantization error holding circuit on the positive electrode side and the negative electrode side on the second direction side of the capacitor array circuit on the positive electrode side and the negative electrode side, one end of the quantization error holding circuit on the positive electrode side and the negative electrode side A short wiring length can be connected between the positive electrode side and the negative electrode side of the capacitor array circuit sampling node. As described above, in one aspect of the present invention, the hybrid A / D conversion circuit of the differential configuration can be efficiently arranged in layout in terms of circuit area and signal transmission.

  In one aspect of the present invention, the comparison circuit may be disposed between the capacitor array circuit on the positive electrode side and the capacitor array circuit on the negative electrode side.

  As described above, the sampling nodes of the capacitor array circuit on the positive side and the negative side are connected to the first and second input nodes of the comparison circuit. According to one aspect of the present invention, the sampling node can be wired with a short wiring length by arranging the comparison circuit between the capacitor array circuits on the positive electrode side and the negative electrode side. Further, according to one aspect of the present invention, since the sampling node is wired between the capacitor array circuit on the positive electrode side and the negative electrode side and the comparison circuit, the sampling node is provided on the second direction side of the capacitor array circuit on the positive electrode side and the negative electrode side. One end of the quantization error holding circuit on the positive side and the negative side can be connected to the sampling node with a short wiring length.

  In one aspect of the present invention, the A / D conversion circuit includes an addition circuit in which an input voltage on the positive electrode side and an input voltage on the negative electrode side are input as the input voltage, and the addition circuit is an input on the positive electrode side. A voltage obtained by adding the voltage and the voltage corresponding to the charge held in the quantization error holding circuit on the negative electrode side is output to the capacitor array circuit on the positive electrode side, and the input voltage on the negative electrode side and the quantum on the positive electrode side The voltage added to the voltage corresponding to the charge held in the integration error holding circuit may be output to the capacitor lay circuit on the negative electrode side.

  According to one aspect of the present invention, the output voltage of the adder circuit is a voltage corresponding to the charge held in the quantization error holding circuit on the positive electrode side from the difference between the input voltage on the positive electrode side and the input voltage on the negative electrode side. It is a voltage obtained by subtracting the difference from the voltage corresponding to the charge held in the quantization error holding circuit on the negative electrode side. A / D conversion of this output voltage can realize a hybrid A / D conversion circuit incorporating a delta sigma configuration. That is, the quantization error (charge) held in the quantization error holding circuit on the positive electrode side and the negative electrode side is fed back to the input voltage on the positive electrode side and the negative electrode side by the adding circuit.

  In one aspect of the present invention, in the addition circuit, the inverting input node is connected to the other end of the quantization error holding circuit on the positive electrode side, and the noninverting input node is the other end of the quantization error holding circuit on the negative electrode side. The operational amplifier may be disposed between the positive side quantization error holding circuit and the negative side quantization error holding circuit.

  According to one aspect of the present invention, the operational amplifier is disposed between the quantization error holding circuit on the positive electrode side and the negative electrode side, so that between the inverting input node and the other end of the quantization error holding circuit on the positive electrode side. And the other end of the non-inverting input node and the other end of the quantization error holding circuit on the negative electrode side can be wired with a short wiring length. Further, according to one aspect of the present invention, the operational amplifier is disposed on the second direction side of the comparison circuit, and the capacitor array circuit on the positive electrode side and the negative electrode side is disposed across the comparison circuit. The quantization error holding circuit on the positive electrode side and the negative electrode side is disposed on either side of the above. As a result, the hybrid A / D conversion circuits of differential configuration can be symmetrically arranged, and efficient layout can be performed in terms of circuit area and signal transmission.

  In one aspect of the present invention, the circuit device receives a first to n-th voltage (n is an integer of 2 or more) and outputs any one of the first to n-th voltages as the input voltage. And the positive side quantization error holding circuit includes first to nth positive side holding circuits for holding charges corresponding to the first to nth voltages, and the negative side quantization circuit The error holding circuit may have first to nth negative electrode side holding circuits for holding charges corresponding to the first to nth voltages.

  According to one aspect of the present invention, the charge corresponding to the quantization error of the A / D conversion for the voltage VIi can be held by the holding circuit on the ith positive electrode side and the holding circuit on the ith negative electrode side.

  In one aspect of the present invention, the first to n-th positive side holding circuits are disposed along the second direction, and the first to n-th negative side holding circuits are preferably It may be arranged along the direction of.

  When the number of input channels to the A / D conversion circuit is changed, the number (value of n) of the holding circuits on the positive electrode side and the negative electrode side changes accordingly. According to one aspect of the present invention, since the first to nth positive electrode side holding circuits and the first to nth negative electrode side holding circuits are disposed along the second direction, the number of the circuits is changed. The layout can be changed by shortening or extending the layout size in the second direction. As described above, according to one aspect of the present invention, even when the number of holding circuits on the positive electrode side and the negative electrode side is changed, efficient layout change using the existing circuit design is possible.

  In one embodiment of the present invention, the A / D conversion circuit is configured to perform the k-1th (k is an integer of 2 or more) A / D conversion of an i-th voltage (i is an integer of 1 or more and n or less). The k-th A / D conversion of the i-th voltage is performed using the charge held in the i-th positive electrode side holding circuit and the i-th negative electrode side holding circuit as the charge corresponding to the quantization error. It is also possible to output the A / D conversion result data in which the quantization error is noise-shaped.

  According to one aspect of the present invention, the A / D conversion of the ith voltage is performed by the successive approximation operation using the charge redistribution type D / A conversion circuit so that the D / A conversion is completed after the successive approximation operation is completed. It becomes possible for the A conversion circuit to output a voltage corresponding to the quantization error in the (k-1) th A / D conversion for the i-th voltage. Since the i-th positive electrode side holding circuit and the i-th negative electrode side holding circuit hold charges based on this voltage, quantization error in the (k−1) -th A / D conversion for the i-th voltage is caused. It can hold the corresponding charge. Then, by performing the k-th A / D conversion on the i-th voltage using this charge, noise shaping of the quantization error is possible. In one aspect of the present invention, by providing positive and negative holding circuits corresponding to each channel, it is possible to cope with multi-channel input. As described above, it is possible to achieve both the high precision of A / D conversion due to the noise shaping effect and the multichannel input.

  Further, according to one aspect of the present invention, in the selector, first to mth temperature detection voltages from the first to mth temperature sensors (m is an integer of 1 or more and n or less) are the 1st to You may input as the 1st-mth voltage of the voltage of n.

  As processing using temperature detection data (data for A / D conversion result of temperature detection voltage), various processing in the vibration device can be assumed. For example, temperature compensation processing of the oscillation frequency in a digital oscillator such as TCXO or OCXO can be considered. Alternatively, processing for correcting temperature dependent error in the physical quantity measuring device (for example, zero point correction in a gyro sensor) can be considered. At this time, there is a possibility that the temperature of the vibrator can be estimated with high accuracy by providing a plurality of temperature sensors at a plurality of positions of the oscillator and the physical quantity measuring device. In one aspect of the present invention, since a hybrid A / D conversion circuit corresponding to multi-channel input can be configured, high-accuracy A / D conversion (high-precision temperature for multi-channel input from a plurality of temperature sensors) Detection).

  In one aspect of the present invention, the circuit device corresponds to a digital signal processing circuit that outputs frequency control data based on the A / D conversion result data corresponding to the input voltage which is a temperature detection voltage, and corresponds to the frequency control data And an oscillation signal generation circuit that generates an oscillation signal of the oscillation frequency to be generated using a vibrator.

  Since the change in temperature is gradual, the signal band of the temperature detection voltage is a low frequency band. Therefore, even a relatively slow A / D conversion circuit such as a successive approximation type can perform A / D conversion at a conversion rate sufficiently higher than the signal band. In one aspect of the present invention, by configuring a hybrid A / D conversion circuit, A / D conversion with the noise shaping effect as described above can be realized, and measurement of high S / N in the signal band of the temperature sensor Is possible.

  Another aspect of the present invention relates to a vibration device including the circuit device described in any of the above and a vibrator connected to the circuit device.

  Yet another aspect of the present invention relates to an electronic device including the circuit device described in any of the above.

  Yet another aspect of the present invention relates to a mobile including the circuit device described in any of the above.

The 1st example of circuit composition of a circuit device. The 1st example of layout composition of a circuit device. The 2nd layout structural example of a circuit apparatus. The 2nd example of circuit composition of a circuit device. The timing chart explaining the basic operation | movement of the circuit apparatus of a 2nd circuit structural example. The example of the frequency characteristic of the A / D conversion result data in this embodiment. The 1st example of detailed composition of a circuit device. The 2nd detailed example of composition of a circuit device. The 2nd detailed example of composition of a circuit device. The structural example of a chopping modulation circuit in the case of performing chopping modulation in an addition circuit, and a chopping demodulation circuit. An example of a time change of A / D conversion result data (output code) when 0 V is input when chopping modulation is not performed. The example of the time change of A / D conversion result data (output code) when 0V is input in this embodiment. 1 shows a first configuration example of a vibration device including a circuit device. The 2nd example of composition of the oscillating device containing circuit equipment. Configuration example of an electronic device. Mobile example.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are essential as the solution means of the present invention. Not necessarily.

1. First Circuit Configuration Example FIG. 1 is a first circuit configuration example of the circuit device 100. As shown in FIG. The circuit device 100 includes an A / D conversion circuit 20 and a quantization error holding circuit 30. The circuit device 100 can also include the selector 10.

  Voltages VI1 to VIn (first to nth voltages (n is an integer of 2 or more)) are input to the selector 10, and the selector 10 selects one of the voltages VI1 to VIn to output voltage VSLP, VSLN. Output as Each of voltages VI1 to VIn is a differential voltage signal configured of a first voltage signal and a second voltage signal, and the first and second voltage signals of the voltage selected by selector 10 are output voltage VSLP. , Output as VSLN. Specifically, the selector 10 sequentially selects the voltages VI1 to VIn in time division, and outputs the voltages selected in that time division as the output voltages VSLP and VSLN. The voltages VI1 to VIn are voltages to be A / D converted, such as an output voltage signal of a sensor. When only one differential voltage signal is input to the A / D conversion circuit 20, the selector 10 can be omitted.

  The A / D conversion circuit 20 has a charge redistribution type D / A conversion circuit 21 and a comparison circuit 22. The output voltages VSLP and VSLN of the selector 10 are input to the A / D conversion circuit 20 as input voltages. The A / D conversion circuit 20 performs A / D conversion of the input voltage (VSLP, VSLN) by successive comparison using the D / A conversion circuit 21 and outputs A / D conversion result data DOUT corresponding to the input voltage. .

  The D / A conversion circuit 21 performs D / A conversion of the successive comparison data SAD by charge redistribution between capacitors based on the successive comparison data SAD. The D / A conversion circuit 21 includes a capacitor array circuit CAP (a capacitor array circuit on the positive electrode side) and a capacitor array circuit CAN (a capacitor array circuit on the negative electrode side). The positive side (non-inversion side, normal rotation side) is the side connected to the non-inversion input node of the comparison circuit 22, and the negative side (inversion side) is connected to the inversion input node of the comparison circuit 22. It is the side to be In the configuration example of FIG. 1, the capacitor array circuit CAP and the quantization error holding circuit QEHP are circuits on the positive side, and the capacitor array circuit CAN and the quantization error holding circuit QEHN are circuits on the negative side.

  The capacitor array circuit CAP D / A converts the successive comparison data SAD to output the difference between the D / A conversion voltage of the successive comparison data SAD and the voltage to be sequentially compared as a voltage DAQP.

  The capacitor array circuit CAN D / A converts the successive comparison data SAD to output the difference between the D / A conversion voltage of the successive comparison data SAD and the voltage to be subjected to the successive comparison as a voltage DAQN.

  The first input node (non-inversion input node) of the comparison circuit 22 is connected to the sampling node NSP (positive side sampling node) of the capacitor array circuit CAP. The second input node (inversion input node) of the comparison circuit 22 is connected to the sampling node NSN (negative side sampling node) of the capacitor array circuit CAN. The comparison circuit 22 is a difference voltage from the D / A conversion circuit 21 for comparing and determining the voltage to be sequentially compared (the output voltages VDFP and VDFN of the addition circuit 40) and the D / A conversion voltage of the successive comparison data SAD. Perform based on DAQP and DAQN. Since the differential voltages DAQP and DAQN are differential voltage signals, the comparison circuit 22 determines whether the differential voltage signals are positive or negative (positive or negative of DAQP-DAQN), and outputs the determination result as a signal CPQ.

  The quantization error holding circuit 30 holds the charge corresponding to the quantization error in A / D conversion of the input voltage (VSLP, VSLN) of the A / D conversion circuit 20. The quantization error is the difference between the voltage to be sequentially compared (VDFP, VDFN) and the D / A conversion voltage of A / D conversion result data DOUT, and when SAD = DOUT is input to the D / A conversion circuit 21. Output voltage of the D / A conversion circuit 21 of FIG. Specifically, the quantization error holding circuit 30 includes a quantization error holding circuit QEHP (one of which is connected to the sampling node NSP) and a quantum one end of which is connected to the sampling node NSN. And a quantization error holding circuit QEHN (a quantization error holding circuit on the negative electrode side).

  The quantization error holding circuit QEHP holds the charge corresponding to the quantization error by holding the output voltage (DAQP) of the D / A conversion circuit 21 with a capacitor. The quantization error holding circuit QEHP includes holding circuits HP1 to HPn (first to n-th holding circuits on the positive electrode side) that hold charges corresponding to quantization errors in A / D conversion of the voltages VI1 to VIn. A charge corresponding to a quantization error in A / D conversion when selector 10 selects voltage VIi (i-th voltage (i is an integer of 1 or more and n or less)) is stored in holding circuit HPi (i-th positive electrode side). Hold circuit) holds.

  The quantization error holding circuit QEHN holds the output voltage (DAQN) of the D / A conversion circuit 21 with a capacitor to hold the charge corresponding to the quantization error. The quantization error holding circuit QEHN includes holding circuits HN1 to HNn (first to nth holding circuits on the negative electrode side) that hold charges corresponding to quantization errors in A / D conversion of the voltages VI1 to VIn. The holding circuit HNi (the holding circuit on the i-th negative electrode side) holds the charge corresponding to the quantization error in A / D conversion when the selector 10 selects the voltage VIi.

  The A / D conversion circuit 20 uses the charge held in the holding circuits HPi and HNi as the charge corresponding to the quantization error in the k−1th (k is an integer) A / D conversion of the voltage VIi, Perform the kth A / D conversion for. Then, the A / D conversion circuit 20 outputs A / D conversion result data DOUT corresponding to the voltage VIi in which the quantization error is noise-shaped. That is, when the selector 10 selects the voltage VIi, the holding circuits HPi, HNi hold the charge corresponding to the quantization error, and when the selector 10 next selects the voltage VIi, the holding circuits HPi, HNi The A / D conversion of the input voltage (VSLP, VSLN) is performed using the held charge. The A / D conversion circuit 20 converts A / D conversion result data DOUT corresponding to the difference voltage between the input voltage (or a voltage multiplied by the gain) and the voltage corresponding to the charge held by the holding circuits HPi and HNi. Ask. This produces a first-order noise shaping effect on the quantization error.

  According to the above embodiment, it is possible to obtain A / D conversion result data DOUT corresponding to the voltage VIi, in which the quantization error in the A / D conversion is noise shaped. That is, a hybrid A / D converter circuit in which a delta sigma type configuration is incorporated in a successive approximation type A / D converter circuit can be realized with a differential configuration.

  In addition, multi-channel input is realized in the hybrid A / D conversion circuit by providing holding circuits HP1 to HPn and HN1 to HNn that hold charges corresponding to quantization errors in A / D conversion of voltages VI1 to VIn. it can. Specifically, the charge redistribution type D / A conversion circuit 21 performs a sequential comparison operation so that the voltage of the sequential comparison target and the D / A conversion voltage of the sequential comparison data SAD become equal, the sequential comparison After the operation is completed, a voltage corresponding to the quantization error can be output to the D / A conversion circuit 21. The voltage corresponding to the quantization error can hold the charge corresponding to the quantization error. By performing this holding for each of the voltages VI1 to VIn, charges corresponding to the quantization error can be held in the holding circuits HP1 to HPn and HN1 to HNn for each channel.

  Hereinafter, a more detailed configuration and operation of the A / D conversion circuit 20 will be described. The A / D conversion circuit 20 includes a control circuit 23 (logic circuit). The A / D conversion circuit 20 can also include an addition circuit 40.

  The adder circuit 40 subtracts the voltage (VDFP, VDFN) obtained by subtracting the voltage corresponding to the charge held in the holding circuits HPi and HNi from the voltage corresponding to the input voltage (VSLP, VSLN) to the D / A conversion circuit 21. Output. For example, the input voltage and a voltage obtained by inverting the voltage corresponding to the charge held in the holding circuits HPi and HNi (for example, multiplied by −1) are added. Specifically, the adding circuit 40 outputs, to the capacitor array circuit CAP, a voltage VDFP obtained by adding the input voltage VSLP and the voltage corresponding to the charge held in the holding circuit HNi (quantization error holding circuit QEHN), A voltage VDFN obtained by adding the input voltage VSLN and the voltage corresponding to the charge held in the holding circuit HPi (quantization error holding circuit QEHP) is output to the capacitor array circuit CAN. Thus, the voltage obtained by subtracting the difference between the voltage corresponding to the charge held in holding circuit HPi and the voltage corresponding to the charge held in holding circuit HNi from the difference between input voltage VSLP and input voltage VSLN is D It is output to the / A conversion circuit 21. The voltages corresponding to the charges held in the holding circuits HPi and HNi are the output voltages (DAQP, DAQN) of the D / A conversion circuit 21 after the successive comparison operation is completed in the previous A / D conversion of the voltage VIi. .

  The D / A conversion circuit 21 samples and holds the output voltages VDFP and VDFN of the addition circuit 40, and D / A converts the successive comparison data SAD by charge redistribution. As a result, differential voltages DAQP and DAQN obtained by subtracting the output voltages VDFP and VDFN of the adding circuit 40 from the D / A converted voltage of the successive approximation data SAD are output.

  The holding circuits HPi and HNi hold charges corresponding to the differential voltages DAQP and DAQN after completing the successive approximation operation for the voltage VIi. For example, the differential voltage DAQP and DAQN are held by the capacitor with reference to the common voltage (given voltage), and the charge charged in the capacitor is held by the potential difference between the common voltage and the differential voltage DAQP and DAQN.

  In the above configuration, the output voltage (DAQP, DAQN) of the D / A conversion circuit 21 becomes a residual voltage due to a quantization error by setting SAD = DOUT after the sequential comparison operation is completed. The holding circuits HPi and HNi can hold the charge corresponding to the quantization error only by holding the charge corresponding to the residual voltage. Then, noise feedback of the quantization error can be performed by feeding back the residual voltage due to the quantization error to the input side using this charge. In the configuration of this embodiment, since the residual voltage due to the quantization error is affected by the residual voltage in the past, an operation equivalent to integration in delta sigma operation is realized, and it is necessary to provide an integrator. There is no Therefore, it is only necessary to provide the quantization error holding circuits for the number of channels when dealing with multi-channel input. Since it is not necessary to provide integrators (amplifiers) for the number of channels, it is possible to reduce an increase in power consumption and an increase in circuit scale due to multi-channel input.

  The comparison circuit 22 determines the positive / negative of the differential voltage DAQP between the output voltage VDF of the addition circuit 40 and the D / A converted voltage of the successive comparison data SAD, DAQN (differential voltage signal), and outputs the determination result as a signal CPQ. Do.

  The control circuit 23 updates the successive approximation data SAD based on the comparison result (CPQ) by the comparison circuit 22 and outputs the updated successive comparison data SAD to the D / A conversion circuit 21. Specifically, control circuit 23 has a register for storing successive approximation data SAD. The control circuit 23 sets successive comparison data SAD for comparison in the register, and outputs the subsequent comparison data SAD for comparison to the D / A conversion circuit 21, and sequentially based on the comparison result by the comparison circuit 22 at that time. Determine the comparison data SAD. As one comparison operation, successive comparison data SAD of the register is successively updated by a method such as binary search, and when this successive comparison operation is completed, A / D conversion result data DOUT is determined. The control circuit 23 sets A / D conversion result data DOUT in a register, and outputs SAD = DOUT to the D / A conversion circuit 21.

  According to the above configuration, A / D conversion of the input voltage can be realized by successive approximation using the charge redistribution type D / A conversion circuit 21. The object of the successive approximation is the output voltages VDFP and VDFN of the adding circuit 40, and the output voltages VDFP and VDFN are voltages to which the quantization errors are fed back by the holding circuits HPi and HNi. Thus, a hybrid A / D conversion circuit incorporating a delta sigma configuration is realized in a differential configuration.

2. Layout Configuration Example FIG. 2 is a first layout configuration example of the circuit device 100. In FIG. 2, solid squares represent arrangement regions of each circuit.

  The placement area is an area where components of the circuit are placed. That is, circuit elements constituting the circuit and wiring for connecting the elements, guard bars (structures for protecting the circuit from noise etc. by connecting diffusion regions provided around the circuit to a power supply etc.) are arranged. It is an area. The circuit element is, for example, a transistor, a resistor, a capacitor or the like, and the polysilicon, the diffusion layer, and the metal layer constituting them are disposed in the region.

  The arrangement is a layout arrangement of circuits formed on a substrate (semiconductor chip) of the circuit device 100 (integrated circuit device) in plan view with respect to the substrate (semiconductor chip).

  As shown in FIG. 2, the capacitor array circuit CAP and the capacitor array circuit CAN are disposed along the direction D1 (first direction). A direction orthogonal to the direction D1 is taken as D2 (second direction). At this time, the quantization error holding circuit QEHP is disposed on the direction D2 side (second direction side) of the capacitor array circuit CAP. The quantization error holding circuit QEHN is disposed on the direction D2 side of the capacitor array circuit CAN.

  Specifically, one side along the direction D1 of the arrangement region of the capacitor array circuit CAP and one side along the direction D1 of the arrangement region of the quantization error holding circuit QEHP oppose each other. That is, the capacitor array circuit CAP and the quantization error holding circuit QEHP are arranged adjacent to each other in the direction D2. For example, no other circuit element (except for the wiring) is disposed between the capacitor array circuit CAP and the quantization error holding circuit QEHP. One side along the direction D1 of the arrangement region of the capacitor array circuit CAN faces one side along the direction D1 of the arrangement region of the quantization error holding circuit QEHN. That is, the capacitor array circuit CAN and the quantization error holding circuit QEHN are arranged adjacent to each other in the direction D2. For example, no other circuit element (except for the wiring) is disposed between the capacitor array circuit CAN and the quantization error holding circuit QEHN.

  The directions D1 and D2 are directions in plan view with respect to the substrate of the circuit device 100. For example, the direction D1 is a direction along the first side of the substrate of the circuit device 100, and the direction D2 is a direction along the second side of the substrate (a side orthogonal to the first side).

  According to the above embodiment, the hybrid A / D conversion circuit of differential configuration can be efficiently arranged in layout in terms of circuit area and signal transmission. Specifically, the capacitor array circuit CAP and CAN are arranged along the direction D1, and the quantization error holding circuits QEHP and QEHN are arranged on the direction D2 side of each to provide the positive side circuit (CAP of differential configuration). , QEHP) and the negative side circuit (CAN, QEHN) can be arranged symmetrically. That is, they can be arranged in line symmetry with respect to the symmetry axis along the direction D2. Further, as described in FIG. 1, one end of the quantization error holding circuit QEHP and QEHN is connected to the capacitor array circuit CAP and sampling nodes NSP and NSN of CAN. By arranging the quantization error holding circuits QEHP and QEHN on the direction D2 side of the capacitor array circuit CAP and CAN, one end of the quantization error holding circuits QEHP and QEHN and the capacitor array circuit CAP, sampling nodes NSP and NSN of CAN and Can be connected with a short wiring length. For example, the sampling nodes NSP and NSN are wired along the direction D2, one end of the quantization error holding circuit QEHP and the capacitor array circuit CAP are connected to the wiring of NSP, one end of the quantization error holding circuit QEHN is connected to the wiring of NSN Capacitor array circuit CAN can be connected.

  Further, by performing charge redistribution between the capacitor of the capacitor array circuit CAP, CAN and the capacitor of the quantization error holding circuit QEHP, QEHN, the quantization error holding circuit QEHP, QEHN holds the charge. At this time, as an example, the areas (total capacitance values) of the capacitor array circuits CAP and CAN and the areas (capacitance values) of the respective holding circuits of the quantization error holding circuits QEHP and QEHN can be made comparable. In this case, by arranging the quantization error holding circuits QEHP and QEHN on the side of the capacitor array circuit CAP and the direction D2 of CAN, efficient arrangement can be achieved in terms of circuit area.

  Further, in the present embodiment, the comparison circuit 22 is disposed between the capacitor array circuit CAP and the capacitor array circuit CAN.

  Specifically, one side along the direction D2 of the arrangement region of the capacitor array circuit CAP and one side along the direction D2 of the comparison circuit 22 oppose each other. One side along the direction D2 of the arrangement region of the capacitor array circuit CAN faces one side along the direction D2 of the comparison circuit 22 (one side different from the one side). That is, the comparison circuit 22 is disposed adjacent to the direction D2 of the capacitor array circuit CAP, and the capacitor array circuit CAN is disposed adjacent to the direction D2 of the comparison circuit 22. For example, no other circuit element (except the wiring) is disposed between the capacitor array circuit CAP, CAN and the comparison circuit 22.

  As described in FIG. 1, the sampling node NSP of the capacitor array circuit CAP is connected to the non-inversion input node of the comparison circuit 22, and the sampling node NSN of the capacitor array circuit CAN is connected to the inversion input node of the comparison circuit 22. Since the capacitor array circuits CAP and CAN perform D / A conversion by charge redistribution, it is desirable that noise propagation to the sampling nodes NSP and NSN via capacitive coupling be as small as possible. According to the present embodiment, by arranging the comparison circuit 22 between the capacitor array circuits CAP and CAN, the sampling nodes NSP and NSN can be wired with a short wiring length. As a result, parasitic capacitance for the sampling nodes NSP and NSN can be reduced, and propagation of noise through capacitive coupling of the parasitic capacitance can be reduced.

  Further, according to the present embodiment, since the sampling nodes NSP and NSN are wired between the capacitor array circuits CAP and CAN and the comparison circuit 22, the quantization error retention provided on the direction D2 side of the capacitor array circuits CAP and CAN. One end of each of the circuits QEHP and QEHN can be connected to the sampling nodes NSP and NSN with a short wiring length.

  Further, in the present embodiment, the addition circuit 40 includes an operational amplifier AMP disposed between the quantization error holding circuit QEHP and the quantization error holding circuit QEHN.

  As described later with reference to FIG. 8, the adder circuit 40 includes an operational amplifier AMP, capacitors CFP, CFN, CIP, CIN, switches SFP, SFN, SDP, SDN, SEP, and SEN. Among these, the operational amplifier AMP is disposed between the quantization error holding circuits QEHP and QEHN. In addition, capacitors CFP and CIP, switches SFP, SDP, and SEP are disposed as the positive side circuit FBA on the direction D2 side of the quantization error holding circuit QEHP. Further, the capacitors CFN and CIN, the switches SFN, SDN and SEN are disposed as the negative side circuit FBB on the direction D2 side of the quantization error holding circuit QEHN.

  As shown in FIG. 8, the inverting input node NIN of the operational amplifier AMP is connected to the other end of the quantization error holding circuit QEHP, and the noninverting input node NIP of the operational amplifier AMP is connected to the other end of the quantization error holding circuit QEHN. Be done. According to the present embodiment, by arranging the operational amplifier AMP between the quantization error holding circuit QEHP and QEHN, between the inverting input node NIN and the other end of the quantization error holding circuit QEHP, and the non-inverting input Wiring can be made between the node NIP and the other end of the quantization error holding circuit QEHN with a short wiring length.

  Further, according to the present embodiment, the operational amplifier AMP is disposed on the direction D2 side of the comparison circuit 22, and the capacitor array circuits CAP and CAN are disposed with the comparison circuit 22 in between, and the operational amplifier AMP is in between. The quantization error holding circuits QEHP and QEHN are arranged. As a result, the hybrid A / D conversion circuits of differential configuration can be arranged symmetrically (above-mentioned line symmetry), and efficient layout arrangement can be achieved from the viewpoint of signal transmission.

  A control circuit 23 can be further disposed between the quantization error holding circuit QEHP and the quantization error holding circuit QEHN (in the direction D2 side of the operational amplifier AMP). Further, a selector is further provided between the positive side circuit FBA and the negative side circuit FBB of the adding circuit 40 or between the quantization error holding circuit QEHP and the quantization error holding circuit QEHN (direction D2 side of the control circuit 23). 10 can be arranged.

  Further, in the present embodiment, the holding circuits HP1 to HPn of the quantization error holding circuit QEHP are arranged along the direction D2, and the holding circuits HN1 to HNn of the quantization error holding circuit QEHN are arranged along the direction D2. .

  That is, in the arrangement region of the quantization error holding circuits QEHP arranged on the direction D2 side of the capacitor array circuit CAP, the holding circuits HP1 to HPn are arranged along the direction D2. For example, the holding circuits HP1 and HP2 are adjacently arranged, and similarly, the holding circuits HP2 to HPn are sequentially adjacently arranged. In the arrangement region of the quantization error holding circuit QEHN arranged on the direction D2 side of the capacitor array circuit CAN, the holding circuits HN1 to HNn are arranged along the direction D2. For example, the holding circuits HN1 and HN2 are adjacently arranged, and similarly, the holding circuits HN2 to HNn are sequentially adjacently arranged. For example, the long sides of the holding circuits HP1 to HPn and HN1 to HNn are sides along the direction D1, and the short sides are sides along the direction D2.

  When the number of input channels to the A / D conversion circuit is changed, the number (value of n) of the holding circuits HP1 to HPn and HN1 to HNn changes accordingly. According to this embodiment, even when the number of holding circuits HP1 to HPn and HN1 to HNn is changed, efficient layout change using existing circuit design is possible. That is, since the holding circuits HP1 to HPn and HN1 to HNn are arranged along the direction D2, the layout size in the direction D2 (the length in the direction D2 of the layout area) is shortened along with the change of the number You can change the layout by stretching it.

  A second layout configuration example of the circuit device 100 is shown in FIG. FIG. 3 shows an example of the layout configuration when the number of input channels is 1 (n = 1). In FIG. 3, the arrangement of the capacitor array circuit CAP, CAN, the comparison circuit 22, and the operational amplifier AMP is the same as that of FIG. On the other hand, only the holding circuits HP1 and HN1 are disposed as the quantization error holding circuits QEHP and QEHN on the direction D2 side of the capacitor array circuit CAP and CAN. The positive side circuit FBA and the negative side circuit FBB of the adding circuit 40 are moved in the opposite direction to the direction D2, and the size of the circuit device 100 as a whole in the direction D2 is reduced. The control circuit 23 is disposed, for example, on the side opposite to the direction D1 of the capacitor array circuit CAP or the holding circuit HP1.

  Thus, when the number of holding circuits HP1 to HPn and HN1 to HNn is changed, the direction D2 is changed without changing the arrangement of other circuits (capacitor array circuit CAP, CAN, comparison circuit 22, operational amplifier AMP, etc.) You can adjust the layout size in. This enables efficient layout change using the existing circuit design.

3. Second Circuit Configuration Example A detailed operation of the circuit device 100 will be described with reference to FIGS. 4 and 5. FIG. 4 is a second circuit configuration example of the circuit device 100. As shown in FIG. Here, the basic configuration of the circuit device 100 is shown, and the operation will be described using the basic configuration.

  As shown in FIG. 4, the circuit device 100 includes a selector 10, an A / D conversion circuit 20, and a quantization error holding circuit 30.

  The selector 10 selects the voltages VI1 to VIn sequentially in time division, and outputs the voltage selected in that time division as the output voltage VSL. VSL corresponds to VSLP and VSLN in FIG.

  Adder circuit 40 amplifies the voltage corresponding to the charge held in quantization error hold circuit QEHi and the input voltage (VSL) with gains of mutually opposite signs and adds them, and outputs the result as output voltage VDF Do. VDF corresponds to VDFP and VDFN in FIG.

  The D / A conversion circuit 21 outputs the difference between the output voltage VDF of the addition circuit 40 and the D / A conversion voltage of the successive approximation data SAD as a D / A conversion result (difference voltage DAQ). DAQ corresponds to DAQP and DAQN in FIG.

  The quantization error holding circuit 30 includes quantization error holding circuits QEH1 to QEHn holding charges corresponding to the quantization errors in A / D conversion of the voltages VI1 to VIn. The quantization error holding circuit QEHi holds (the attenuation voltage of) the differential voltage DAQ after the successive comparison operation is completed in the A / D conversion when the selector 10 selects the voltage VIi. QEHi corresponds to HPi and HNi in FIG.

  The comparison circuit 22 performs comparison and determination between the output voltage VDF of the addition circuit 40 and the D / A conversion voltage of the successive approximation data SAD based on the differential voltage DAQ from the D / A conversion circuit 21.

  The control circuit 23 performs a successive approximation operation of sequentially updating the successive approximation data SAD output to the D / A conversion circuit 21 based on the comparison result (CPQ) by the comparison circuit 22.

  FIG. 5 is a timing chart explaining the basic operation of the circuit device 100 of FIG. Hereinafter, although the case of n = 2 is demonstrated, it is not limited to n = 2. In addition to the operation of FIG. 5, the reset operation and sampling operation of the addition circuit 40, and the reset operation and sampling operation of the quantization error holding circuits QEH1 and QEH2 may be further included.

  In the first period of the (k−1) th A / D conversion, the selector 10 selects the voltage VI1 as the voltage VSL, and the adding circuit 40 samples and holds the voltage VSL = VI1. The held voltage is denoted by VI1 (k-1). The quantization error holding circuit QEH1 holds a charge corresponding to the output voltage (E1 (k-2)) of the D / A conversion circuit 21 after the successive comparison operation is completed in the k-2nd A / D conversion. ing. The adder circuit 40 outputs VDF = VI (k-1) -E1 (k-2) based on the charge. Here, although the gain of the addition circuit 40 with respect to the voltage VSL is set to 1, the gain is not limited to 1. The D / A conversion circuit 21, the comparison circuit 22, and the control circuit 23 perform a successive approximation operation to A / D convert the output voltage VDF of the addition circuit 40, and A / D conversion result data DOUT = D1 (k-1) Output In addition, (X) of DOUT shows don't care. The control circuit 23 outputs SAD = D1 (k-1), the D / A conversion circuit 21 outputs a voltage E1 (k-1) corresponding to the quantization error, and the quantization error holding circuit QEH1 outputs the voltage The charge corresponding to E1 (k-1) is held.

  Next, in the second period of the (k−1) -th A / D conversion, the selector 10 selects the voltage VI2 as the voltage VSL, and the adding circuit 40 samples and holds the voltage VSL = VI2. This held voltage is VI2 (k-1). By the same operation as described above, D / A conversion circuit 21 outputs voltage E2 (k-1) corresponding to the quantization error, and quantization error holding circuit QEH2 corresponds to the voltage E2 (k-1). Hold the charge.

  Next, in the first period of the k-th A / D conversion, the selector 10 selects the voltage VI1 as the voltage VSL, and the adding circuit 40 samples and holds the voltage VSL = VI1. This held voltage is denoted by VI1 (k). By the same operation as described above, D / A conversion circuit 21 outputs voltage E1 (k) corresponding to the quantization error, and quantization error holding circuit QEH1 holds the charge corresponding to the voltage E1 (k). .

  Next, in the second period in the k-th A / D conversion, the selector 10 selects the voltage VI2 as the voltage VSL, and the adding circuit 40 samples and holds the voltage VSL = VI2. This held voltage is denoted by VI2 (k). By the same operation as described above, D / A conversion circuit 21 outputs voltage E2 (k) corresponding to the quantization error, and quantization error holding circuit QEH2 holds the charge corresponding to the voltage E2 (k). . The same operation is repeated in the (k + 1) th and subsequent A / D conversions.

The transfer function realized by the above operation is shown in the following equation (1). V (Di) represents A / D conversion result data DOUT = Di of the voltage VIi as a voltage, and specifically, is a D / A converted voltage of Di. In the following equation (1), the effect of the first-order high-pass filter (1-z-1) is generated with respect to the voltage Ei which is a quantization error. That is, in the A / D conversion result data DOUT = Di, a first-order noise shaping effect occurs with respect to noise due to the quantization error.

  FIG. 6 is an example of the frequency characteristic of A / D conversion result data DOUT in the present embodiment. In the example of FIG. 6, a signal of a predetermined frequency is input as an input signal, which is shown as a peak of the frequency characteristic. The input signal is not limited to the signal of the predetermined frequency, and a signal including frequency components of the signal band BNS can be assumed. When this signal band BNS is lower than the conversion rate of A / D conversion, the signal band BNS is oversampled at a high conversion rate. For example, the conversion rate is five times or more, or ten times or more the upper limit frequency of the signal band BNS. As shown by the straight line FLN, floor noise (quantization noise) in the low frequency band is reduced by the noise shaping effect. Therefore, S / N is improved by reducing noise with a higher frequency than the signal band BNS with the low pass filter. it can. As a result, it is possible to realize high accuracy (for example, expansion of the number of effective bits) of A / D conversion result data.

4. First Detailed Configuration Example FIG. 7 is a first detailed configuration example of the circuit device 100. As shown in FIG. The circuit device 100 of FIG. 7 includes a selector 10, an A / D conversion circuit 20, a quantization error holding circuit 30, and an addition circuit 40. The circuit device 100 can also include a reference voltage generation circuit GVR. Although the case of n = 8 will be described below, it is not limited to n = 8.

  The temperature sensors TS1 to TS7 are sensors for measuring the temperature of the temperature measurement target. As the temperature sensors TS1 to TS7, it is possible to use, for example, a temperature sensor utilizing temperature dependency of a band gap voltage of a PN junction or a thermistor utilizing temperature dependency of resistance value of resistance. A part of the temperature sensors TS1 to TS7 is incorporated in the circuit device 100, and the rest is provided outside the circuit device 100 (for example, inside the oscillation device including the circuit device 100). Alternatively, all of the temperature sensors TS1 to TS7 may be incorporated in the circuit device 100, or all of the temperature sensors TS1 to TS7 may be provided outside the circuit device 100.

  The selector 10 includes a selector 11 (a selector on the positive electrode side, a first selector), and a selector 12 (a selector on the negative electrode side, a second selector).

  The temperature detection voltages VT1 to VT7 (first to seventh positive side voltages) from the temperature sensors TS1 to TS7 are input to the selector 11 and the selector 11, respectively. Further, an arbitrary voltage VXP (eighth positive electrode side voltage) used for a test or the like may be input to the selector 11, for example. The reference voltage VRF (first negative side voltage) from the reference voltage generation circuit GVR is input to the selector 12. For example, an arbitrary voltage VXN (second negative electrode side voltage) used for a test or the like may be input to the selector 12. For example, the reference voltage generation circuit GVR is a band gap reference circuit, and the reference voltage VRF is a band gap reference voltage (voltage having no temperature dependency).

  The selector 11 sequentially selects the temperature detection voltages VT1 to VT7 and the arbitrary voltage VXP, and outputs them as a time division output voltage VSLP. When the selector 11 outputs the temperature detection voltages VT1 to VT7, the selector 12 selects the reference voltage VRF and outputs it as the output voltage VSLN. When the selector 11 selects the arbitrary voltage VXP, the selector 11 selects the arbitrary voltage VXN and outputs it as the output voltage VSLN.

  In the present configuration example, the differential voltage signal configured by (VT1, VRF) corresponds to the voltage VI1 in FIGS. 1 and 4. Similarly, a differential consisting of (VT2, VRF), (VT3, VRF), (VT4, VRF), (VT5, VRF), (VT6, VRF), (VT7, VRF), (VXP, VXN) The voltage signals correspond to the voltages VI2, VI3, VI4, VI5, VI6, VI7, VI8 of FIGS.

  The adder circuit 40 differentially amplifies the differential voltage signals (VSLP, VSLN) from the selector 10, and converts the charge on the positive side and the charge on the negative side from the quantization error holding circuit 30 into charge voltage (differential QV) Convert and output differential voltage signals (VDFP, VDFN) obtained by adding the differential voltage signals.

  The A / D conversion circuit 20 is a differential input A / D conversion circuit 20. That is, the differential voltage signal composed of the output voltages VDFP and VDFN of the adding circuit 40 is A / D converted, and A / D conversion result data DOUT corresponding to the difference between the output voltages VDFP and VDFN is output.

  The quantization error holding circuit 30 holds differential voltage signals (DAQP, DAQN) which are output signals of the D / A conversion circuit 21 after the successive approximation operation of the A / D conversion circuit 20 is completed. Specifically, the charge corresponding to the voltage DAQP constituting the differential voltage signal and the charge corresponding to the voltage DAQN are held.

  According to the present embodiment, the temperature detection voltages VT1 to VT7 from the temperature sensors TS1 to TS7 are input to the selector 10 as the voltages VI1 to VI7 of the voltages VI1 to VI8. The number of temperature sensors is not limited to seven. That is, in the selector 10, the first to mth temperature detection voltages from the first to mth temperature sensors (m is an integer of 1 or more and n or less) are the first to It may be input as a voltage of m.

  Since the change in temperature is gradual, the signal band of the temperature detection voltages VT1 to VT7 output by the temperature sensors TS1 to TS7 is a low frequency band (for example, 100 Hz or less). Therefore, even a relatively slow A / D conversion circuit such as a successive approximation type can perform A / D conversion at a conversion rate sufficiently higher than the signal band. In the present embodiment, by configuring the hybrid A / D conversion circuit, it is possible to realize the oversampling state with the noise shaping effect as described above, and to enable measurement with high S / N in the signal band of the temperature sensor. Become.

  As processing using temperature detection data (A / D conversion result data of temperature detection voltage), temperature compensation processing in a digital oscillator such as TCXO (Temperature Compensated Crystal Oscillator) or OCXO (Oven Controlled Crystal Oscillator) can be considered, for example . By using a plurality of temperature sensors provided at a plurality of positions inside (or inside and outside) the oscillator, there is a possibility that the temperature of the vibrator (for example, a crystal vibrator or the like) can be estimated with high accuracy. Since the temperature of the oscillator can be estimated with high accuracy, the accuracy of temperature compensation can be improved, and the stability of the oscillation frequency can be improved. In this embodiment, since a hybrid A / D conversion circuit corresponding to multi-channel input can be configured, high-precision A / D conversion can be performed on multi-channel input from a plurality of temperature sensors.

5. Second Detailed Configuration Example FIGS. 8 and 9 show a second detailed configuration example of the circuit device 100. FIG. The second detailed configuration example is shown separately in FIGS. 8 and 9, and the same components are denoted by the same reference numerals. Although the case of n = 8 will be described below, it is not limited to n = 8.

  As shown in FIG. 8, the adder circuit 40 includes a capacitor CIP (positive electrode side input capacitor), a capacitor CIN (negative electrode side input capacitor), a capacitor CFP (positive electrode side feedback capacitor), and a capacitor CFN (negative electrode side). Capacitors for feedback, switches SDP, SDN, SEP, SEN, SFP, SFN, and a fully differential operational amplifier AMP. The fully differential operational amplifier is an operational amplifier of differential input and differential output.

  The switch SDP connects one end of the capacitor CIP to one of the output node NSLP (first output node of the selector 10) of the selector 11 and the node of the common voltage VCM. The switch SDN connects one end of the capacitor CIN to one of the output node NSLN (second output node of the selector 10) of the selector 12 and the node of the common voltage VCM. The switch SEP connects the other end of the capacitor CIP to one of the noninverting input node NIP of the operational amplifier AMP and the node of the common voltage VCM. The switch SEN connects the other end of the capacitor CIN to one of the inverting input node NIN of the operational amplifier AMP and the node of the common voltage VCM. One end of the capacitor CFP and one end of the switch SFP are connected to the non-inverting input node NIP of the operational amplifier AMP, and the other end of the capacitor CFP and the other end of the switch SFP are connected to the inverting output node NDFP of the operational amplifier AMP. One end of the capacitor CFN and one end of the switch SFN are connected to the inverting input node NIN of the operational amplifier AMP, and the other end of the capacitor CFN and the other end of the switch SFN are connected to the noninverting output node NDFN of the operational amplifier AMP. The switches SDP, SDN, SEP, SEN, SFP, and SFN are analog switches configured of, for example, transistors.

  As shown in FIGS. 8 and 9, the D / A conversion circuit 21 is a differential D / A conversion circuit. The D / A conversion circuit 21 includes a capacitor array circuit CAP (a capacitor array circuit on the positive electrode side) and a capacitor array circuit CAN (a capacitor array circuit on the negative electrode side).

As shown in FIG. 9, the capacitor array circuit CAP includes capacitors CP1 to CP6 and switches SP1 to SP6, SCP1, and SCP2. One end of the switch SCP1 is connected to the sampling node NSP of the capacitor array circuit CAP, and the other end is connected to the node of the common voltage VCM. One end of capacitor CPj (j is an integer of 1 or more and 6 or less) is connected to sampling node NSP. The switch SPj connects the other end of the capacitor CPj to either the node NCP2 or the node of the voltage VDD (power supply voltage, first voltage) or the node of the voltage VSS (ground voltage, second voltage). The switch SCP2 connects the node NCP2 to one of the inverting output node NDFP of the operational amplifier AMP and the node of the common voltage VCM. The capacitance value of the capacitor CPj is CP1 × 2 ^j−1 . The switches SP1 to SP6, SCP1, and SCP2 are analog switches configured with, for example, transistors.

The capacitor array circuit CAN includes capacitors CN1 to CN6 and switches SN1 to SN6, SCN1 and SCN2. One end of the switch SCN1 is connected to the sampling node NSN of the capacitor array circuit CAN, and the other end is connected to the node of the common voltage VCM. One end of the capacitor CNj is connected to the sampling node NSN. The switch SNj connects the other end of the capacitor CNj to either the node NCN2, the node of the voltage VDD, or the node of the voltage VSS. The switch SCN2 connects the node NCN2 to one of the non-inversion output node NDFN of the operational amplifier AMP and the node of the common voltage VCM. The capacitance value of the capacitor CNj is CN1 × 2 ^j−1 . The switches SN1 to SN6, SCN1 and SCN2 are, for example, analog switches configured with transistors.

  The number of capacitors included in the capacitor array circuit CAP and CAN is not limited to six, and the capacitor array circuit CAP includes the first to kth positive electrode side capacitors (k is an integer of 2 or more). May include the first to kth negative electrode side capacitors. At this time, j is an integer of 1 or more and k or less. The successive approximation data is k-bit data SAD [k-1: 0].

  As shown in FIGS. 8 and 9, the quantization error holding circuit 30 includes a quantization error holding circuit QEHP (a quantization error holding circuit on the positive electrode side) and a quantization error holding circuit QEHN (a quantization error holding circuit on the negative electrode side). Circuit) and.

  As shown in FIG. 8, the quantization error holding circuit QEHP includes holding circuits HP1 to HP8 (first to nth holding circuits on the positive electrode side). The holding circuit HPi (i-th positive side holding circuit) includes a capacitor CEPi (positive side holding capacitor), a switch SAPi (first positive side switch), and a switch SBPi (second positive side switch). ,including. The switch SAPi connects one end of the capacitor CEPi to one of the sampling node NSP and the node of the common voltage VCM, or sets it in a floating state. The switch SBPi connects the other end of the capacitor CEPi to one of the inverting input node NIN of the operational amplifier AMP and the node of the common voltage VCM. The capacitance values of the capacitors CEP1 to DEP8 are the same. The switches SAP1 to SAP8 and SBP1 to SBP8 are analog switches configured of, for example, transistors.

  The quantization error holding circuit QEHN includes holding circuits HN1 to HN8 (first to nth holding circuits on the negative electrode side). A holding circuit HNi (i-th negative electrode side holding circuit) includes a capacitor CENi (negative electrode side holding capacitor), a switch SANi (first negative electrode side switch), and a switch SBNi (second negative electrode side switch) ,including. The switch SANi connects one end of the capacitor CENi to one of the sampling node NSN and the node of the common voltage VCM, or sets it in a floating state. The switch SBNi connects the other end of the capacitor CENi to one of the noninverting input node NIP of the operational amplifier AMP and the node of the common voltage VCM. The capacitance values of the capacitors CEN1 to CEN8 are the same. The switches SAN1 to SAN8 and SBN1 to SBN8 are analog switches configured of, for example, transistors.

  The holding circuit HPi and the holding circuit HNi in FIGS. 8 and 9 correspond to the quantization error holding circuit QEHi in FIG.

  The comparison circuit 22 is a differential input single-ended output comparator. The non-inversion input node of comparison circuit 22 is connected to sampling node NSP, and the inversion input node is connected to sampling node NSN. The voltages DAQP and DAQN, which are D / A converted voltages, are output as the voltages of the sampling nodes NSP and NSN. When DAQP-DAQN> 0 V, the comparison circuit 22 outputs a high level signal CPQ, and when DAQP-DAQN <0 V, the comparison circuit 22 outputs a low level signal CPQ. Control circuit 23 updates sequential comparison data SAD [5: 0] based on signal CPQ, and outputs sequential comparison data SAD [5: 0] to switches SP1 to SP6 and SN1 to SN6. The control circuit 23 also controls switches included in the addition circuit 40, the D / A conversion circuit 21, and the quantization error holding circuit 30.

  The operation of the circuit device 100 of FIGS. 8 and 9 will be described below. Hereinafter, an operation in the k-th A / D conversion when the selector 10 selects the voltage VIi will be described. The states of the switches not mentioned in each period are the same as in the previous period.

  In the reset period (initialization period), the switches SFP and SFN of the adder circuit 40 are on. As a result, both ends of the capacitors CFP and CFN are connected, and the charges of the capacitors CFP and CFN are reset (initialized). Further, the switches SCP1 and SCN1 of the capacitor array circuit CAP and CAN are turned on, the switches SCP2 and SCN2 select the nodes of the common voltage VCM, and the switches SP1 to SP6 and SN1 to SN6 select the nodes NCP2 and NCN2. Thereby, both ends of the capacitors CP1 to CP6 and CN1 to CN6 become the common voltage VCM, and the charges of the capacitors CP1 to CP6, CN1 to CN6 are reset. Further, the switches SAP1 to SAP8 and SAN1 to SAN8 of the quantization error holding circuit QEHP and QEHN select the floating state, and the switches SBP1 to SBP8 and SBN1 to SBN8 select the node of the common voltage VCM. Thereby, capacitors CEPi and CENi hold the charge corresponding to the quantization error in the (k−1) -th A / D conversion for voltage VIi. That is, assuming that DAQP = EPi and DAQN = ENi after completion of the k−1th A / D conversion successive comparison operation, the capacitors CEPi and CENi have common voltages EPi and ENi corresponding to the quantization error. Hold voltage VCM as a reference. However, as described by the following equation (2), a voltage in which the voltages EPi and ENi are attenuated is maintained.

  In the first addition operation period after the reset period, the switches SFP and SFN of the adder circuit 40 are off, and the switches SBPi and SBNi of the quantization error holding circuits QEHP and QEHN are input nodes NIN and NIP of the operational amplifier AMP. And the switches SAPi, SANi select the node of the common voltage VCM. As a result, the charge held by the capacitor CEPi is redistributed by the capacitors CEPi and CFN, and the charge held by the capacitor CENi is redistributed by the capacitors CENi and CFP. That is, a differential voltage signal composed of (the attenuation voltage of) EPi and ENi corresponding to the quantization error in the (k−1) th A / D conversion is differentially amplified with a negative gain. Further, in the first addition operation period, the switches SDP and SDN of the addition circuit 40 select the output nodes NSLP and NSLN of the selector 10, and the switches SEP and SEN select the node of the common voltage VCM. Thereby, capacitors CIP and CIN sample input voltages (VSLP and VSLN) with reference to common voltage VCM.

  In the second addition operation period after the first addition operation period, the switches SDP and SDN select the node of the common voltage VCM, and the switches SEP and SEN select the input nodes NIP and NIN of the operational amplifier AMP. As a result, differential voltage signals composed of input voltages (VSLP, VSLN) are differentially amplified with positive gain. By the above operation, the differential voltage signal obtained by differentially amplifying the differential voltage signal composed of the input voltage (VSLP, VSLN) with positive gain, and the difference composed of the voltages EPi and ENi (attenuation voltage of) The dynamic voltage signal is added to the differential voltage signal differentially amplified with negative gain. The addition result is output as a differential voltage signal composed of output voltages VDFP and VDFN. When the second addition operation period ends, the switches SDP and SDN of the addition circuit 40 select the output nodes NSLP and NSLN of the selector 10, and the switches SEP and SEN select the node of the common voltage VCM. That is, the capacitors CIP and CIN resample the input voltages (VSLP and VSLN) with reference to the common voltage VCM.

  In the sampling period after the second addition operation period, the switches SCP1 and SCN1 of the capacitor array circuit CAP and CAN are on, and the switches SCP2 and SCN2 select the output nodes NDFP and NDFN of the addition circuit 40. Thus, the capacitors CP1 to CP6 and CN1 to CN6 sample the output voltages VDFP and VDFN of the adding circuit 40 with reference to the common voltage VCM.

  In the successive approximation operation period after the sampling period, the capacitor array circuit CAP, the switches SCP1 and SCN1 of CAN are off, and the switches SP1 to SP6 and SN1 to SN6 are voltage VDD based on the successive approximation data SAD [5: 0]. Or select the voltage VSS. Specifically, when SAD [j] = 1, the switch SPj selects the voltage VDD, and the switch SNj selects the voltage VSS. When SAD [j] = 0, the switch SPj selects the voltage VSS, and the switch SNj selects the voltage VDD. As a result, voltages DAQP and DAQN, which are DAQP-DAQN = V (SAD [5: 0])-(VDFP-VDFN), are output to the sampling nodes NSP and NSN. The comparator circuit 22 determines whether DAQP-DAQN is positive or negative, and outputs the result as a signal CPQ. Control circuit 23 updates successive approximation data SAD [5: 0] based on signal CPQ. The above operation is sequentially repeated until A / D conversion result data is determined.

  In the next quantization error holding period of the successive approximation operation period, the control circuit 23 outputs the A / D conversion result data as the successive comparison data SAD [5: 0]. As a result, voltages EPi and ENi corresponding to the quantization error in the k-th A / D conversion of voltage VIi are output to sampling nodes NSP and NSN. The switches SAPi and SANi of the quantization error holding circuits QEHP and QEHN select the sampling nodes NSP and NSN, and the switches SBPi and SBNi select the nodes of the common voltage VCM. Thereby, capacitors CEPi and CENi hold a charge corresponding to the quantization error in the k-th A / D conversion for voltage VIi. That is, the capacitors CEPi and CENi hold the voltages EPi and ENi with reference to the common voltage VCM. However, as described by the following equation (2), a voltage in which the voltages EPi and ENi are attenuated is maintained.

  After the quantization error holding period, the k-th A / D conversion of the voltage VIi + 1 is performed. After the kth A / D conversion of the voltage VIn is completed, the (k + 1) th A / D conversion of the voltage VI1 is performed.

In the above operation, the output voltage of the adder circuit 40 is expressed by the following equation (2). k represents that it is the voltage in the kth A / D conversion operation. VDF (k) is VDFP-VDFN after the second addition operation period. CI is the capacitance value of the capacitor CIP, and the capacitance value of the capacitor CIN is also CI. CF is the capacitance value of the capacitor CFP, and the capacitance value of the capacitor CFN is also CF. VSL (k) is VSLP-VSLN after the first addition operation period. CE is the capacitance value of the capacitor CEPi, and the capacitance value of the capacitor CENi is also CE. Ctotal is a sum of capacitance values of the capacitors CP1 to CP6. E (k-1) is EPi-ENi in the (k-1) th A / D conversion.

  In the above equation (2), the capacitance values CE, CF and Ctotal are set such that the gain of E (k-1) is -1. E (k-1) represents charge redistribution between capacitors CP1 to CP6 (Ctotal) and capacitor CEPi (CE), and charge redistribution between capacitors CN1 to CN6 (Ctotal) and capacitor CENi (CE) Attenuates by the gain Ctotal / (Ctotal + CE). Since the gain CE / CF is multiplied when the adding circuit 40 performs the adding operation, the attenuated E (k-1) can be amplified. As a result, it is possible to set the gain of E (k-1) to -1, and it is possible to realize a transfer function having a noise shaping characteristic as shown in the above equation (1).

  According to the above embodiment, the switch SAPi connects one end of the capacitor CEPi to the sampling node NSP, and the switch SBPi connects the other end of the capacitor CEPi to the node of the common voltage VCM, whereby the capacitor CEPi has a quantization error. Can hold the corresponding charge. Similarly, switch SANi connects one end of capacitor CENi to sampling node NSN, and switch SBNi connects the other end of capacitor CENi to the node of common voltage VCM, whereby capacitor CENi holds a charge corresponding to a quantization error. it can. The switch SAPi connects one end of the capacitor CEPi to the node of the common voltage VCM, and the switch SBPi connects the other end of the capacitor CEPi to the inverting input node NIN of the operational amplifier AMP, whereby the charge held by the capacitor CEPi is It is redistributed between the capacitors CEPi and CFN. The switch SANi connects one end of the capacitor CENi to the node of the common voltage VCM, and the switch SBNi connects the other end of the capacitor CENi to the noninverting input node NIP of the operational amplifier AMP, whereby the charge held by the capacitor CENi is a capacitor. Redistributed between CENi and CFP. Thereby, the voltage corresponding to the quantization error can be subtracted from the input voltage (VSLP, VSLN) of the A / D conversion circuit 20.

6. Chopping Modulation FIG. 10 is a configuration example of the chopping modulation circuit and the chopping demodulation circuit in the case where chopping modulation is performed in the adding circuit 40. In FIG. In FIG. 10, the adding circuit 40 includes a chopping modulation circuit CHCM and a chopping demodulation circuit CHCD. When the configuration of FIG. 10 is applied to FIG. 8, the nodes NIP, NIN, NDFP, and NDFN of FIG. 10 correspond to the nodes NIP, NIN, NDFP, and NDFN of FIG.

  The chopping modulation circuit CHCM modulates chopping on the voltage input to the non-inverted input node NIP ′ and the inverted input node NIN ′ of the operational amplifier AMP. That is, the chopping modulation circuit CHCM chopping modulates the voltages VIP and VIN of the nodes NIP and NIN, and outputs the modulated voltages to the nodes NIP 'and NIN'.

  The chopping modulation circuit CHCM includes switches SMA1, SMA2, SMB1, and SMB2. One end of each of the switches SMA1 and SMB1 is connected to the node NIP, and one end of each of the switches SMA2 and SMB2 is connected to the node NIN. The other ends of the switches SMA1 and SMB2 are connected to the node NIP ', and the other ends of the switches SMA2 and SMB1 are connected to the node NIN'. The switches SMA1, SMA2, SMB1, and SMB2 are analog switches configured with, for example, transistors. In the non-inversion operation, the switches SMA1 and SMA2 are on, the switches SMB1 and SMB2 are off, and the voltages VIP and VIN are input to the nodes NIP 'and NIN'. In the reverse operation, the switches SMA1 and SMA2 are off, the switches SMB1 and SMB2 are on, and the voltages VIN and VIP are input to the nodes NIP 'and NIN'.

  The chopping demodulation circuit CHCD demodulates chopping on the voltages output from the inverted output node NDFP 'and the non-inverted output node NDFN' of the operational amplifier AMP. That is, the chopping demodulation circuit CHCD performs chopping demodulation on the voltages of the nodes NDFP 'and NDFN', and outputs the voltages VDFP and VDFN after the demodulation to the nodes NDFP and NDFN.

  The chopping demodulation circuit CHCD includes switches SDA1, SDA2, SDB1, and SDB2. One end of the switches SDA1 and SDB1 is connected to the node NDFP ', and one end of the switches SDA2 and SDB2 is connected to the node NDFN'. The other ends of the switches SDA1 and SDB2 are connected to the node NFDF, and the other ends of the switches SDA2 and SDB1 are connected to a node NDFN. In the non-inversion operation, the switches SDA1 and SDA2 are on, the switches SDB1 and SDB2 are off, and the voltages of the nodes NDFP 'and NDFN' are output to the nodes NDFP and NDFN as voltages VDFP and VDFN. The switches SDA1, SDA2, SDB1, and SDB2 are analog switches configured of, for example, transistors. In the reverse operation, the switches SDA1 and SDA2 are off, the switches SDB1 and SDB2 are on, and the voltages of the nodes NDFN 'and NDFP' are output to the nodes NDFP and NDFN as voltages VDFP and VDFN.

  The operational amplifier AMP has an offset. For example, an offset is generated between the nodes NIP 'and NIN' by making the sizes of the two transistors constituting the differential pair of the operational amplifier AMP different.

  The chopping modulation circuit CHCM and the chopping demodulation circuit CHCD alternately repeat the inversion operation and the non-inversion operation. Specifically, one of the inversion operation and the non-inversion operation is performed in the (k−1) -th A / D conversion, and the other of the inversion operation and the non-inversion operation is performed in the k-th A / D conversion. Thereby, the offset of the operational amplifier AMP is modulated at the chopping frequency. Specifically, the polarity of the offset is inverted in the (k-1) th A / D conversion and the kth A / D conversion.

  FIG. 11 is an example of a time change of A / D conversion result data (output code) when 0 V is input when chopping modulation is not performed. In this embodiment, since a first-order noise shaping mechanism is provided, when a DC signal is input to the A / D conversion circuit 20, the A / D conversion result data DOUT has a specific time change pattern, and the A / D conversion is performed. An unnecessary frequency component may occur in the result data DOUT. This phenomenon is called idle tone. For example, it is assumed that A / D conversion result data of the temperature detection voltage is used for the temperature compensation process of TCXO. At this time, when the A / D conversion result data changes at a constant cycle, the oscillation frequency is corrected at that cycle, which may lower the oscillation characteristic.

  FIG. 12 is an example of a time change of A / D conversion result data (output code) when 0 V is input in the present embodiment. In the present embodiment, since chopping modulation is performed, the polarity of the offset is inverted every A / D conversion. For this reason, the change in A / D conversion result data due to the offset becomes a high frequency by the chopping frequency, and the idle tone as described above can be reduced. For example, in the temperature compensation processing of TCXO, the possibility that the oscillation characteristic is degraded by the idle tone can be reduced.

7. Vibration Device Hereinafter, a configuration example of the vibration device 2 including the circuit device 100 will be described. FIG. 13 is a first configuration example of the vibration device 2 including the circuit device 100. As shown in FIG. In FIG. 13, the case where the vibration device 2 is an oscillator will be described as an example. Specifically, an application example to TCXO which is a temperature compensation type oscillator will be described. The temperature compensated oscillator may be OCXO.

  The vibrating device 2 (oscillator) includes the vibrator 110 and the circuit device 100. The vibrating device 2 can also include a temperature sensor TS2. For example, the vibrator 110, the circuit device 100, and the temperature sensor TS2 are housed in a package, whereby the vibration device 2 is configured.

  One end of the vibrator 110 is connected to the terminal T1, and the other end is connected to the terminal T2. The vibrator 110 (resonator) is an element (vibrating element) that generates mechanical vibration by an electrical signal. The vibrator 110 can be realized by a vibrating reed (piezoelectric vibrating reed) such as a quartz vibrating reed, for example. For example, the cutting angle can be realized by a quartz crystal vibrating piece that vibrates in a thickness slip manner such as AT cut or SC cut. For example, the vibrator 110 is a vibrator incorporated in a temperature compensated oscillator (TCXO) which does not have a constant temperature bath. Alternatively, the vibrator 110 may be a vibrator or the like built in a thermostatic oscillator (OCXO) including a thermostatic chamber. The vibrator 110 according to this embodiment can be realized by, for example, various vibrating bars such as vibrating bars other than the thickness shear vibration type, and piezoelectric vibrating bars formed of materials other than quartz. For example, as the vibrator 110, a surface acoustic wave (SAW) resonator or a micro electro mechanical systems (MEMS) vibrator as a silicon vibrator formed using a silicon substrate may be adopted.

  Circuit device 100 includes a processing circuit 123, an oscillation signal generation circuit 150, a selector 10, and an A / D converter 127. The circuit device 100 also includes a storage unit 124 (memory), a temperature sensor TS1 and an output circuit 122, terminals T1 and T2, an output terminal TM, a sensor input terminal TTS, signal terminals TSD and TSC, and a power supply. Power supply terminals TV and TG. The circuit device 100 is an integrated circuit device (IC, semiconductor chip). The terminals T1 and T2, the output terminal TM, the sensor input terminal TTS, the signal terminals TSD and TSC, and the power supply terminals TV and TG are, for example, so-called pads of an integrated circuit device.

  The oscillation signal generation circuit 150 generates an oscillation signal of an oscillation frequency corresponding to the frequency control data using the vibrator 110. The oscillation signal generation circuit 150 includes an oscillation circuit 121 that causes the oscillator 110 to oscillate. The oscillation signal generation circuit 150 may further include a D / A conversion circuit 125 described later.

  The oscillation circuit 121 has a drive circuit, and drives the vibrator 110 by the drive circuit via the terminals T1 and T2 to cause the vibrator 110 to oscillate. For example, a Pierce type oscillation circuit can be adopted as the oscillation circuit 121. In this case, the drive circuit includes a bipolar transistor and a resistor connected between the base and the collector of the bipolar transistor. The base of the bipolar transistor is the input node of the drive circuit, and the collector is the output node of the drive circuit. A variable capacitance circuit is provided for at least one connection node of an output node and an input node of the drive circuit. The variable capacitance circuit can be realized by, for example, a varactor whose capacitance value changes based on a control voltage, or a capacitor array in which the number of capacitors connected to a connection node is switched based on frequency control data.

  The output circuit 122 buffers a clock signal which is an output signal from the oscillation circuit 121, and outputs the buffered clock signal from the output terminal TM to the outside of the circuit device 100. For example, the output circuit 122 is configured by a buffer circuit that buffers a clock signal which is an output signal from the oscillation circuit 121.

  The temperature sensors TS1 and TS2 output, as a temperature detection voltage, a temperature dependent voltage that changes in accordance with the temperature of the environment (for example, the circuit device 100 or the vibrator 110). For example, the temperature sensors TS1 and TS2 generate a temperature dependent voltage using a circuit element having temperature dependency, and output the temperature dependent voltage based on a temperature independent voltage (for example, a band gap reference voltage). For example, the forward voltage of the PN junction is output as a temperature dependent voltage. The temperature detection voltage from the temperature sensor TS2 is input to the selector 10 via the sensor input terminal TTS.

  The selector 10 sequentially selects the temperature detection voltages from the temperature sensors TS1 and TS2, and outputs the temperature detection voltages of that time division to the A / D converter 127. The number of temperature sensors included in the vibrating device 2 is not limited to two, and the vibrating device 2 can include first to mth temperature sensors (m is an integer of 1 or more and n or less). At this time, the first to nth voltages may be input to the selector 10, and the first to mth voltages from the first to mth temperature sensors may be input as the first to mth voltages of the first to nth voltages. The ~ m th temperature detection voltage may be input. The selector 10 sequentially selects the first to nth voltages, and outputs the temperature detection voltage of that time division to the A / D converter 127.

  The A / D converter 127 A / D converts the output voltage of the selector 10. That is, the temperature detection voltage from the temperature sensors TS1 and TS2 output by the selector 10 in time division is A / D converted, and the result is output as time division temperature detection data. The A / D converter 127 includes the A / D conversion circuit 20 and the quantization error holding circuit 30 described with reference to FIG.

  The processing circuit 123 (digital signal processing circuit) performs various signal processing. For example, the processing circuit 123 (temperature compensation unit) performs temperature compensation processing to compensate for the temperature characteristic of the oscillation frequency of the vibrator 110 based on the temperature detection data, and outputs frequency control data for controlling the oscillation frequency. Specifically, the processing circuit 123 generates an oscillation frequency due to temperature change based on temperature detection data (temperature dependent data) that changes according to temperature, coefficient data for temperature compensation processing (data of coefficients of approximate function), and the like. Temperature compensation processing is performed to cancel or reduce the fluctuation of (to make the oscillation frequency constant even when there is a temperature change). The coefficient data for the temperature compensation process is stored in the storage unit 124. The storage unit 124 may be realized by a semiconductor memory such as a RAM (SRAM, DRAM) or may be realized by a non-volatile memory. The processing circuit 123 can be realized by a DSP (Digital Signal Processor) that executes various signal processing including temperature compensation processing in a time division manner. Alternatively, the processing circuit 123 may be realized by an ASIC circuit by automatic placement and wiring such as a gate array, or may be realized by a processor (for example, a CPU, an MPU, etc.) and a program operating on the processor. Further, the processing circuit 123 may perform correction processing (for example, aging correction) other than temperature compensation. The processing circuit 123 may also perform heater control (oven control) or the like of a thermostatic chamber in a thermostatic oscillator (OCXO).

  The processing circuit 123 includes an interface circuit that performs serial communication with an external device using the clock signal SCL and the data signal SDA. The interface circuit is, for example, an interface circuit such as I2C or SPI. Signal terminals TSC and TSD are terminals for the clock signal SCL and the data signal SDA.

  The D / A conversion circuit 125 D / A converts the frequency control data, and outputs a control voltage corresponding to the frequency control data to the oscillation circuit 121. The variable capacitance circuit provided in the oscillation circuit 121 is variably controlled in capacitance value based on the control voltage. The variable capacitance circuit in this case can be realized by the above-described varactor or the like.

  The high potential side power supply voltage VDD is supplied to the power supply terminal TV, and the low potential side power supply voltage VSS (for example, ground voltage) is supplied to the power supply terminal TG. The circuit device 100 operates by being supplied with these power supply voltages VDD and VSS.

  FIG. 14 is a second configuration example of the vibration device 2 including the circuit device 100. As shown in FIG. In FIG. 14, an example in which the vibrating device 2 is a physical quantity measuring device (physical quantity detecting device) for measuring a physical quantity will be described. As physical quantities to be measured, various physical quantities such as angular velocity, acceleration, angular acceleration, velocity, distance or time can be assumed. In the following, a gyro sensor (vibration gyro sensor) for detecting an angular velocity will be described as an example.

  The vibration device 2 of FIG. 14 includes a vibrator 110, a circuit device 100, and a temperature sensor TS2. The circuit device 100 includes a drive circuit 130, a detection circuit 160, an output circuit 122, a processing circuit 190, a temperature sensor TS1, a selector 10, an A / D converter 127, and terminals T1, T2, T5, T6. , A sensor input terminal TTS, and an output terminal TM.

  The vibrator 110 (sensor element, physical quantity transducer) is an element for detecting a physical quantity, and includes vibrating bars 141 and 142, drive electrodes 143 and 144, detection electrodes 145 and 146, and a ground electrode 147. The vibrating bars 141 and 142 are piezoelectric vibrating bars formed of a thin plate of a piezoelectric material such as quartz. Specifically, the vibrating bars 141 and 142 are vibrating bars formed of a Z-cut quartz substrate. The piezoelectric materials of the vibrating bars 141 and 142 may be ceramics or silicon other than quartz.

  A drive signal DS (output signal in a broad sense) from the drive circuit 130 of the circuit device 100 is supplied to the drive electrode 143 via the terminal T1, and the drive vibrating reed 141 vibrates. The vibrating reed 141 is, for example, a drive arm of the vibrator 110. Then, a feedback signal DG (input signal in a broad sense) from the drive electrode 144 is input to the drive circuit 130 via the terminal T2. For example, a feedback signal DG due to vibration of the vibrating reed 141 is input to the drive circuit 130.

  The vibrating vibrating bar 141 for driving vibrates and the vibrating vibrating bar 142 for detection vibrates, and charges (currents) generated by this vibration are detected as detection signals S1 and S2 from the detection electrodes 145 and 146 through the terminals T5 and T6. Is input to the detection circuit 160. Here, the ground electrode 147 is set to the ground potential. The detection circuit 160 detects physical quantity information (such as angular velocity) corresponding to the detection signals S1 and S2 based on the detection signals S1 and S2. Here, the case where the vibrator 110 is a gyro sensor element will be mainly described by way of example, but the present embodiment is not limited to this and may be an element for detecting other physical quantities such as acceleration. . Further, as the vibrator 110, for example, a vibrator element of a double T-type structure can be used, but a vibrator element such as a tuning fork type or an H type may be used.

  The driving circuit 130 receives an input of the feedback signal DG from the vibrator 110 and amplifies the signal, an AGC circuit (gain control circuit) performing automatic gain control, and an output for outputting the driving signal DS to the vibrator 110. A circuit etc. can be included. For example, the AGC circuit automatically adjusts the gain variably so that the amplitude of the feedback signal DG from the vibrator 110 becomes constant. The AGC circuit can be realized by a full-wave rectifier that full-wave rectifies the signal from the amplification circuit, an integrator that integrates the output signal of the full-wave rectifier, or the like. The output circuit outputs, for example, a drive signal DS of a rectangular wave. In this case, the output circuit can be realized by a comparator and a buffer circuit. The output circuit may output a sinusoidal drive signal DS. The drive circuit 130 also generates a synchronization signal SYC based on, for example, an output signal of the amplification circuit, and outputs the synchronization signal SYC to the detection circuit 160.

  The detection circuit 160 detects physical quantity information corresponding to the detection signals S1 and S2 based on the detection signals S1 and S2 from the vibrator 110 driven by the drive circuit 130. The detection circuit 160 can include an amplification circuit, a synchronous detection circuit, an adjustment circuit, and the like. The detection signals S1 and S2 from the vibrator 110 are input to the amplification circuit via the terminals T1 and T2, and charge-voltage conversion and signal amplification of the detection signals S1 and S2 are performed. The detection signals S1 and S2 constitute a differential signal. Specifically, the amplification circuit includes a first Q / V conversion circuit for amplifying the detection signal S1, a second Q / V conversion circuit for amplifying the detection signal S2, and first and second Q / V conversions. A differential amplifier can be included to differentially amplify the output signal of the circuit. The synchronous detection circuit performs synchronous detection using the synchronous signal SYC from the drive circuit 130. For example, synchronous detection is performed to extract a desired wave from the detection signals S1 and S2. The adjustment circuit performs offset adjustment for zero point correction and gain correction for sensitivity adjustment. The detection circuit 160 also has an A / D conversion circuit. The A / D conversion circuit A / D converts the signal after synchronous detection, and outputs the result as digital detection data to the processing circuit 190. The detection circuit 160 can also include a filter circuit that attenuates unnecessary signals that could not be removed by synchronous detection or the like.

  The configurations and operations of the temperature sensors TS1 and TS2, the selector 10, and the A / D converter 127 are the same as those in FIG.

  The processing circuit 190 performs various correction processes such as a correction process for offset adjustment and a correction process for sensitivity adjustment based on detection data from the detection circuit 160. For example, the processing circuit 190 performs the zero point correction process of the physical quantity (angular velocity) based on the temperature detection data from the A / D converter 127. That is, a correction value that cancels (or reduces) the temperature dependency of the zero point is obtained based on the temperature detection data, and the physical quantity is corrected by the correction value.

  The output circuit 122 outputs the detection data DTQ after the correction processing from the processing circuit 190 to the outside of the circuit device 100 via the output terminal TM. The output circuit 122 in this case may be realized by an interface circuit such as I2C or SPI, for example.

8. Electronic Device, Mobile Body FIG. 15 shows a configuration example of an electronic device 500 including the vibration device 2 (circuit device 100) of the present embodiment. The electronic device 500 includes the vibration device 2 having the circuit device 100 and the vibrator 110, and a processing unit 520. In addition, the communication unit 510, the operation unit 530, the display unit 540, the storage unit 550, and the antenna ANT can be included.

  The electronic device 500 may be, for example, a network-related device such as a base station or a router, a high-accuracy measuring device for measuring physical quantities such as distance, time, flow rate or flow rate, a biological information measuring device for measuring biological information (ultrasonic measurement device Pulse wave meter, blood pressure measurement device, etc., on-vehicle equipment (device for automatic driving etc.), etc. can be assumed. The electronic device 500 may be a wearable device such as a head-mounted display device or a watch-related device, a robot, a printing device, a projection device, a portable information terminal (such as a smartphone), a content providing device for distributing content, or a digital camera or video An imaging device such as a camera can be assumed.

  Communication unit 510 (communication interface) performs processing for receiving data from the outside via antenna ANT and transmitting data to the outside. The processing unit 520 (processor) performs control processing of the electronic device 500, various digital processing of data transmitted and received via the communication unit 510, and the like. The function of the processing unit 520 can be realized by a processor such as a microcomputer, for example. The operation unit 530 (operation interface) is for the user to perform an input operation, and can be realized by an operation button, a touch panel display, or the like. The display unit 540 displays various types of information, and can be realized by a display such as a liquid crystal or an organic EL. The storage unit 550 stores data, and its function can be realized by a semiconductor memory such as a RAM or a ROM, an HDD (hard disk drive), or the like.

  FIG. 16 shows an example of a mobile including the vibration device 2 (circuit device 100) of the present embodiment. The vibrating device 2 (oscillator, physical quantity measuring device) of the present embodiment can be incorporated into various moving bodies such as a car, an airplane, a bike, a bicycle, a robot, or a ship, for example. The movable body is, for example, an apparatus or device that moves on the ground, in the sky, or in the sea, provided with a drive mechanism such as an engine or a motor, a steering mechanism such as a steering wheel or a rudder, and various electronic devices (vehicle devices). FIG. 16 schematically shows a car 206 as an example of a mobile. The vibration device 2 of the present embodiment is incorporated in the automobile 206. The control device 208 performs various control processes based on the clock signal generated by the vibration device 2 and the measured physical quantity information. For example, when distance information of an object around the automobile 206 is measured as physical quantity information, the control device 208 performs various control processes for automatic driving using the measured distance information. The control device 208 controls the hardness of the suspension or controls the brakes of the individual wheels 209 in accordance with, for example, the posture of the vehicle body 207. The device into which the vibration device 2 of the present embodiment is incorporated is not limited to such a control device 208, and can be incorporated into various devices provided on a mobile body such as an automobile 206 or a robot.

  It should be understood by those skilled in the art that although the present embodiment has been described in detail as described above, many modifications can be made without departing substantially from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention. For example, in the specification or the drawings, the terms described together with the broader or synonymous different terms at least once can be replaced with the different terms anywhere in the specification or the drawings. Further, all combinations of the present embodiment and the modifications are also included in the scope of the present invention. In addition, the configuration and operation of the circuit device, the vibration device, the electronic device, and the moving body, and the layout configuration of the circuit device are not limited to those described in the present embodiment, and various modifications can be made.

DESCRIPTION OF SYMBOLS 2: Vibration device, 10, 11, 12, selector: 20: A / D conversion circuit, 21: D / A conversion circuit, 22: comparison circuit, 23: control circuit, 30: quantization error holding circuit, 40: addition Circuits 100: circuit devices 110: vibrators 121: oscillation circuits 122: output circuits 123: processing circuits 124: storage units 125: D / A conversion circuits 127: A / D converters 130: Drive circuit, 141, 142: vibrating piece, 143, 144: drive electrode, 145, 146: detection electrode, 147: ground electrode, 150: oscillation signal generation circuit, 160: detection circuit, 190: processing circuit, 206: automobile (car Moving body) 207 Vehicle body 208 Control device 209 wheels 500 electronic device 510 communication unit 520 processing unit 530 operation unit 540 display unit 550 storage unit AMP Operational amplifier, CAN, CAP: capacitor array circuit, CEN1 to CEN8, CEP1 to CEP8: capacitor (holding capacitor), CFN, CFP: capacitor (feedback capacitor), CHCD: chopping demodulation circuit, CHCM: chopping modulation circuit, D1 , D2 ... direction, DOUT ... A / D conversion result data, HN1 to HN8, HP1 to HP8 ... holding circuit, NSN, NSP ... sampling node, QEHP, QEHN ... quantization error holding circuit, SAD ... successive comparison data, TS1 to TS7: Temperature sensor, VI1 to VIn: Voltage

Claims (12)

An A / D conversion circuit having a charge redistribution type D / A conversion circuit and performing A / D conversion of an input voltage by successive comparison using the D / A conversion circuit;
A quantization error holding circuit holding a charge corresponding to a quantization error in the A / D conversion of the input voltage;
Including
The D / A conversion circuit
A capacitor array circuit on the positive side,
A capacitor array circuit on the negative side,
Have
The A / D conversion circuit
A first input node is connected to the positive side sampling node which is a sampling node of the capacitor array circuit on the positive side, and a second input node is connected to the negative side sampling node which is a sampling node of the capacitor array circuit on the negative side. Have a comparator circuit
The quantization error holding circuit
A positive side quantization error holding circuit whose one end is connected to the positive side sampling node;
A negative side quantization error holding circuit whose one end is connected to the negative side sampling node;
Have
The positive side capacitor array circuit and the negative side capacitor array circuit are disposed along a first direction,
When a direction orthogonal to the first direction is a second direction,
The positive side quantization error holding circuit is disposed on the second direction side of the positive side capacitor array circuit.
The circuit device characterized in that the quantization error holding circuit on the negative electrode side is disposed on the second direction side of the capacitor array circuit on the negative electrode side. In the circuit device according to claim 1,
The comparison circuit is
A circuit device disposed between the capacitor array circuit on the positive electrode side and the capacitor array circuit on the negative electrode side. In the circuit device according to claim 1 or 2,
The A / D conversion circuit
An adder circuit including a positive side input voltage and a negative side input voltage as the input voltage;
The addition circuit
A voltage obtained by adding the input voltage on the positive electrode side and the voltage corresponding to the charge held in the quantization error holding circuit on the negative electrode side is output to the capacitor array circuit on the positive electrode side, and the input voltage on the negative electrode side A circuit device characterized in that a voltage obtained by adding a voltage corresponding to the charge held in the quantization error holding circuit on the positive electrode side is added to the capacitor array circuit on the negative electrode side. In the circuit device according to claim 3,
The addition circuit
The operational amplifier has an inverting input node connected to the other end of the positive side quantization error holding circuit and a non-inverting input node connected to the other side of the negative side quantization error holding circuit.
The operational amplifier is
A circuit device, which is disposed between the quantization error holding circuit on the positive electrode side and the quantization error holding circuit on the negative electrode side. The circuit device according to any one of claims 1 to 4.
A selector for receiving first to nth voltages (n is an integer of 2 or more) and outputting any of the first to nth voltages as the input voltage;
The positive side quantization error holding circuit is
The first to n-th positive electrode side holding circuits for holding charges corresponding to the first to n-th voltages,
The negative side quantization error holding circuit is
A circuit device comprising: first to nth negative electrode side holding circuits for holding charges corresponding to the first to nth voltages. In the circuit device according to claim 5,
The first to nth positive electrode side holding circuits are
Disposed along the second direction,
The first to nth negative electrode side holding circuits are
A circuit device arranged along the second direction. In the circuit device according to claim 5 or 6,
The A / D conversion circuit
The holding circuit on the i-th positive electrode side as a charge corresponding to the quantization error in the A / D conversion of the k-1th (k is an integer of 2 or more) of the i-th voltage (i is an integer of 1 or more and n or less) And the i-th negative electrode side holding circuit is used to perform the k-th A / D conversion on the i-th voltage, and A / D conversion result data in which quantization errors are noise-shaped A circuit device characterized by outputting. The circuit device according to any one of claims 5 to 7.
In the selector, first to mth temperature detection voltages from the first to mth temperature sensors (m is an integer of 1 or more and n or less) are first to fourth of the first to nth voltages. A circuit device characterized in that it is input as a voltage of m. A circuit arrangement according to any one of the preceding claims.
A digital signal processing circuit that outputs frequency control data based on the A / D conversion result data corresponding to the input voltage which is a temperature detection voltage;
An oscillation signal generation circuit that generates an oscillation signal of an oscillation frequency corresponding to the frequency control data using a vibrator;
A circuit device comprising: A circuit arrangement according to any one of the preceding claims.
A vibrator connected to the circuit device;
An oscillating device characterized in that it includes.   An electronic device comprising the circuit device according to any one of claims 1 to 9.   A mobile unit comprising the circuit device according to any one of claims 1 to 9.