JP2015211391A - A/d converter and a/d conversion method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D converter which implements delta sigma modulation in SARADC by reducing influences of a relative error of capacitance, and an A/D conversion method.SOLUTION: A capacitive D/A converter 14 includes a plurality of capacitive elements which are connected to a sample/hold circuit 11 for storing electric charge corresponding to a sampled/held signal Vin, and by switching connections of the plurality of capacitive elements, a comparison signal is generated. A comparator 12 compares the comparison signal with a reference potential VCM. An error feedback section 15 includes a capacitive element 15b, stores a quantization error in the capacitive element 15b as electric charge, and adds the stored electric charge to the electric charge sampled by each capacitive element of the capacitive D/A converter 14 in accordance with an input signal during the next sequential comparing operation. A sequential comparison resistor 13 sequentially stores an output signal of the comparator 12 and outputs an output signal Dout.

Description

  The present invention relates to an AD converter and an AD conversion method, and more particularly to an AD converter and an AD conversion method that realize delta-sigma modulation in a successive approximation AD converter with a configuration that reduces the influence of a relative error in capacitance.

2. Description of the Related Art In recent years, AD converters (analog-digital converters; ADCs) that convert analog signals into digital signals are installed in all electronic devices. In particular, recently, an AD converter called a successive approximation type, which is low-cost and high-performance and has a wide range of product applications, is known.
That is, as one of AD converters (ADC) that convert an analog value into a digital value, a successive approximation AD converter (Successive Application Resistor ADC; SARADC) shown in Non-Patent Document 1 or the like is known.
The demand for accuracy and conversion speed of this type of successive approximation AD converter is increasing year by year. The successive approximation AD converter has a built-in voltage comparator. In order to realize highly accurate A / D conversion by the successive approximation AD converter, it is preferable that the built-in voltage comparator has a high gain and a low offset. In order to realize high-speed A / D conversion, it is preferable that the built-in voltage comparator operates at high speed.

  In the voltage comparator design, there is a trade-off between offset and operating speed. In order to keep the offset small, it is necessary to design a large element size. However, an increase in element size causes an increase in parasitic capacitance. Therefore, there is a problem that it is difficult to increase the speed of the voltage comparator. In addition, there is a problem that designing the element size larger leads to an increase in the core size and thus the chip size. In order to solve these problems, a technique for correcting the offset of the voltage comparator by adding and controlling a correction capacitor is also known.

FIG. 8 is a basic circuit configuration diagram of a conventional successive approximation AD converter. As shown in FIG. 8, the basic configuration of the successive approximation AD converter (SARADC) 50 includes a sample hold circuit 51, a comparator 52, a successive approximation register (SAR) 53, and a DA converter (DAC) 54. Yes.
The difference value between the voltage Vin obtained by sampling and holding the input signal and the voltage D corresponding to the digital output value Dout stored in the SAR 53 output by the DAC 54 is sequentially compared with the reference voltage VCM by the comparator 52. Get the digital output value closest to the signal. Normally, the voltage range of the input signal is equal to the output voltage range of the DAC 54, and the median value of the voltage range is selected as the VCM. For example, when the signal input range is −Vref to + Vref using the reference voltage Vref, VCM = 0V is selected.

This conversion algorithm normally uses binary weighted elements, and in the case of N-bit resolution SARADC, by sequentially converting from the most significant bit, an N-bit digital output value is obtained after N determination cycles. Dout is obtained.
In recent years, a charge redistribution type SARADC using a binary-weighted capacitive DAC (CDAC) as the DA converter 54 has been mainstream, and therefore, SARADC using the CDAC will be described below.
A typical example of the charge redistribution type SARADC is the configuration of FIG. 9 disclosed in Non-Patent Document 2, for example.

FIG. 9 is a basic circuit configuration diagram of the charge redistribution type SARADC described in Non-Patent Document 2. The charge redistribution type SARADC samples the analog input voltage, and compares the sampled analog input voltage with the comparison target voltage generated by the charge redistribution type CDAC from the most significant bit of the DAC digital input signal. Repeat sequentially until the least significant bit. That is, the CDAC has the functions of both the sample hold circuit 51 and the DAC 54 in FIG.
In addition, as disclosed in Patent Document 1, in the configuration of CDAC, a configuration in which the upper bit side and the lower bit side are connected by a coupling capacitor is also known. The thing of this patent document 1 is related with DAC which can produce | generate an analog output level with high precision, even if a parasitic capacitance exists. The configurations illustrated in FIGS. 8 and 9 and Patent Document 1 are described using a single-ended configuration for the sake of simplicity. However, the operation principle is not limited to the single-ended configuration, and the entire difference is easily achieved. Dynamic configuration can be realized.

However, SARADC has a problem that the area of the DAC increases as the number of bits is increased. Since the DAC uses a binary weighted element group, if an element corresponding to the most significant bit is added to increase the bit by one, the area of the DAC is increased approximately twice. On the other hand, if an element corresponding to the least significant bit is added, the expected resolution cannot often be realized due to the influence of the relative error of the element.
Even in the configuration using the coupling capacitance disclosed in Patent Document 1, a control circuit for ensuring the linearity of the DAC is necessary to achieve high resolution, and an increase in area is inevitable.

Thus, in recent years, as shown in Non-Patent Document 3, a configuration has been proposed in which high resolution is realized without increasing the area of the DAC by performing delta-sigma modulation in a conventional SAR ADC.
FIGS. 10A to 10C are circuit configuration diagrams of an ADC that realizes the first-order delta-sigma modulation shown in Non-Patent Document 3. FIG. 10A is a block diagram, and FIG. A specific circuit configuration diagram, FIG. 10 (c) is a timing chart.
The ADC shown in FIG. 10A includes, in addition to the CDAC, the comparator, and the SAR, which are constituent elements of the conventional SARADC, three capacitors CR, CR1, CR2, and a switch SW1, which have the same capacitance value as the operational amplifier. It consists of SW2, SWstart, SWend.

  The outline of the operation of the ADC is as follows. First, the voltage remaining in the CDAC at the end of the conventional SARADC successive approximation operation, which is the SARADC quantization error E, is sampled by the capacitor CR1 or CR2 whose connection is controlled by the switches SW1 and SW2. Subsequently, the common terminal voltage of the CDAC when the next input signal voltage is sampled is set to the previous residual voltage by the operational amplifier and the capacitor CR1 or CR2 and CR which sampled the residual voltage earlier. Subtract. By this operation, a temporal correlation is given to the quantization error, and the quantization error voltage is low in the low frequency region and has high noise shaping characteristics in the high frequency region.

JP 2010-45723 A

“Introduction to Illustrated A / D Converter”, Ohm, p. 99-104 R. Y. -K. Choi and C.I. -Y. Tsui, “A Low Energy Two-step Successful Application Algorithm for ADC design”, Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on. K. Kim, J. et al. Kim, and S.K. H. Cho, “Nth-order multi-Bit ADC using SAR quantizer,” Electron. Lett. , Vol. 46, no. 19, Sep. 2010.

  However, the above-described patent documents and non-patent documents have various problems as described above. In the configuration of Non-Patent Document 3 described above, the quantization error voltage applied when sampling the input signal voltage is determined by the capacitance ratio between the capacitors CR1 and CR or the capacitors CR2 and CR. If the relative accuracy of CR1, CR2, and CR is low, the quantization error in the low frequency region is not sufficiently offset, and there is a problem that it is difficult to increase the resolution. Further, if the areas of the three capacitors CR1, CR2, and CR are increased in order to improve the relative error, an increase in power consumption cannot be avoided in addition to an increase in circuit area.

  The present invention has been made in view of such problems, and an object of the present invention is to provide an AD converter and an AD conversion method that realize delta-sigma modulation in SAR ADC with a configuration that reduces the influence of the relative error of capacitance. It is to provide.

  The present invention has been made to achieve such an object, and the invention according to claim 1 is a charge redistribution type AD conversion including a capacitive DA converter (14, 34a, 34b, 44). The capacitor (10, 30, 40) includes a capacitive element (15b, 35b-1, 35b-2, 45b), and the capacitive element (15b, 35b-1, 35b-2, 45b) using a quantization error as a charge. ), And the stored charge was sampled in each capacitive element (Cs in FIGS. 4 and 7) of the capacitive DA converter (14, 34a, 34b, 44) according to the input signal in the next successive comparison operation. An error feedback unit (15, 35, 45) for adding charges is provided. (FIGS. 1, 3, 4, and 7; Embodiments 1 and 2 and Examples 1 and 2)

  The invention according to claim 2 generates a signal (Vin) obtained by sampling and holding an input signal in a charge redistribution AD converter (10, 30, 40) including a capacitive DA converter (CDAC). A sample-and-hold circuit (11, 31), and a plurality of capacitive elements (Cs in FIGS. 4 and 7) connected to the sample-and-hold circuit (11, 31) and storing charges according to the sample-held signal (Vin). And a capacitor DA converter (14, 34a, 34b, 44) that generates a comparison signal by switching the connection of the plurality of capacitor elements (Cs in FIGS. 4 and 7), and the capacitor DA converter ( 14, 34 a, 34 b, 44), connected to the comparator (12, 32, 42) for comparing the comparison signal with a reference potential (VCM), and to the comparator (12, 32, 42), capacity Having a child (15b, 35b-1, 35b-2, 45b), and storing the quantization error as a charge in the capacitive element (15b, 35b-1, 35b-2, 45b). An error feedback unit (15, 35) that adds the charge sampled in each capacitive element (Cs in FIGS. 4 and 7) of the capacitive DA converter (14, 34a, 34b, 44) according to the input signal during the successive approximation operation. 45) and a successive approximation register (13, 33, 43) for sequentially accumulating the output signals of the comparators (12, 32, 42) and outputting an output signal (Dout). To do.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the error feedback section (15, 35, 45) has an input terminal connected to the capacitive DA converter (14, 34a, 34b, 44), each operational element (15a, 35a, 45a) connected to one end of each capacitive element (Cs in FIGS. 4 and 7), and each capacitive element of the capacitive DA converter (14, 34a, 34b, 44). (Cs in FIGS. 4 and 7) and a first switch (15c-1, 35c-) that allow the capacitive element (15b, 35b-1, 35b-2, 45b) to be connected between one end of the reference voltage terminal and a reference voltage terminal. 1a, 35c-1b, 45c-1) and the capacitive element (15b, 35b-1, 35b-2, 45b) between the input terminal and the output terminal of the operational amplifier (15a, 35a, 45a) The second switch (15c-2, 3 c-2a, 35c-2b, characterized by comprising a 45 c-2) and.

According to a fourth aspect of the present invention, the capacitive DA converter (34a, 34b) and the error feedback unit (35) in the first, second, or third aspect of the present invention have a fully differential configuration. Features. (FIG. 3; Embodiment 2)
The invention according to claim 5 is the invention according to claim 3, further comprising a third switch (45c-3) capable of connecting an input terminal and an output terminal of the operational amplifier (45a). It is characterized by being. (FIG. 7; Example 2)

  According to a sixth aspect of the present invention, in the AD conversion method in the charge redistribution type AD converter (10, 30, 40) including the capacitive DA converter (CDAC), the input signal (Vin) is input to the capacitor. Sampling is performed on each capacitor element (Cs in FIGS. 4 and 7) of the DA converter (14, 34a, 34b, 44), and each capacitor element (Cs in FIGS. 4 and 7) of the capacitor DA converter (14). The voltage of the sampled charge is compared with the reference voltage (VCM), and the operation of connecting the high reference voltage or the low reference voltage to each of the capacitive elements (Cs in FIGS. 4 and 7) is sequentially performed according to the comparison result, A quantization error is stored as a charge in a capacitive element (15b, 35b-1, 35b-2, 45b) connectable between the input terminal and the output terminal of the operational amplifier (15a, 35a, 45a), and a successive comparison operation is performed. When The presence and charge the capacitor DA converter (14,34a, 34b, 44) each capacitive element, characterized in that added to the sampled charge (FIG. 4, Cs in Figure 7).

According to a seventh aspect of the present invention, in the sixth aspect of the present invention, the input signal (Vin) is converted into each capacitive element (FIG. 4, FIG. 4) of the capacitive DA converter (14, 34a, 34b, 44). 7 (Cs), the input terminal and the output terminal of the operational amplifier (15a, 35a, 45a) are short-circuited.
The invention described in claim 8 is characterized in that, in the invention described in claim 6 or 7, the capacitive DA converter (34a, 34b) and the error feedback section (35) are configured to be fully differential. To do.

  ADVANTAGE OF THE INVENTION According to this invention, the AD converter and AD conversion method which implement | achieved the delta-sigma modulation in SARADC by the structure which reduces the influence of the relative error of a capacity | capacitance are realizable.

It is a circuit block diagram for demonstrating Embodiment 1 of the AD converter which concerns on this invention. FIG. 2 is a system equivalent diagram of the AD converter according to the first embodiment illustrated in FIG. 1. It is a circuit block diagram for demonstrating Embodiment 2 of the AD converter which concerns on this invention. 1 is a circuit configuration diagram for explaining a specific example 1 of an AD converter according to the present invention; FIG. FIG. 5 is an operation timing chart of the AD converter shown in FIG. 4. It is a voltage transition diagram of the AD converter which concerns on Example 1 of this invention. It is a circuit block diagram for demonstrating the specific Example 2 of the AD converter which concerns on this invention. It is a basic circuit block diagram of the conventional SARADC. 3 is a basic circuit configuration diagram of a charge redistribution type SARADC described in Non-Patent Document 2. FIG. (A) thru | or (c) are the circuit block diagrams of ADC which implement | achieves the 1st-order delta-sigma modulation shown by the nonpatent literature 3. FIG.

Hereinafter, each embodiment of the present invention will be described with reference to the drawings.
[Embodiment 1]
FIG. 1 is a circuit configuration diagram for explaining Embodiment 1 of the AD converter according to the present invention, and is a circuit configuration diagram in a single-ended configuration of the AD converter. In the figure, reference numeral 10 denotes an AD converter, 11 denotes a sample and hold circuit (S / H), 12 denotes a comparator, 13 denotes a successive approximation register (SAR), 14 denotes a digital / analog converter (DAC), 15 denotes an error feedback unit, Reference numeral 15a denotes an operational amplifier, 15b denotes a capacitive element, and 15c-1 and 15c-2 denote first and second switches.

As the DAC 14, a charge redistribution type SARADC using a binary weighted capacitance DA converter (CDAC) is the mainstream, and hence the SARADC using the CDAC will be described below.
The AD converter 10 shown in FIG. 1 includes an error feedback unit 15 in addition to a sample hold circuit (S / H) 11, a comparator 12, a successive approximation register (SAR) 13, and a DAC 14. In other words, the error feedback unit 15 is added to the configuration of the conventional SARADC shown in FIG. Therefore, the operation other than the error feedback unit 15 is the same as that of the AD converter shown in FIG.

That is, the AD converter 10 according to the first embodiment is a charge redistribution type AD converter including the capacitive DA converter (CDAC) 14. The error feedback unit 15 includes a capacitive element 15b, stores the quantization error as a charge in the capacitive element 15b, and stores the stored charge in each capacitive element (capacitor element of the capacitive DA converter 14 in accordance with an input signal during the next successive comparison operation. The sampled charge is added to Cs) in FIG. 4 to be described later.
Specifically, the following configuration is provided.
The sample hold circuit 11 generates a signal Vin obtained by sampling and holding an input analog signal. The capacitor DA converter 14 is connected to the sample-and-hold circuit 11 and includes a plurality of capacitor elements (Cs in FIG. 4) that store charges corresponding to the sampled and held signal Vin. The comparison signal is generated by switching the connection of Cs).

The comparator 12 is connected to the capacitor DA converter 14 and compares the comparison signal with the reference potential VCM. Further, the error feedback unit 15 is connected to the comparator 12. The successive approximation register (SAR) 13 sequentially accumulates output signals from the comparator 12 and outputs an output signal Dout.
The error feedback unit 15 includes an operational amplifier 15a whose input terminal is connected to one end of each capacitive element (Cs in FIG. 4) of the capacitive DA converter 14, and each capacitive element (in FIG. 4) of the capacitive DA converter 14. Cs) and a first switch 15c-1 enabling connection of the capacitive element 15b between the reference voltage terminal and the first switch 15c-1 enabling connection of the capacitive element 15b between the input terminal and the output terminal of the operational amplifier 15a. 2 switch 15c-2.

Next, the operation of the AD converter according to the first embodiment will be described.
As an initial state, it is assumed that the output of the error feedback unit 15 outputs the same potential as the reference voltage VCM. First, AD conversion is performed by bringing the difference value between the input voltage Vin and the voltage value D corresponding to the digital output value Dout closer to the reference voltage VCM by the successive approximation operation described above. That is, if VCM is used as a reference (VCM = 0), the SAR 13 controls the DAC 14 so that the input voltage Vin and the voltage value D coincide with each other. At this time, when the quantization error E of SARADC is used, the relationship between the input voltage Vin and the voltage value D is expressed by the following equation (1).

即ち、比較器１２の入力電圧ノードＶｘは、次式（２）

That is, the input voltage node Vx of the comparator 12 is expressed by the following equation (2).

と表される。
続いて、この残渣電圧（Ｖｉｎ−Ｄ）を誤差帰還部１５に保存し、次回ＡＤ変換時に入力電圧Ｖｉｎに加算する。この時、遅延演算子としてＺ^−１を用いると、ＳＡＲ１３は、Ｖｉｎ＋（−ＥＺ^−１）とデジタル出力値Ｄｏｕｔに対応した電圧値Ｄを一致させるようにＤＡＣ１４を制御するため、ＡＤ変換後の電圧値Ｄは、次式（３）

It is expressed.
Subsequently, the residual voltage (Vin−D) is stored in the error feedback unit 15 and added to the input voltage Vin at the next AD conversion. At this time, when Z ⁻¹ is used as the delay operator, the SAR 13 controls the DAC 14 so that the voltage value D corresponding to the Vin + (− EZ ⁻¹ ) and the digital output value Dout is matched. The voltage value D is expressed by the following equation (3)

と表される。また、この時、比較器１２の入力電圧ノードＶｘは、次式（４）

It is expressed. At this time, the input voltage node Vx of the comparator 12 is expressed by the following equation (4).

となり、式（２）と同じく−Ｅの電圧となっている。したがって、この残渣電圧を誤差帰還部１５に保存し、次回ＡＤ変換時に入力電圧Ｖｉｎに加算した後にＡＤ変換を行うという変換サイクルにおいて、式（３）は定常的に成立する。この式（３）は一次デルタシグマ変調を示す式として知られており、周波数領域において、量子化誤差Ｅは低域で抑えられ、高域で増大するノイズシェーピング特性を示すことを表している。

Thus, the voltage is -E, as in the equation (2). Therefore, in the conversion cycle in which this residual voltage is stored in the error feedback unit 15 and added to the input voltage Vin at the next AD conversion, and then AD conversion is performed, Equation (3) is constantly established. This expression (3) is known as an expression indicating first-order delta-sigma modulation, and represents that in the frequency domain, the quantization error E is suppressed in a low frequency range and exhibits a noise shaping characteristic that increases in a high frequency range.

FIG. 2 is a system equivalent diagram of the AD converter according to the first embodiment shown in FIG. This system includes a multi-bit ADC 20, a DAC 21 that outputs an analog value D corresponding to the digital output Dout, and a delay device 22.
First, by subtracting the input of the ADC 20 and the output D of the DAC 21, a quantization error E added by AD conversion is taken out. Subsequently, the quantization error stored in the delay unit 22 is subtracted from the input signal Vin of the next AD conversion, so that the quantization error has frequency characteristics. Such a system means that an error feedback type delta-sigma modulation is realized.
In this way, it is possible to realize an AD converter that realizes error feedback type delta-sigma modulation in SARADC with a configuration that reduces the influence of the relative error of capacitance.

[Embodiment 2]
FIG. 3 is a circuit configuration diagram for explaining Embodiment 2 of the AD converter according to the present invention, and is a circuit configuration diagram in a fully differential configuration of the AD converter. In the figure, reference numeral 30 is an AD converter, 31 is a sample hold circuit (S / H), 32 is a comparator, 33 is a successive approximation register (SAR), 34a and 34b are digital / analog converters (DAC), and 35 is error feedback. 35a is an operational amplifier, 35b-1 and 35b-2 are capacitive elements, 35c-1a and 35c-1b are first switches, and 35c-2a and 35c-2b are second switches.

The AD converter 30 according to the second embodiment is a charge redistribution AD converter 30 including capacitive DA converters 34a and 34b. The error feedback unit 35 includes capacitive elements 35b-1 and 35b-2, stores the quantization error as a charge in the capacitive elements 35b-1 and 35b-2, and stores the stored charge as an input signal during the next successive comparison operation. Accordingly, the charge sampled in each capacitive element (Cs in FIG. 4 to be described later) of the capacitive DA converters 34a and 34b is added.
Specifically, the following configuration is provided.
The sample hold circuit 31 generates a signal Vin obtained by sampling and holding an input signal. The capacitive DA converters 34a and 34b are connected to the sample and hold circuit 31 and include a plurality of capacitive elements (Cs in FIG. 4 to be described later) that store charges according to the sampled and held signal Vin. The comparison signal is generated by switching the connection of Cs) in FIG.

The comparator 32 is connected to the capacitor DA converters 34a and 34b, and compares the comparison signal with the reference potential VCM. Further, the error feedback unit 35 is connected to the comparator 32. The successive approximation register 33 sequentially accumulates the output signal of the comparator 32 and outputs an output signal Dout.
The error feedback unit 35 includes an operational amplifier 35a whose input terminal is connected to one end of each capacitive element (Cs in FIG. 4) of the capacitive DA converters 34a and 34b, and each capacitive element of the capacitive DA converters 34a and 34b. Capacitance elements 35b-1 and 35b-2 are connectable between one end of (Cs in FIG. 4) and the reference voltage terminal, and an input terminal and an output of the operational amplifier 35a. Second switches 35c-2a and 35c-2b that allow the capacitive elements 35b-1 and 35b-2 to be connected between the terminals are provided.

As described above, the single-ended configuration is shown in FIG. 1, but it can be easily extended to a fully differential configuration as shown in FIG.
In the AD converter 30 according to the second embodiment, the capacitive DA converters 34a and 34b and the error feedback unit 35 are configured to be fully differential. That is, the AD converter shown in FIG. 3 includes an error feedback unit 35 in addition to a sample hold circuit (S / H) 31, a comparator 32, a successive approximation register (SAR) 33, and DACs 34a and 34b.
Assuming that the reference voltage VCM = 0, if the two output voltages of the sample hold circuit 31 are symmetric with respect to VCM = 0 such as + Vin and −Vin, the configuration shown in FIG. Can be regarded as equivalent to the configuration shown in FIG. Therefore, also in the configuration shown in FIG. 3, the system equivalent diagram is shown in FIG. 2, and error feedback type delta-sigma modulation can be realized.

FIG. 4 is a circuit configuration diagram for explaining a specific example 1 of the AD converter according to the present invention, and is a circuit configuration diagram in a single-ended configuration of the AD converter. In the figure, reference numeral 40 is an AD converter, 42 is a comparator, 43 is a successive approximation register (SAR), 44 is a capacitive digital-to-analog converter (CDAC), 45 is an error feedback unit, 45a is an operational amplifier, 45b is a capacitive element ( Cf), 45c-1, 45c-2 indicate first and second switches.
The AD converter 40 according to the first embodiment is a charge redistribution AD converter including a capacitive DA converter (CDAC) 44 as the DAC 14 in the first embodiment shown in FIG. The error feedback unit 45 includes a capacitive element (Cf) 45b, stores the quantization error as a charge in the capacitive element 45b, and stores the stored charge in each capacitor DA converter 44 in accordance with an input signal in the next successive comparison operation. The electric charge sampled in the capacitive element Cs is added.

Specifically, the following configuration is provided.
The capacitor DA converter 44 includes a plurality of capacitor elements Cs that store charges corresponding to the sampled and held signal Vin as a sample and hold circuit, and generates a comparison signal by switching the connection of the plurality of capacitor elements Cs.
The comparator 42 is connected to the capacitor DA converter 44 and compares the comparison signal with the reference potential VCM. Further, the error feedback unit 45 is connected to the comparator 42. The successive approximation register 43 sequentially accumulates the output signal of the comparator 42 and outputs an output signal Dout.

The error feedback unit 45 includes an operational amplifier 45 a whose input terminal is connected to one end of each capacitive element Cs of the capacitive DA converter 44, one end of each capacitive element Cs of the capacitive DA converter 44, and a reference voltage terminal. A first switch 45c-1 that allows a capacitive element (Cf) 45b to be connected therebetween, and a second switch 45c-2 that allows a capacitive element 45b to be connected between an input terminal and an output terminal of the operational amplifier 45a. I have.
That is, the AD converter 40 shown in FIG. 4 includes a dummy capacitor Cd, a capacitor group Cs having binary weighted capacitors C0 to CN-1, a CDAC 44 having a switch group SWg, a switch SWs, and a capacitor. A comparator 42 that compares the common terminal Vx of the group Cs with a reference potential VCM (for example, 0 V) that is a threshold voltage, and an SAR circuit that sequentially accumulates outputs of the comparator 42 and outputs a multi-bit digital output signal Dout. 43, an operational amplifier 45a, a capacitor Cf, and an error feedback unit 45 having switches SWc and SWt.

In this example, the digital output signal Dout is N bits (N is an integer equal to or greater than 1), and the AD converter 40 converts the analog input voltage VIN into a digital signal of 2 ^N gradations. The values of the dummy capacitor Cd and the capacitors C0 to CN-1 of the capacitor group Cs are 1C, 1C, 2C, 4C, 8C, 16C,..., ^2N- 1C, as shown in the figure. . Here, C means a unit capacity value. The capacitor Cd is a dummy capacitor for converting an analog input voltage into a digital output signal with a resolution of 1 / ^N. However, even if the dummy capacitor Cd is not provided, the capacitor Cd can be divided into ^2N-1 equal parts. Since the resolution is only 1, it may not be provided.

The operational amplifier 45a has a positive input terminal connected to the VCM, a negative input terminal connected to the node Vx, and an output node Vo.
The switch SWs has one end connected to the reference voltage VCM and the other end connected to a node Vx (common terminal of CDAC). The switch SWc has one end connected to the reference voltage VCM and the other end connected to the node Vy. The switch SWt has one end connected to the node Vy and the other end connected to the output node Vo of the operational amplifier 43. Further, one end of each switch group SWg is connected to the capacitance group Cs, and the other end is connected to one of the high reference voltage VRH, the low reference voltage VRL, and the analog input voltage Vin according to a control signal output from the SAR. ing.

FIG. 5 is an operation timing chart of the AD converter shown in FIG.
When the data output frequency of the AD converter is denoted as Fs [Hz], the operation time of one cycle is 1 / Fs = Ts [s]. The operation of one cycle of the AD converter is divided into three phases: a sampling phase φs, a successive approximation phase φc, and an error transfer phase φt. As shown in FIG. 5, the time division is divided so that the total is Ts, for example, φs is Ts / 2, φc is 2Ts / 5, and φt is Ts / 10. Note that there are non-overlap sections φNO so that there is no overlap in these phases, but since they are very small with respect to the entire time of one cycle, the following description will be made ignoring the time of φNO.

Next, a schematic operation of the AD converter according to the first embodiment will be described with reference to FIGS. 4 and 5. For simplicity, VCM = 0, VRH = VREF, and VRL = −VREF.
First, in the sampling phase φs in FIG. 5, all the switch groups SWg in FIG. 4 are connected to the terminals of the analog input voltage Vin, and the switch SWs is turned on to connect the reference potential VCM to the node Vx. At this time, the switches SWt and SWc are non-conductive. As a result, when Cs is the sum of the capacitance values of the dummy capacitor Cd and the capacitors C0 to CN in the capacitance group Cs, the following equation (5)

の電荷がＶｘノード側に蓄積される。すなわち、アナログ入力電圧ＶｉｎがＣＤＡＣ４４の容量群Ｃｓにサンプリングされる。
また、このとき容量Ｃｆには電圧Ｖｆを用いて、次式（６）

Are accumulated on the Vx node side. That is, the analog input voltage Vin is sampled into the capacitance group Cs of the CDAC 44.
At this time, the voltage Vf is used for the capacitance Cf, and the following equation (6)

の電荷がノードＶｘ側に蓄積されているとする。
したがって、サンプリングフェーズφｓでは、ノードＶｘ側に合計で、次式（７）

Is stored on the node Vx side.
Therefore, in the sampling phase φs, the following expression (7) is given in total on the node Vx side.

の電荷が蓄積されており、容量群Ｃｓに対して、｛Ｖｉｎ＋（Ｃｆ／Ｃｓ）・Ｖｆ｝の電圧をサンプリングすることと等価の電荷が蓄積されている。

Are stored, and charges equivalent to sampling the voltage of {Vin + (Cf / Cs) · Vf} are stored in the capacitor group Cs.

Next, when the successive approximation phase φc in FIG. 5 is started, first, the switch SWs is turned off. Subsequently, at the same time as the switch SWc becomes conductive, the switch of the uppermost capacitor CN-1 in the switch group SWg is connected to the high reference voltage VRH side, and the other capacitors Cd, C0 to CN− The second switch is connected to the low reference voltage VRL side. At this time, since the capacitance value connected to the high reference voltage VRH side and the capacitance value connected to the low reference voltage VRL side are equal, weighting with the capacitance value as a weight at each switch side node of the capacitance group Cs The average voltage is VCM = 0.
Thus, assuming that the voltage at the node Vx is Vx2, the total charge Q2 on the node Vx side is expressed by the following equation (8).

となる。
上記式（７）と（８）の電荷は、電荷保存則により等しいので、Ｑ１＝Ｑ２を解くと、次式（９）

It becomes.
Since the charges of the above equations (7) and (8) are equal according to the law of conservation of charge, when Q1 = Q2 is solved, the following equation (9)

を得る。

Get.

This Vx2 is compared with VCM = 0 by the comparator 42, and the switch SWg is operated by the SAR 43 according to the result. When the comparison result is Vx2 <0, since {Vin + (Cf / Cs) · Vf}> 0, the MSB is determined to be 1, and the uppermost capacitor CN-1 remains connected to the high reference voltage VRH side. The capacitor CN-2 (capacitance value 2 ^N-2 C = Cs / 4) is connected to the high reference voltage VRH side, and the next bit is determined.
At this time, the voltage ΔVxp that changes at the node Vx is expressed by the following equation (10).

であるので、この時のノードＶｘの電圧Ｖｘ３は、

Therefore, the voltage Vx3 of the node Vx at this time is

と表される。
一方、Ｖｘ２＞０の場合、｛Ｖｉｎ＋（Ｃｆ／Ｃｓ）・Ｖｆ｝＜０であるので、ＭＳＢは０と決定され、最上位の容量ＣＮ−１を低基準電圧ＶＲＬ側に、容量ＣＮ−２を高基準電圧ＶＲＨ側に接続し、次ビットの判定を行う。
この時、ノードＶｘにおいて変化する電圧ΔＶｘｎは、次式（１２）

It is expressed.
On the other hand, if Vx2> 0, {Vin + (Cf / Cs) · Vf} <0, the MSB is determined to be 0, and the most significant capacitor CN-1 is placed on the low reference voltage VRL side, and the capacitor CN-2 Is connected to the high reference voltage VRH side to determine the next bit.
At this time, the voltage ΔVxn that changes at the node Vx is expressed by the following equation (12).

であるので、この時のノードＶｘの電圧Ｖｘ３は、次式（１３）

Therefore, the voltage Vx3 of the node Vx at this time is expressed by the following equation (13).

と表される。

It is expressed.

By sequentially performing these operations, digital outputs are determined in order from the highest bit, and after N determinations, N-bit digital output values Dout = (δ ₁ , δ ₂ ,..., Δ _N ) are obtained. However, δ _k (k = 1, 2,..., N) is a value determined to be 0 if the kth determination result from the MSB is Vx ≧ 0, and 1 if Vx <0.
The digital output value Dout corresponds to the voltage value D obtained by quantizing the voltage range of −VREF to VREF into 2 ^N equal parts, and the following equation (14)

と表すことができる。
また、この電圧値Ｄは容量群Ｃｓの各スイッチ側のノードにおける電圧値の容量値を重みとした加重平均電圧と見なせる。したがって、｛Ｖｉｎ＋（Ｃｆ／Ｃｓ）・Ｖｆ｝に対して逐次比較動作が行われることを考えると、量子化誤差Ｅを用いれば、次式（１５）

It can be expressed as.
The voltage value D can be regarded as a weighted average voltage weighted by the capacitance value of the voltage value at the node on each switch side of the capacitance group Cs. Therefore, considering that the successive approximation operation is performed on {Vin + (Cf / Cs) · Vf}, if the quantization error E is used, the following equation (15)

の関係として示せる。
したがって、Ｎビット判定後、ノードＶｘの電圧Ｖｘ４は、次式（１６）

It can be shown as a relationship.
Therefore, after determining N bits, the voltage Vx4 of the node Vx is expressed by the following equation (16).

と表される。
すなわち、逐次比較フェーズφｃにおいて、Ｎ回の判定を終え、容量群Ｃｓに接続されたスイッチの接続先を確定したときのノードＶｘ側に蓄積された全容量Ｑ４は、次式（１７）

It is expressed.
That is, in the successive approximation phase φc, the total capacity Q4 accumulated on the node Vx side when N determinations are completed and the connection destination of the switch connected to the capacity group Cs is determined is expressed by the following equation (17).

となり、式（１７）に式（１６）を代入すると、次式（１８）

When substituting equation (16) into equation (17), the following equation (18)

と示すことができる。
続いて、図５における誤差転送フェーズφｔでは、スイッチＳＷｃを非導通状態にした後、スイッチＳＷｔが導通状態となり、ノードＶｘは演算増幅器によりＶＣＭ＝０となる。また、演算増幅器の出力電圧をＶｏと示す。
この時の、ノードＶｘにおける電荷保存則を考えると、次式（１９）

Can be shown.
Subsequently, in the error transfer phase φt in FIG. 5, after the switch SWc is turned off, the switch SWt is turned on, and the node Vx becomes VCM = 0 by the operational amplifier. The output voltage of the operational amplifier is denoted as Vo.
Considering the charge conservation law at the node Vx at this time, the following equation (19)

となり、容量ＣｆにはノードＶｘ側にＣｆ・（０−Ｖｏ）＝Ｃｓ・Ｅの電荷が保存されている。

Thus, a charge of Cf · (0−Vo) = Cs · E is stored in the capacitor Cf on the node Vx side.

Similarly, in the next sampling phase φs, all the switch groups SWg are connected to the terminals of the analog input voltage Vin, the switches SWs are turned on, and the reference potential VCM is connected to the node Vx. At this time, the switches SWt and SWc are non-conductive.
Next, when the successive approximation phase φc starts, first, similarly, the switch SWs is turned off. Subsequently, at the same time as the switch SWc becomes conductive, the switches of the capacitors Cd and C0 to CN-1 in the switch group SWg are connected to the high reference voltage VRH side or the low reference voltage VRL side. At this time, the charge stored as the quantization error E in the capacitor Cf in the error transfer phase φt is added to the charge sampled in the capacitor group Cs.
In the equation (19), Vf is a voltage generated by the electric charge stored in the capacitor Cf at the start of the sampling phase φs. Therefore, when the delay operator Z ⁻¹ corresponding to the cycle Ts [s] is used, (20)

の関係がある。したがって、式（１５）は、式（２０）を用いれば、次式（２１）

There is a relationship. Therefore, the equation (15) can be expressed by the following equation (21) using the equation (20).

となる。この式（２１）は、一次デルタシグマ変調を示す式として知られており、周波数領域において、量子化誤差Ｅは低域で抑えられ、高域で増大するノイズシェーピング特性を示すことを表している。このため、量子化誤差電力の大きい高周波側（例えば、Ｆｓ／３２以上の周波数領域）をデジタル低域通過フィルタにより除去すれば、従来のＳＡＲＡＤＣに比べ高い分解能でＡＤ変換が実現できる。

It becomes. This expression (21) is known as an expression indicating first-order delta-sigma modulation, and represents that in the frequency domain, the quantization error E is suppressed in a low frequency and shows a noise shaping characteristic that increases in a high frequency. . For this reason, if the high frequency side (for example, frequency region of Fs / 32 or more) with a large quantization error power is removed by the digital low-pass filter, AD conversion can be realized with higher resolution than the conventional SARADC.

In the ADC according to the present invention, the quantization error E in the AD conversion of the SARADC is temporarily stored as a charge in the capacitor Cf, and then added to the charge sampled in the capacitor group Cs at the next AD conversion, Delta-sigma modulation is realized by giving temporal correlation to the quantization error. Since the quantization error E is transferred to the next determination as an electric charge, the capacitance Cf is insensitive to the capacitance ratio with the capacitance group Cs, and its area is not limited by the relative error accuracy.
Further, in the configuration of Non-Patent Document 3 shown in FIG. 10, there are three capacitors responsible for charge transfer, CR, CR1, and CR2, but in this configuration, only the capacitor Cf is shown in FIG. Also, it has the advantage of area reduction.
In the present configuration, the configuration as shown in FIG. 4 is shown as the CDAC 40. However, it is sufficient that the charge corresponding to the quantization error E of the ADC remains as a residue by the successive approximation operation. But no problem.
Further, in this configuration, the configuration for realizing the first-order delta-sigma modulation is shown, but the configuration for realizing the n-th order delta-sigma modulation (n is 2 or more) can also be adopted.

FIG. 6 is a voltage transition diagram of the AD converter according to the first embodiment of the present invention, and is a voltage transition diagram of the node Vx in the case of N = 3 bits regarding the operation in the successive approximation phase φc.
Times t1, t2, and t3 are based on the start time of the successive approximation phase φc, and indicate the determination times of the first bit, the second bit, and the third bit, respectively. Further, it is assumed that the settling time for each capacity is sufficiently secured.
For example, a case where {Vin + (Cf / Cs) · Vf} = − (1.6 / 4) · Vref is shown.
First, at the end of the sampling phase φs, the voltage of the node VxVx where VCM = 0 is such that the switch of the uppermost capacitor C2 is connected to the high reference voltage VRH side, and the switches of the other capacitors Cd, C0, C1 are Connected to the low reference voltage VRL side. At this time, the weighted average voltage weighted by the capacitance value at the node on each switch side of the capacitance group Cs is VCM = 0. Therefore, when expressed as β = Cs / (Cs + Cf), Vx is expressed by the equation (5). , −β · {Vin + (Cf / Cs) · Vf} = (1.6 / 4) · β · Vref (> 0), the first bit is 0 and δ1 = 0 is determined. Is done.

Subsequently, in response to the determination of the first bit, the uppermost capacitor C2 is connected to the low reference voltage VRL side and the capacitor C1 is connected to the high reference voltage VRH side, and the next bit is determined. From Equation 8, the voltage of Vx changes by −β · (VREF / 2) and becomes a voltage value of (−0.4 / 4) · β · Vref (<0), so the second bit is 1. It is determined that δ2 = 1.
Further, in response to the determination of the second bit, the capacitor C1 (capacitance value 20C = Cs / 8) is connected to the high reference voltage VRH side while the capacitor C1 is connected to the high reference voltage VRH side, and the next bit is determined. Do. Since the voltage of Vx changes by β · (VREF / 4) and becomes a voltage value of (0.6 / 4) · β · Vref (> 0), the third bit is 0 and δ3 = 0 is determined. Is done.
Finally, upon receiving the determination of the third bit, the capacitor C0 is connected to the low reference voltage VRL side, and the determination for N = 3 bits is completed.
With the above operation, Dout = (0, 1, 0) is determined, and the voltage D corresponding to Dout is expressed by the following equation (22).

となるため、式（１１）より量子化誤差Ｅは、Ｅ＝−（０．４／４）・Ｖｒｅｆと求められる。
以上より本発明によれば、容量の相対誤差の影響を低減する構成でＳＡＲＡＤＣにおけるデルタシグマ変調を実現し、高分解能で小面積のＡＤ変換器を実現することができる。

Therefore, the quantization error E is obtained as E = − (0.4 / 4) · Vref from the equation (11).
As described above, according to the present invention, it is possible to realize delta-sigma modulation in SAR ADC with a configuration that reduces the influence of the relative error of capacitance, and to realize a high-resolution and small-area AD converter.

FIG. 7 is a circuit configuration diagram for explaining a specific example 2 of the AD converter according to the present invention, and is a circuit configuration diagram in a single-ended configuration of the AD converter. Reference numeral 45c-3 (SWs) in the drawing indicates a third switch. In addition, the same code | symbol is attached | subjected to the component which has the same function as FIG.
That is, the AD converter 40 according to the second embodiment further includes the third switch 45c-3 that enables the input terminal and the output terminal of the operational amplifier 45a to be connected.
That is, the AD converter 40 shown in FIG. 7 includes a CDAC 44 having a dummy capacitor Cd, a capacitance group Cs having binary weighted capacitances C0 to CN-1, and a switch group SWg, as in FIG. A comparator 42 that compares a common terminal Vx of the capacitor group Cs with a reference potential VCM (for example, 0 V) that is a threshold voltage, and an SAR circuit that sequentially accumulates outputs of the comparator 42 and outputs a multi-bit digital output signal Dout. 43, an operational amplifier 45a, a capacitor Cf, an error feedback unit 45 having switches SWc and SWt, and a switch SWs.

The connection of the components is the same as in FIG. 4 except for the switch SWs. In FIG. 7, the switch SWs has one end connected to the node Vx and the other end connected to the output node Vo of the operational amplifier 45a.
The operation timing chart of the AD converter shown in FIG. 7 is the same as the operation timing chart of FIG. Hereinafter, a schematic operation of the AD converter according to the second embodiment of the present invention will be described with reference to FIGS. 5 and 7. For simplicity, VCM = 0, VRH = VREF, and VRL = −VREF. The difference between the second embodiment and the first embodiment described above is that when the operational amplifier 45a has low frequency noise Voff such as offset and flicker noise, it has an effect of reducing the influence as an output digital value.

  First, in the sampling phase φs in FIG. 5, all the switch groups SWg in FIG. 7 are connected to the terminals of the analog input voltage VIN, and the switches SWs are turned on to connect the output node of the operational amplifier 45a to the common terminal Vx. At this time, the switches SWt and SWc are non-conductive. When the operational amplifier 45a has low frequency noise such as offset and flicker noise, if the input equivalent noise voltage is Voff, it is equivalent to VCM + Voff = 0 + Voff = Voff being input to the positive input terminal of the operational amplifier 45a. The voltage Vo at the output node is expressed by the following equation (23).

となる。したがって、容量群Ｃｓには、ＣｓをダミーキャパシタＣｄ及び容量Ｃ０〜ＣＮの容量値の総和とした時、次式（２４）

It becomes. Accordingly, in the capacitance group Cs, when Cs is the sum of the capacitance values of the dummy capacitor Cd and the capacitances C0 to CN, the following equation (24)

の電荷がノードＶｘ側に蓄積される。すなわち、アナログ入力電圧Ｖｉｎと入力換算雑音電圧Ｖｏｆｆの差分値がＣＤＡＣ４０の容量群Ｃｓにサンプリングされる。
また、このとき容量Ｃｆには電圧Ｖｆを用いて、次式（２５）

Are accumulated on the node Vx side. That is, the difference value between the analog input voltage Vin and the input converted noise voltage Voff is sampled in the capacitance group Cs of the CDAC 40.
At this time, the voltage Vf is used for the capacitance Cf, and the following equation (25)

の電荷がノードＶｘ側に蓄積されているとする。
したがって、サンプリングフェーズφｓでは、ノードＶｘ側に合計で、次式（２６）

Is stored on the node Vx side.
Therefore, in the sampling phase φs, the following expression (26) is given in total on the node Vx side.

の電荷が蓄積されており、容量群Ｃｓに対して、｛Ｖｉｎ＋（Ｃｆ／Ｃｓ）・Ｖｆ−Ｖｏｆｆ｝の電圧をサンプリングすることと等価の電荷が蓄積されている。

Are stored, and charges equivalent to sampling the voltage of {Vin + (Cf / Cs) · Vf−Voff} are stored in the capacitor group Cs.

Next, when the successive approximation phase φc in FIG. 5 is started, first, the switch SWs is turned off. Subsequently, at the same time as the switch SWc becomes conductive, the switch of the uppermost capacitor CN-1 in the switch group SWg is connected to the high reference voltage VRH side, and the other capacitors Cd, C0 to CN− The second switch is connected to the low reference voltage VRL side.
Thus, assuming that the voltage at the node Vx is Vx2a, the total charge Q2a on the node Vx side is expressed by the following equation (27)

となる。
上記式（２６）と（２７）の電荷は、電荷保存則により等しいので、Ｑ１ａ＝Ｑ２ａを解くと、次式（２８）

It becomes.
Since the charges in the equations (26) and (27) are equal according to the law of conservation of charge, when Q1a = Q2a is solved, the following equation (28)

を得る。

Get.

The voltage Vx2a is compared with Vc = 0 by the comparator 42, and the switch group SWg is operated by the SAR 43 according to the result. When the comparison result is Vx2a <0, since {Vin + (Cf / Cs) · Vf−Voff}> 0, the MSB is determined to be 1, and the switch of the uppermost capacitor CN-1 is set to the high reference voltage VRH side. The capacitor CN-2 (capacitance value 2 ^N-2 C = Cs / 4) is connected to the high reference voltage VRH side while being connected, and the next bit is determined.
By sequentially performing the above operations, the digital output is determined in order from the highest bit, and after N determinations, N-bit digital output values Dout = (δ ₁ , δ ₂ ,..., Δ _N ) are obtained. However, δ _k (k = 1, 2,..., N) is a value determined to be 0 if the kth determination result from the MSB is Vx ≧ 0, and 1 if Vx <0.
The digital output value Dout corresponds to a voltage value D obtained by quantizing the voltage range of −VREF to VREF into 2 ^N equal parts, and the following equation (29)

と表すことができる。
また、この電圧値Ｄは、容量群Ｃｓの各スイッチ側のノードにおける電圧値の容量値を重みとした加重平均電圧と見なせる。したがって、｛Ｖｉｎ＋（Ｃｆ／Ｃｓ）・Ｖｆ−Ｖｏｆｆ｝に対して逐次比較動作が行われることを考えると、量子化誤差Ｅを用いれば、次式（３０）

It can be expressed as.
The voltage value D can be regarded as a weighted average voltage weighted by the capacitance value of the voltage value at each switch-side node of the capacitance group Cs. Therefore, considering that the successive approximation operation is performed on {Vin + (Cf / Cs) · Vf−Voff}, if the quantization error E is used, the following equation (30)

の関係として示せる。
したがって、Ｎビット判定後、ノードＶｘの電圧Ｖｘ４ａは、次式（３１）

It can be shown as a relationship.
Therefore, after determining N bits, the voltage Vx4a of the node Vx is expressed by the following equation (31).

と表される。
すなわち、逐次比較フェーズφｃにおいて、Ｎ回の判定を終え、容量Ｃ１に接続されたスイッチの接続先を確定したときのノードＶｘ側に蓄積された全容量Ｑ４ａは、次式（３２）

It is expressed.
That is, in the successive approximation phase φc, the total capacity Q4a accumulated on the node Vx side when the determination of N times is finished and the connection destination of the switch connected to the capacity C1 is determined is expressed by the following equation (32).

となり、式（３２）に式（３１）を代入すると、次式（３３）

When substituting equation (31) into equation (32), the following equation (33)

と示すことができる。

Can be shown.

Subsequently, in the error transfer phase φt, after the switch SWc is turned off, the switch SWt is turned on. At this time, the node Vx becomes VCM + Voff = 0 + Voff = Voff by the operational amplifier 45a. The output voltage of the operational amplifier 45a is denoted as Voa.
Considering the charge conservation law at the node Vx at this time, the following equation (34)

となり、容量ＣｆにはノードＶｘ側にＣｆ・（Ｖｏｆｆ−Ｖｏａ）＝Ｃｓ・（Ｅ−Ｖｏｆｆ）の電荷が保存されている。式（３０）において、Ｖｆはサンプリングフェーズφｓ開始時に容量Ｃｆに保存されていた電荷による電位であるので、周期Ｔｓ［ｓ］に対応する遅延演算子Ｚ^−１と周期Ｔｓ／２［ｓ］に対応する遅延演算子Ｚ^−１／２を用いると、式（３４）におけるＥはＥ・Ｚ^−１、ＶｏｆｆはＶｏｆｆ・Ｚ^−１／２と変換されることに注意すると、Ｖｆは次式（３５）

Thus, a charge of Cf · (Voff−Voa) = Cs · (E−Voff) is stored in the capacitor Cf on the node Vx side. In Expression (30), Vf is a potential due to the charge stored in the capacitor Cf at the start of the sampling phase φs, so that the delay operator Z ⁻¹ corresponding to the period Ts [s] and the period Ts / 2 [s] Note that using the corresponding delay operator Z ^−1/2 , E in Equation (34) is converted to E · Z ⁻¹ , and Voff is converted to Voff · Z ^−1/2. 35)

と表すことができる。したがって、式（３０）は、式（３５）を用いれば、次式（３６）

It can be expressed as. Therefore, the expression (30) can be expressed by the following expression (36) using the expression (35).

となる。したがって、以上の動作により量子化誤差Ｅに対して１次デルタシグマ変調がなされたうえに、演算増幅器４５ａに由来するオフセット及びフリッカノイズなどの低域ノイズ（入力換算雑音電圧Ｖｏｆｆ）もまた抑制される。量子化誤差Ｅは低域で抑えられ、高域で増大するノイズシェーピング特性を示すため、量子化誤差電力の大きい高周波側（例えば、Ｆｓ／３２以上の周波数領域）をデジタル低域通過フィルタにより除去すれば、従来のＳＡＲＡＤＣに比べ高い分解能でＡＤ変換が実現できることを意味する。

It becomes. Therefore, the first-order delta-sigma modulation is performed on the quantization error E by the above operation, and low-frequency noise (input equivalent noise voltage Voff) such as offset and flicker noise derived from the operational amplifier 45a is also suppressed. The Since the quantization error E is suppressed in the low frequency range and exhibits noise shaping characteristics that increase in the high frequency range, the high frequency side (for example, the frequency region of Fs / 32 or higher) where the quantization error power is large is removed by the digital low pass filter. This means that AD conversion can be realized with higher resolution than the conventional SARADC.

  In the ADC according to the present invention, the quantization error E in the AD conversion of the SARADC is temporarily stored as a charge in the capacitor Cf, and then the input voltage Vin is added to the charge sampled in the capacitor group Cs at the next AD conversion. The quantization error is correlated with time to realize delta-sigma modulation. Since the quantization error E is transferred to the next determination as an electric charge, the capacitance Cf is insensitive to the capacitance ratio with the capacitance group Cs, and its area is not limited by the relative error accuracy. Further, in the configuration of Non-Patent Document 3 shown in FIG. 10, there are three capacitors responsible for charge transfer, CR, CR1, and CR2, but in this configuration, only the capacitor Cf is shown in FIG. Also, it has the advantage of area reduction.

In this configuration, the configuration as shown in FIG. 7 is shown as the CDAC 44. However, as in the first embodiment described above, it is sufficient that the charge corresponding to the quantization error E of the ADC remains as a residue by the successive approximation operation. The configuration of the CDAC as in Patent Document 1 has no problem.
Further, in this configuration, the configuration for realizing the first-order delta-sigma modulation is shown, but the configuration for realizing the n-th order delta-sigma modulation (n is 2 or more) can also be adopted.
As described above, according to the present invention, low-frequency noise such as offset and flicker noise derived from the operational amplifier 45a, and delta-sigma modulation in SAR ADC are realized with a configuration that reduces the influence of the relative error of capacitance, and high resolution and small area are achieved. AD converter can be realized.

Next, the AD conversion method of the present invention will be described.
The AD conversion method of the present invention is an AD conversion method that realizes error feedback type delta-sigma modulation in a charge redistribution type AD converter including a capacitive DA converter (CDAC).
First, the input signal Vin is sampled into each capacitive element (Cs in FIGS. 4 and 7) of the capacitive DA converters 14, 34a, 34b, and 44.
Next, the voltage based on the charge sampled in each capacitive element (Cs in FIGS. 4 and 7) of the capacitive DA converters 14, 34a, 34b, and 44 is compared with the reference voltage VCM.

Next, an operation of connecting a high reference voltage or a low reference voltage to each capacitor (Cs in FIGS. 4 and 7) is sequentially performed based on the comparison result.
Next, the quantization error is stored as electric charges in the capacitive elements 15b, 35b-1, 35b-2, 45b that can be connected between the input terminals and the output terminals of the operational amplifiers 15a, 35a, 45a.
Next, when the successive approximation operation is performed, the stored charge is added to the charge sampled in each capacitive element (Cs in FIGS. 4 and 7) of the capacitive DA converters 14, 34a, 34b, and 44.
Further, when the input signal Vin is sampled to the capacitive elements (Cs in FIGS. 4 and 7) of the capacitive DA converters 14, 34a, 34b, 44, the input terminals and output terminals of the operational amplifiers 15a, 35a, 45a are connected. Short circuit.
In addition, the capacitive DA converters 34a and 34b and the error feedback unit 35 can be configured to be fully differential.
In this way, it is possible to realize an AD conversion method that realizes error feedback delta-sigma modulation in SARADC with a configuration that reduces the influence of the relative error of capacitance.

10, 30, 40 AD converter 11, 31, 51 Sample hold circuit (S / H)
12, 32, 42, 52 Comparator 13, 33, 43, 53 Successive approximation register (SAR)
14, 34a, 34b, 54 Digital-to-analog converter (DAC)
15, 35, 45 Error feedback units 15a, 35a, 45a Operational amplifiers 15b, 35b-1, 35b-2, 45b Capacitance elements (Cf)
15c-1, 35c-1a, 35c-1b, 45c-1, first switch 15c-2, 35c-2a, 35c-2b, 45c-2 second switch 20 multi-bit ADC
21 DAC
22 Delay device 44 Capacitance DA converter (CDAC)
50 SARADC

Claims (8)

In a charge redistribution type AD converter having a capacitive DA converter,
A capacitor element is included, and the quantization error is stored in the capacitor element as a charge, and the stored charge is added to the sampled charge in each capacitor element of the capacitor DA converter in accordance with an input signal in the next successive comparison operation. An AD converter comprising an error feedback unit. In a charge redistribution type AD converter having a capacitive DA converter,
A sample-and-hold circuit that generates a signal obtained by sampling and holding an input signal;
A capacitor DA converter connected to the sample and hold circuit, including a plurality of capacitive elements for storing charges according to the sampled and held signal, and generating a comparison signal by switching connection of the plurality of capacitive elements;
A comparator connected to the capacitive DA converter for comparing the comparison signal with a reference potential;
A capacitor is connected to the comparator, and a quantization error is stored in the capacitor as a charge, and the stored charge is stored in each capacitor of the capacitor DA converter in accordance with an input signal in the next successive comparison operation. An error feedback unit for adding to the sampled charge;
An AD converter comprising: a successive approximation register that sequentially accumulates output signals of the comparator and outputs an output signal. The error feedback unit is
An operational amplifier having an input terminal connected to one end of each capacitive element of the capacitive DA converter;
A first switch that enables connection of the capacitive element between one end of each capacitive element of the capacitive DA converter and a reference voltage terminal;
The AD converter according to claim 1, further comprising: a second switch that allows the capacitive element to be connected between an input terminal and an output terminal of the operational amplifier.   4. The AD converter according to claim 1, wherein the capacitive DA converter and the error feedback unit are configured to be fully differential. 5.   The AD converter according to claim 3, further comprising a third switch capable of connecting an input terminal and an output terminal of the operational amplifier. In an AD conversion method in a charge redistribution type AD converter having a capacitive DA converter,
Sampling the input signal to each capacitive element of the capacitive DA converter,
Comparing the voltage due to the charge sampled in each capacitive element of the capacitive DA converter with a reference voltage, and sequentially performing an operation of connecting a high reference voltage or a low reference voltage to each capacitive element according to the comparison result,
The quantization error is stored as a charge in a capacitive element that can be connected between the input terminal and the output terminal of the operational amplifier.
An AD conversion method comprising: adding a stored charge to a charge sampled in each capacitor element of the capacitive DA converter when performing a successive approximation operation.   7. The AD conversion method according to claim 6, wherein the input terminal and the output terminal of the operational amplifier are short-circuited when the input signal is sampled in each capacitive element of the capacitive DA converter.   The AD conversion method according to claim 6, wherein the capacitive DA converter and the error feedback unit are configured to be fully differential.

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