JP2012044347A - Integrated circuit device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit device that performs a precise analog-to-digital (A/D) conversion of a signal corresponding to a difference between a first signal and a second signal when a channel signal of a sensor device is composed of the first signal and the second signal.SOLUTION: An integrated circuit device includes: an amplifier circuit where a first signal SG1 from a sensor device is input during a first duration, a second signal SG2 which forms a pair with the first signal SG1 to make up a channel signal of the sensor device is input during a second duration, and a signal corresponding to a difference between the first signal SG1 and the second signal SG2 is output; and an A/D converter that performs A/D conversion for an output signal of the amplifier circuit. The amplifier circuit comprises a switched capacitor circuit that cancels offset voltage of an operational amplifier of the amplifier circuit.

Description

  The present invention relates to an integrated circuit device, an electronic device, and the like.

  In recent years, motion sensors such as gyro sensors and acceleration sensors have attracted attention. By using such a motion sensor, for example, camera shake correction or intuitive operation input in a game machine can be realized. As a prior art of an apparatus that receives a detection signal from such a sensor device and performs A / D conversion processing and filter processing, there is a technology disclosed in Patent Document 1, for example.

  By the way, in the gyro sensor or the acceleration sensor, an angular velocity (or angular acceleration) or acceleration detection signal is output as a DC voltage detection voltage signal. Then, the application side integrates the angular velocity and acceleration obtained from the detected voltage signal by software processing, and obtains the angle, velocity, distance, and the like.

  However, the DC voltage level of the detection voltage signal from the gyro sensor or the acceleration sensor has a DC offset due to process variation or the like. Therefore, if the detected voltage signal having such a DC offset is integrated as described above to obtain the angle, speed, and distance, the error becomes very large.

  In this regard, in the above-described prior art of Patent Document 1, a plurality of amplifiers, a plurality of offset adjustment registers, and a plurality of D / A converters are provided to cancel the offset voltage of the operational amplifier.

  However, the technique of providing offset cancellation by providing a plurality of D / A converters and the like in this way has a problem that the integrated circuit device becomes large-scale and the load of offset adjustment processing becomes excessive. In particular, in order to perform offset adjustment with high accuracy, it is necessary to increase the number of bits of the D / A converter, which leads to further enlargement of the integrated circuit device.

JP 2009-20829 A

  According to some aspects of the present invention, when the channel signal from the sensor device is constituted by the first and second signals, the A / D with high accuracy of the signal corresponding to the difference between the first and second signals An integrated circuit device and an electronic device that can realize conversion can be provided.

  In one embodiment of the present invention, a first signal from a sensor device is input in a first period, and a second signal that forms a pair of the first signal and forms a channel signal of the sensor device is input in a second period. An amplifier circuit that outputs a signal corresponding to a difference between the first signal and the second signal, and an A / D converter that performs A / D conversion on the output signal of the amplifier circuit, The present invention relates to an integrated circuit device configured by a switched capacitor circuit that cancels an offset voltage of an operational amplifier included in the amplifier circuit.

  According to one embodiment of the present invention, the first signal and the second signal from the sensor device are input by the amplifier circuit in the first period and the second period, respectively. These first signal and second signal are paired to form a channel signal of the sensor device. The amplifier circuit outputs a signal corresponding to the difference between the first signal and the second signal, and the A / D converter performs A / D conversion on the output signal. In one embodiment of the present invention, the amplifier circuit is configured by a switched capacitor circuit that cancels the offset voltage of the operational amplifier. Therefore, it is possible to reduce a measurement error due to the offset voltage of the operational amplifier being superimposed on the signal corresponding to the difference between the first signal and the second signal. Therefore, when the channel signal from the sensor device is composed of the first and second signals, it is possible to realize highly accurate A / D conversion of the signal corresponding to the difference between the first and second signals.

  In one embodiment of the present invention, the amplifier circuit is provided between the operational amplifier, a first input node of the operational amplifier in which an analog ground voltage is set at a second input node, and a node of the analog ground voltage. An offset canceling capacitor may be provided that stores charge corresponding to the offset voltage of the operational amplifier.

  In this way, by storing (accumulating) the charge corresponding to the offset voltage of the operational amplifier in the offset canceling capacitor, the offset voltage is superimposed on the signal corresponding to the difference between the first signal and the second signal. Can reduce the measurement error.

  In the aspect of the invention, the amplifier circuit may include a sampling capacitor provided between an input node of the amplifier circuit and the first input node of the operational amplifier.

  According to this configuration, the charge corresponding to the voltage applied to the input node of the amplifier circuit is stored in the sampling capacitor and the charge corresponding to the offset voltage is stored in the offset canceling capacitor. An offset cancel function can be realized.

  In the aspect of the invention, the offset canceling capacitor may be provided between the first input node and the first node of the operational amplifier, and the amplifier circuit may include the first node and the analog ground voltage. A first switching element that is turned on in the first period and turned off in the second period, and is provided between the first node and the output node of the operational amplifier, A second switching element that is turned off in the first period and turned on in the second period; and is provided between the output node and the first input node of the operational amplifier, and is turned on in the first period. And a third switch element that is turned off in the second period may be included.

  In this way, a voltage follower-connected operational amplifier is realized by turning on the third switch element in the first period. Then, when the first signal is input to one end of the sampling capacitor in the first period, the charge corresponding to the differential voltage between the voltage of the first signal and the voltage obtained by adding the offset voltage to the analog ground voltage is used for sampling. It will be accumulated in the capacitor. Further, when the first switch element is turned on in the first period, the first node is set to the analog ground voltage, and the charge corresponding to the offset voltage can be stored in the offset canceling capacitor. In the second period, the second signal is input to one end of the sampling capacitor and the second switch element is turned on, so that a signal corresponding to the difference between the first signal and the second signal can be output to the output node. It becomes like this.

  In one embodiment of the present invention, the amplifier circuit is provided between the output node of the operational amplifier and the output node of the amplifier circuit, and is turned off in the first period and turned on in the second period. The fourth switch element may be included.

  In this way, the fourth switch element is turned off in the first period, thereby disconnecting the electrical connection between the output node of the operational amplifier and the output node of the amplifier circuit, and the fourth switch element in the second period. When the element is turned on, the voltage at the output node of the operational amplifier can be output as the output voltage of the amplifier circuit.

  In the aspect of the invention, the offset canceling capacitor may be composed of a plurality of unit capacitors for adjusting the gain of the amplifier circuit.

  By doing so, the gain of the amplifier circuit can be variably adjusted by setting the connection / non-connection of the plurality of unit capacitors constituting the offset canceling capacitor.

  In one embodiment of the present invention, the amplifier circuit corresponds to a difference between the first signal and the second signal with respect to an analog ground voltage that is a center voltage in an A / D conversion range of the A / D converter. A voltage signal obtained by adding the voltages to be output may be output.

  In this way, even when the detection signal of the sensor device is transmitted by the differential voltage between the first signal and the second signal, the A / D conversion range is set to a wide range centered on the analog ground voltage, A / D conversion can be performed.

  In one aspect of the present invention, a first channel first signal constituting a first channel signal of the sensor device and a second channel first signal constituting a second channel signal of the sensor device are input. A first multiplexer that outputs the first channel first signal as a first signal in a first channel measurement period, and outputs the second channel first signal as the first signal in a second channel measurement period; The first channel second signal constituting the first channel signal and the second channel second signal constituting the second channel signal are input, and the first channel is input during the first channel measurement period. A second multi signal that outputs the second signal as the second signal and outputs the second channel second signal as the second signal in the second channel measurement period. The first signal from the first multiplexer is input to the amplifier circuit during the first period of the first channel measurement period and the second channel measurement period, and the amplifier circuit includes the lexer. The second signal from the second multiplexer may be input during the second period of the second channel measurement period.

  Thus, in one aspect of the present invention, the first channel first signal is output from the first multiplexer and the first channel second signal is output from the second multiplexer in the first channel measurement period. The amplifier circuit outputs a signal corresponding to the difference between the first channel first signal and the first channel second signal, and the A / D converter performs A / D conversion of the output signal. On the other hand, in the second channel measurement period, the second channel first signal is output from the first multiplexer, and the second channel second signal is output from the second multiplexer. The amplifier circuit outputs a signal corresponding to the difference between the second channel first signal and the second channel second signal, and the A / D converter performs A / D conversion on the output signal.

  In this way, when the signal of each channel is composed of the first and second signals, the signal corresponding to the difference between the first and second signals of each channel is A / D converted in a time division manner. It becomes like this. Therefore, A / D conversion of a signal corresponding to the difference between the first and second signals can be realized with a small circuit scale.

  In one aspect of the present invention, a signal from a second sensor device and an output signal from the amplifier circuit are input and a third multiplexer that outputs a third signal is included, and the A / D converter includes You may perform A / D conversion about the said 3rd signal from a 3rd multiplexer.

  In this way, not only the signal from the sensor device but also the signal from the second sensor device can be A / D converted in a time division manner.

  In the aspect of the invention, the first multiplexer receives a third channel first signal that constitutes a third channel signal from the sensor device, and the third channel first signal is input during a third channel measurement period. 1 signal is output as the first signal, and the second multiplexer receives the third channel second signal constituting the signal of the third channel from the sensor device, and in the third channel measurement period, The third channel second signal is output as the second signal, and the amplifier circuit includes the first channel measurement period, the second channel measurement period, and the third channel measurement period in the first period of the third channel measurement period. The first signal from one multiplexer is input, the first channel measurement period, the second channel measurement period, and the third channel measurement. Said second signal from said second multiplexer in the second period between may be input.

  According to this configuration, in the third channel measurement period, the third channel first signal is output from the first multiplexer, the third channel second signal is output from the second multiplexer, and the third channel first signal is output. A / D conversion of the signal corresponding to the difference between the signal and the second signal of the third channel is performed.

  In the aspect of the invention, the third multiplexer receives the fourth channel signal, the fifth channel signal, and the sixth channel signal from the second sensor device, and in the fourth channel measurement period, The fourth channel signal is output as the third signal, the fifth channel signal is output as the third signal in the fifth channel measurement period, and the sixth channel signal is output in the sixth channel measurement period. May be output as the third signal.

  In this way, in the first channel measurement period to the third channel measurement period, the signal corresponding to the difference between the first and second signals from the sensor device is A / D converted in a time division manner, and the fourth channel measurement period In the sixth channel measurement period, the signal from the second sensor device can be A / D converted in a time division manner.

  In one embodiment of the present invention, the sensor device is a gyro sensor device, the second sensor device is an acceleration sensor device, the signal of the first channel from the gyro sensor device, the signal of the second channel, The signal of the third channel is an angular velocity or angular acceleration detection signal around the X axis, an angular velocity or angular acceleration detection signal around the Y axis, an angular velocity or angular acceleration detection signal around the Z axis, and the acceleration sensor The fourth channel signal, the fifth channel signal, and the sixth channel signal from the device are an X axis direction acceleration detection signal, a Y axis direction acceleration detection signal, and a Z axis direction acceleration detection signal, respectively. It may be.

  If it does in this way, about the 1st and 2nd signal which constitutes the angular velocity or angular acceleration detection signal from a 3 axis gyro sensor, the difference signal will be generated in an amplifier circuit, and A / D converter will perform A / D Can be converted. On the other hand, the acceleration detection signal from the triaxial acceleration sensor can be directly input to the A / D converter and A / D converted. Therefore, it is possible to provide a measurement system suitable for a 6-axis motion sensor including a 3-axis gyro sensor and a 3-axis acceleration sensor.

  In the aspect of the invention, the first channel first signal is a signal of a first detection voltage of the first channel, and the first channel second signal is a reference of the first detection voltage. The second channel first signal is a second detection voltage signal of the second channel, and the second channel second signal is a reference of the second detection voltage. It may be a signal of two reference voltages.

  In this way, since the differential voltage between the detection voltage of each channel and the reference voltage can be A / D converted, high-precision measurement can be realized even if the reference voltage differs between channels.

  In one aspect of the present invention, the first channel first signal and the first channel second signal are a first differential signal in a balanced relationship with a predetermined voltage level as a reference, and the second channel first signal The signal and the second channel second signal may be a second differential signal in a balanced relationship with a predetermined voltage level as a reference.

  In this way, even when the signal of each channel is a differential signal, high-precision measurement can be realized.

  Another aspect of the invention relates to an electronic device including any one of the integrated circuit devices described above.

2 is a basic configuration example of an integrated circuit device of the present embodiment. 2A and 2B are configuration examples of an amplifier circuit configured by a switched capacitor circuit. Operation | movement explanatory drawing of the amplifier circuit comprised by a switched capacitor circuit. The modification of the amplifier circuit comprised by a switched capacitor circuit. 1 is a detailed first configuration example of an integrated circuit device according to an embodiment; Operation | movement explanatory drawing of a 1st structural example. 6 shows a detailed second configuration example of the integrated circuit device of the present embodiment. Operation | movement explanatory drawing of a 2nd structural example. FIG. 9A to FIG. 9C are explanatory diagrams of first and second signals constituting each channel signal. FIG. 10A is an explanatory diagram of the operation of the amplifier circuit, and FIG. 10B is an example in which the first and second signals constituting each channel signal are differential signals. The detailed 3rd structural example of the integrated circuit device of this embodiment. Operation | movement explanatory drawing of a 3rd structural example. Detailed operation explanatory view of the present embodiment. A configuration example in the case of sharing a sampling switch element and a multiplexer switch element. 1 is a configuration example of an electronic device including an integrated circuit device according to an embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration Example FIG. 1 shows a basic configuration example of an integrated circuit device (circuit device) of this embodiment. This integrated circuit device includes an amplifier circuit AMP and an A / D converter ADC.

  A channel signal from the sensor device 10 is composed of a first signal SG1 and a second signal SG2. That is, the first signal SG1 and the second signal SG2 are paired to form a channel signal of the sensor device 10, and a physical quantity detection signal detected by the sensor device 10 is transmitted.

  The first signal SG1 from the sensor device 10 is input to the amplifier circuit AMP in the first period T1. In addition, the second signal SG2 that forms a pair with the first signal SG1 and constitutes the channel signal of the sensor device 10 is input in the second period T2. The amplifier circuit AMP outputs a signal AMQ corresponding to the difference (difference voltage) between the first signal SG1 and the second signal. Here, the signal corresponding to the difference between the first and second signals SG1 and SG2 is the difference signal itself between the first and second signals SG1 and SG2, or a signal obtained by multiplying the difference signal by a gain. Other circuit elements such as a multiplexer described later may be interposed between the sensor device 10 and the amplifier circuit AMP or between the amplifier circuit AMP and the A / D converter ADC.

  The A / D converter ADC performs A / D conversion on the output signal AMQ of the amplifier circuit AMP. Here, the A / D conversion for the output signal AMQ is A / D conversion of the signal AMQ itself directly output from the amplifier circuit AMP, or A / D via other circuit elements such as a multiplexer from the amplifier circuit AMP. For example, A / D conversion of a signal input to the converter ADC.

  As the A / D converter ADC, for example, a successive approximation A / D converter (for example, 10 to 16 bits) can be employed. The successive approximation type A / D converter includes, for example, a comparison circuit, a successive approximation register, and a D / A converter, and performs A / D conversion on a signal obtained by sampling (sample / hold) an input signal by successive approximation operation. To output digital data. As the A / D converter ADC, an A / D converter other than the successive approximation type can be adopted.

  FIG. 2A shows a configuration example of the amplifier circuit AMP. The amplifier circuit AMP is configured by a switched capacitor circuit that cancels the offset voltage of the operational amplifier OP included in the amplifier circuit AMP. Here, the offset voltage of the operational amplifier OP is an input conversion offset voltage, for example, an offset voltage between the first and second input nodes NI1 and NI2 of the operational amplifier OP.

  Note that the amplifier circuit AMP of the present embodiment is not limited to the configuration shown in FIG. 2A, and various components such as omitting some of the components, adding other components, and changing the connection relationship thereof. Can be implemented.

  The amplifier circuit AMP in FIG. 2A includes an operational amplifier OP and an offset canceling capacitor COF. The offset canceling capacitor COF has a first input node NI1 (inverted input node) of an operational amplifier OP (voltage-follower-connected operational amplifier) whose analog input voltage AGND is set at the second input node NI2 (non-inverted input node). And the ANGD node. Then, charges corresponding to the offset voltage of the operational amplifier OP are stored (accumulated). Specifically, one end of the capacitor COF is connected to the first input node NI1 and to the output node NPQ of the operational amplifier OP via the switch element SW3. On the other hand, the other end of the capacitor COF is connected to the AGND node via the switch element SW1.

  The second input node (non-inverting input node) of the operational amplifier OP is set to the analog ground voltage AGND. By doing so, as shown in FIG. 10A described later, the amplifier circuit AMP makes the first and second signals with respect to the analog ground voltage AGND serving as the center voltage VCT of the A / D conversion range RAD. Thus, it is possible to output a voltage signal obtained by adding the difference voltages.

  The amplifier circuit AMP includes a sampling capacitor CS provided between the input node NI of the amplifier circuit AMP and the first input node NI1 of the operational amplifier OP. Specifically, one end of the sampling capacitor CS is connected to the first input node NI1 of the operational amplifier OP, and the other ends of the sampling capacitor CS are the first sampling switch element SWS1 and the second sampling switch element SWS2. Connected to the other end. The first signal SG1 and the second signal SG2 are input to one ends of the first sampling switch element SWS1 and the second sampling switch element SWS2, respectively.

  As shown in FIG. 2A, the offset canceling capacitor COF is provided between the first input node NI1 and the first node NOF of the operational amplifier OP. The amplifier circuit AMP further includes a first switch element SW1, a second switch element SW2, and a third switch element SW3.

  The first switch element SW1 is provided between the first node NOF and the node of the analog ground voltage AGND. The first switch element SW1 is turned on in the first period T1, and is turned off in the second period T2.

  The second switch element SW2 is provided between the first node NOF and the output node NPQ of the operational amplifier OP. The second switch element SW2 is turned off in the first period T1 and turned on in the second period T2.

  The third switch element SW3 is provided between the output node NPQ and the first input node NI1 of the operational amplifier OP. The third switch element SW3 is turned on in the first period T1, and is turned off in the second period T2.

  The amplifier circuit AMP includes a fourth switch element SW4. The fourth switch element SW4 is provided between the output node NPQ of the operational amplifier OP and the output node NQ of the amplifier circuit AMP. The fourth switch element SW4 is turned off in the first period T1, and turned on in the second period T2.

  The switch elements SW1 to SW4, SWS1, and SWS2 are realized by, for example, CMOS transistors (N-type transistors), transfer gates, and the like. In this embodiment, the case where the period following the first period T1 is the second period T2 will be described as an example. However, the period following the second period T2 may be the first period T1.

  FIG. 3 is a signal waveform diagram for explaining the operation of the amplifier circuit AMP. In FIG. 3, the H level of the signal indicates that the corresponding switch element is on, and the L level of the signal indicates that the corresponding switch element is off.

  2A shows the on / off state of each switch element in the first period T1, which is the sampling period of the switched capacitor circuit, and FIG. 2B shows the hold period (output period). The ON / OFF state of each switch element in the second period T2 is shown.

  As shown in FIGS. 2A and 3, in the first period T1, the switch elements SWS1, SW1, and SW3 are turned on, and the switch elements SWS2, SW2, and SW4 are turned off. When the switch elements SWS1 and SW1 are turned on, a charge corresponding to a differential voltage between the voltage of the signal SG1 and the voltage obtained by adding the offset voltage of the operational amplifier OP to the analog ground voltage AGND is accumulated in the capacitor CS. When the switch element SW3 is turned on, the operational amplifier OP becomes a so-called voltage follower connection, and charges corresponding to the offset voltage of the operational amplifier OP are accumulated in the capacitor COF. Further, when the switch element SW4 is turned off, the connection between the output node NPQ of the operational amplifier OP and the output node NQ of the amplifier circuit AMP is cut off.

  As shown in FIGS. 2B and 3, in the second period T2, the switch elements SWS2, SW2, and SW4 are turned on, and the switch elements SWS1, SW1, and SW3 are turned off. When the switch elements SWS2, SW2, and SW4 are turned on, a voltage obtained by adding the differential voltage between the signals SG1 and SG2 to the analog ground voltage AGND is output to the output node NQ of the amplifier circuit AMP.

  For example, in FIG. 2A, the voltages of the signals SG1 and SG2 are represented as VQ and VR, respectively, and the capacitance values of the capacitors CS and COF are represented as C1 and C2. Further, the offset voltage of the operational amplifier OP is represented as VOF, and the analog ground voltage is represented as AGND.

  Then, in the first period T1 in FIG. 2A, the potential of the node NI becomes VQ, the potential of the node NI1 becomes AGND + VOF, and the potential of the node NOF becomes AGND. Therefore, the electric charges Q1 and Q2 accumulated in the capacitors CS and COF are expressed by the following expressions (1) and (2).

Q1 = C1. (VQ-AGND-VOF) (1)
Q2 = -C2 · VOF (2)
On the other hand, the output voltage of the node NQ in the second period T2 in FIG. Then, in the second period T2, the potential of the node NI becomes VR, the potential of the node NI1 becomes AGND + VOF, and the potential of the node NOF becomes VPQ. Accordingly, the electric charges Q1 ′ and Q2 ′ accumulated in the capacitors CS and COF are expressed by the following equations (3) and (4).

Q1 '= C1. (VR-AGND-VOF) (3)
Q2 ′ = C2 · (VPQ−AGND−VOF) (4)
Then, the following equation (5) is established by the law of charge conservation.

Q1 + Q2 = Q1 ′ + Q2 ′ (5)
Then, the following expression (6) is obtained by substituting the above expressions (1) to (4) into the above expression (5).

VPQ = (C1 / C2). (QV-VR) + AGND (6)
Therefore, as shown in FIG. 10A described later, the voltage VDF = (C1 / C2) · (QV−VR) corresponding to the difference between the signals SG1 and SG2 is set to AGND at the output node NQ of the amplifier circuit AMP. The added voltage VPQ is output.

  Further, as apparent from the above equation (6), the offset voltage VOF of the operational amplifier OP is canceled and does not appear in the output voltage VPQ. Therefore, a so-called offset-free amplifier circuit AMP can be realized.

  That is, in the above-described prior art of Patent Document 1, a plurality of D / A converters and a plurality of offset adjustment registers are required to cancel the offset voltage of an operational amplifier or the like, which increases the circuit scale. is there. In particular, in order to increase the accuracy of measurement, the number of bits of the D / A converter becomes large, which leads to further scale-up of the circuit. Further, the conventional technique has a problem that the offset cancellation process becomes complicated and the processing load of the control unit becomes excessive.

  In this regard, according to the amplifier circuit AMP having the configuration of FIG. 2A, the offset voltage of the operational amplifier OP is canceled by analog processing. By canceling the offset voltage of the operational amplifier OP in this way, the output voltage VPQ, which is the measurement voltage, is also highly accurate, and the sensor output can be measured with high accuracy. Further, since a D / A converter and an offset adjustment register are not required, the circuit scale can be greatly reduced and power saving can be realized. In addition, there is an advantage that high-precision measurement is possible without using a D / A converter having a large number of bits.

  In particular, when the sensor device 10 has a large number of channels, it is effective to use an amplifier circuit AMP of a switched capacitor circuit as shown in FIG. That is, by using a switched capacitor circuit having an offset cancel function as the amplifier circuit AMP, signals of a plurality of channels can be measured with high accuracy in a time division manner. Further, it is not necessary to provide an amplifier circuit corresponding to each channel as in the prior art, and it is only necessary to provide one amplifier circuit AMP. Therefore, the circuit can be reduced in size and power consumption can be realized. Further, the control processing of the control unit 50 can be performed only by switching the signal selection of a multiplexer, which will be described later, and the operation control of the amplifier circuit AMP and the A / D converter ADC, so that the processing load of the control unit 50 can be reduced.

  Note that the configuration of the amplifier circuit AMP of the present embodiment is not limited to that shown in FIG. 2A. For example, various modifications can be made to the connection configuration of the switch element and the capacitor.

  For example, FIG. 4 shows a modification of the amplifier circuit AMP configured by a switched capacitor circuit. In this modification, the gain GA of signal amplification of the amplifier circuit AMP can be adjusted by adjusting the capacitor ratio CR = C1 / C2 in the above equation (6).

  In FIG. 4, the sampling capacitor CS of FIG. 2A is composed of a plurality of unit capacitors CS1, CS2, CS3, and CS4. These unit capacitors CS1 to CS4 are connected in parallel between the input node NI of the amplifier circuit AMP and the first input node NI1 of the operational amplifier OP.

  In FIG. 4, the offset canceling capacitor COF in FIG. 2A is also composed of a plurality of unit capacitors COF1, COF2, COF3, and COF4. That is, the offset canceling capacitor COF includes a plurality of unit capacitors COF1 to COF4 for adjusting the gain GA of the amplifier circuit AMP. These unit capacitors COF1 to COF4 are connected in parallel between the first input node NI1 and the node NOF of the operational amplifier OP. The gain GA of the amplifier circuit AMP is variably adjusted by setting the connection / disconnection of the unit capacitors COF1 to COF4 between the first input node NI1 and the node NOF. Specifically, gain switching switch elements SL11 and SL12 are provided at both ends of the unit capacitor COF1. Similarly, switch elements SL21 and SL22 for switching the gain, switch elements SL31 and SL32, and switch elements SL41 and SL42 are provided at both ends of the unit capacitors COF2, COF3, and COF4, respectively.

  For example, the unit capacitors CS1 to CS4 and COF1 to COF4 in FIG. 4 are set to the same capacitance value C. Accordingly, the capacitance value of the sampling capacitor CS constituted by the unit capacitors CS1 to CS4 is C1 = 4C.

  In FIG. 4, the switch elements SL11 and SL12, SL21 and SL22 are on, and the switch elements SL31 and SL32, SL41 and SL42 are off. Therefore, the capacitance value of the offset canceling capacitor COF is C2 = 2C. Therefore, the capacitor ratio CR = C1 / C2 = 4C / 2C = 2 in the above equation (6). Accordingly, the signal amplification gain of the amplifier circuit AMP is set to GA = 2.

  As described above, in the modification of FIG. 4, the gain GA of the signal amplification of the amplifier circuit AMP can be variably adjusted by setting the switch elements SL11 to SL42 on / off.

2. First Configuration Example FIG. 5 shows a detailed first configuration example of the integrated circuit device (circuit device) of this embodiment. This integrated circuit device includes a first multiplexer MUX1, a second multiplexer MUX2, an amplifier circuit AMP, and an A / D converter ADC.

  The signal of the first channel CH1 is composed of a first channel first signal VQ1 and a first channel second signal VR1. That is, the VQ1 and VR1 signals are paired to form the CH1 signal. Similarly, the signal of the second channel CH2 includes a second channel first signal VQ2 and a second channel second signal VR2. In other words, the CH2 signal is formed by pairing the VQ2 and VR2 signals. As will be described later, the number of channels is not limited to two, and may be three or more.

  Here, the first channel first signal VQ1 and the first channel second signal VR1 are signals output from the first channel CH1 of the sensor device. The second channel first signal VQ2 and the second channel second signal VR2 are signals output from the second channel CH2 of the sensor device. For example, when the sensor device detects a physical quantity (for example, acceleration) on each coordinate axis of a plurality of coordinate axes or a physical quantity (for example, angular velocity, angular acceleration) around each coordinate axis, the physical quantity detected around each coordinate axis or each coordinate axis The signal shown is output as a signal for each channel.

For example, as will be described later, the first channel first signal VQ1 is a signal of the first detection voltage (first sensor detection voltage) of the channel CH1, and the first channel second signal VR1 is a reference of the first detection voltage. The first reference voltage signal. The second channel first signal VQ2 is a signal of the second detection voltage (second sensor detection voltage) of the channel CH2, and the second channel second signal VR2 is a second reference voltage serving as a reference for the second detection voltage. Signal. Note that the signals VQ1 and VR1 are first differential signals in a balanced relationship with a predetermined voltage level (center voltage) as a reference, and the signals VQ2 and VR2 are in a second relationship in a balanced relationship with a predetermined voltage level as a reference. These signals VQ1, VR1, VQ2, and VR2 may be differential signals. The signals VQ1, VR1, VQ2, and VR2 are output from the sensor device and input into the integrated circuit device through terminals (pads) of the integrated circuit device. It should be noted that other circuit elements (for example, a circuit element of a passive filter described later) may be interposed between the sensor device and the integrated circuit device.

  The first multiplexer MUX1 receives the first channel first signal VQ1 constituting the signal of the first channel CH1 and the second channel first signal VQ2 constituting the signal of the second channel CH2, and receives the first signal SG1. Output. Specifically, in the first channel measurement period, the first channel first signal VQ1 is output as the first signal SG1. On the other hand, in the second channel measurement period, the second channel first signal VQ2 is output as the first signal SG1.

  The second multiplexer MUX2 receives the first channel second signal VR1 constituting the signal of the first channel CH1 and the second channel second signal VR2 constituting the signal of the second channel CH2, and receives the second signal SG2. Output. Specifically, in the first channel measurement period, the first channel second signal VR1 is output as the second signal SG2. On the other hand, in the second channel measurement period, the second channel second signal VR2 is output as the second signal SG2.

  The amplifier circuit AMP receives the first signal SG1 from the first multiplexer MUX1 and the second signal SG2 from the second multiplexer MUX2. Then, a signal AMQ corresponding to the difference (difference voltage) between the first signal SG1 and the second signal SG2 is output. Here, the signal corresponding to the difference between the first and second signals SG1 and SG2 is the difference signal itself between the first and second signals SG1 and SG2, or a signal obtained by multiplying the difference signal by a gain.

  The A / D converter ADC performs A / D conversion on the output signal AMQ of the amplifier circuit AMP. Here, A / D conversion for the output signal AMQ means A / D conversion of the signal AMQ itself directly output from the amplifier circuit AMP, or A / D from the amplifier circuit AMP through other circuit elements such as other multiplexers. For example, A / D conversion of a signal input to the converter ADC.

  FIG. 6 is an explanatory diagram of the operation of the integrated circuit device of FIG. As shown in FIG. 6, in the first channel measurement period TCH1, the first channel first signal VQ1 is selected by the multiplexer MUX1, and is output to the amplifier circuit AMP as the first signal SG1. Further, the multiplexer MUX2 selects the first channel second signal VR1 and outputs it to the amplifier circuit AMP as the second signal SG2.

  On the other hand, in the second channel measurement period TCH2, the multiplexer MUX1 selects the second channel first signal VQ2, and outputs the first signal SG1 to the amplifier circuit AMP. Also, the second channel second signal VR2 is selected by the multiplexer MUX2, and is output to the amplifier circuit AMP as the second signal SG2.

  Specifically, the first signal SG1 from the multiplexer MUX1 is input to the amplifier circuit AMP in the first period T1 of the first channel measurement period TCH1 and the second channel measurement period TCH2. That is, as shown in FIG. 6, SG1 = VQ1 is input to the amplifier circuit AMP in the first period T1 of the first channel measurement period TCH1. In addition, SG1 = VQ2 is input in the first period T1 of the second channel measurement period TCH2.

  Further, the second signal SG2 from the multiplexer MUX2 is input to the amplifier circuit AMP in the second period T2 of the first channel measurement period TCH1 and the second channel measurement period TCH2. That is, as shown in FIG. 6, SG2 = VR1 is input to the amplifier circuit AMP in the second period T2 of the first channel measurement period TCH1. SG2 = VR2 is input in the second period T2 of the second channel measurement period TCH2.

  As described above, in the integrated circuit device of the present embodiment, the multiplexer MUX1 is used for the first signals VQ1 and VQ2 (for example, the positive voltage side signal of the detection voltage signal or the differential signal) constituting the signals of the channels CH1 and CH2. The signal SG1 is input to the amplifier circuit AMP. On the other hand, the second signals VR1 and VR2 (for example, the negative side signal of the reference voltage signal or the differential signal) constituting the signals of the channels CH1 and CH2 are input to the amplifier circuit AMP as the signal SG2 via the multiplexer MUX2. Is done.

  Then, in the first channel measurement period, the amplifier circuit AMP receives the signals VQ1 and VR1, and outputs a signal corresponding to the difference between VQ1 and VR1 to the A / D converter ADC. On the other hand, in the second channel measurement period, the signals VQ2 and VR2 are input, and a signal corresponding to the difference between VQ2 and VR2 is output to the A / D converter ADC.

  In this way, when the signals of each channel are composed of a pair of first and second signals, the first signal is input to the amplifier circuit AMP via the multiplexer MUX1, and the second signal is The signal can be input to the amplifier circuit AMP via the multiplexer MUX2. Then, the differential signal between the first signal and the second signal can be generated by the amplifier circuit AMP and input to the A / D converter ADC. In this case, the difference signal between the first and second signals of the first channel is input to the A / D converter ADC in the first channel measurement period, and the difference signal of the first and second signals of the second channel is input. Can be input to the A / D converter ADC in the second channel measurement period, and the difference signal can be input to the A / D converter ADC in a time division manner. Therefore, when the signal of each channel is composed of the first and second signals, A / D conversion of the signal corresponding to the difference between the first and second signals can be realized with a small circuit scale.

3. Second Configuration Example FIG. 7 shows a detailed second configuration example of the integrated circuit device of this embodiment. In the second configuration example, a gyro sensor device is used as the sensor device 10. As the gyro sensor, it is possible to adopt an angular velocity sensor such as a vibration type that detects angular velocity from Coriolis force due to rotation of the vibrator, an angular acceleration sensor that detects angular acceleration from changes in capacitance and inertial force, etc. .

  In FIG. 7, an angular velocity (or angular acceleration) detection signal around the X axis, an angular velocity (or angular acceleration) detection signal around the Y axis, and an angular velocity (or angular acceleration) detection signal around the Z axis are: The detection voltage signals VQ1, VQ2, and VQ3 of the channels CH1, CH2, and CH3 are output from the sensor device 10, respectively. Further, reference voltage signals VR1, VR2, and VR3 that are reference voltages for the detection voltage signals VQ1, VQ2, and VQ3 of CH1, CH2, and CH3 are output from the sensor device 10.

  The signals VQ1 and VR1 of CH1, the signals VQ2 and VR2 of CH2, and the signals VQ3 and VR3 of CH3 are input from the sensor device 10 into the integrated circuit device through terminals (pads) of the integrated circuit device. In FIG. 7, a passive low-pass filter including a resistor R11 and a capacitor C11, and a passive resistor including a resistor R12 and a capacitor C12 are respectively provided between the terminals VQ1 and VR1 of the integrated circuit device and the channel CH1 of the sensor device 10. A low-pass filter is provided. A passive low-pass having the same configuration is also provided between the terminals of the integrated circuit device VQ2 and VR2 and the terminal of the channel CH2 of the sensor device 10, and between the terminals of VQ3 and VR3 of the integrated circuit device and the terminal of the channel CH3 of the sensor device 10. A filter is provided. Each of these low-pass filters (anti-alias filters) is constituted by, for example, a resistor and a capacitor that are external components of the integrated circuit device.

  As shown in FIG. 7, the integrated circuit device of the second configuration example includes multiplexers MUX1 and MUX2, an amplifier circuit AMP, an A / D converter ADC, a control unit 50, and a power supply circuit 60. The control unit 50 includes a digital filter 52. The integrated circuit device of the present embodiment is not limited to the configuration shown in FIG. 7, and various modifications such as omitting some of the components or adding other components are possible.

  The difference between the first configuration example in FIG. 5 and the second configuration example in FIG. 7 is that the number of channels is two in FIG. 5 whereas the number of channels is three in FIG.

  Specifically, the multiplexer MUX1 in FIG. 7 includes the signal of the channel CH3 in addition to the first channel first signal VQ1 and the second channel first signal VQ2 constituting the signals of the channels CH1 and CH2 from the sensor device 10. The third channel first signal VQ3 that constitutes is input. The multiplexer MUX1 outputs the third channel first signal VQ3 as the first signal SG1 in the third channel measurement period.

  The multiplexer MUX2 includes a third channel that constitutes a signal of the channel CH3 in addition to the first channel second signal VR1 and the second channel second signal VR2 that constitute the signals of the channels CH1 and CH2 from the sensor device 10. The second signal VR3 is input. The multiplexer MUX2 outputs the third channel second signal VR3 as the second signal SG2 in the third channel measurement period.

  The amplifier circuit AMP receives the signals SG1 and SG2, and outputs a signal AMQ corresponding to the difference between these signals to the A / D converter ADC. The A / D converter ADC performs A / D conversion of the signal AMQ and outputs the obtained digital data DQ to the control unit 50.

  The controller 50 performs various digital processes based on the digital data DQ from the A / D converter ADC. Specifically, the digital filter 52 of the control unit 50 performs digital filter processing based on the digital data DQ. The function of the control unit 50 can be realized by a logic circuit such as a gate array (G / A).

  The digital filter 52 performs low-pass filter processing with a cutoff frequency equal to or lower than ½ of the sampling frequency of the A / D converter ADC, and removes signals of frequency components other than the frequency component of the desired signal. For example, when the A / D converter ADC is sampling at a frequency of 1 kHz, the digital filter 52 performs a low-pass filter process with a cutoff frequency of 250 Hz or 125 Hz, for example. By performing the low-pass filter processing in the integrated circuit device in this way, it becomes possible to reduce the processing load of a subsequent microcomputer (MCU) connected to the integrated circuit device.

  The control unit 50 controls each circuit block in the integrated circuit device. For example, the control unit 50 outputs control signals SCAM and SCAD to control the amplifier circuit AMP and the A / D converter ADC. Control signals SCM1 and SCM2 are output to control signal selection in the multiplexers MUX1 and MUX2.

  The power supply circuit 60 generates a power supply voltage VDDA for analog circuits and an analog ground voltage AGND (analog reference voltage). The power supply circuit 60 can include, for example, a reference voltage generation circuit that generates a reference voltage and a regulator that generates the power supply voltage VDDA based on the generated reference voltage. The regulator also includes a voltage divider circuit provided between the output node of the power supply voltage VDDA of the power supply circuit 60 and the VSS node (low potential side power supply node), and a reference voltage supplied to the first input node. An operational amplifier may be included in which the voltage from the voltage fine adjustment tap is supplied to the second input node. The analog ground voltage AGND can be generated based on the voltage from the analog ground tap of the voltage dividing circuit.

  The amplifier circuit AMP and the A / D converter ADC operate based on the power supply voltage VDDA supplied from the power supply circuit 60. The amplifier circuit AMP is a voltage obtained by adding a voltage corresponding to the difference between the first and second signals SG1 and SG2 to the analog ground voltage AGND serving as the center voltage of the A / D conversion range of the A / D converter ADC. The signal is output as signal AMQ.

  FIG. 8 is an operation explanatory diagram of the second configuration example. As shown in FIG. 8, in the first channel measurement period TCH1, signals VQ1 and VR1 are selected by the multiplexers MUX1 and MUX2, respectively, and are output as signals SG1 and SG2 to the amplifier circuit AMP. In the second channel measurement period TCH2, the signals VQ2 and VR2 are selected by the multiplexers MUX1 and MUX2, respectively, and are output as signals SG1 and SG2 to the amplifier circuit AMP. Further, in the third channel measurement period TCH3, the signals VQ3 and VR3 are selected by the multiplexers MUX1 and MUX2, respectively, and are output to the amplifier circuit AMP as the signals SG1 and SG2.

  Specifically, as shown in FIG. 8, the amplifier circuit AMP includes a first channel measurement period TCH1, a second channel measurement period TCH2, and a first channel T1 from the multiplexer MUX1 in the first period T1 of the third channel measurement period TCH3. 1 signal SG1 is input. That is, as shown in FIG. 8, SG1 = VQ1 is input to the amplifier circuit AMP in the first period T1 of the first channel measurement period TCH1, and SG1 = VQ2 is set in the first period T1 of the second channel measurement period TCH2. In the first period T1 of the third channel measurement period TCH3, SG1 = VQ3 is input.

  As shown in FIG. 8, the amplifier circuit AMP includes a second signal SG2 from the multiplexer MUX2 in the second channel T2 of the first channel measurement period TCH1, the second channel measurement period TCH2, and the third channel measurement period TCH3. Is entered. That is, as shown in FIG. 8, SG2 = VR1 is input to the amplifier circuit AMP in the first period T2 of the first channel measurement period TCH1, and SG2 = VR2 is set in the second period T2 of the second channel measurement period TCH2. In the second period T2 of the third channel measurement period TCH3, SG2 = VR3 is input.

  FIG. 9A is an explanatory diagram showing the relationship between the signals VQ1 and VQ2 and the signals VR1 and VR2. As shown in the figure, the first channel first signal VQ1 is a signal of the first detection voltage of the channel CH1, and the first channel second signal VR1 is a signal of the first reference voltage serving as a reference of the first detection voltage. It is. The second channel first signal VQ2 is a signal of the second detection voltage of the second channel, and the second channel second signal VR2 is a signal of the second reference voltage serving as a reference for the second detection voltage. The relationship between the third channel first signal VQ3 and the third channel second signal VR3 is also the same.

  In the following description, the detection voltages indicated by the signals VQ1, VQ2, and VQ3 are appropriately expressed as detection voltages VQ1, VQ2, and VQ3, and the reference voltages indicated by the signals VR1, VR2, and VR3 are appropriately set to the reference voltage VR1, It is written as VR2 and VR3.

  The sensor device 10 in FIG. 7 includes an X-axis sensor that detects an angular velocity around the X-axis, a Y-axis sensor that detects an angular velocity around the Y-axis, and a Z-axis sensor that detects an angular velocity around the Z-axis. That is, these independent X-axis sensor, Y-axis sensor, and Z-axis sensor are mounted in one package (housing). The X-axis sensor outputs signals VQ1 and VR1 of channel CH1, the Y-axis sensor outputs signals VQ2 and VR2 of channel CH2, and the Z-axis sensor outputs signals VQ3 and VR3 of channel CH3.

  The angular velocity around the X axis is represented by a differential voltage VDF1 between the detection voltage VQ1 and the reference voltage VR1, and the angular velocity around the Y axis is represented by a differential voltage VDF2 between the detection voltage VQ2 and the reference voltage VR2. The same applies to the angular velocity around the Z axis.

  In this case, the X-axis, Y-axis, and Z-axis sensors are composed of independent sensor units, so the reference voltage (analog ground voltage of each sensor unit) serving as a reference for the detection voltage varies depending on the process. The voltage becomes different because of the above. For example, in FIG. 9A, the reference voltage VR1 of the channel CH1 is lower than the reference voltage VR2 of the channel CH2, and a voltage difference ΔVR exists between VR1 and VR2.

  For example, FIG. 9B shows a configuration example of each sensor for the X axis, the Y axis, and the Z axis. Each sensor includes a vibrator 310 (physical quantity transducer in a broad sense), a drive circuit 320, and a detection circuit 330. The detection circuit 330 includes an amplification circuit 332, a synchronous detection circuit 334, and a filter unit 336. Then, the drive circuit 320 drives the vibrator 310 with the drive signal, and the detection signal from the vibrator 310 is input to the amplification circuit (QV conversion circuit) 332 of the detection circuit 330. The synchronous detection circuit 334 performs synchronous detection on the output signal of the amplifier circuit 332 based on the synchronous signal from the drive circuit 320 and extracts a desired signal. Then, the filter unit 336 performs low-pass filter processing for removing unnecessary signals, and outputs a signal of the detection voltage VQ (VQ1, VQ2, VQ3) and a signal of the reference voltage VR (VR1, VR2, VR3).

  Here, as shown in FIG. 9C, the detection voltage VQ is a DC voltage proportional to the angular velocity (dps). For example, the higher the angular velocity, the higher the voltage of VQ.

  The X-axis, Y-axis, and Z-axis sensors in FIG. 7 output the detection voltage and the reference voltage as a pair, and as shown in FIG. 9C, the difference voltage between the detection voltage and the reference voltage is It represents the magnitude of the angular velocity.

  Therefore, the multiplexer MUX1 in FIG. 7 selects the detection voltages VQ1, VQ2, and VQ3 and outputs them to the amplifier circuit AMP in each measurement period of the channels CH1, CH2, and CH3 as shown in FIG. Further, the multiplexer MUX2 selects the reference voltages VR1, VR2, and VR3 and outputs them to the amplifier circuit AMP in each measurement period of the channels CH1, CH2, and CH3. Then, the amplifier circuit AMP generates differential voltages of VDF1 = VQ1-VR1, VDF2 = VQ2-VR2, and VDF3 = VQ3-VR3 in the measurement periods of the channels CH1, CH2, and CH3, respectively, and the A / D converter Output to ADC.

  As described above, according to this embodiment, even when each of the X-axis, Y-axis, and Z-axis sensors in FIG. 7 outputs the detection voltage and the reference voltage as a pair, the difference voltage between the detection voltage and the reference voltage. Can be appropriately A / D converted by the A / D converter ADC. Therefore, as shown in FIG. 9A, even when the reference voltage is different between channels, measurement with high accuracy can be realized.

According to this embodiment, even when the sensor device 10 outputs a 3-channel signal, it is not necessary to provide three amplifier circuits, and only one amplifier circuit AMP is provided. That is, the number of amplifier circuits AMP can be reduced by performing time division processing using the multiplexers MUX1 and MUX2. As a result, the circuit scale of the integrated circuit device can be greatly reduced, and both improvement in detection accuracy and downsizing of the integrated circuit device can be achieved. In FIG. Voltage AGND is supplied. As shown in FIG. 10A, the analog ground voltage AGND is the center voltage VCT of the A / D conversion range RAD of the A / D converter ADC. Here, the upper limit voltage of the A / D conversion range RAD is the power supply voltage VDDA, and the lower limit voltage is the low potential side power supply voltage VSS (= 0 V).

  The amplifier circuit AMP outputs a voltage signal AMQ obtained by adding a voltage VDF (difference voltage between the detection voltage and the reference voltage) corresponding to the difference between the signals SG1 and SG2 to the analog ground voltage AGND that is the center voltage VCT.

  In this way, even when the angular velocity detection signal is transmitted by the differential voltage between the detection voltage and the reference voltage, the A / D conversion range RAD is set to a wide range centering on AGND, and the differential voltage is set to A / D. D conversion is possible. As a result, the A / D conversion of the angular velocity detection signal that makes the best use of the dynamic range of the A / D converter ADC becomes possible, and the detection accuracy can be improved.

  In the above, the case where the first and second signals output from each channel of the sensor device 10 are a detection voltage signal and a reference voltage signal as shown in FIG. 9A has been described. The embodiment is not limited to this. For example, as shown in FIG. 10B, the first signal and the second signal may be differential signals VP and VN that are in a balanced relationship with a predetermined voltage level (center voltage) as a reference. That is, the first signal may be a positive signal constituting a differential signal, and the second signal may be a negative signal constituting a differential signal. Taking FIG. 7 as an example, the first channel first signal VQ1 and the first channel second signal VR1 are first differential signals in a balanced relationship with reference to a predetermined voltage level, and the second channel first signal VQ2 and the second channel second signal VR2 may be a second differential signal in a balanced relationship with a predetermined voltage level as a reference. The same applies to the signals VQ3 and VR3.

  Thus, even when the first and second signals are differential signals, multiplexers MUX1 and MUX2 are provided, the amplifier circuit AMP outputs a differential voltage, and the A / D converter ADC performs A / D conversion. This makes it possible to achieve both improvement in detection accuracy and downsizing of the integrated circuit device.

4). Third Configuration Example FIG. 11 shows a detailed third configuration example of the integrated circuit device of this embodiment. In the third configuration example, a gyro sensor device is used as the sensor device 10, and an acceleration sensor device is used as the sensor device 20 (second sensor device). As an acceleration sensor, a capacitive sensor that detects a change in position at a movable part supported by a beam structure as a change in capacitance, or a piezoresistive sensor that detects a change in position of a diaphragm by a piezoresistive element Or a gas temperature distribution type sensor can be used. The sensor device 10 and the sensor device 20 may be integrally mounted in the same package (housing), or may be mounted in different packages.

  In the third configuration example of FIG. 11, a third multiplexer MUX3 is further provided to measure a signal from such a sensor device 20 (acceleration sensor). The third multiplexer MUX3 receives the signals VQ4, VQ5, and VQ6 from the sensor device 20 (second sensor device) and the output signal AMQ from the amplifier circuit AMP, and outputs a third signal SG3. The A / D converter ADC performs A / D conversion on the third signal SG3 from the third multiplexer MUX3.

  Specifically, the signal VQ4 of the fourth channel CH4, the signal VQ5 of the fifth channel CH5, and the signal VQ6 of the sixth channel CH6 from the sensor device 20 are input to the third multiplexer MUX3. The third multiplexer MUX3 outputs the signal VQ4 of the fourth channel CH4 as the third signal SG3 during the fourth channel measurement period, and the signal VQ5 of the fifth channel CH5 as the third signal SG3 during the fifth channel measurement period. Output as. In the sixth channel measurement period, the signal of the sixth channel CH6 is output as the third signal SG3.

  When the sensor device 20 is an acceleration sensor device as shown in FIG. 11, the signal VQ4 of the fourth channel CH4, the signal VQ5 of the fifth channel CH5, and the signal VQ6 of the sixth channel CH6 from the sensor device 20 are respectively The acceleration detection signal in the X-axis direction, the acceleration detection signal in the Y-axis direction, and the acceleration detection signal in the Z-axis direction.

  In FIG. 11, potential stabilizing capacitors C4, C5, and C6 are provided between the terminals of the integrated circuit device VQ4, VQ5, and VQ6 and the terminals of the sensor device 20, respectively. Thus, a passive low-pass filter (anti-alias filter) including the capacitors C4, C5, C6 and the output resistance of the sensor device 20 is configured.

  FIG. 12 is a diagram for explaining the operation of the third configuration example. As shown in FIG. 12, in the first channel measurement period TCH1, the signals VQ1 and VR1 are selected by the multiplexers MUX1 and MUX2, respectively, and the amplifier circuit AMP outputs the differential voltage signal VDF1 between VQ1 and VR1 as the output signal AMQ. To do. The multiplexer MUX3 outputs the differential voltage signal VDF1 as the third signal SG3 to the A / D converter ADC. Similarly, in the second channel measurement period TCH2, the multiplexer MUX3 outputs the differential voltage signal VDF2 between the signals VQ2 and VR2 as the third signal SG3 to the A / D converter ADC. In the third channel measurement period TCH3, the multiplexer MUX3 outputs the differential voltage signal VDF3 between the signals VQ3 and VR3 as the third signal SG3 to the A / D converter ADC.

  On the other hand, in the fourth channel measurement period TCH4, the multiplexer MUX3 selects the signal VQ4 from the sensor device 20 and outputs it as the third signal SG3 to the A / D converter ADC. Similarly, the multiplexer MUX3 selects the signals VQ5 and VQ6 in the fifth and sixth channel measurement periods TCH5 and TCH6, respectively, and outputs them as the third signal SG3 to the A / D converter ADC.

  According to the configuration of FIG. 11, it is possible to provide an optimal measurement system for a 6-axis motion sensor including a 3-axis gyro sensor and a 3-axis acceleration sensor. That is, for the first and second signals constituting the angular velocity detection signal from the 6-axis motion sensor, the differential voltage signal is generated in the amplifier circuit AMP and can be A / D converted by the A / D converter ADC. On the other hand, the single-ended acceleration detection signal from the motion sensor can be input to the A / D converter ADC via the multiplexer MUX3 and A / D converted. Then, the three-channel angular velocity detection signal and the three-channel acceleration detection signal from the motion sensor are time-divisionally measured and A / D converted as shown in FIG. . Further, as described in FIG. 9A and the like, the angular velocity detection signal and the acceleration detection signal can be detected with high accuracy.

  For example, when the angular velocity and acceleration are integrated by a microcomputer at the subsequent stage to obtain the angle, velocity, and distance, if the DC offset of the angular velocity and acceleration is large, the DC offset is integrated and an error in the angle, velocity, and distance is obtained. There will be a situation that will become larger. When such a situation occurs, the electronic device on which the motion sensor is mounted is detected as rotating or moving even if the electronic device is not actually rotating or moving.

  In this regard, according to the present embodiment, the DC offset of angular velocity and acceleration can be minimized. Therefore, it is possible to prevent a situation in which an electronic device is detected as rotating or moving even if it is not actually rotating or moving.

  FIG. 13 is a detailed operation explanatory diagram of the integrated circuit device of this embodiment. As shown in A1 and A2 of FIG. 13, the amplifier circuit AMP configured by the switched capacitor circuit performs the sampling operation of the input signal in the first channel measurement period TCH1, and then performs the hold (output) operation. As indicated by A3 and A4, the A / D converter ADC performs the sampling operation of the output signal of the amplifier circuit AMP, and then performs the hold and conversion operation. Thereafter, similar operations are performed for the channels CH1 and CH2 as indicated by A5 and A6. In FIG. 13, “SA1”, “SA2”, and “SA3” represent the sampling operation of the amplifier circuit AMP in the channels CH1, CH2, and CH3, and “HL” represents the hold operation. “SA” represents a sampling operation of the A / D converter ADC, and “HL & C” represents a hold & conversion operation.

  As indicated by A7 in FIG. 13, the digital filter 52 of the control unit 50 performs digital filter processing DFLT1, DFLT2, and the like of the digital data DQ from the A / D converter ADC. Then, as shown at A8, the digital data DATA1, DATA2, and the like after the digital filter processing are output to a subsequent microcomputer or the like.

  As described above, in this embodiment, the processing of each channel in the amplifier circuit AMP, the A / D converter ADC, and the digital filter 52 is performed in a time division manner by pipeline processing.

5. Sharing of Switch Elements The sampling switch elements SWS1 and SWS2 in FIGS. 2A and 2B can be shared with the switch elements of the multiplexers MUX1 and MUX2 in FIG. FIG. 14 is a diagram illustrating a configuration example in the case of sharing the switching elements of the multiplexers MUX1 and MUX2 as described above.

  For example, in the first channel measurement period TCH1, the functions of the switch elements SWS1 and SWS2 of FIGS. 2A and 2B are realized by the switch elements SWQ1 and SWR1 of the multiplexers MUX1 and MUX2 of FIG.

  That is, in the first period T1 of the first channel measurement period TCH1, the switch element SWQ1 in FIG. 14 is turned on and the switch element SWR1 is turned off. Thus, the switch element SWS1 shown in FIG. 2A is turned on and the switch element SWS2 is turned off, and the detection voltage VQ1 is applied to one end of the capacitor CS.

  Further, in the second period T2 of the first channel measurement period TCH1, the switch element SWQ1 in FIG. 14 is turned off and the switch element SWR1 is turned on. Thereby, the switch element SWS1 and the switch element SWS2 shown in FIG. 2B are turned off and the reference voltage VR1 is applied to one end of the capacitor CS.

  In the second channel measurement period TCH2, the functions of the switch elements SWS1 and SWS2 in FIGS. 2A and 2B are realized by the switch elements SWQ2 and SWR2 of the multiplexers MUX1 and MUX2.

  That is, in the first period T1 of the second channel measurement period TCH2, the switch element SWQ2 is turned on and the switch element SWR2 is turned off. Accordingly, the switch element SWS1 shown in FIG. 2A is turned on and the switch element SWS2 is turned off, and the detection voltage VQ2 is applied to one end of the capacitor CS.

  In the second period T2 of the second channel measurement period TCH2, the switch element SWQ2 is turned off and the switch element SWR2 is turned on. Thereby, the switch element SWS1 and the switch element SWS2 shown in FIG. 2B are turned off and the reference voltage VR2 is applied to one end of the capacitor CS.

  The third channel measurement period TCH3 is the same as described above, and the functions of the switch elements SWS1 and SWS2 are realized by the switch elements SWQ3 and SWR3 of the multiplexers MUX1 and MUX2.

  Thus, by sharing the switching element of the multiplexer and the sampling switching element of the switched capacitor circuit, the circuit can be further reduced in size and simplified.

6). Electronic Device Next, a configuration example of an electronic device including the integrated circuit device of this embodiment will be described with reference to FIG. Note that the electronic apparatus of the present embodiment is not limited to the configuration shown in FIG. 15, and various modifications such as omitting some of the components or adding other components are possible.

  15 includes the sensor devices 10 and 20 and the integrated circuit device 500 of the present embodiment. Further, a processing unit 510, a storage unit 520, a wireless circuit 530, and an antenna 540 can be included.

  The sensor devices 10 and 20 (physical quantity transducers) detect various physical quantities (angular velocity, acceleration, angular acceleration, force, mass, etc.). Then, the physical quantity is converted into current (charge), voltage or the like and output as a detection signal.

  The integrated circuit device 500 receives detection signals from the sensor devices 10 and 20 and performs A / D conversion of the detection signals, or if necessary, performs arithmetic processing (signal processing) on the digital data after A / D conversion. . Then, the obtained digital data is output to the processing unit 510 or the like.

  The processing unit 510 performs various digital processes on the digital data. The function of the processing unit 510 is realized by, for example, a microcomputer. The storage unit 520 temporarily stores digital data and the like. The function of the storage unit 520 is realized by a memory such as a RAM.

  The radio circuit 530 performs modulation processing on the digital data obtained by the integrated circuit device 500 and transmits the digital data to an external device (an electronic device on the other side) using the antenna 540. The antenna 540 may be used to receive data from an external device, perform ID authentication, control the sensor devices 10 and 20, and the like.

  According to the configuration in FIG. 15, information detected by the sensor devices 10 and 20 can be transmitted to an external device, and various electronic devices having a wireless function and a sensor function can be realized.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. Further, the configurations and operations of the integrated circuit device and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

AMP amplifier circuit, ADC A / D converter,
OP operational amplifier, SW1 to SW4, SWS1, SWS2 switch element,
CS sampling capacitor, COF offset canceling capacitor,
AGND Analog ground voltage, T1 first period, T2 second period,
VDDA power supply voltage, RAD A / D conversion range,
MUX1 to MUX3 first multiplexer to third multiplexer,
CH1 to CH6 1st channel to 6th channel,
VQ1 to VQ3 first channel first signal to third channel first signal,
VR1 to VR3 first channel second signal to third channel second signal,
VQ4 to VQ6 4th channel to 6th channel signals,
TCH1 to TCH6 1st channel measurement period to 6th channel measurement period,
10, 20 sensor device, 50 control unit, 52 digital filter,
60 power supply circuit, 310 vibrator, 320 drive circuit, 330 detection circuit,
332 amplifier circuit, 334 synchronous detection circuit, 336 filter unit,
500 integrated circuit device, 510 processing unit, 520 storage unit, 530 wireless circuit,
540 antenna

Claims (15)

A first signal from a sensor device is input in a first period, and a second signal constituting a channel signal of the sensor device paired with the first signal is input in a second period, and the first signal and the An amplifier circuit that outputs a signal corresponding to the difference between the second signals;
An A / D converter that performs A / D conversion on the output signal of the amplifier circuit;
Including
The amplifier circuit is
An integrated circuit device comprising a switched capacitor circuit that cancels an offset voltage of an operational amplifier included in the amplifier circuit. In claim 1,
The amplifier circuit is
The operational amplifier;
An offset provided between a first input node of the operational amplifier having an analog ground voltage set at a second input node and a node of the analog ground voltage, and stores a charge corresponding to the offset voltage of the operational amplifier. An integrated circuit device comprising a canceling capacitor. In claim 2,
The amplifier circuit is
An integrated circuit device comprising a sampling capacitor provided between an input node of the amplifier circuit and the first input node of the operational amplifier. In claim 3,
The offset canceling capacitor is provided between the first input node and the first node of the operational amplifier,
The amplifier circuit is
A first switch element provided between the first node and the node of the analog ground voltage, which is turned on in the first period and turned off in the second period;
A second switch element provided between the first node and the output node of the operational amplifier, turned off in the first period, and turned on in the second period;
An integrated circuit comprising a third switch element provided between the output node and the first input node of the operational amplifier and turned on in the first period and turned off in the second period. apparatus. In claim 4,
The amplifier circuit is
An integrated circuit comprising: a fourth switch element provided between the output node of the operational amplifier and the output node of the amplifier circuit, which is turned off in the first period and turned on in the second period. Circuit device. In any of claims 2 to 5,
The integrated circuit device, wherein the offset canceling capacitor includes a plurality of unit capacitors for adjusting a gain of the amplifier circuit. In any one of Claims 1 thru | or 6.
The amplifier circuit is
A voltage signal obtained by adding a voltage corresponding to a difference between the first signal and the second signal to an analog ground voltage serving as a center voltage in an A / D conversion range of the A / D converter is output. An integrated circuit device. In any one of Claims 1 thru | or 7,
The first channel first signal constituting the first channel signal of the sensor device and the second channel first signal constituting the second channel signal of the sensor device are input, and in the first channel measurement period A first multiplexer that outputs the first channel first signal as a first signal and outputs the second channel first signal as the first signal in a second channel measurement period;
The first channel second signal constituting the first channel signal and the second channel second signal constituting the second channel signal are inputted, and the first channel second signal is inputted during the first channel measurement period. A second multiplexer that outputs two signals as a second signal and outputs the second channel second signal as the second signal in the second channel measurement period;
The amplifier circuit includes
The first signal from the first multiplexer is input in the first period of the first channel measurement period and the second channel measurement period,
The integrated circuit device, wherein the second signal from the second multiplexer is input in the second period of the first channel measurement period and the second channel measurement period. In claim 8,
A third multiplexer that receives a signal from the second sensor device and an output signal from the amplifier circuit and outputs a third signal;
The A / D converter is
An integrated circuit device that performs A / D conversion on the third signal from the third multiplexer. In claim 9,
The first multiplexer includes:
A third channel first signal constituting a third channel signal from the sensor device is input, and in the third channel measurement period, the third channel first signal is output as the first signal,
The second multiplexer is
A third channel second signal constituting the third channel signal from the sensor device is input, and the third channel second signal is output as the second signal in the third channel measurement period,
The amplifier circuit includes
The first signal from the first multiplexer is input in the first period of the first channel measurement period, the second channel measurement period, and the third channel measurement period,
The integrated circuit device, wherein the second signal from the second multiplexer is input in the second period of the first channel measurement period, the second channel measurement period, and the third channel measurement period. In claim 10,
The third multiplexer is
The fourth channel signal, the fifth channel signal, and the sixth channel signal from the second sensor device are input, and the fourth channel signal is output as the third signal in the fourth channel measurement period, An integrated circuit characterized in that the fifth channel signal is output as the third signal in the fifth channel measurement period, and the sixth channel signal is output as the third signal in the sixth channel measurement period. apparatus. In claim 11,
The sensor device is a gyro sensor device;
The second sensor device is an acceleration sensor device;
The first channel signal, the second channel signal, and the third channel signal from the gyro sensor device are respectively an angular velocity or angular acceleration detection signal around the X axis, and an angular velocity or angular acceleration detection around the Y axis. Signal, angular velocity or angular acceleration detection signal around the Z axis,
The fourth channel signal, the fifth channel signal, and the sixth channel signal from the acceleration sensor device are respectively an X axis direction acceleration detection signal, a Y axis direction acceleration detection signal, and a Z axis direction acceleration signal. An integrated circuit device characterized by being an acceleration detection signal. In any one of Claims 8 thru | or 12.
The first channel first signal is a signal of a first detection voltage of the first channel,
The first channel second signal is a signal of a first reference voltage serving as a reference for the first detection voltage,
The second channel first signal is a signal of a second detection voltage of the second channel;
2. The integrated circuit device according to claim 2, wherein the second channel second signal is a signal of a second reference voltage that serves as a reference for the second detection voltage. In any one of Claims 8 thru | or 12.
The first channel first signal and the first channel second signal are a first differential signal in a balanced relationship with a predetermined voltage level as a reference,
The integrated circuit device, wherein the second channel first signal and the second channel second signal are second differential signals in a balanced relationship with a predetermined voltage level as a reference.   An electronic apparatus comprising the integrated circuit device according to claim 1.

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