CN114696834A

CN114696834A - Successive approximation type analog-to-digital converter, test equipment and capacitance weighted value calibration method

Info

Publication number: CN114696834A
Application number: CN202210611172.7A
Authority: CN
Inventors: 黄胜; 虞少平
Original assignee: Zhejiang Geoforcechip Technology Co Ltd
Current assignee: Zhejiang Geoforcechip Technology Co Ltd
Priority date: 2022-06-01
Filing date: 2022-06-01
Publication date: 2022-07-01
Anticipated expiration: 2042-06-01
Also published as: CN114696834B

Abstract

The embodiment of the application provides a successive approximation type analog-to-digital converter, a testing device and a capacitance weighted value calibration method, and relates to the field of semiconductor integrated circuits. The successive approximation analog-to-digital converter includes: the circuit comprises a capacitor array, a logic comparison device, a residual error amplifier, a unit capacitor, a load capacitor and a control device; the input end and the output end of the residual error amplifier are respectively and electrically connected with two ends of the unit capacitor, and the output end of the residual error amplifier is also electrically connected with the load capacitor; the load capacitor is used for storing a plurality of capacitor conversion residual differences, connecting the plurality of capacitor conversion residual differences back to the capacitor array and correcting the plurality of capacitor conversion arrays; the control device is electrically connected with the logic comparison device. The capacitance conversion residual difference provided by the load capacitance and the residual difference amplifier is used as feedback, the decimal place level of the weight of the capacitance to be calibrated is determined, the capacitance mismatch error of the analog-to-digital converter can be calibrated, and the precision of the analog-to-digital converter is improved.

Description

Successive approximation type analog-to-digital converter, test equipment and capacitance weighted value calibration method

Technical Field

The application relates to the field of semiconductor integrated circuits, in particular to a successive approximation type analog-to-digital converter, a test device and a capacitance weighted value calibration method.

Background

An Analog-to-Digital Converter (ADC) is a device that converts an Analog signal into a Digital signal. Common ADC structures include various types, wherein a Successive Approximation Register (SAR) ADC can realize extremely low power consumption through a simple architecture, and is widely used in devices requiring low power consumption. The SAR ADC obtains a digital quantity output signal through digital weight addition and subtraction of a binary weighted capacitor array, however, in the prior art, adjacent capacitors have capacitor mismatch, and the improvement of ADC precision is limited.

The prior art methods for calibrating the capacitance mismatch include analog calibration techniques and digital calibration techniques. The analog calibration technology is used for correcting the capacitor through a laser chip element in the analog field, and the digital calibration technology is used for describing mismatch errors in the capacitor through a low-level capacitor in the digital field and then adjusting the mismatched capacitor.

However, the existing digital calibration technology can only represent high-order capacitance by low-order capacitance in integer, and is difficult to describe the error with higher precision.

Disclosure of Invention

The purpose of the application comprises that a successive approximation type analog-to-digital converter, a testing device and a capacitance weighted value calibration method are provided, a decimal place level of the weight of a capacitor to be calibrated is determined by taking a capacitance conversion residual difference provided by a load capacitance and a residual difference amplifier as feedback, the capacitance mismatch error of the analog-to-digital converter can be calibrated, and the precision of the analog-to-digital converter is improved.

The embodiment of the application can be realized as follows:

in a first aspect, an embodiment of the present application provides a successive approximation analog-to-digital converter, including: the circuit comprises a capacitor array, a logic comparison device, a residual error amplifier, a unit capacitor, a load capacitor and a control device;

the capacitor array is respectively and electrically connected with the logic comparison device, the input end of the residual error amplifier, the unit capacitor and the load capacitor, and the capacitor array is used for outputting a plurality of capacitor conversion arrays of capacitors to be calibrated in the capacitor array through the logic comparison device;

the input end and the output end of the residual error amplifier are respectively electrically connected with two ends of the unit capacitor, the output end of the residual error amplifier is also electrically connected with the load capacitor, the residual error amplifier is used for receiving a plurality of residual errors of the capacitor to be calibrated output by the capacitor array, amplifying the plurality of residual errors of the capacitor to be calibrated and outputting a plurality of capacitor conversion residual errors, and the capacitor conversion residual errors and the capacitor conversion array have a one-to-one correspondence relationship;

the load capacitor is used for storing the plurality of capacitor conversion residual differences, and connecting the plurality of capacitor conversion residual differences back to the capacitor array to correct the plurality of capacitor conversion arrays;

the control device is electrically connected with the logic comparison device and used for determining the capacitance weight value of the capacitor to be calibrated according to the plurality of capacitance conversion arrays.

In an alternative embodiment, the capacitive array comprises: the capacitor comprises a high-order capacitor, a low-order capacitor and a redundant capacitor which are connected with each other, wherein the redundant capacitor is the redundant capacitor of any one capacitor in the low-order capacitor;

the first ends of the high-order capacitor, the low-order capacitor and the redundant capacitor are respectively and electrically connected with the logic comparison device, the residual error amplifier and the unit capacitor;

and second ends of the high-order capacitor, the low-order capacitor and the redundant capacitor are electrically connected with the load capacitor.

In an optional embodiment, the control device is specifically configured to:

determining a plurality of capacitance values to be selected of the capacitor to be calibrated according to the plurality of capacitor conversion arrays;

and carrying out averaging processing on the plurality of capacitance values to be selected to obtain the capacitance weight value of the capacitor to be calibrated.

In an optional implementation, the successive approximation analog-to-digital converter further includes: the load switch is electrically connected with the capacitor array, the load capacitor and the control device respectively;

the control device controls whether the load capacitor is connected to the capacitor array or not through the load switch.

In an optional implementation, the successive approximation analog-to-digital converter further includes: a first amplifier switch and a second amplifier switch;

the first end of the first amplifier switch is electrically connected with the capacitor array and the control device respectively, and the second end of the first amplifier switch is electrically connected with the input end of the residual error amplifier and the first end of the unit capacitor;

a first end of the second amplifier switch is electrically connected with an output end of the residual error amplifier, the control device and a second end of the unit capacitor respectively, and a second end of the second amplifier switch is electrically connected with the load capacitor;

the first amplifier switch and the second amplifier switch are used for controlling whether the residual error amplifier is connected with the successive approximation type analog-to-digital converter or not.

In an optional implementation manner, the high-side capacitor, the low-side capacitor and the redundant capacitor all determine whether one of the high-side capacitors is used as the capacitor to be calibrated through a three-pole switch.

In an optional embodiment, the capacitor array is connected to a high potential reference voltage, a common mode potential reference voltage and a low potential reference voltage through the three-pole switch, respectively.

In an optional implementation, the successive approximation analog-to-digital converter further includes: a unit capacitor switch;

the first end of the unit capacitor switch is electrically connected with the first amplifier switch and the control device respectively;

the first end of the unit capacitor switch is electrically connected with the second amplifier switch;

the unit capacitor switch is used for controlling whether the unit capacitor is connected to the successive approximation type analog-to-digital converter or not.

In an alternative embodiment, the logic comparing device includes: a comparator and logic control circuit;

the first end of the comparator is connected with the capacitor array, and the second end of the comparator is electrically connected with the first end of the logic control circuit;

and the second end of the logic control circuit is electrically connected with the control device.

In a second aspect, an embodiment of the present application provides a test apparatus, including: the successive approximation analog-to-digital converter according to any one of the first aspect and the sampling power supply, wherein an output end of the sampling power supply is electrically connected with an input end of the successive approximation analog-to-digital converter;

the sampling power supply is used for outputting sampling voltage to the successive approximation type analog-to-digital converter;

the successive approximation type analog-to-digital converter is used for estimating the voltage value of the sampling voltage after determining and calibrating the capacitance weight value of each capacitor of the capacitor array.

In a third aspect, an embodiment of the present application provides a capacitance weight value calibration method applied to the successive approximation type analog-to-digital converter described in any one of the first aspects, where the method includes:

after capacitance conversion is carried out on the capacitor array, the capacitor array outputs a capacitor conversion array of the capacitor to be calibrated in the capacitor array to a control device through a logic comparison device, and the capacitor array outputs the residual difference of the capacitor to be calibrated to a residual difference amplifier;

receiving the residual difference of the capacitor to be calibrated output by the capacitor array through the residual difference amplifier, amplifying the residual difference of the capacitor to be calibrated, and outputting a capacitor conversion residual difference to a load capacitor, wherein the capacitor conversion residual difference and the capacitor conversion array have a one-to-one correspondence relationship;

storing the capacitance conversion residual difference by the load capacitor, and connecting the capacitance conversion residual difference back to the capacitor array;

repeating the steps until the preset times are reached to obtain a plurality of capacitance conversion arrays;

and determining the capacitance weight value of the capacitor to be calibrated according to the plurality of capacitance conversion arrays by the control device.

The beneficial effects of the embodiment of the application include:

by adopting the successive approximation type analog-to-digital converter, the test equipment and the capacitance weighted value calibration method provided by the application, the plurality of capacitance conversion residual differences are connected back to the capacitor array through the residual difference amplifier and the load capacitor so as to correct the output value of the capacitance conversion array, and the capacitance weighted value of the capacitor to be calibrated is determined through the plurality of capacitance conversion arrays. The influence of capacitance mismatch in the capacitance conversion process is eliminated, and the capacitance mismatch error of the analog-to-digital converter is calibrated, so that the conversion precision of the successive approximation type analog-to-digital converter is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic diagram of a successive approximation analog-to-digital converter in the prior art;

FIG. 2 is a schematic diagram of a capacitor array structure of a successive approximation analog-to-digital converter in the prior art;

fig. 3 is a schematic structural diagram of a successive approximation analog-to-digital converter according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a successive approximation analog-to-digital converter according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a successive approximation analog-to-digital converter according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a successive approximation analog-to-digital converter according to an embodiment of the present application;

FIG. 7 is a schematic structural diagram of a test apparatus provided in an embodiment of the present application;

fig. 8 is a flowchart illustrating steps of a capacitance weight value calibration method according to an embodiment of the present disclosure.

Icon: 101-digital control logic circuit; 102-a digital-to-analog converter; 103-a sample and hold circuit; 104-a comparison device; 201-a capacitor array; 2011-high capacitance; 2012-redundant capacitance; 2013-low capacitance; 202-logical comparison means; 2021-a comparator; 2022-logic control circuit; 203-residual amplifier; 204-unit capacitance; 205-load capacitance; 206-a control device; 207-load switch; 208-a first amplifier switch; 209-a second amplifier switch; 210-unit capacitance switch; 20-successive approximation analog-to-digital converter; 30-sampling the power supply.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.

In the description of the present application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which the present invention product is usually put into use, it is only for convenience of describing the present application and simplifying the description, but it is not intended to indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and thus, should not be construed as limiting the present application.

Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.

The function of the analog-to-digital converter is to convert an input analog signal into a corresponding binary digital signal, and the essence of the analog-to-digital converter is to sample the amplitude of the analog signal, quantize it with a reference voltage, and convert it into a discrete digital signal.

The successive approximation type analog-to-digital converter works according to a binary search principle, and fig. 1 is a structural and working schematic diagram of the successive approximation type analog-to-digital converter in the prior art. As shown in fig. 1, the successive approximation analog-to-digital converter includes: a Digital control logic circuit 101, an Analog-to-Digital Converter (DAC) 102, a sample-and-hold circuit 103, and a comparator 104. clk is a clock cycle signal that controls the duty cycle of the digital logic circuit,

as a reference voltage, the voltage of the reference voltage,

is the input sampled voltage.

The working process of the SAR ADC shown in fig. 1 is: first of all, the first step is to,

after passing through the sample hold circuit 103, is held

Inputting the digital signal into one end of the comparison device 104, the digital control logic circuit 101 outputs the digital signal with the highest position "1" and the other positions "0", and the digital signal is applied to the digital-to-analog converter 102 to generate the corresponding digital signal

Analog signal of

. Next, the comparison means 104 compares

And

in the size of (1)

If so, the comparator 104 outputs 0, otherwise, the comparator 104 outputs 1 and the most significant bit of the register of the digital control logic 101 is held. And finally, presetting the next highest bit as '1', carrying out next comparison by the SAR ADC according to the same method until the lowest bit is obtained, wherein the final state of the output register is the sampling voltage of the SAR ADC

An estimate of (d).

Generally, taking the 7-bit SAR ADC shown in fig. 2 as an example, the digital-to-analog converter 102 is composed of 7-bit binary-weighted DAC capacitor arrays B1 through B7. In the sampling stage, the common end, i.e. the lower end, of the DAC capacitor array is connected with a common-mode voltage

The free, i.e. upper, end being connected to the input signal

And sampling is carried out. After the sampling is completed, the public end is connected with

Disconnect, free end and

off, a charge proportional to the input voltage is obtained on the DAC capacitor array. Then, according to the provided SAR ADC working process, the DAC capacitor array performs repeated electricityThe process of capacitance comparison and charge redistribution finally obtains the digital output code by the digital control logic circuit 101

，…，

]。

For an ideal SAR ADC, if necessary

Analog signal of

The weight value of the capacitor corresponding to each data bit should be twice the weight value of the next smaller capacitor, i.e., the capacitor weight values of the DAC capacitor array should be incremented in binary form. Therefore, capacitance matching is the key to achieving a high-precision SAR ADC.

However, due to the manufacturing process and physical circuit design, the capacitance of the upper bit may be difficult to maintain a double relationship with the capacitance of the lower bit, resulting in a capacitance mismatch. This mismatch can reduce the signal-to-noise ratio and spurious-free dynamic range of the SAR ADC. Therefore, in order to improve the accuracy of the SAR ADC, the capacitance mismatch error needs to be determined and calibrated.

The calibration technology in the prior art includes an analog calibration technology and a digital calibration technology, wherein the digital calibration technology describes the mismatch error of the capacitor to be calibrated correspondingly in the digital field by using a calibration code, and determines the error value of the capacitor mismatch so as to achieve the purpose of calibrating the capacitor mismatch. However, in the digital calibration mode, it is difficult to describe capacitance mismatch errors of fractional order by the capacitance of the integer, which limits the calibration accuracy of the SAR ADC and further limits the capacitance conversion accuracy thereof.

Based on this, the applicant provides a successive approximation type analog-to-digital converter, a testing device and a capacitance weight value calibration method, and the capacitance weight value of the capacitor to be calibrated is determined by a residual error amplifier and a feedback capacitor, and storing and feeding back a capacitance conversion residual error to a capacitor array. Therefore, the influence of capacitance mismatch in the capacitance conversion process can be eliminated, and the conversion precision of the successive approximation type analog-to-digital converter is improved.

Fig. 3 is a schematic structural diagram of a successive approximation analog-to-digital converter according to an embodiment of the present application, and as shown in fig. 3, the successive approximation analog-to-digital converter includes: capacitor array 201, logic comparator 202, residual amplifier 203, unit capacitor 204, load capacitor 205 and control device 206.

The capacitor array 201 is electrically connected to the logic comparator 202, the input terminal of the residual error amplifier 203, the unit capacitor 204, and the load capacitor 205, and the capacitor array 201 is configured to output a plurality of capacitor conversion arrays of the capacitors to be calibrated in the capacitor array 201 through the logic comparator 202.

The capacitor array 201 may be an array formed by N capacitors which are connected with each other and gradually increase from small to large in a binary capacitor mode, and the number of the capacitors is related to the accuracy of the SAR ADC.

The input end and the output end of the residual error amplifier 203 are respectively electrically connected with two ends of the unit capacitor 204, the output end of the residual error amplifier 203 is further electrically connected with the load capacitor 205, the residual error amplifier 203 is used for receiving a plurality of residual errors of the capacitor to be calibrated output by the capacitor array 201, amplifying the plurality of residual errors of the capacitor to be calibrated, and outputting a plurality of capacitor conversion residual errors, and the capacitor conversion residual errors and the capacitor conversion arrays have a one-to-one correspondence relationship.

The residual error amplifier 203 may be an amplifier for amplifying residual errors, and in this embodiment, the residual error amplifier 203 may be configured to amplify the residual errors of the capacitors to be calibrated by 2 times, obtain a plurality of capacitor conversion residual errors, and store the plurality of capacitor conversion residual errors in the load capacitor 205.

The load capacitor 205 is used to store a plurality of capacitance conversion residual differences, and connect the plurality of capacitance conversion residual differences back to the capacitor array 201 to correct the plurality of capacitance conversion arrays.

The control device 206 is electrically connected to the logic comparing device 202, and the control device 206 is configured to determine a capacitance weight value of the capacitor to be calibrated according to the plurality of capacitance conversion arrays.

The workflow of the SAR ADC is detailed below:

firstly, after the capacitor array 201 is connected with voltage, capacitance conversion is carried out on the capacitor array 201, charge connected with the capacitor array 201 is redistributed, a residual difference Vres1 of the capacitor to be calibrated is obtained and is output to a residual difference amplifier 203, and a group of numerical values A1 are output to a control device 206 through a logic comparison device 202, wherein for the capacitor array 201 with N bits, A1 is composed of N-bit binary digits and is used for representing the corresponding relation of the low-order capacitor of the capacitor to be calibrated in the capacitor array 201 and the capacitor to be calibrated on an integer level. Since the weighted value of the capacitor to be calibrated may not be an integer, Vres1 may be used to compensate for the fractional representation of the lower capacitor integer level, which is the voltage between capacitor array 201 and residual amplifier 203. That is, the sum of the capacitance values represented by a1 and Vres1 is the capacitance weight value of the capacitor to be calibrated.

Next, the input end and the output end of the residual error amplifier 203 are electrically connected to the unit capacitor 204, and the capacitance weight value of the unit capacitor 204 may be the same as the capacitance weight value of the capacitor to be calibrated, so as to avoid short circuit of the residual error amplifier. Vres1 is amplified by 2 times by residual amplifier 203 and then stored in load capacitor 205 connected to the output of residual amplifier 203.

Then, the load capacitor 205 is connected in parallel with the capacitor array 201, and the capacitance conversion process is executed again, so that a group of values A2 and a residual difference Vres2 of the capacitor to be calibrated are obtained, wherein A2 and A1 have the same meaning, and Vres2 and Vres1 have the same meaning. It will be appreciated that after the second conversion by coupling load capacitor 205 into capacitor array 201, the resulting values of a2 and Vres2 change accordingly due to the compensation of load capacitor 205.

After the capacitance conversion process is repeatedly executed for multiple times, a plurality of capacitance conversion arrays and a plurality of capacitance conversion residual differences are obtained. Since the plurality of capacitance conversion arrays are obtained by correcting the plurality of capacitance conversion residual differences, and the load capacitor 205 causes a positive offset and a negative offset of the capacitance weight value of the capacitor to be calibrated with respect to the actual value of the capacitance weight value, the control device 206 may determine the capacitance weight value of the capacitor to be calibrated according to the mutual compensation of the plurality of capacitance conversion arrays, and the specific determination manner is described in detail in the following embodiments.

Optionally, the number of repetitions of the capacitance conversion may be set according to the accuracy requirement, and may be 512, for example.

After the capacitance weight value of the capacitor to be calibrated is determined, the capacitor to be calibrated can be calibrated according to the weight value which should be set by the capacitor to be calibrated, and the specific calibration process can be selected according to needs and is not repeated herein.

In this embodiment, the load capacitor connects the plurality of residual capacitance conversion differences back to the capacitor array to correct the output value of the next capacitor conversion array, and finally, a plurality of capacitor conversion arrays are obtained through a plurality of times of capacitance conversion, and the capacitance weight value of the capacitor to be calibrated is determined. Therefore, the capacitance mismatch error of the analog-to-digital converter is calibrated, and the conversion precision of the successive approximation type analog-to-digital converter is improved.

Optionally, with continued reference to fig. 3, the control device 206 is specifically configured to:

and determining a plurality of capacitance values to be selected of the capacitor to be calibrated according to the plurality of capacitor conversion arrays.

Since the plurality of capacitance conversion arrays are binary strings output by the logic comparison apparatus 202, the control apparatus 206 can convert the binary strings into decimal values representing the capacitance values to be selected of the capacitors to be calibrated according to the binary and decimal conversion relationship. For example, for a 7-bit SAR ADC, the capacitance conversion array is 0001010, and the candidate capacitance is 10V.

And averaging the plurality of capacitance values to be selected to obtain the capacitance weight value of the capacitor to be calibrated.

Alternatively, the control device 206 may also directly perform an averaging process on the capacitance conversion array in a binary manner without converting the capacitance conversion array into the capacitance value to be selected, so as to determine the capacitance weight value of the capacitor to be calibrated.

As can be seen from the foregoing embodiments, the capacitance values to be selected of the capacitances to be calibrated, which are represented by the capacitance conversion arrays obtained by the control device 206, are all integer values floating around the actual capacitance value of the capacitance to be calibrated. Then, the control device 206 may determine the capacitance weight value of the capacitor to be calibrated by performing a ratio, i.e., an averaging process, on the accumulated sum of the capacitance values to be selected of the capacitors to be calibrated and the number of times of capacitance conversion. It can be understood that, since positive or negative integer deviations exist between the capacitance values to be selected of the capacitors to be calibrated and the actual capacitance values, the obtained capacitance weight values of the capacitors to be calibrated can include integer levels and decimal levels after the control device 206 averages the values.

In this embodiment, the control device can determine the integer level and the decimal level of the capacitance weight value of the capacitor to be calibrated according to the plurality of capacitance conversion arrays in an averaging manner, so that the calibration accuracy of the capacitance mismatch error is improved.

Alternatively, as shown in fig. 4, the capacitor array includes: the capacitor 2012 is a redundant capacitor of any one of the

capacitors

2013, 2011, 2013 and 2012 connected to each other.

As shown in fig. 4, taking a 7-bit SAR ADC as an example, the low-bit capacitor 2013 includes: referring to the capacitor B0, the first capacitor B1, the second capacitor B2, the third capacitor B3, the fourth capacitor B4, and the fifth capacitor B5, the redundant capacitor 2012 may be a redundant capacitor of any one of the high-side capacitor 2011 or the low-side capacitor 2013, in this embodiment, the redundant capacitor 2012 is used as the redundant capacitor

For illustration, the redundant capacitor 2012

The capacitance weight value of (a) is equal to the capacitance weight value of the corresponding fifth capacitor B5, and is 16 capacitance units. The high-side capacitor 2011 includes: sixth capacitances B6, B7.

As shown in fig. 4, the high-side capacitor 2011, the low-side capacitor 2013 and the redundant capacitor 2012 are connected to each other, that is, the upper plate terminals of the capacitors are all connected to the same common voltage input terminal through a common line.

It should be noted that the number and division of the high-order capacitors 2011 and the low-order capacitors 2013 may be determined according to specific needs, and several capacitors with higher capacitance weight values and which are prone to capacitance mismatch in the SAR ADC may be used as the high-order capacitors 2011. The low-side capacitor 2013 and the redundant capacitor 2012 can be calibrated first according to the reference capacitor B0 at the low side, and then the high-side capacitor is calibrated.

The calibration mode of the low-side capacitor 2013 may be the same as that of the high-side capacitor 2011, or other calibration modes may be adopted, which is not limited herein.

The first terminals of the high-side capacitor 2011, the low-side capacitor 2013 and the redundant capacitor 2012 are electrically connected to the logic comparator 202, the residual amplifier 203 and the unit capacitor 204, respectively.

The second terminals of the high-side capacitor 2011, the low-side capacitor 2013 and the redundant capacitor 2012 are electrically connected to the load capacitor 205.

In calibrating the sixth capacitor B6, the capacitance weight value due to B6 is determined by the capacitance conversion arrays represented by the low-order capacitor 2013 and the capacitance conversion residual. In the presence of a redundant capacitor 2012

Then, the capacitance conversion array in the capacitance weight value of B6 can be represented by the low-order capacitor 2013 and the redundant capacitor 2012, so that the range of the capacitance conversion array capable of representing the capacitance is expanded, and when the error of the capacitance weight value of B6 is large, the error range can be covered.

The capacitance weight values of the high-order capacitor 2011 are sequentially determined from low to high according to the calibration method provided in the above embodiment, a plurality of capacitance conversion arrays are determined by the low-order capacitor 2013 and the redundant capacitor 2012, and finally, the control device 206 determines the capacitance weight value of the capacitor to be calibrated according to the plurality of capacitance conversion arrays.

In the embodiment, the redundant capacitor is additionally arranged, so that the error representation range of the capacitor array is expanded, and the representation precision of the SAR ADC is increased when the error of the capacitance weight value of B6 is wide.

Optionally, with continued reference to fig. 4, the high-side capacitor 2011, the low-side capacitor 2013 and the redundant capacitor 2012 all determine whether one of the high-side capacitors is used as the capacitor to be calibrated through the three-pole switch.

It should be noted that a switch in which one movable contact can make contact with a fixed contact is referred to as a single-pole switch, and a switch in which 3 parallel movable contacts make contact with the respective fixed contacts is referred to as a three-pole switch.

Optionally, the capacitor to be calibrated in the high-side capacitor 2011 needs to be switched to a first target position through a three-pole switch, the low-side capacitor 2013, the redundant capacitor 2012 and the low-side capacitor of the high-side capacitor 2011 which are opposite to the capacitor to be calibrated are switched to a second target position, and the high-side capacitor of the high-side capacitor 2011 which is opposite to the capacitor to be calibrated is switched to a third target position. In this way, one of the high-side capacitors 2011 can be determined to be the capacitor to be calibrated.

Alternatively, as shown in fig. 4, the capacitor array is switched in the high potential reference voltage, the common mode reference voltage and the low potential reference voltage through the three-pole switch, respectively.

Wherein the common mode potential is referenced to the voltage

Can be 0V, high potential reference voltage

May have a voltage value of + XV, a low potential reference voltage

The voltage value of (a) may be-XV, and the specific value thereof is not limited herein.

Illustratively, when the capacitor to be calibrated is the sixth capacitor B6, the higher capacitor B7 of the capacitor to be calibrated is connected to the common-mode potential reference voltage

The capacitor B6 to be calibrated is connected to a high-potential reference voltage

Low-level capacitor 2013 and redundant capacitor 2012Go to a low potential reference voltage

. Wherein, the control device adaptively determines to switch in the low potential reference voltage according to the value of B6

The capacitance of (c). Then, voltage conversion is performed according to the steps provided in the above embodiment, the capacitance conversion array of B6 is obtained, the electrical connection between each capacitor and the corresponding reference voltage is disconnected after the voltage conversion of the residual difference is completed, and the residual difference of B6 is amplified by the residual difference amplifier 203 and stored in the load capacitor 205. Next, the load capacitor 205 is connected to the capacitor array, and the process is repeated, so that the control device 206 receives a plurality of capacitor conversion arrays. Finally, the control device 206 determines the capacitance weight value of the capacitance B6 to be calibrated according to the plurality of capacitance conversion arrays.

It can be understood that when the capacitor to be calibrated is the seventh capacitor B7, the capacitor to be calibrated B7 is connected to the high-potential reference voltage

The low-level capacitor 2013 and the redundant capacitor 2012 are connected to a low-level reference voltage

. Then, as in the process of calibrating B6, capacitance conversion is performed according to the steps provided in the above embodiments, and finally the control device 206 determines the capacitance weight value of the capacitance B7 to be calibrated according to a plurality of capacitance conversion arrays.

Alternatively, the control device 206 may control the high-side capacitor 2011, the low-side capacitor 2013 and the redundant capacitor 2012 to be switched by the connected voltage of the three-pole switch according to a preset clock cycle.

In the embodiment, the capacitor array is controlled to be connected to different high potential reference voltages, common mode potential reference voltages and low potential reference voltages through the three-knife switch so as to determine the capacitor to be calibrated and perform capacitance conversion, and the efficiency and the precision of the capacitance conversion are improved.

Optionally, as shown in fig. 5, the successive approximation analog-to-digital converter further includes: and the load switch 207 is electrically connected with the capacitor array 201, the load capacitor 205 and the control device 206 respectively.

The control device 206 controls whether the load capacitor 205 is connected to the capacitor array 201 through the load switch 207.

The control device 206 is used for controlling the on or off of the load switch 207 during multiple capacitance conversion processes to control whether the load capacitor 205 is connected to the capacitor array.

For example, taking the first capacitance conversion as an example, after the first capacitance conversion is completed, a first capacitance conversion array a1 and a first residual difference Vres1 of the capacitor to be calibrated are obtained, a1 outputs to the control device 206 via the logic comparison device 202, Vres1 obtains the first capacitance conversion residual difference after being amplified by the residual difference amplifier and stores in the load capacitor 205. Next, the control device 206 controls the load switch 207 to close, and returns the stored first capacitance conversion residual difference to the capacitor array 201 to perform the second capacitance conversion.

After the second capacitance conversion is finished, the second capacitance conversion array a2 and the second residual difference Vres2 of the capacitor to be calibrated are obtained, the control device 206 controls the load switch 207 to be switched off, and the load capacitor 205 stores the second capacitance conversion residual difference amplified by the residual difference amplifier 203. Then, the control device 206 controls the load switch 207 to close, and returns the stored second capacitance conversion residual difference to the capacitor array 201 to perform the third capacitance conversion.

Repeating the above process to preset times to obtain multiple capacitance conversion arrays and multiple capacitance conversion residual differences.

It should be noted that the ratio between the value of the second capacitance conversion residual difference and the value of the first capacitance conversion residual difference can be determined according to the following transfer function NTF:

the transfer function NTF is a first order noise shaping, where z is the value of the fourier transform of the value of the first capacitive transfer residual in the z-domain.

In this embodiment, the time for accessing the load capacitor to the capacitor array and the time sequence relationship for performing the capacitor conversion on the capacitor array are controlled by the load switch, so that the influence of the early or late access of the feedback capacitor on the next capacitor conversion array and the value of the residual difference of the capacitor conversion is avoided.

Optionally, with continued reference to fig. 5, the successive approximation analog-to-digital converter further comprises: a first amplifier switch 208 and a second amplifier switch 209.

The first amplifier switch 208 and the second amplifier switch 209 may be single-pole switches respectively disposed at the input end and the output end of the residual error amplifier 203.

A first terminal of the first amplifier switch 208 is electrically connected to the capacitor array 201 and the control device 206, respectively, and a second terminal of the first amplifier switch 208 is electrically connected to the input terminal of the residual amplifier 203 and the first terminal of the unit capacitor 204.

A first terminal of the second amplifier switch 209 is electrically connected to the output terminal of the residual error amplifier 203, the control device 206, and a second terminal of the unit capacitor 204, respectively, and a second terminal of the second amplifier switch 209 is electrically connected to the load capacitor 205.

The first amplifier switch 208 and the second amplifier switch 209 are both controlled to be closed and opened by the control device 206.

The first amplifier switch 208 and the second amplifier switch 209 are used to control whether the residual error amplifier 203 is connected to the successive approximation analog-to-digital converter.

In the above embodiment, after the capacitor array 201 performs one capacitor conversion, a group of capacitor conversion arrays and the residual difference of the capacitor to be calibrated are determined. In order to avoid errors in the capacitance conversion process, after each capacitance conversion is completed, the control device 206 controls the first amplifier switch 208 and the second amplifier switch 209 to be closed, the residual error amplifier 203 is connected, the residual error of the capacitor to be calibrated is amplified, a corresponding capacitance conversion residual error is obtained, and the obtained residual error is stored in the load capacitor 205. The specific amplification factor of the residual error amplifier 203 is not specifically limited herein.

After the residual error amplifier 203 outputs the corresponding capacitance conversion residual error, before the control device 206 controls the load capacitor 205 to be connected to the capacitor array 201, the control device 206 controls the first amplifier switch 208 and the second amplifier switch 209 to be disconnected, so as to disconnect the residual error amplifier 203 from the SAR ADC.

After multiple capacitance conversions, the above process is repeatedly performed until a preset number of times is reached.

In this embodiment, the control device controls the on/off of the residual error amplifier by controlling the on/off of the first amplifier switch and the second amplifier switch, so as to avoid the influence of the residual error amplifier on the capacitance conversion process and improve the accuracy of the capacitance conversion.

Optionally, with continued reference to fig. 5, the successive approximation analog-to-digital converter further comprises: a unit capacitor switch 210.

The unit capacitor switch 210 may also be a single-pole switch, and is controlled by the control device 206 to be turned on or off to control whether the unit capacitor 204 is connected to both ends of the residual error amplifier 203.

It should be noted that the values of the unit capacitor 204 and the load capacitor 205 may be equal, and are determined according to the value of the capacitor to be calibrated, for example, if the capacitor to be calibrated in fig. 5 is B7, and the capacitance weight value of the capacitor to be calibrated is 64 capacitor units, the capacitance weight value of the unit capacitor 204 and the load capacitor 205 may be 64 capacitor units, and the capacitance with the capacitance weight value of 64 capacitor units may be, as shown in fig. 5, composed of two capacitances with the capacitance weight value of 32 capacitor units, or may be, as shown, composed of one capacitance with the capacitance weight value of 64 capacitor units, and the specific composition manner of the present application is not limited herein.

Optionally, for the SAR ADC shown in fig. 5, when the capacitance to be calibrated is B5, capacitance weight values of the unit capacitor 204 and the load capacitor 205 may be 32 capacitance units, and the capacitance with the capacitance weight value of 64 capacitance units may be composed of two capacitances with capacitance weight values of 16 capacitance units, or may be composed of one capacitance with capacitance weight value of 32 capacitance units, which is not limited herein.

In addition, the capacitance values of the unit capacitor 204, the load capacitor 205 and the capacitor to be calibrated may not be in a corresponding relationship, and if the SAR ADC shown in fig. 5 is 8 bits, when the capacitor to be calibrated is B8, the capacitance weight values of the unit capacitor 204 and the load capacitor 205 may also be 64 capacitor units, which is not limited to this.

The first end of the unit capacitor switch 210 is electrically connected to the first amplifier switch 208 and the control device 206, respectively.

A first terminal of the unit capacitance switch 210 is electrically connected to the second amplifier switch 209.

The unit capacitor switch 210 is used to control whether the unit capacitor 204 is connected to the successive approximation analog-to-digital converter.

When the control device controls the first amplifier switch 208 and the second amplifier switch 209 to be closed, the control device 206 may simultaneously control the unit capacitor switch 210 to be closed, and connect the unit capacitor 204 to both ends of the residual error amplifier 203, thereby preventing the residual error amplifier 203 from being short-circuited.

When the control device 206 controls the first amplifier switch 208 and the second amplifier switch 209 to be turned off, the control device 206 may simultaneously control the unit capacitor 204 to be turned off, and may turn off the unit capacitor 204 from the residual amplifier 203.

In this embodiment, the control device controls the on or off of the unit capacitor switch to be synchronous with the access of the residual error amplifier, so as to avoid the short circuit of the residual error amplifier and improve the safety of the SAR ADC.

Alternatively, as shown in fig. 6, the logic comparing device includes: a comparator 2021 and a logic control circuit 2022.

The comparator 2021 is a circuit or device that compares the analog voltage signal with a reference voltage signal to determine whether they are equal. In the embodiment of the present application, a single-ended structure is adopted, one end of the comparator 2021 is grounded, and the input voltage is zero.

The logic control circuit 2022 may be a register for temporarily storing the digital signal output from the comparator 2021, and is transmitted to the electronic device of the control apparatus 206.

A first terminal of the comparator 2021 is connected to the capacitor array 201, and a second terminal of the comparator 2021 is electrically connected to a first terminal of the logic control circuit 2022.

A second terminal of the logic control circuit 2022 is electrically connected to the control device 206.

During the capacitance conversion process, the lower plate of the capacitor to be calibrated of the capacitor array 201 is connected to a high-potential reference voltage

The low-level capacitor and the redundant capacitor are connected to a low-level reference voltage

. Then, the comparator 2021 compares the voltage output by the capacitor array 201

And, the first output bit can be obtained

And output to the logic control circuit 2022 for temporary storage.

And continuously repeating the comparison and charge redistribution processes until the last digital code is obtained, thus obtaining a capacitance conversion array and completing the capacitance conversion process once.

In the embodiment, through the comparator and the logic control circuit, a plurality of capacitance conversion arrays are determined in the process of multiple capacitance conversion, and the accuracy of the conversion process is improved.

As shown in fig. 7, an embodiment of the present application further provides a test apparatus, where the test apparatus includes: the successive approximation analog-to-digital converter 20 and the sampling power supply 30 are provided in any one of the foregoing embodiments, and the output terminal of the sampling power supply 30 is electrically connected to the input terminal of the successive approximation analog-to-digital converter 20.

The sampling power supply 30 is used for outputting the sampling voltage to the successive approximation analog-to-digital converter 20.

The sampling power supply 30 may be a source for providing a sampling voltage

The device of (1) may be a battery or other forms of power source, and the application is not limited herein.

The successive approximation analog-to-digital converter 20 is configured to estimate a voltage value of the sampled voltage after determining and calibrating a capacitance weight value of each capacitor of the capacitor array.

The successive approximation analog-to-digital converter 20 may be a successive approximation analog-to-digital converter structure provided in the foregoing embodiment, and after the capacitance mismatch error is determined and calibrated by the successive approximation analog-to-digital converter 20 in the manner provided in the foregoing embodiment, the capacitance mismatch error may be used to sample the sampling voltage output by the sampling power supply 30

Sampling and estimation are performed.

As shown in fig. 8, an embodiment of the present application further provides a capacitance weight value calibration method, which is applied to the successive approximation analog-to-digital converter provided in the foregoing embodiment, and the method includes the following steps:

s401, after capacitance conversion is carried out on the capacitor array, the capacitor array outputs a capacitance conversion array of the capacitor to be calibrated in the capacitor array to the control device through the logic comparison device, and the capacitor array outputs the residual difference of the capacitor to be calibrated to the residual difference amplifier.

As described in the foregoing embodiments, the capacitor to be calibrated in the capacitor array is first connected to the high-potential reference voltage

And performing capacitance conversion to obtain a capacitance conversion array of the capacitor to be calibrated and a residual difference of the capacitor to be calibrated.

S402, the residual difference amplifier receives the residual difference of the capacitor to be calibrated output by the capacitor array, amplifies the residual difference of the capacitor to be calibrated, and outputs the capacitor conversion residual difference to the load capacitor.

The capacitance conversion residual difference and the capacitance conversion array have a one-to-one correspondence relationship.

Further, the residual error amplifier can amplify the residual error of the capacitor to be calibrated by a preset multiple to obtain a capacitor conversion residual error and store the capacitor conversion residual error to the load capacitor.

And S403, storing the capacitance conversion residual difference by the load capacitor, and connecting the capacitance conversion residual difference back to the capacitor array.

After the load capacitor stores the capacitance conversion residual difference, the load capacitor is connected back to the capacitor array, and as described in the foregoing embodiment, the value of the capacitance conversion array is corrected in the next capacitance conversion process.

S404, repeating the steps until reaching the preset times to obtain a plurality of capacitance conversion arrays.

In the present embodiment, the preset number may be any one of larger numbers, and exemplarily, the preset number may be 512 times.

S405, determining a capacitance weight value of the capacitor to be calibrated according to the plurality of capacitance conversion arrays by the control device.

After each capacitance conversion, the capacitance array receives one capacitance conversion array through the logic comparison device, and a plurality of capacitance conversion arrays are obtained after the preset times are repeated. Optionally, the control device may determine the capacitance weight value of the capacitance to be calibrated by performing an averaging process on the plurality of capacitance conversion arrays.

In this embodiment, the residual error of the capacitor conversion is received back to the capacitor array through the residual error amplifier and the load capacitor to correct the output value of the capacitor conversion array, and the capacitance weight value of the capacitor to be calibrated is determined through the plurality of capacitor conversion arrays. The influence of capacitance mismatch in the capacitance conversion process is eliminated, and the capacitance mismatch error of the analog-to-digital converter is calibrated, so that the conversion precision of the successive approximation type analog-to-digital converter is improved.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A successive approximation analog-to-digital converter, comprising: the circuit comprises a capacitor array, a logic comparison device, a residual error amplifier, a unit capacitor, a load capacitor and a control device;

the load capacitor is used for storing the plurality of capacitance conversion residual differences, connecting the plurality of capacitance conversion residual differences back to the capacitor array and correcting the plurality of capacitance conversion arrays;

2. The successive approximation analog-to-digital converter of claim 1, wherein the capacitor array comprises: the capacitor comprises a high-order capacitor, a low-order capacitor and a redundant capacitor which are connected with each other, wherein the redundant capacitor is the redundant capacitor of any one-order capacitor in the low-order capacitor;

3. The successive approximation analog-to-digital converter according to claim 1, wherein said control means is specifically configured to:

4. The successive approximation analog-to-digital converter of claim 1, further comprising: the load switch is electrically connected with the capacitor array, the load capacitor and the control device respectively;

5. The successive approximation analog-to-digital converter of claim 1, further comprising: a first amplifier switch and a second amplifier switch;

6. The successive approximation analog-to-digital converter according to claim 2, wherein the high-side capacitor, the low-side capacitor and the redundant capacitor all determine whether one of the high-side capacitors is used as the capacitor to be calibrated through a three-pole switch.

7. The successive approximation analog-to-digital converter according to claim 6, wherein the capacitor array is connected to a high potential reference voltage, a common mode potential reference voltage and a low potential reference voltage through the three-pole switch, respectively.

8. The successive approximation analog-to-digital converter of claim 5, further comprising: a unit capacitor switch;

9. The successive approximation analog-to-digital converter according to claim 1, wherein said logic comparing means comprises: a comparator and logic control circuit;

10. A test apparatus, characterized in that the test apparatus comprises: the successive approximation analog-to-digital converter of any one of claims 1 to 9 and a sampling power supply, an output of the sampling power supply being electrically connected to an input of the successive approximation analog-to-digital converter;

11. A method for calibrating capacitance weight value, applied to a successive approximation analog-to-digital converter according to any one of claims 1 to 9, the method comprising:

repeating the steps until reaching a preset number of times to obtain a plurality of capacitance conversion arrays;