JP2019083083A - Shift register - Google Patents

Abstract

To suppress stress on a transistor while suppressing occurrence of malfunction.SOLUTION: There is provided a pulse output circuit having a function of outputting a pulse signal and having a transistor controlling whether or not to set the pulse signal to a high level, in which a potential of one of a source and a drain of the transistor is set to be higher than a low level potential of a clock signal and set to be higher than a high level potential of the clock signal, during a period when the pulse signal outputted from the pulse output circuit is a low level signal, thereby suppressing stress on the transistor.SELECTED DRAWING: Figure 1

Description

The present invention relates to a pulse output circuit. Furthermore, the present invention relates to a display device. Furthermore, the present invention relates to an electronic device.

In recent years, for the purpose of simplification of a manufacturing process, development of a circuit (also referred to as a unipolar circuit) in which all transistors have the same conductivity type has been advanced.

An example of the unipolar circuit is a pulse output circuit that constitutes a shift register.

For example, Patent Document 1 discloses a shift register including a plurality of pulse output circuits in which pulses of a clock signal are used to generate pulses of the pulse signal. Furthermore, Patent Document 1 discloses a shift register that suppresses a reduction in the amplitude of a pulse signal to be output with respect to the amplitude of a clock signal by using a bootstrap.

JP 2002-335153 A

However, in the configuration of the conventional pulse output circuit, if the amplitude of the clock signal is large, the transistor is degraded, and there is a problem that the electrical characteristics of the transistor are fluctuated.

For example, in the shift register of Patent Document 1, a transistor that controls whether or not to set the pulse signal to be output to a high level when the pulse signal to be output from the pulse output circuit is at a low level (for example, FIG. The potential of the gate of the transistor 15) of (B) is the potential VS
S is held for a fixed period. At this time, since the potential of the source or the drain of the transistor repeatedly changes in accordance with the clock signal, the transistor is stressed. This degrades the transistor. In particular, in the shift register of Patent Document 1, since the time during which the stress is applied is very long, the transistor is easily deteriorated, and the fluctuation of the electrical characteristics proceeds.

In order to suppress the influence of the above-mentioned stress given to the transistor, for example, measures such as lengthening the channel length of the transistor can be mentioned. However, if the channel length of the transistor that controls whether or not to set the pulse signal to be output to a high level is increased, the pulse signal to be output is delayed due to, for example, parasitic capacitance, and the possibility of malfunction may increase. Another problem arises.

In view of the above problems, in one embodiment of the present invention, it is an object to suppress stress on a transistor that controls whether or not a pulse signal to be output is set to a high level while suppressing occurrence of operation failure. .

In one aspect of the present invention, during a period in which the pulse signal output from the pulse output circuit is at a low level,
The potential of one of the source and the drain of the transistor for controlling whether or not the pulse signal is set to the high level is made lower than the potential of the high level of the clock signal. Thus, stress on the transistor is suppressed.

One embodiment of the present invention has a function of generating a pulse signal in accordance with a set signal, a reset signal, and a clock signal, and one of the source and the drain changes in accordance with the clock signal.
And one of the source and the drain is electrically connected to the other of the source and the drain of the first transistor, the other potential of the source and the drain is the potential of the pulse signal, and the potential of the gate is the set signal and the reset signal A second transistor that varies according to
One of the source and the drain is supplied with a first potential, the other of the source and the drain is electrically connected to the other of the source and the drain of the second transistor, and is turned on or off depending on the potential of the gate. To control whether the pulse signal is set low or not, the second potential is applied to one of the source and the drain, and the other of the source and the drain is electrically supplied to the gate of the first transistor. And the fourth transistor whose gate potential changes according to the set signal and the reset signal, the potential of one of the source and the drain changes according to the set signal and the reset signal, and the other of the source and the drain is the first A fifth transistor electrically connected to the gate of the second transistor, the potential of the gate changing according to the set signal, The first to fifth transistors have the same conductivity type, and the second potential is higher than the low level potential of the clock signal and lower than the high level potential of the clock signal; The potential difference between the potential of the clock signal and the low level of the clock signal is a pulse output circuit which is larger than the threshold voltage of the first transistor.

According to one embodiment of the present invention, stress on a transistor can be reduced without increasing the channel length of the transistor which controls whether to set a pulse signal to be output to a high level. Therefore, deterioration of the transistor can be suppressed, and fluctuation of electrical characteristics can be suppressed.

FIG. 6 is a diagram for illustrating an example of a pulse output circuit. FIG. 6 is a diagram for illustrating an example of a pulse output circuit. FIG. 6 is a diagram for illustrating an example of a pulse output circuit. FIG. 6 is a diagram for illustrating an example of a pulse output circuit. FIG. 6 is a diagram for illustrating an example of a pulse output circuit. FIG. 6 is a diagram for illustrating an example of a pulse output circuit. FIG. 6 illustrates an example of a display device. FIG. 6 illustrates an example of a display device. FIG. 6 illustrates an example of a display device. FIG. 6 illustrates an example of a display device. FIG. 6 illustrates an example of an electronic device.

An example of an embodiment according to the present invention will be described. Those skilled in the art can easily change the contents of the embodiment without departing from the spirit and scope of the present invention. Thus, for example, the present invention is not limited to the contents described in the following embodiments.

The contents of the embodiments can be combined with one another as appropriate. In addition, the contents of each embodiment can be replaced with each other as appropriate.

Also, the first and second ordinal numbers are attached to avoid confusion of components, and the number of each component is not limited to the ordinal numbers.

In the present specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "vertical" means that two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore,
The case of 85 ° or more and 95 ° or less is also included.

In the present specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

Embodiment 1
In this embodiment, an example of a pulse output circuit is described.

FIG. 1 is a diagram for explaining an example of a pulse output circuit according to the present embodiment. The pulse output circuit SR has a function of generating a pulse signal (output signal OUT) in accordance with the input set signal S, reset signal R, and clock signal CK as shown in FIG. 1 (A). A plurality of clock signals may be input to the pulse output circuit SR.

Further, the pulse output circuit SR illustrated in FIG. 1A includes the transistors 11 to 15 as illustrated in FIG. For example, the transistors 11 to 15
Are of the same conductivity type. The conduction of each of the transistors 11 to 15 is controlled in accordance with one or more of the set signal S, the reset signal R, and the clock signal CK. Note that the pulse output circuit SR shown in FIG.
Elements other than the above may be provided.

The potential of one of the source and the drain of the transistor 11 changes in accordance with the clock signal CK. The transistor 11 has a function of controlling the high level potential of the pulse signal (output signal OUT). For example, the transistor 11 has a function of controlling whether the pulse signal (the output signal OUT) is to be the first high level or not and the second high level.
At this time, the second high level potential is smaller than the first high level potential.

Note that "the potential changes according to the signal" is not limited to "when the potential changes to the potential of the signal when the signal is directly input". For example, "when the potential changes when the switch is turned on according to the signal" or "when the potential changes according to the signal change due to capacitive coupling", etc. included.

In addition, the “potential according to the signal” is not limited to “the potential of the same value as the potential of the signal”.
For example, a value obtained by changing the potential of a signal due to a voltage drop is also included in the “potential corresponding to the signal”.

One of the source and the drain of the transistor 12 is electrically connected to the other of the source and the drain of the transistor 11, and the other potential is the potential of the pulse signal (the output signal OUT). Furthermore, the potential of the gate of the transistor 12 changes in accordance with the set signal S and the reset signal R. The transistor 12 has a function of controlling whether or not the pulse signal (output signal OUT) is set to the high level.

One of the source and the drain of the transistor 13 is supplied with the potential VSS, and the other is electrically connected to the other of the source and the drain of the transistor 12. Further, the potential of the gate of the transistor 13 changes in accordance with the set signal S and the reset signal R. Note that the potential of the gate of the transistor 13 may be controlled by a clock signal different from the clock signal CK. The transistor 13 has a function of controlling whether or not the pulse signal (output signal OUT) is set to a low level by being turned on or off in accordance with the potential of the gate.

The potential Va is applied to one of the source and the drain of the transistor 14, and the other is electrically connected to the gate of the transistor 11. Further, the potential of the gate of the transistor 14 changes in accordance with the set signal S and the reset signal R, or changes in accordance with the clock signal CK. The transistor 14 has a function of controlling whether or not the potential of the gate of the transistor 11 is set to a value corresponding to the potential Va.

The “value corresponding to the potential” is not limited to “the same value as the potential”. For example, also when it changes from the value of the said electric potential by a voltage drop, it is contained in "the value according to the electric potential."

The potential of one of the source and the drain of the transistor 15 changes in accordance with the set signal S and the reset signal R, and the other is electrically connected to the gate of the transistor 11. Furthermore, the potential of the gate of the transistor 15 changes in accordance with the set signal S. The transistor 15 is
It has a function of controlling whether or not the gate of the transistor 11 is in a floating state.

As the transistors 11 to 15, for example, a transistor including a semiconductor having a wider band gap than silicon in a channel formation region can be used. As a semiconductor having a wide band gap, an oxide semiconductor can be used, for example. However, the present invention is not limited thereto. For example, a transistor including a semiconductor having an element of Group 14 (such as silicon) may be used as the transistor 1
You may use for 1 thru | or the transistor 15. FIG. At this time, the semiconductor having a Group 14 element may be single crystal, polycrystal or amorphous.

As the oxide semiconductor, an In-based metal oxide, a Zn-based metal oxide, an In-Zn-based metal oxide, an In-Ga-Zn-based metal oxide, or the like can be used, for example. Also, the above In-G
A metal oxide containing another metal element instead of part or all of Ga contained in the a-Zn-based metal oxide may be used.

Hereinafter, the structure of the oxide semiconductor film is described.

Oxide semiconductor films are roughly classified into single crystal oxide semiconductor films and non-single crystal oxide semiconductor films. The non-single crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a CAAC-OS (C Axis Aligned Crystalline).
Oxide Semiconductor) film etc.

The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal component. An oxide semiconductor film which does not have a crystal part even in a minute region and has a completely amorphous structure is typical.

The microcrystalline oxide semiconductor film includes, for example, microcrystalline (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm. Thus, the microcrystalline oxide semiconductor film has higher regularity in atomic arrangement than an amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film is characterized in that the density of defect states is lower than that of an amorphous oxide semiconductor film.

The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts fit inside a cube whose one side is less than 100 nm. Therefore, CAAC-O
The crystal part included in the S film is also included in the case where one side is smaller than 10 nm, less than 5 nm, or smaller than 3 nm. The CAAC-OS film is characterized in that the density of defect states is lower than that of a microcrystalline oxide semiconductor film. Hereinafter, the CAAC-OS film is described in detail.

CAAC-OS film as a transmission electron microscope (TEM: Transmission Elect)
When observed with a ron microscope, it is not possible to confirm a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary). Therefore, CA
It can be said that in the AC-OS film, the decrease in electron mobility due to grain boundaries is unlikely to occur.

When the CAAC-OS film is observed by TEM from a direction substantially parallel to the sample surface (cross-sectional TEM observation), it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape (also referred to as a formation surface) on which the CAAC-OS film is to be formed (also referred to as a formation surface) or a shape reflecting the unevenness of the top surface, and is arranged parallel to the formation surface or top surface of the CAAC-OS film .

On the other hand, the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (planar TE
M observation), it can be confirmed that the metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

From the cross-sectional TEM observation and the planar TEM observation, it is found that the crystal part of the CAAC-OS film has orientation.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis points in a direction substantially perpendicular to the formation surface or the top surface. It can be confirmed that

On the other hand, in-pl, in which X-rays are made incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis
In the analysis by the ane method, a peak may appear when 2θ is around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of an InGaZnO ₄ single crystal oxide semiconductor film, analysis (φ scan) is performed while fixing 2θ at around 56 ° and rotating the sample with the normal vector of the sample surface as the axis (φ axis), Six peaks attributed to crystal planes equivalent to the 110) plane are observed. On the other hand, in the case of a CAAC-OS film, 2θ is 5
Even in the case of? Scan fixed at around 6 °, a clear peak does not appear.

From the above, in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal parts, but the c-axis has c-axis orientation and the c-axis is a normal to the formation surface or the top surface It turns out that it is pointing in the direction parallel to the vector. Therefore, each layer of the metal atoms arranged in a layer, which is confirmed by the above-mentioned cross-sectional TEM observation, is a plane parallel to the ab plane of the crystal.

Note that the crystal part is formed when a CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film.

In addition, the degree of crystallinity in the CAAC-OS film may not be uniform. For example, in the case where the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, the region in the vicinity of the top surface has higher crystallinity than the region in the vicinity of the formation surface is there. Also, CAA
When an impurity is added to the C-OS film, the degree of crystallization of the region to which the impurity is added may change, and a region with a partially different degree of crystallinity may be formed.

Note that in the analysis by a out-of-plane method of a CAAC-OS film having an InGaZnO ₄ crystal, in addition to the peak at 2θ of around 31 °, the peak may also appear at around 36 ° of 2θ. The peak at 2θ of around 36 ° indicates that a part of the CAAC-OS film contains a crystal having no c-axis alignment. It is preferable that the CAAC-OS film has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

The transistor including the CAAC-OS film has less variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Thus, the transistor is highly reliable.

Note that the oxide semiconductor film is, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or CA.
Among the AC-OS films, a laminated film having two or more types may be used.

The above is the description of the structure of the oxide semiconductor film.

Furthermore, a configuration example of the pulse output circuit according to the present embodiment will be described with reference to FIG.

The pulse output circuit shown in FIG. 2A includes a set signal LIN corresponding to the set signal S, a reset signal RIN corresponding to the reset signal R, clock signals CK1 to CK3,
And a function of generating and outputting a pulse signal (output signal OUT) according to the initialization signal RES. Note that the initialization signal RES may not necessarily be used.

The pulse output circuit illustrated in FIG. 2A includes transistors 61 to 76.

The potential VDD is applied to one of the source and the drain of the transistor 61. further,
The set signal LIN is input to the gate of the transistor 61.

One of the source and the drain of the transistor 62 is supplied with the potential VSS, and the other is electrically connected to the other of the source and the drain of the transistor 61.

One of the source and the drain of the transistor 63 is electrically connected to the other of the source and the drain of the transistor 61. Further, the gate of the transistor 63 is connected to the set signal L.
IN is input. The transistor 63 corresponds to the transistor 15 illustrated in FIG.

One of the source and the drain of the transistor 64 is electrically connected to the other of the source and the drain of the transistor 61. Further, the potential VDD is applied to the gate of the transistor 64.

Note that the transistor 64 may not necessarily be provided.

The clock signal CK1 is input to one of the source and the drain of the transistor 65.
Further, the gate of the transistor 65 is electrically connected to the other of the source and the drain of the transistor 63. The transistor 65 corresponds to the transistor 11 illustrated in FIG.

One of the source and the drain of the transistor 66 is electrically connected to the other of the source and the drain of the transistor 65, and the other potential is the potential of the pulse signal (the output signal OUT). The transistor 66 corresponds to the transistor 12 illustrated in FIG.

Furthermore, a capacitance C1 is formed between the gate of the transistor 65 and the other of the source and the drain of the transistor 66. The capacitance C1 may not necessarily be formed.

In addition, a capacitance C2 is formed between the gate of the transistor 66 and the other of the source and the drain of the transistor 66. Note that a parasitic capacitance between the gate of the transistor 66 and the other of the source and the drain may be used for the capacitor C2. The capacitance C2 may not necessarily be formed.

The potential VSS is applied to one of the source and the drain of the transistor 67, and the other is electrically connected to the other of the source and the drain of the transistor 66. The transistor 67 corresponds to the transistor 13 illustrated in FIG.

The clock signal CK1 is input to one of the source and the drain of the transistor 68.
Furthermore, the gate of the transistor 68 is electrically connected to the other of the source and the drain of the transistor 63.

One of the source and the drain of the transistor 69 is electrically connected to the other of the source and the drain of the transistor 68, and the other potential is the potential of the pulse signal (output signal SROUT). Further, the gate of the transistor 69 is electrically connected to the other of the source and the drain of the transistor 64.

Furthermore, a capacitance C3 is formed between the gate of the transistor 68 and the other of the source and drain of the transistor 69. The capacitance C3 may not necessarily be formed.

In addition, a capacitor C4 is formed between the gate of the transistor 69 and the other of the source and the drain of the transistor 69. Note that a parasitic capacitance between the gate of the transistor 69 and the other of the source and the drain may be used for the capacitor C4. The capacitance C4 may not necessarily be formed.

The potential VSS is applied to one of the source and the drain of the transistor 70, and the other is electrically connected to the other of the source and the drain of the transistor 69. Further, the gate of the transistor 70 is electrically connected to the gate of the transistor 62.

Note that the transistors 68 to 70 may not necessarily be provided.

The potential Va is applied to one of the source and the drain of the transistor 71, and the other is electrically connected to the gate of the transistor 65 and the gate of the transistor 68. Further, the potential of the gate of the transistor 71 changes in accordance with the set signal LIN, the reset signal RIN, the initialization signal RES, the clock signal CK2, and the clock signal CK3. Transistor 7
Reference numeral 1 corresponds to the transistor 14 shown in FIG.

One of the source and the drain of the transistor 72 is supplied with the potential VDD, and the other is electrically connected to the gate of the transistor 67 and the gate of the transistor 70. further,
The reset signal RIN is input to the gate of the transistor 72.

The potential VDD is applied to one of the source and the drain of the transistor 73, and the other is electrically connected to the gate of the transistor 67 and the gate of the transistor 70. further,
The initialization signal RES is input to the gate of the transistor 72.

The potential VSS is applied to one of the source and the drain of the transistor 74, and the other is electrically connected to the gate of the transistor 67 and the gate of the transistor 70. further,
The set signal LIN is input to the gate of the transistor 74.

The potential VDD is applied to one of the source and the drain of the transistor 75. further,
The clock signal CK3 is input to the gate of the transistor 75.

One of the source and the drain of the transistor 76 is electrically connected to the other of the source and the drain of the transistor 75, and the other is the gate of the transistor 67 and the transistor 70.
Electrically connected to the gate of Further, the clock signal CK2 is input to the gate of the transistor 76.

The potential VSS is applied to one of the pair of electrodes of the capacitor C5, and the other is electrically connected to the gate of the transistor 71. The capacitance C5 has a function as a holding capacitance. The capacitance C5 may not necessarily be provided.

As the transistors 61 to 76, for example, transistors including the above-described oxide semiconductor in a channel formation region can be used.

Next, as an example of a method of driving the pulse output circuit according to this embodiment, an example of a method of driving the pulse output circuit illustrated in FIG. 2A will be described with reference to a timing chart of FIG.
Here, as an example, each of the transistors 61 to 76 is an n-channel transistor, the potential VDD is a positive potential, the potential VSS is a negative potential, and the value of the potential Va is (VDD + VSS) / 2. Explain as. Further, the high level potentials of the set signal LIN, the reset signal RIN, and the clock signals CK1 to CK3 have a potential V
The low level potential is the same as DD, and is the same as the potential VSS. Further, the threshold voltage of the transistor 65 and the threshold voltage of the transistor 68 are the same. Further, the threshold voltage of the transistor 66 and the threshold voltage of the transistor 69 are the same. Further, it is assumed that the potential difference between the potential Va and the low level potential of the clock signal CK1 is larger than the threshold voltage of the transistor 65. Further, before the period T1, the pulse of the initialization signal RES is input, the transistor 73 is turned on, and the transistors 67, 70, and 71 are turned on to initialize the pulse output circuit. It is also good. Further, a connection point between the gate of the transistor 66 and the other element is a node NA, a connection point between the gate of the transistor 67 and the other element is a node NB, and a connection point between the gate of the transistor 65 and the other element is a node Let NC be a connection point of the other of the source and drain of the transistor 65 and one of the source and drain of the transistor 66 be a node ND.

In the present specification, the potential VSS means at least two potentials required to operate the circuit.
Of the two power supply potentials, it is the lower one. The higher one of the two power supply potentials is the potential VDD.

In the driving method example of the pulse output circuit shown in FIG. 2A, the set signal LIN becomes high level in the period T1 of FIG. 2B, and the transistor 72 and the transistor 74 are turned on. Further, since the reset signal RIN is at the low level, the transistor 72 is turned off. Further, since the clock signal CK1 to the clock signal CK3 are at low level, the transistor 75 and the transistor 76 are turned off.

At this time, the potential of the node NC rises to a value equal to the potential VDD, the transistors 65 and 68 are turned on, and the potential of the node ND becomes a value corresponding to the low level potential of the clock signal CK1. Furthermore, the transistor 63 is turned off. Further, the potential of the node NA rises to a value equal to the potential VDD, and the transistors 66 and 69 are turned on. Furthermore, the transistor 64 is turned off. Output signal OU at this time
T, the output signal SROUT is at low level. Thus, the pulse output circuit illustrated in FIG. 2A is in the set state.

Next, in the period T2, since the set signal LIN remains at the high level, the transistor 61 and the transistor 74 remain in the on state. Also, the clock signal CK1 becomes high level. Further, since the reset signal RIN, the clock signal CK2, and the clock signal CK3 remain at the low level, the transistor 72, the transistor 75, the transistor 76
Remains off.

At this time, the transistor 62, the transistor 67, the transistor 70, the transistor 71
Remains off. Furthermore, the transistors 65 and 66 remain on, and the capacitive coupling generated by the capacitance C1 and the capacitance C2 causes the nodes NA and N
The potential of C rises to a value higher than the sum of the potential VDD and the threshold voltage (Vth65) of the transistor 65, that is, VDD + Vth65 + Vx (Vx is an arbitrary value). As a result, the potential of the output signal OUT becomes equal to the high level potential of the clock signal CK1. Also, transistor 68 and transistor 69 remain on, and output signal S
The potential of ROUT is equal to the high level potential of the clock signal CK1.

Next, in a time period T3, the set signal LIN goes low, and the transistors 61, 72, and 74 are turned off. Also, the clock signal CK1 remains at high level. In addition, the clock signal CK2 becomes high level, and the transistor 76 is turned on. In addition, since the reset signal RIN and the clock signal CK3 remain at low level, the transistor 72 and the transistor 75 remain in the off state.

At this time, the transistor 62, the transistor 67, the transistor 70, the transistor 71
Remains in the off state. Further, the voltage between the gate and drain of the transistor 66 and the transistor 69 is maintained at VDD + Vx, and the potentials of the output signal OUT and the output signal SROUT remain equal to the high level potential of the clock signal CK1. Therefore, the output signal OUT and the output signal SROUT maintain the high level.

Next, in a period T4, the reset signal RIN becomes high level, and the transistor 72 is turned on. Also, the clock signal CK1 becomes low level. Also, clock signal C
Since K2 remains high, transistor 76 remains high. Further, the clock signal CK3 becomes high level, and the transistor 75 is turned on. Also,
Since the set signal LIN remains low, the transistors 61 and 63
, Transistor 74 remains off.

At this time, the potential of the node NB becomes equal to the potential VDD, and the transistor 62, the transistor 67, the transistor 70, and the transistor 71 are turned on. Also, node NC
The potential of the transistor 65 becomes a value corresponding to the potential Va, and the transistors 65 and 68 remain in the on state. In addition, when the potential of the node NA becomes a value corresponding to the potential VSS, the transistors 66 and 69 are turned off. Therefore, the potential of the node ND has a value corresponding to the low level potential of the clock signal CK1. Therefore, the potentials of the output signal OUT and the output signal SROUT become values corresponding to the low level potential of the clock signal CK1, and the output signal OUT and the output signal SROUT become low level. As a result, the pulse output circuit shown in FIG. 2A is in the reset state.

Next, in the period T5, the reset signal RIN remains high, so the transistor 72 remains on. In addition, the clock signal CK2 becomes low level, and the transistor 76 is turned off. In addition, since the clock signal CK3 remains high, the transistor 75 remains on. Further, since the set signal LIN and the clock signal CK1 remain at the low level, the transistors 61, 63, and 74 remain in the off state.

At this time, the potential of the node NB remains at a value corresponding to the potential VDD.
The transistors 67, 70, and 71 remain on. Further, the potential of the node NC remains at the same value as the potential Va, and the transistor 65 and the transistor 68 remain on. Further, since the potential of the node NA remains equal to the potential VSS, the transistors 66 and 69 remain off. Therefore, the potential of the node ND becomes equal to the potential of the low level of the clock signal CK1. Therefore, the potentials of the output signal OUT and the output signal SROUT become the same value as the low level potential of the clock signal CK1, and the output signal OUT and the output signal SROUT become low level.

Next, in a period T6, the reset signal RIN becomes low level, and the transistor 72 is turned off. Also, the clock signal CK1 becomes high level. Also, clock signal C
K3 goes low, and the transistor 75 is turned off. Furthermore, the set signal LI
N. Since the clock signal CK2 remains at the low level, the transistors 61, 63, and 74 remain in the off state.

At this time, the potential of the node NB remains at the same value as the potential VDD.
2. The transistor 67, the transistor 70, and the transistor 71 remain on.
Further, since the potential of the node NC remains at the same value as the potential Va, the transistor 65 and the transistor 68 remain on. Further, since the potential of the node NA remains equal to the potential VSS, the transistors 66 and 69 remain off. Further, since the potential of the gate of the transistor 65 is a potential Va lower than the potential VDD, the potential of the node ND is Va-Vth65. This is higher than the low level potential of the clock signal CK1 and lower than the high level potential. Further, the potentials of the output signal OUT and the output signal SROUT have values equivalent to the low level of the clock signal CK1. As shown in the period T4 to the period T6, when the output signal OUT and the output signal SROUT are at low level, the potential of the node ND is higher than the potential VSS and the low level of the clock signal CK1.
It alternately changes to Va-Vth65 lower than the high level potential. Therefore, stress on the transistor can be suppressed as compared to the case where the potential of the drain of the transistor 66 is alternately changed to the potential VDD and the potential VSS.

The above is the description of the pulse output circuit illustrated in FIG.

The configuration of the pulse output circuit according to the present embodiment is not limited to the above configuration, and may be another configuration.

For example, instead of electrically connecting the gate of the transistor 62 of the pulse output circuit shown in FIG. 2B to the other of the source and the drain of the transistor 72, the pulse output circuit shown in FIG. A reset signal RIN is input to the gate. Thus, when the pulse output circuit is reset, the speed at which the potential of the node NA is set to a value equal to the potential VSS can be increased.

Also, as shown in FIG. 3B, the transistor 64 of the pulse output circuit shown in FIG.
The transistors 68, 69, 70, 73, 75, and 76 may not necessarily be provided.

Further, as shown in FIG. 4, a back gate may be provided for each of the transistors 62 to 76, and the threshold voltage of the transistors 62 to 76 may be controlled by controlling the potential of the back gate. For example, when a negative potential is applied to the back gate of the n-channel transistor, the threshold voltage of the n-channel transistor can be shifted in the positive direction. In the pulse output circuit illustrated in FIG. 4, the transistor 61, the transistor 64, the transistor 72, the transistor 73, the transistor 75, and the transistor 7 are included.
A potential BG1 is applied to each of the back gates 6 and a potential BG2 is applied to each of the back gates of the transistor 62, the transistor 63, the transistors 65 to 71, and the transistor 74. Note that in the case of using a negative potential as the potential BG1 and the potential BG2, the value of the potential BG2 is preferably lower than the potential BG1. Potential BG
This is because if the threshold voltage of the transistor supplied with 1 is too high, malfunction of the pulse output circuit is likely to occur.

Note that a back gate may be provided for the transistor in the structure shown in FIG. 3A or 3B as well.

Further, an example of a shift register including a plurality of pulse output circuits illustrated in FIG. 2A will be described with reference to FIG.

The shift register 30 shown in FIG. 5A includes a plurality of pulse output circuits (pulse output circuits 31).
_1 to pulse output circuit 31_N (N is a natural number of 2 or more). FIG. 5A shows the case of N = 4 or more as an example.

Each of the pulse output circuits 31_1 to 31_N corresponds to the pulse output circuit illustrated in FIG. The pulse output circuits 31_1 to 31_N are shown in FIG.
As shown in (B), according to the set signal LIN, the reset signal RIN, the initialization signal RES, the clock signal CK1, the clock signal CK2, and the clock signal CK3, the output signal OUT
, Has a function of generating and outputting a plurality of pulse signals as the output signal SROUT.

The start pulse signal SP is input to the pulse output circuit 31_1 as the set signal LIN. Further, a pulse signal (output signal SROU) output from the pulse output circuit 31_K-1 as the set signal LIN to the pulse output circuit 31_K (K is a natural number not less than 2 and not more than N) is output.
T) is input.

A pulse signal (output signal SROUT) output from the pulse output circuit 31_M + 2 is input as the reset signal RIN to the pulse output circuit 31_M (M is a natural number less than or equal to N-1).

Further, the pulse output circuit 31_1 receives the clock signal CLK1 as the clock signal CK1.
Is input, the clock signal CLK2 is input as the clock signal CK2, and the clock signal CLK3 is input as the clock signal CK3. Furthermore, with reference to the pulse output circuit 31_1, the clock signal CLK is used as the clock signal CK1 for every third pulse output circuit.
1 is input, the clock signal CLK2 is input as the clock signal CK2, and the clock signal CLK3 is input as the clock signal CK3.

Furthermore, the pulse output circuit 31_2 receives the clock signal CLK2 as the clock signal CK1.
Is input, the clock signal CLK3 is input as the clock signal CK2, and the clock signal CLK4 is input as the clock signal CK3. Furthermore, with reference to the pulse output circuit 31_2, the clock signal CLK is used as the clock signal CK1 for every three pulse output circuits.
2 is input, the clock signal CLK3 is input as the clock signal CK2, and the clock signal CLK4 is input as the clock signal CK3.

Further, the pulse output circuit 31_3 receives the clock signal CLK3 as the clock signal CK1.
Is input, the clock signal CLK4 is input as the clock signal CK2, and the clock signal CLK1 is input as the clock signal CK3. Furthermore, with the pulse output circuit 31_3 as a reference, the clock signal CLK is used as the clock signal CK1 for every third pulse output circuit.
3 is input, the clock signal CLK4 is input as the clock signal CK2, and the clock signal CLK1 is input as the clock signal CK3.

The clock signal CLK4 is input as the clock signal CK1 to the pulse output circuit 31_4, the clock signal CLK1 is input as the clock signal CK2, and the clock signal CLK2 is input as the clock signal CK3. Furthermore, with reference to the pulse output circuit 31_4, the clock signal CLK4 is input as the clock signal CK1 every three pulse output circuits, the clock signal CLK1 is input as the clock signal CK2, and the clock signal CK3 is generated.
The clock signal CLK2 is input as In FIG. 5A, as an example, the clock signal CK1 and the clock signal CK2 which are input to the pulse output circuit 31_N + 2, and the clock signal CK1 and the clock signal CK2 which are input to the pulse output circuit 31_4. , And the clock signal CK3.

Further, each configuration of the pulse output circuit 31_N + 1 and the pulse output circuit 31_N + 2 is a configuration without the transistor 72 in the configuration of the pulse output circuit shown in FIG. Pulse signal (output signal SROUT_N + 1 output from the pulse output circuit 31_N + 1
) Is input to the pulse output circuit 31_N-1 as a reset signal RIN. The pulse signal (output signal SROUT_N + 2) output from the pulse output circuit 31_N + 2 is
The pulse output circuit 31_N is input as the reset signal RIN. A pulse signal generated separately may be input to the pulse output circuit 31_N-1 and the pulse output circuit 31_N without providing the pulse output circuit 31_N + 1 and the pulse output circuit 31_N + 2. Also, the output signal OUT_N + 1 and the output signal OUT_N + 2 may not necessarily be output.

Further, an initialization signal INI_RES is input as an initialization signal RES to each of the pulse output circuits 31_1 to 31_N + 2.

Next, an example of a method of driving the shift register 30 shown in FIG. 5A will be described with reference to a timing chart of FIG. Here, as an example, the potential VDD is a positive potential, the potential VSS is a negative potential, and the potential Va is (VDD + VSS) / 2. Also, as an example, the set signal LIN, the reset signal RIN, and the clock signal CL
The high level potentials of the clock signals K1 to CLK4 are the same as the potential VDD, and the low level potential is the same as the potential VSS. Also, as an example, clock signal CLK
It is assumed that the duty ratio of 1 to the clock signal CLK4 is 50%. Also, as an example,
It is assumed that the clock signal CLK2 is delayed by 1/4 cycle from the clock signal CLK1, and the clock signal CLK3 is delayed by 1/4 cycle from the clock signal CLK2. The clock signal CLK4 is 1/4 of the clock signal CLK3. It is assumed that the period is delayed. Further, as an example, it is assumed that the pulse width of the start pulse signal SP is the same as the pulse width of the clock signals CLK1 to CLK4. In addition, before each pulse output circuit is in the set state, the pulse of the initialization signal INI_RES is input to initialize the pulse output circuit.

As shown in FIG. 5C, in the shift register 30 shown in FIG. 5A, when the start pulse signal SP becomes high at time T11, the clock signal CLK1 becomes high at time T12. Further, the shift register 30 sequentially outputs the pulses of the output signals SROUT_1 to SROUT_N according to the clock signals CLK1 to CLK4, and sequentially outputs the pulses of the output signals OUT_1 to OUT_N.

The above is the description of the example of the method for driving the shift register 30 illustrated in FIG.

Note that a protective circuit may be provided in the shift register 30 illustrated in FIG. For example, FIG.
In the shift register 30 shown in A), in the shift register shown in FIG. 5A, the protection circuit 32 is electrically connected to the wiring for inputting the initialization signal INI_RES, the clock signals CLK1 to CLK4, and the start pulse signal SP. Are connected to each other.

Further, the shift register 30 shown in FIG. 6B has a configuration in which the protection circuit 33 is electrically connected to the wiring for outputting the output signal OUT_1 to the output signal OUT_N from the shift register 30 shown in FIG. 6A. It is.

Further, in the shift register 30 shown in FIG. 5A, the protection circuit 32 shown in FIG.
A protective circuit 33 shown in B) may be provided.

The protective circuit 32 and the protective circuit 33 are circuits that, when a potential outside a certain range is applied to a wire connected thereto, electrically connect the wire to another power supply line. The protection circuit 32 and the protection circuit 33 are configured using, for example, a diode.

As shown in FIG. 6, by providing a protective circuit, electrical resistance of overvoltage generated by electrostatic discharge (also referred to as ESD) or the like can be increased in the shift register.

As described with reference to FIGS. 1 to 6, in the example of the pulse output circuit according to this embodiment, the transistor 11 is provided, and the transistor 11 outputs the pulse signal of the transistor 12 during the low level period. The potential of one of the source and the drain is made lower than the high level potential of the clock signal. Thus, stress applied to the transistor 12 can be suppressed, so that deterioration of the transistor can be suppressed.

Second Embodiment
In this embodiment, an example of a display device using the pulse output circuit according to Embodiment 1 will be described with reference to FIGS.

The display device illustrated in FIG. 7A includes a pixel portion 201 and a driver circuit portion 202.

The pixel unit 201 includes a plurality of pixel circuits 211 arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more), and the drive circuit unit 202 includes a gate driver 221 and a source driver 223. And other drive circuits.

The gate driver 221 includes a shift register (for example, the shift register 30 illustrated in FIG. 5A) including a plurality of stages of the pulse output circuit described in Embodiment 1. For example, the gate driver 221 controls the scan lines GL_1 to GL_ according to pulse signals output from the shift register.
It has a function of controlling the potential of X. Note that a plurality of gate drivers 221 may be provided and the scan lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 221.

An image signal is input to the source driver 223. The source driver 223 has a function of generating a data signal to be written to the pixel circuit 211 based on an image signal. Further, the source driver 223 has a function of controlling the potentials of the data lines DL_1 to DL_Y.

The source driver 223 is configured using, for example, a plurality of analog switches. The source driver 223 can output a signal obtained by time-dividing an image signal as a data signal by sequentially turning on the plurality of analog switches. Further, the source driver 223 may be configured using a shift register or the like. At this time, as the shift register, a shift register (for example, the shift register 30 illustrated in FIG. 5A) including a plurality of stages of the pulse output circuit described in Embodiment 1 can be used.

Each of the plurality of pixel circuits 211 receives a pulse signal via one of the plurality of scanning lines GL, and receives a data signal via one of the plurality of data lines DL. Multiple pixel circuits 21
In each of 1s, the gate driver 221 controls writing and holding of data of the data signal. For example, in the pixel circuit 211 in the m-th row and the n-th column, a pulse signal is input from the gate driver 221 via the scanning line GL_m (m is a natural number less than or equal to X), and the data line DL_n (n Is a natural number less than or equal to Y) and the data signal is input from the source driver 223.

Each of the plurality of pixel circuits 211 is, for example, a liquid crystal element 2 as shown in FIG. 7 (B-1).
30, a transistor 231_1, and a capacitor 233_1.

The potential of one of the pair of electrodes of the liquid crystal element 230 is appropriately set in accordance with the specification of the pixel circuit 211. The alignment state of the liquid crystal element 230 is set according to the data to be written. Note that a potential common to one of the pair of electrodes of the liquid crystal element 230 included in each of the plurality of pixel circuits 211 (
Common potential) may be given. Further, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 230 for each pixel circuit 211 in each row.

For example, as a display method of a display device provided with a liquid crystal element, TN (Twisted Nem
atic) mode, IPS (In Plane Switching) mode, STN (
Super Twisted Nematic mode, VA (Vertical Al)
ignment mode, ASM (Axially Symmetric Aligne)
d Micro-cell mode, OCB (Optically Compensat)
ed Birefringence) mode, FLC (Ferroelectric L)
Liquid Crystal) mode, AFLC (AntiFerroelectric)
Liquid Crystal mode, MVA (Multi-Domain Ver)
tical Alignment mode, PVA (Patterned Vertic)
al Alignment mode, FFS (Fringe Field Switch)
ing) mode or TBA (Transverse Bend Alignment)
A mode or the like may be used.

Alternatively, the liquid crystal element may be formed of a liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent. A liquid crystal exhibiting a blue phase has a short response speed of 1 msec or less and is optically isotropic, so alignment processing is unnecessary and the viewing angle dependency is small.

In the pixel circuit 211 in the m-th row and the n-th column, one of the source and the drain of the transistor 231_1 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 230. The gate of the transistor 231_1 is electrically connected to the scan line GL_m. The transistor 231_1 has a function of controlling data writing of a data signal by being turned on or off.

One of the pair of electrodes of the capacitor 233_1 is electrically connected to the potential supply line VL, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 230. Note that the value of the potential of the potential supply line VL is appropriately set in accordance with the specification of the pixel circuit 211. The capacitor 233_1 has a function as a storage capacitor for storing written data.

In the display device including the pixel circuit 211 in FIG. 7B-1, the gate driver 221 sequentially selects the pixel circuits 211 in each row, turns on the transistor 231_1, and writes data signal data.

The pixel circuit 211 to which data is written is brought into the holding state as the transistor 231_1 is turned off. Images can be displayed by sequentially performing this on a row-by-row basis.

The pixel circuit illustrated in FIG. 7B2 includes the transistor 231_2 and the capacitor 233_.
, A transistor 234, and a light emitting element (also referred to as EL) 235.

One of the source and the drain of the transistor 231_2 is electrically connected to the data line DL_n. Further, the gate of the transistor 231_2 is electrically connected to the gate signal line GL_m.

The transistor 231_2 has a function of controlling data writing of a data signal by being turned on or off.

One of the pair of electrodes of the capacitor 233_2 is electrically connected to the power supply line VL_a, and the other is electrically connected to the other of the source and the drain of the transistor 231_2.

The capacitor 233_2 has a function as a storage capacitor for storing written data.

One of the source and the drain of the transistor 234 is electrically connected to the power supply line VL_a. Further, the gate of the transistor 234 is electrically connected to the other of the source and the drain of the transistor 231_2.

One of the anode and the cathode of the light emitting element 235 is electrically connected to the power supply line VL_b,
The other is electrically connected to the other of the source and the drain of the transistor 234.

As the light emitting element 235, for example, an organic electroluminescent element or the like can be used.

Note that the potential VDD is applied to one of the power supply line VL_a and the power supply line VL_b, and the potential VSS is applied to the other.

In the display device including the pixel circuit 211 in FIG. 7B-2, the pixel circuit 211 in each row is sequentially selected by the gate driver 221, the transistor 231_2 is turned on, and data signal data is written.

The pixel circuit 211 to which data is written is brought into a holding state by turning off the transistor 231_2. Furthermore, the transistor 234 responds to the potential of the written data signal.
The amount of current flowing between the source and the drain of the light emitting diode 235 is controlled, and the light emitting element 235 emits light at a luminance corresponding to the amount of current flowing. Images can be displayed by sequentially performing this on a row-by-row basis.

Further, an example of a driving method in the case where the display device illustrated in FIG. 7A can operate in the low power consumption mode will be described with reference to a timing chart in FIG. Here, as an example, the case where the shift register described in Embodiment 1 is used for the gate driver 221 will be described.

The operation of the display device shown in FIG. 7A can be divided into a normal mode and a low power consumption mode.

The operation in the normal mode will be described. At this time, as shown in a period 311 of FIG.
When the start pulse signal SP, the power supply voltage PWR, and the clock signal CLK1 to the clock signal CLK4 are input to the shift register, the shift register sequentially outputs the pulses of the output signal SROUT_1 to the output signal SROUT_N according to the pulse of the start pulse signal SP, Pulses of the output signal OUT_1 to the output signal OUT_N are sequentially output. The power supply voltage PWR includes a power supply voltage including the potential VDD and the potential VSS, and a power supply voltage including the potential Va and the potential VSS.

Next, the operation when changing from the normal mode to the low power consumption mode will be described. At this time,
As shown in a period 312 of FIG. 8, the output of the power supply voltage PWR, the clock signals CLK1 to CLK4 and the start pulse signal SP to the shift register is stopped.

At this time, the input of the start pulse signal SP is first stopped for the shift register, then the input of the clock signals CLK1 to CLK4 is sequentially stopped, and then the power supply voltage P
It is preferable to stop the input of WR. Thereby, the malfunction of the shift register can be suppressed.

Power supply voltage PWR for shift register, clock signal CLK1 to clock signal CLK
4 and stop the input of the start pulse signal SP, the output of the pulses of the output signal SROUT_1 to the output signal SROUT_N is stopped, and the output signal OUT_1 to the output signal OUT
The output of the _N pulse is stopped. Thus, the display device is in the low power consumption mode.

Thereafter, when the shift register is returned to the normal mode, the input of the start pulse signal SP, the clock signals CLK1 to CLK4 and the power supply voltage PWR to the shift register is resumed as shown in a period 313 of FIG.

At this time, for the shift register, first, the input of the power supply voltage PWR is resumed, and then the input of the clock signals CLK1 to CLK4 is resumed, and then the start pulse signal SP
Resume typing. Furthermore, at this time, clock signal CLK1 to clock signal CLK4 are
It is preferable that the input of the clock signals CLK1 to CLK4 be sequentially resumed after setting the potential of the wiring to which the signal is input to the potential VDD.

When input of start pulse signal SP, clock signal CLK1 to clock signal CLK4, and power supply voltage PWR to the shift register is resumed, the shift register sequentially pulses the output signal SROUT_1 to output signal SROUT_N according to the pulse of the start pulse signal SP. It outputs and sequentially outputs pulses of the output signal OUT_1 to the output signal OUT_N. Thus, the display device returns to the normal mode.

The above is the description of the example of the display device.

As described with reference to FIG. 8, in the example of the display device according to this embodiment, the operation of the drive circuit including the shift register can be stopped as needed. Therefore, for example, when a transistor with a low off current is used as a transistor in a pixel circuit and rewriting of a data signal is unnecessary in some or all pixel circuits when displaying an image, the operation of the driver circuit is stopped to perform rewriting. Power consumption can be reduced by increasing the interval.

As shown in FIG. 9, the gate driver 221 and the pixel circuit 211 (a gate signal line G
A protection circuit 225 may be connected to L). Also, the source driver 223 and the pixel circuit 211
The protection circuit 225 may be connected during (data signal line DL). The protection circuit 225 is a circuit that brings a wiring and another power supply line into conduction when a potential outside the predetermined range is applied to the wiring that the protection circuit 225 itself connects. The protection circuit 225 is configured using, for example, a diode.

As shown in FIG. 9, the provision of the protection circuit can enhance the tolerance of the display device to overvoltage generated by ESD or the like.

As described with reference to FIGS. 1 to 9, in the example of the display device according to this embodiment, a driver circuit such as a gate driver or a source driver is formed using the pulse output circuit described in Embodiment 1. . In the above driver circuit, since the stress on the transistor is small, the reliability of the display device can be improved.

Furthermore, a structural example of the display device according to the present embodiment will be described with reference to FIG.

The display device illustrated in FIG. 10A is a vertical electric field liquid crystal display device.

The conductive layers 703 a and 703 b are provided on one surface of the substrate 700 with the insulating layer 701 interposed therebetween.

The conductive layer 703 a is provided in the driver circuit portion 202. The conductive layer 703a functions as a gate of a transistor in the driver circuit.

The conductive layer 703 b is provided in the pixel portion 201. The conductive layer 703 b functions as a gate of the transistor in the pixel circuit.

An insulating layer 704 is provided over the conductive layers 703a and 703b. The insulating layer 704 functions as a gate insulating layer of a transistor in a driver circuit and a gate insulating layer of a transistor in a pixel circuit.

The semiconductor layer 705a overlaps with the conductive layer 703a with the insulating layer 704 interposed therebetween. Semiconductor layer 705
a has a function as a layer (also referred to as a channel formation layer) in which a channel of a transistor of a driver circuit is formed.

The semiconductor layer 705 b overlaps with the conductive layer 703 b with the insulating layer 704 interposed therebetween. Semiconductor layer 705
b has a function as a channel formation layer of the transistor of the pixel circuit.

The conductive layer 706a is electrically connected to the semiconductor layer 705a. The conductive layer 706a functions as one of a source and a drain of the transistor in the driver circuit.

The conductive layer 706b is electrically connected to the semiconductor layer 705a. The conductive layer 706 b functions as the other of the source and the drain of the transistor in the driver circuit.

The conductive layer 706c is electrically connected to the semiconductor layer 705b. The conductive layer 706c functions as one of a source and a drain of the transistor in the pixel circuit.

The conductive layer 706 d is electrically connected to the semiconductor layer 705 b. The conductive layer 706d functions as the other of the source and the drain of the transistor in the pixel circuit.

The insulating layer 707 is provided over the semiconductor layers 705a and 705b and the conductive layers 706a to 706d. The insulating layer 707 has a function as an insulating layer which protects the transistor (also referred to as a protective insulating layer).

The insulating layer 708 is provided over the insulating layer 707. The insulating layer 708 functions as a planarization layer. By providing the insulating layer 708, generation of parasitic capacitance between the conductive layer below the insulating layer 708 and the conductive layer above the insulating layer 708 can be suppressed.

The conductive layer 709 a and the conductive layer 709 b 1 are provided over the insulating layer 708.

The conductive layer 709 a overlaps with the semiconductor layer 705 a with the insulating layer 707 and the insulating layer 708 interposed therebetween. The conductive layer 709a functions as a gate of a transistor in the driver circuit. For example,
The conductive layer 709a may function as a back gate of the transistor in the driver circuit. For example, in the case of an n-channel transistor, the threshold voltage of the transistor can be shifted in the positive direction by applying a negative potential to the back gate. Also, the back gate may be grounded.

The conductive layer 709 b 1 functions as one of a pair of electrodes of a capacitor of a pixel circuit.

The insulating layer 710 is provided on the surface of the insulating layer 708 and the conductive layer 709 b 1. Note that hydrogen and water in the insulating layer 708 can be released to the outside by removing a portion of the insulating layer 710 which is formed over the transistor in the driver circuit; It is possible to suppress the The insulating layer 710 has a function as a protective insulating layer.
The insulating layer 710 also functions as a dielectric layer of a capacitor of the pixel circuit.

The conductive layer 711 is provided over the insulating layer 710, and is electrically connected to the conductive layer 706d through an opening provided through the insulating layer 707, the insulating layer 708, and the insulating layer 710. Further, the conductive layer 711 overlaps with the conductive layer 709 b 1 with the insulating layer 710 interposed therebetween. Conductive layer 711
Has a function as one of the pair of electrodes of the liquid crystal element in the pixel circuit and the other of the pair of electrodes of the capacitor.

The coloring layer 722 is provided on part of one plane of the substrate 720. The colored layer 722 has a function as a color filter.

The insulating layer 723 is provided on one surface of the substrate 720 with the coloring layer 722 interposed therebetween. Insulating layer 723
Has a function as a planarization layer.

The conductive layer 721 is provided on one plane of the insulating layer 723. The conductive layer 721 has a function as the other of the pair of electrodes of the liquid crystal element in the pixel circuit. Note that an insulating layer may be separately provided over the conductive layer 721.

The liquid crystal layer 750 is provided between the conductive layer 711 and the conductive layer 721 using the sealant 751. Note that a portion of the insulating layer 707 and the insulating layer 710 located below the sealant 751 may be removed.

Furthermore, the display device illustrated in FIG. 10B is a display device using a lateral electric field mode (FFS mode), and has a conductive layer 703 c separately as compared to the display device illustrated in FIG. 70
It differs in that a conductive layer 709 b 2 is provided instead of 9 b 1, a conductive layer 712 is provided instead of the conductive layer 711, and a liquid crystal layer 760 is provided instead of the liquid crystal layer 750. The description of the display device illustrated in FIG. 10A is incorporated as appropriate for the same portions as the display device illustrated in FIG.

The conductive layer 703 c is provided over the insulating layer 701. At this time, the conductive layer 706 d overlaps with the conductive layer 703 c with the insulating layer 704 interposed therebetween.

The conductive layer 709 b 2 is provided over the insulating layer 708. The conductive layer 709 b 2 functions as one of a pair of electrodes of a liquid crystal element in a pixel circuit. Further, the conductive layer 709 b 2 functions as one of a pair of electrodes of a capacitor of a pixel circuit.

The conductive layer 712 is provided over the insulating layer 710, and electrically connected to the conductive layer 706d through an opening provided through the insulating layer 707, the insulating layer 708, and the insulating layer 710. The conductive layer 712 has a comb-tooth portion, and the comb-tooth portions overlap with the conductive layer 709 b 2 with the insulating layer 710 interposed therebetween. The conductive layer 712 has a function as the other of the pair of electrodes of the liquid crystal element in the pixel circuit. Further, the conductive layer 712 has a function as the other of the pair of electrodes of the capacitor in the pixel circuit.

The liquid crystal layer 760 is provided over the conductive layer 711 and the conductive layer 712 by the sealant 751.

Note that although the transistor is a channel etch type transistor in FIGS. 10A and 10B, the present invention is not limited to this. For example, a channel stop type transistor may be used. Alternatively, a top gate transistor may be used.

Further, each component of the display device shown in FIGS. 10A and 10B will be described.
Each layer may have a laminated structure.

For example, a glass substrate or a plastic substrate can be used as the substrates 700 and 720.

As the insulating layer 701, a layer containing a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, or hafnium oxide can be used, for example.

As the conductive layers 703a to 703c, for example, molybdenum, titanium, chromium, tantalum, or the like can be used.
A layer containing a metallic material such as magnesium, silver, tungsten, aluminum, copper, neodymium, or scandium can be applied.

As the insulating layer 704, a layer containing a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride, or hafnium oxide can be used, for example. For example, the insulating layer 70
As 4, a stack of a silicon nitride layer and a silicon oxynitride layer can be applied. At this time, the silicon nitride layer may be a stack of a plurality of silicon nitride layers having different compositions. Alternatively, an oxide layer may be used as the insulating layer 704. As the above oxide layer, for example, In: Ga
An oxide layer or the like having an atomic ratio of Zn: 1: 3: 2 can be used.

For example, an oxide semiconductor layer can be used as the semiconductor layer 705a and the semiconductor layer 705b.

As the oxide semiconductor, as described in Embodiment 1, for example, an In-based metal oxide, Zn,
For example, a base metal oxide, an In-Zn-based metal oxide, or an In-Ga-Zn-based metal oxide can be used. Alternatively, a metal oxide containing another metal element instead of part or all of Ga contained in the above In-Ga-Zn-based metal oxide may be used. Note that the above oxide semiconductor may have a crystal. For example, the oxide semiconductor may be polycrystalline or single crystal. In addition, the above oxide semiconductor may be amorphous.

As the other metal element, for example, a metal element capable of binding to more oxygen atoms than gallium may be used, and for example, any one or more elements of titanium, zirconium, hafnium, germanium, and tin may be used. Just do it. In addition, as the other metal element, any one or more of lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium and lutetium can be used. Good. These metal elements have a function as a stabilizer. In addition, the addition amount of these metal elements is an amount which a metal oxide can function as a semiconductor. By using a metal element that can form more bonds with oxygen atoms than gallium and by supplying oxygen to the metal oxide, oxygen defects in the metal oxide can be reduced.

Furthermore, for example, a first oxide semiconductor layer having an atomic ratio of In: Ga: Zn = 1: 1: 1, I
a second oxide semiconductor layer having an atomic ratio of n: Ga: Zn = 3: 1: 2, and In: Ga: Z
The semiconductor layer 705a and the semiconductor layer 705b may be formed by stacking a third oxide semiconductor layer in which the atomic ratio of n is 1: 1: 1. The semiconductor layer 705a and the semiconductor layer 7 are formed by the above lamination.
By forming 05b, for example, the field-effect mobility of the transistor can be increased.

The transistor including the oxide semiconductor has a wide band gap and thus has less leakage current due to thermal excitation. Furthermore, the effective mass of holes is as heavy as 10 or more, and the height of the tunnel barrier is 2.8
It is as high as eV or more. This reduces the tunnel current. Furthermore, the number of carriers in the semiconductor layer is extremely small. Thus, the off current can be reduced. For example, the off current is 1 × 10 ⁻¹⁹ A (100 zA) or less per 1 μm of the channel width at room temperature (25 ° C.). More preferably 1
× ^10-22 A (100 y A) or less. The lower the off-state current of the transistor, the better, but the lower limit of the off-state current of the transistor is estimated to be about 1 × 10 ^-30 A / μm. Note that the semiconductor layer 705 a and the semiconductor layer 70 are not limited to the above oxide semiconductor layer.
A semiconductor layer containing an element of Group 14 (such as silicon) may be used as 5b. For example, as a semiconductor layer containing silicon, a single crystal silicon layer, a polycrystalline silicon layer, an amorphous silicon layer, or the like can be used.

For example, the transistor including the above oxide semiconductor can be manufactured by removing impurities such as hydrogen or water as much as possible and supplying oxygen to reduce oxygen vacancies as much as possible. At this time,
In the channel formation region, the amount of hydrogen referred to as donor impurity is 1 × 10 ¹⁹ / cm ³ or less, preferably 1 × 10 ¹⁸ / cm or less as measured by secondary ion mass spectrometry (also referred to as SIMS).
It is preferable to reduce to cm ³ or less.

The carrier density of the oxide semiconductor layer is less than 1 × 10 ¹⁴ / cm ³ , preferably less than 1 × 10 ¹² / cm ³ , more preferably 1 by using the highly purified oxide semiconductor layer for a field effect transistor. It can be less than 10 ¹¹ / cm ³ . Thus, by reducing the carrier density, the off-state current of the field effect transistor per channel width 1 μm is 1 ×.
It can be suppressed to 10 ⁻¹⁹ A (100 zA) or less, more preferably 1 × 10 ⁻²² A (100 yA) or less. The lower the off current of the field effect transistor, the better, but the lower limit of the off current of the field effect transistor is estimated to be about 1 × 10 ^-30 A / μm.

Note that the above oxide semiconductor may be a CAAC-OS.

For example, the oxide semiconductor layer which is a CAAC-OS can be formed by a sputtering method.
At this time, sputtering is performed using a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, the crystal region included in the sputtering target is cleaved from the a-b plane, and is separated as flat-plate-like or pellet-like sputtering particles having a plane parallel to the a-b plane. is there. At this time, while the crystalline state is maintained, the sputtered particles reach the substrate, whereby the crystalline state of the sputtering target is transferred to the substrate. Thus, a CAAC-OS is formed.

Further, in order to form a CAAC-OS, the following conditions are preferably applied.

For example, when the impurity concentration is reduced to form the CAAC-OS, collapse of the crystalline state of the oxide semiconductor due to the impurity can be suppressed. For example, impurities (hydrogen,
It is preferable to reduce water, carbon dioxide, nitrogen and the like. Further, it is preferable to reduce impurities in the deposition gas. For example, as a deposition gas, the dew point is -80 ° C or less, preferably-
It is preferable to use a deposition gas whose temperature is 100 ° C. or less.

Further, it is preferable to increase the substrate temperature at the time of film formation. By raising the temperature of the substrate, when flat-plate-like sputtered particles reach the substrate, migration of the sputtered particles occurs, and the sputtered particles can be attached to the substrate with the flat surface facing. For example, the substrate heating temperature is 100 ° C. to 740 ° C., preferably 200 ° C. to 500 ° C.
The oxide semiconductor layer is formed by deposition of an oxide semiconductor film at 0 ° C. or lower.

Further, it is preferable to increase the proportion of oxygen in the deposition gas and optimize the power to suppress plasma damage during deposition. For example, the proportion of oxygen in the film formation gas is preferably 30% by volume or more, preferably 100% by volume.

As the conductive layers 706a to 706d, for example, molybdenum, titanium, chromium, tantalum, magnesium, silver, tungsten, aluminum, copper, neodymium, scandium,
Alternatively, a layer containing a metal material such as ruthenium can be applied.

As the insulating layer 707, a layer containing a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, or hafnium oxide can be used, for example.

As the insulating layer 708, a layer of an organic insulating material or an inorganic insulating material can be used, for example. For example, the insulating layer 708 may be formed using an acrylic resin or the like.

As the conductive layer 709a, the conductive layer 709b1, and the conductive layer 709b2, for example, a layer of a metal oxide which has a function as a conductor and transmits light can be used. For example, indium oxide zinc oxide or indium tin oxide can be applied.

As the insulating layer 710, for example, a material applicable to the insulating layer 704 can be used.

As the conductive layer 711, the conductive layer 712, and the conductive layer 721, for example, a layer of a metal oxide which transmits light can be used. For example, indium oxide zinc oxide or indium tin oxide can be applied.

The coloring layer 722 has a function of transmitting light exhibiting one of red (R), green (G), and blue (B), for example. As the coloring layer 722, a layer containing a dye or a pigment can be used.

As the insulating layer 723, a layer containing a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride, or hafnium oxide can be used, for example. In addition, the insulating layer 723
Layers of materials applicable to the

As the liquid crystal layer 750, for example, a layer containing TN liquid crystal, OCB liquid crystal, STN liquid crystal, VA liquid crystal, ECB liquid crystal, GH liquid crystal, polymer dispersed liquid crystal, or discotic liquid crystal can be used.

As the liquid crystal layer 760, a layer including liquid crystal exhibiting a blue phase can be used, for example.

The layer containing liquid crystal exhibiting a blue phase is constituted of, for example, a liquid crystal composition including a liquid crystal exhibiting a blue phase, a chiral agent, a liquid crystalline monomer, a non-liquid crystalline monomer, and a polymerization initiator. A liquid crystal exhibiting a blue phase has a short response time and is optically isotropic, so alignment processing is unnecessary and the viewing angle dependency is small. Therefore, the operation of the liquid crystal display device can be speeded up by using the liquid crystal exhibiting a blue phase.

The above is the description of the structural example of the display device illustrated in FIG.

As described with reference to FIG. 10, in the example of the display device according to this embodiment, the driver circuit is provided over the same substrate as the pixel circuit. Thus, the number of wirings for connecting the pixel circuit and the driver circuit can be reduced.

Third Embodiment
In this embodiment, an example of an electronic device provided with a panel using the display device of Embodiment 2 will be described with reference to FIG.

The electronic device illustrated in FIG. 11A is an example of a portable information terminal.

The electronic device illustrated in FIG. 11A includes a housing 1011 and a panel 10 provided in the housing 1011.
12, a button 1013, and a speaker 1014.

Note that the housing 1011 may be provided with a connection terminal and an operation button for connecting to an external device.

Furthermore, the display device of Embodiment 2 may be used to form a panel 1012.

Furthermore, the panel 1012 may be configured using a touch panel. Thus, panel 1
At 012, touch detection can be performed. As the touch panel, for example, an optical touch panel, a capacitive touch panel, a resistive touch panel, or the like can be applied.

The button 1013 is provided on the housing 1011. For example, when the button 1013 is a power button, the on state of the electronic device can be controlled by pressing the button 1013.

The speaker 1014 is provided in the housing 1011. The speaker 1014 outputs sound.

Note that the housing 1011 may be provided with a microphone. By providing the microphone in the housing 1011, for example, the electronic device illustrated in FIG. 7A can function as a telephone set.

The electronic device illustrated in FIG. 11A has functions as one or more of a telephone set, an e-book reader, a personal computer, and a game machine, for example.

The electronic device illustrated in FIG. 11B is an example of a foldable information terminal.

The electronic device illustrated in FIG. 11B includes a housing 1021 a, a housing 1021 b, and a housing 1021 a.
, A panel 1022b provided in the housing 1021b, a shaft portion 1023, a button 1024, a connection terminal 1025, a recording medium insertion portion 1026, and a speaker 1027.

The housing 1021 a and the housing 1021 b are connected by the shaft portion 1023.

Furthermore, the panels 1022 a and 1022 b may be configured using the display device of Embodiment 2.

Furthermore, the panels 1022 a and 1022 b may be configured using a touch panel. Thus, touch detection can be performed on the panels 1022 a and 1022 b. As the touch panel, for example, an optical touch panel, a capacitive touch panel, a resistive touch panel, or the like can be applied.

The electronic device illustrated in FIG. 11B includes the shaft portion 1023, so that the panel 1022a and the panel 1022b can be folded to be opposed to each other.

The button 1024 is provided on the housing 1021 b. Note that a button 102 is attached to the housing 1021a.
4 may be provided. For example, when the button 1024 is a power button, the on state of the electronic device can be controlled by pressing the button 1024.

The connection terminal 1025 is provided in the housing 1021 a. Note that connection terminal 1 is attached to the housing 1021 b.
025 may be provided. In addition, the connection terminal 1025 corresponds to the housing 1021 a and the housing 10.
A plurality of members may be provided on one or both of the members 21 b. The connection terminal 1025 is illustrated in FIG.
These terminals are for connecting the electronic device shown in FIG.

The recording medium insertion unit 1026 is provided in the housing 1021 a. A recording medium insertion unit 1026 may be provided in the housing 1021 b. In addition, the recording medium insertion unit 1026 is a housing 1021a.
And two or more may be provided in one or both of housing | casing 1021b. For example, by inserting a card-type recording medium into the recording medium insertion portion, data of the card-type recording medium can be read out to the electronic device or data in the electronic device can be written to the card-type recording medium.

The speaker 1027 is provided in the housing 1021 b. The speaker 1027 outputs an audio. Note that the speaker 1027 may be provided in the housing 1021 a.

Note that a microphone may be provided in the housing 1021 a or the housing 1021 b. With the microphones provided in the housings 1021a and 1021b, for example, the electronic device illustrated in FIG. 11B can function as a telephone set.

The electronic device illustrated in FIG. 11B functions as one or more of a telephone set, an e-book reader, a personal computer, and a game machine, for example.

The electronic device illustrated in FIG. 11C is an example of a stationary information terminal. The electronic device illustrated in FIG. 11C includes a housing 1031, a panel 1032 provided in the housing 1031, and a button 10.
33 and a speaker 1034.

Furthermore, the display device of Embodiment 2 may be used to configure the panel 1032.

Furthermore, the panel 1032 may be configured using a touch panel. Thus, panel 1
At 032, touch detection can be performed. As the touch panel, for example, an optical touch panel, a capacitive touch panel, a resistive touch panel, or the like can be applied.

Note that a panel similar to the panel 1032 may be provided on the deck portion 1035 of the housing 1031.

Furthermore, a ticket output unit that outputs a ticket or the like, a coin insertion unit, a bill insertion unit, or the like may be provided in the housing 1031.

The button 1033 is provided on the housing 1031. For example, when the button 1033 is a power button, the on state of the electronic device can be controlled by pressing the button 1033.

The speaker 1034 is provided in the housing 1031. The speaker 1034 outputs an audio.

The electronic device illustrated in FIG. 11C functions as, for example, an automatic teller machine, an information communication terminal (also referred to as a multimedia station) for ordering a ticket or the like, or a game machine.

FIG. 11D illustrates an example of a stationary information terminal. The electronic device illustrated in FIG. 11D includes a housing 1041, a panel 1042 provided in the housing 1041, a support base 1043 for supporting the housing 1041, a button 1044, a connection terminal 1045, and a speaker 1046. And.

Note that the housing 1041 may be provided with a connection terminal for connecting to an external device.

Further, the display device of Embodiment 2 may be used to form the panel 1042.

Furthermore, the panel 1042 may be configured using a touch panel. Thus, panel 1
At 042, touch detection can be performed. As the touch panel, for example, an optical touch panel, a capacitive touch panel, a resistive touch panel, or the like can be applied.

The button 1044 is provided on the housing 1041. For example, when the button 1044 is a power button, the on state of the electronic device can be controlled by pressing the button 1044.

The connection terminal 1045 is provided in the housing 1041. The connection terminal 1045 is a terminal for connecting the electronic device illustrated in FIG. 11D to another device. For example, when the electronic device illustrated in FIG. 11D and the personal computer are connected to each other through the connection terminal 1045, an image corresponding to a data signal input from the personal computer can be displayed on the panel 1042. For example, if the panel 1042 of the electronic device illustrated in FIG. 11D is larger than the panel of the other electronic device to be connected, the display image of the other electronic device can be enlarged, which facilitates visual recognition by a plurality of persons simultaneously. Become.

The speaker 1046 is provided in the housing 1041. The speaker 1046 outputs a sound.

The electronic device illustrated in FIG. 11D has one or more functions of, for example, an output monitor, a personal computer, and a television set.

The above is the description of the example of the electronic device illustrated in FIG.

As described with reference to FIG. 11, the electronic device according to this embodiment can provide a highly reliable electronic device by providing a panel using the display device of Embodiment 2 on the panel.

11 transistor 12 transistor 13 transistor 14 transistor 15 transistor 31 pulse output circuit 32 protection circuit 61 protection circuit 61 transistor 62 transistor 64 transistor 64 transistor 65 transistor 66 transistor 67 transistor 68 transistor 69 transistor 70 transistor 71 transistor 72 transistor 73 transistor 75 transistor 75 transistor 76 transistor 201 pixel portion 202 drive circuit portion 211 pixel circuit 221 gate driver 223 source driver 225 protection circuit 230 liquid crystal element 231_1 transistor 231_2 transistor 233_1 capacitive element 233_2 capacitive element 234 transistor 235 light emitting element 311 period 312 period 313 period basis 701 insulating layer 703a conductive layer 703b conductive layer 703c conductive layer 704 insulating layer 705a semiconductor layer 705b conductive layer 706a conductive layer 706b conductive layer 706c conductive layer 707 insulating layer 708 insulating layer 709a conductive layer 709b1 conductive layer 709b2 conductive layer 710 insulating Layer 711 Conductive layer 712 Conductive layer 720 Substrate 721 Conductive layer 722 Colored layer 723 Insulating layer 750 Liquid crystal layer 751 Sealing material 760 Liquid crystal layer 1011 Panel 1013 Panel 1013 Button 1014 Speaker 1021a Housing 1021a Housing 1021b Housing 1022a Panel 1022b Panel 1023 Shaft portion 1024 Button 1025 connection terminal 1026 recording medium insertion portion 1027 speaker 1031 housing 1032 panel 1033 button 1034 speaker 1035 deck portion 1041 housing 1042 Panel 1043 Support stand 1044 Button 1045 Connection terminal 1046 Speaker

Claims (1)

A shift register comprising first to fifth transistors and first and second capacitive elements, wherein
A first clock signal is input to one of the source and the drain of the first transistor,
One of the source or the drain of the second transistor is electrically connected to the other of the source or the drain of the first transistor,
One of the source or the drain of the third transistor is electrically connected to the other of the source or the drain of the second transistor,
One of the source or the drain of the third transistor is electrically connected to the output terminal,
A power supply potential is input to the other of the source and the drain of the third transistor,
One of the source or the drain of the fourth transistor is electrically connected to the gate of the first transistor,
The other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor,
A first set signal is input to the gate of the fourth transistor,
The other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,
The first electrode of the first capacitive element is electrically connected to the gate of the first transistor,
The second electrode of the first capacitive element is electrically connected to the output terminal,
The first electrode of the second capacitive element is electrically connected to the gate of the second transistor,
A shift register in which a second electrode of the second capacitive element is electrically connected to the output terminal.

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