JP2022002162A - Output circuit - Google Patents

Abstract

To provide an output circuit capable of suppressing stress for a transistor while suppressing an occurrence of malfunction.SOLUTION: In a pulse output circuit having a function of outputting a pulse signal and having a transistor for controlling whether or not the pulse signal is set to a high level, a potential of one of a source and a drain of the transistor is set to be higher than a low-level potential of a clock signal and be higher than a high-level potential while the pulse signal output from the pulse output circuit is at a low level. Thereby, stress on the transistor is suppressed.SELECTED DRAWING: Figure 1

Description

The present invention relates to a pulse output circuit. Furthermore, the present invention relates to a display device. Furthermore, the present invention relates to electronic devices.

In recent years, for the purpose of simplifying the manufacturing process, a circuit (also referred to as a unipolar circuit) in which all transistors are of the same conductive type has been developed.

Examples of the unipolar circuit include a pulse output circuit constituting a shift register.

For example, Patent Document 1 discloses a shift register having a plurality of stages of pulse output circuits in which a pulse of a clock signal is used to generate a pulse of a pulse signal. Further, Patent Document 1 discloses a shift register that suppresses a decrease in the amplitude of the output pulse signal with respect to the amplitude of the clock signal by using the bootstrap.

Japanese Unexamined Patent Publication No. 2002-335153

However, in the conventional pulse output circuit configuration, there is a problem that if the amplitude of the clock signal is large, the transistor deteriorates and the electrical characteristics of the transistor fluctuate.

For example, in the shift register of Patent Document 1, a transistor that controls whether or not to set the output pulse signal to a high level when the pulse signal output from the pulse output circuit is at a low level (for example, FIG. 1 of Patent Document 1). The potential of the gate of the transistor 15) of (B) is the potential VS.
It is held in S for a certain period of time. At this time, since the potential of the source or drain of the transistor changes repeatedly according to the clock signal, stress is applied to the transistor. As a result, the transistor deteriorates. In particular, in the shift register of Patent Document 1, since the stress is applied for a very long time, the transistor is liable to deteriorate and the electrical characteristics are fluctuated.

In order to suppress the influence of the stress applied to the transistor, for example, measures such as lengthening the channel length of the transistor can be mentioned. However, if the channel length of the transistor that controls whether or not the output pulse signal is set to a high level is lengthened, the output pulse signal is delayed due to, for example, parasitic capacitance, and there is a high possibility that malfunction will occur. Another problem arises.

In view of the above problems, one of the problems in one aspect of the present invention is to suppress the stress on the transistor that controls whether or not the output pulse signal is set to a high level while suppressing the occurrence of malfunction. ..

In one aspect of the present invention, during a period when the pulse signal output by the pulse output circuit is at a low level,
The potential of one of the source and drain of the transistor that controls whether or not the pulse signal is set to a high level is set lower than the high level potential of the clock signal. As a result, stress on the transistor is suppressed.

One aspect of the present invention has a function of generating a pulse signal according to a set signal, a reset signal, and a clock signal, and the potential of one of the source and the drain changes according to the clock signal.
Transistor and one of the source and drain are electrically connected to the other of the source and drain of the first transistor, the potential of the other of the source and drain becomes the potential of the pulse signal, and the potential of the gate becomes the set signal and reset signal. The second transistor that changes according to
One of the source and drain is given a first potential, the other of the source and drain is electrically connected to the other of the source and drain of the second transistor, and is turned on or off depending on the potential of the gate. A second potential is applied to one of the source and drain and the third transistor that controls whether or not the pulse signal is set to a low level, and the other of the source and drain is electrically connected to the gate of the first transistor. A fourth transistor whose gate potential changes according to the set signal and reset signal, and one potential of the source and drain changes according to the set signal and reset signal, and the other of the source and drain changes according to the set signal and the reset signal. The fifth transistor is electrically connected to the gate of the transistor and the potential of the gate changes according to the set signal, and the first to fifth transistors are of the same conductive type and have a second potential. Is higher than the low level potential of the clock signal and lower than the high level potential of the clock signal, and the potential difference between the second potential and the low level potential of the clock signal is the threshold value of the first transistor. It is a pulse output circuit that is larger than the voltage.

According to one aspect of the present invention, stress on the transistor can be reduced without increasing the channel length of the transistor that controls whether or not the output pulse signal is set to a high level. Therefore, deterioration of the transistor can be suppressed, and fluctuations in electrical characteristics can be suppressed.

The figure for demonstrating an example of a pulse output circuit. The figure for demonstrating an example of a pulse output circuit. The figure for demonstrating an example of a pulse output circuit. The figure for demonstrating an example of a pulse output circuit. The figure for demonstrating an example of a pulse output circuit. The figure for demonstrating an example of a pulse output circuit. The figure for demonstrating the example of a display device. The figure for demonstrating the example of a display device. The figure for demonstrating the example of a display device. The figure for demonstrating the example of a display device. The figure for demonstrating the example of the electronic device.

An example of the embodiment according to the present invention will be described. It is easy for a person skilled in the art to change the contents of the embodiment without departing from the spirit and scope of the present invention. Therefore, for example, the present invention is not limited to the contents described in the following embodiments.

The contents of each embodiment can be combined with each other as appropriate. In addition, the contents of each embodiment can be appropriately replaced with each other.

Further, the ordinal numbers such as the first and the second are attached to avoid confusion of the components, and the number of each component is not limited to the ordinal number.

As used herein, the term "parallel" means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore,
The case of 85 ° or more and 95 ° or less is also included.

Further, in the present specification, when the crystal is a trigonal crystal or a rhombohedral crystal, it is represented as a hexagonal system.

(Embodiment 1)
In this embodiment, an example of a pulse output circuit will be described.

FIG. 1 is a diagram for explaining an example of a pulse output circuit according to the present embodiment. As shown in FIG. 1A, the pulse output circuit SR has a function of generating a pulse signal (output signal OUT) according to the input set signal S, reset signal R, and clock signal CK. A plurality of types of clock signals may be input to the pulse output circuit SR.

Further, the pulse output circuit SR shown in FIG. 1 (A) has transistors 11 to 15 as shown in FIG. 1 (B). For example, transistor 11 to transistor 15
Is the same conductive type. Continuity of each of the transistors 11 to 15 is controlled according to one or more of the set signal S, the reset signal R, and the clock signal CK. The transistor 11 to the transistor 15 are connected to the pulse output circuit SR shown in FIG. 1 (A).
Elements other than the above may be provided.

The potential of one of the source and drain of the transistor 11 changes according to the clock signal CK. The transistor 11 has a function of controlling a high-level potential of a pulse signal (output signal OUT). For example, the transistor 11 has a function of controlling whether or not the pulse signal (output signal OUT) is set to the first high level and whether or not the pulse signal is set to the second high level.
At this time, the potential of the second high level is smaller than the potential of the first high level.

It should be noted that "the potential changes according to the signal" is not limited to "when the potential changes to the potential of the signal by directly inputting the signal". For example, "when the potential changes when the switch is turned on according to the signal" or "when the potential changes according to the change in the signal due to capacitive coupling" also becomes "the potential changes according to the signal". included.

Further, the "potential according to the signal" is not limited to only the "potential having the same value as the potential of the signal".
For example, the value at which the potential of the signal changes due to the voltage drop is also included in the "potential according to the signal".

One of the source and drain of the transistor 12 is electrically connected to the other of the source and drain of the transistor 11, and the potential of the other becomes the potential of the pulse signal (output signal OUT). Further, the potential of the gate of the transistor 12 changes according to the set signal S and the reset signal R. The transistor 12 has a function of controlling whether or not the pulse signal (output signal OUT) is set to a high level.

One of the source and drain of the transistor 13 is given a potential VSS and the other is electrically connected to the other of the source and drain of the transistor 12. Further, the potential of the gate of the transistor 13 changes according to the set signal S and the reset signal R. The potential of the gate of the transistor 13 may be controlled by a clock signal different from the clock signal CK. The transistor 13 has a function of controlling whether or not the pulse signal (output signal OUT) is set to a low level by turning on or off depending on the potential of the gate.

One of the source and drain of the transistor 14 is given a potential Va, and the other is electrically connected to the gate of the transistor 11. Further, the potential of the gate of the transistor 14 changes according to the set signal S and the reset signal R, or changes according to the clock signal CK. The transistor 14 has a function of controlling whether or not the potential of the gate of the transistor 11 is set to a value corresponding to the potential Va.

The "value according to the potential" is not limited to "the same value as the potential". For example, a case where the value of the potential changes due to a voltage drop is also included in the "value according to the potential".

The potential of one of the source and drain of the transistor 15 changes according to the set signal S and the reset signal R, and the other is electrically connected to the gate of the transistor 11. Further, the potential of the gate of the transistor 15 changes according to the set signal S. Transistor 15
It has a function of controlling whether or not the gate of the transistor 11 is in a floating state.

As the transistor 11 to the transistor 15, a transistor including a semiconductor having a bandgap wider than that of silicon, for example, can be applied to the channel forming region. As a semiconductor having a wide band gap, for example, an oxide semiconductor can be applied. However, the present invention is not limited to this, and for example, a transistor including a semiconductor having a group 14 (such as silicon) element is included in the transistor 1.
It may be used for 1 to the transistor 15. At this time, the semiconductor having the element of Group 14 may be single crystal, polycrystal, or amorphous.

As the oxide semiconductor, for example, an In-based metal oxide, a Zn-based metal oxide, an In-Zn-based metal oxide, an In-Ga-Zn-based metal oxide, or the like can be applied. In addition, the above In-G
A metal oxide containing another metal element may be used in place of a part or all of Ga contained in the a-Zn-based metal oxide.

Hereinafter, the structure of the oxide semiconductor film will be described.

Oxide semiconductor films are roughly classified into single crystal oxide semiconductor films and non-single crystal oxide semiconductor films. The non-single crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and CAAC-OS (C Axis Aligned Crystalline).
Oxide Semiconductor) Membrane and the like.

The amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal component. A typical oxide semiconductor film has no crystal part even in a minute region and the entire film has a completely amorphous structure.

The microcrystal oxide semiconductor film includes, for example, microcrystals (also referred to as nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the polycrystalline oxide semiconductor film has a higher regularity of atomic arrangement than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film is characterized by having a lower defect level density than the amorphous oxide semiconductor film.

The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal portions, and most of the crystal portions have a size that can be accommodated in a cube having a side of less than 100 nm. Therefore, CAAC-O
The crystal portion contained in the S film includes a case where one side is less than 10 nm and has a size of less than 5 nm or less than 3 nm so as to fit in a cube. The CAAC-OS film is characterized by having a lower defect level density than the polycrystalline oxide semiconductor film. Hereinafter, the CAAC-OS film will be described in detail.

Transmission electron microscope (TEM: Transmission Electro) through the CAAC-OS membrane
When observed by a ron Microscope), a clear boundary between crystal portions, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed. Therefore, CA
It can be said that the AC-OS film is unlikely to cause a decrease in electron mobility due to grain boundaries.

When the CAAC-OS film is observed by TEM from a direction substantially parallel to the sample surface (cross-section TEM observation), it can be confirmed that the metal atoms are arranged in layers in the crystal portion. Each layer of the metal atom has a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and is arranged in parallel with the formed surface or the upper surface of the CAAC-OS film. ..

On the other hand, the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (plane TE).
(M observation), it can be confirmed that the metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal portion. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

From the cross-sectional TEM observation and the planar TEM observation, it can be seen that the crystal portion of the CAAC-OS film has orientation.

When the structure of the CAAC-OS film is analyzed using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the _{CAAC-OS film having InGaZnO 4} crystals by the out-of-plane method, A peak may appear near the diffraction angle (2θ) of 31 °. Since this peak is _{attributed to the (009) plane of the InGaZnO 4} crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented substantially perpendicular to the surface to be formed or the upper surface. It can be confirmed that it is.

On the other hand, in-pl in which X-rays are incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis.
In the analysis by the ane method, a peak may appear near 56 ° in 2θ. This peak is attributed to the (110) plane of the crystal of _{InGaZnO 4.} In the case of _{a single crystal oxide semiconductor film of InGaZnO 4} , 2θ is fixed in the vicinity of 56 °, and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis). 110) Six peaks attributed to the crystal plane equivalent to the plane are observed. On the other hand, in the case of CAAC-OS film, 2θ is 5
Even when fixed at around 6 ° and φ-scanned, no clear peak appears.

From the above, in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal portions, but the orientation is c-axis, and the c-axis is the normal of the surface to be formed or the upper surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of the metal atoms arranged in layers confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

The crystal portion is formed when a CAAC-OS film is formed or when a crystallization treatment such as a heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film.

Further, the crystallinity in the CAAC-OS film does not have to be uniform. For example, when the crystal portion of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the surface to be formed. be. Also, CAA
When an impurity is added to the C-OS film, the crystallinity of the region to which the impurity is added changes, and a region having a partially different crystallinity may be formed.

In the _{analysis of the CAAC-OS film having InGaZnO 4} crystals by the out-of-plane method, a peak may appear in the vicinity of 2θ at 31 ° as well as in the vicinity of 2θ at 36 °. The peak in which 2θ is in the vicinity of 36 ° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. In the CAAC-OS film, it is preferable that 2θ shows a peak near 31 ° and 2θ does not show a peak near 36 °.

Transistors using a CAAC-OS film have small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor is highly reliable.

The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or CA.
Among the AC-OS films, a laminated film having two or more kinds may be used.

The above is the description of the structure of the oxide semiconductor film.

Further, a configuration example of the pulse output circuit according to the present embodiment will be described with reference to FIG.

The pulse output circuit shown in FIG. 2A has a set signal LIN corresponding to the set signal S, a reset signal RIN corresponding to the reset signal R, and clock signals CK1 to CK3.
It also has a function of generating and outputting a pulse signal (output signal OUT) according to the initialization signal RES. It is not always necessary to use the initialization signal RES.

The pulse output circuit shown in FIG. 2A has transistors 61 to 76.

A potential VDD is given to one of the source and drain of the transistor 61. Moreover,
A set signal LIN is input to the gate of the transistor 61.

One of the source and drain of the transistor 62 is given a potential VSS and the other is electrically connected to the other of the source and drain of the transistor 61.

One of the source and drain of the transistor 63 is electrically connected to the other of the source and drain of the transistor 61. Further, a set signal L is attached to the gate of the transistor 63.
IN is input. The transistor 63 corresponds to the transistor 15 shown in FIG. 1 (B).

One of the source and drain of the transistor 64 is electrically connected to the other of the source and drain of the transistor 61. Further, a potential VDD is given to the gate of the transistor 64.

It should be noted that the transistor 64 does not necessarily have to be provided.

The clock signal CK1 is input to one of the source and drain of the transistor 65.
Further, the gate of the transistor 65 is electrically connected to the other of the source and drain of the transistor 63. The transistor 65 corresponds to the transistor 11 shown in FIG. 1 (B).

One of the source and drain of the transistor 66 is electrically connected to the other of the source and drain of the transistor 65, and the potential of the other becomes the potential of the pulse signal (output signal OUT). The transistor 66 corresponds to the transistor 12 shown in FIG. 1 (B).

Further, a capacitance C1 is formed between the gate of the transistor 65 and the other of the source and drain of the transistor 66. It is not always necessary to form the capacitance C1.

Further, the capacitance C2 is formed between the gate of the transistor 66 and the other of the source and drain of the transistor 66. The parasitic capacitance between the gate of the transistor 66 and the other of the source and drain may be used for the capacitance C2. It is not always necessary to form the capacitance C2.

One of the source and drain of the transistor 67 is given a potential VSS and the other is electrically connected to the other of the source and drain of the transistor 66. The transistor 67 corresponds to the transistor 13 shown in FIG. 1 (B).

A clock signal CK1 is input to one of the source and drain of the transistor 68.
Further, the gate of the transistor 68 is electrically connected to the other of the source and drain of the transistor 63.

One of the source and drain of the transistor 69 is electrically connected to the other of the source and drain of the transistor 68, and the potential of the other becomes the potential of the pulse signal (output signal SROUT). Further, the gate of the transistor 69 is electrically connected to the other of the source and drain of the transistor 64.

Further, a capacitance C3 is formed between the gate of the transistor 68 and the other of the source and drain of the transistor 69. It is not always necessary to form the capacitance C3.

Further, a capacitance C4 is formed between the gate of the transistor 69 and the other of the source and drain of the transistor 69. The parasitic capacitance between the gate of the transistor 69 and the other of the source and drain may be used for the capacitance C4. It is not always necessary to form the capacitance C4.

One of the source and drain of the transistor 70 is given a potential VSS and the other is electrically connected to the other of the source and drain of the transistor 69. Further, the gate of the transistor 70 is electrically connected to the gate of the transistor 62.

It is not always necessary to provide the transistor 68 to the transistor 70.

One of the source and drain of the transistor 71 is given a potential Va, and the other is electrically connected to the gate of the transistor 65 and the gate of the transistor 68. Further, the potential of the gate of the transistor 71 changes according to the set signal LIN, the reset signal RIN, the initialization signal RES, the clock signal CK2, and the clock signal CK3. Transistor 7
1 corresponds to the transistor 14 shown in FIG. 1 (B).

One of the source and drain of the transistor 72 is given a potential VDD, and the other is electrically connected to the gate of the transistor 67 and the gate of the transistor 70. Moreover,
A reset signal RIN is input to the gate of the transistor 72.

One of the source and drain of the transistor 73 is given a potential VDD, and the other is electrically connected to the gate of the transistor 67 and the gate of the transistor 70. Moreover,
The initialization signal RES is input to the gate of the transistor 72.

One of the source and drain of the transistor 74 is given a potential VSS, and the other is electrically connected to the gate of the transistor 67 and the gate of the transistor 70. Moreover,
A set signal LIN is input to the gate of the transistor 74.

A potential VDD is given to one of the source and drain of the transistor 75. Moreover,
The clock signal CK3 is input to the gate of the transistor 75.

One of the source and drain of the transistor 76 is electrically connected to the other of the source and drain of the transistor 75, and the other is the gate and the transistor 70 of the transistor 67.
It is electrically connected to the gate of. Further, a clock signal CK2 is input to the gate of the transistor 76.

One of the pair of electrodes of capacitance C5 is given the potential VSS and the other is electrically connected to the gate of the transistor 71. The capacity C5 has a function as a holding capacity. It is not always necessary to provide the capacity C5.

As the transistor 61 to the transistor 76, for example, a transistor containing the oxide semiconductor in the channel forming region can be applied.

Next, as an example of the driving method of the pulse output circuit according to the present embodiment, an example of the driving method of the pulse output circuit shown in FIG. 2A will be described with reference to the timing chart of FIG. 2B.
Here, as an example, each of the transistors 61 to 76 is an N-channel type, the potential VDD is a positive potential, the potential VSS is a negative potential, and the value of the potential Va is (VDD + VSS) / 2. It is explained as. Further, the high-level potentials of the set signal LIN, the reset signal RIN, and the clock signals CK1 to CK3 are the potential V.
It is the same as DD, and the low level potential is the same as the potential VSS. Further, the threshold voltage of the transistor 65 and the threshold voltage of the transistor 68 are the same. Further, the threshold voltage of the transistor 66 and the threshold voltage of the transistor 69 are the same. Further, it is assumed that the potential difference between the potential Va and the low-level potential of the clock signal CK1 is larger than the threshold voltage of the transistor 65. Further, before the period T1, the pulse of the initialization signal RES is input, the transistor 73 is turned on, and the transistor 67, the transistor 70, and the transistor 71 are turned on to initialize the pulse output circuit. May be good. Further, the connection point between the gate of the transistor 66 and another element is a node NA, the connection point between the gate of the transistor 67 and another element is a node NB, and the connection point between the gate of the transistor 65 and another element is a node. NC is used, and the connection point between the other of the source and drain of the transistor 65 and one of the source and drain of the transistor 66 is referred to as a node ND.

In the present specification, the potential VSS is at least 2 necessary for operating the circuit.
It is the lower potential of the two power supply potentials. Of the two power supply potentials, the higher potential is the potential VDD.

In the example of the driving method of the pulse output circuit shown in FIG. 2A, the set signal LIN becomes high level and the transistor 72 and the transistor 74 are turned on during the period T1 of FIG. 2B. Further, since the reset signal RIN is at a low level, the transistor 72 is turned off. Further, since the clock signal CK1 to the clock signal CK3 are at a low level, the transistor 75 and the transistor 76 are turned off.

At this time, the potential of the node NC rises to a value equivalent to the potential VDD, the transistor 65 and the transistor 68 are turned on, and the potential of the node ND becomes a value corresponding to the low level potential of the clock signal CK1. Further, the transistor 63 is turned off. Further, the potential of the node NA rises to a value equivalent to the potential VDD, and the transistor 66 and the transistor 69 are turned on. Further, the transistor 64 is turned off. Output signal OU at this time
T, the output signal SROUT is low level. As a result, the pulse output circuit shown in FIG. 2A is in the set state.

Next, in the period T2, the transistor 61 and the transistor 74 remain on because the set signal LIN remains at a high level. Further, the clock signal CK1 becomes a high level. Further, since the reset signal RIN, the clock signal CK2, and the clock signal CK3 remain at the low level, the transistor 72, the transistor 75, and the transistor 76
Remains off.

At this time, the transistor 62, the transistor 67, the transistor 70, and the transistor 71
Remains off. Further, the transistor 65 and the transistor 66 remain on, and node NA and node N due to the capacitive coupling caused by the capacitance C1 and the capacitance C2.
The potential of C rises to a value higher than the sum of the potential VDD and the threshold voltage (Vth65) of the transistor 65, that is, VDD + Vth65 + Vx (Vx is an arbitrary value). As a result, the potential of the output signal OUT becomes a value equivalent to the high level potential of the clock signal CK1. Further, the transistor 68 and the transistor 69 remain in the ON state, and the output signal S
The potential of ROUT becomes a value equivalent to the potential of the high level of the clock signal CK1.

Next, in the period T3, the set signal LIN becomes low level, and the transistor 61, the transistor 72, and the transistor 74 are turned off. Also, the clock signal CK1 remains at a high level. Further, the clock signal CK2 becomes high level and the transistor 76 is turned on. Further, since the reset signal RIN and the clock signal CK3 remain at the low level, the transistor 72 and the transistor 75 remain in the off state.

At this time, the transistor 62, the transistor 67, the transistor 70, and the transistor 71
Remains off. Further, the voltage between the gate and the drain of the transistor 66 and the transistor 69 is maintained at VDD + Vx, and the potentials of the output signal OUT and the output signal SROUT remain the same as the high level potentials of the clock signal CK1. Therefore, the output signal OUT and the output signal SROUT maintain high levels.

Next, in the period T4, the reset signal RIN becomes high level and the transistor 72 is turned on. Further, the clock signal CK1 becomes low level. Also, the clock signal C
Transistor 76 remains at high level because K2 remains at high level. Further, the clock signal CK3 becomes high level and the transistor 75 is turned on. also,
Transistor 61, transistor 63 because the set signal LIN remains low level
, Transistor 74 remains off.

At this time, the potential of the node NB becomes a value equivalent to the potential VDD, and the transistor 62, the transistor 67, the transistor 70, and the transistor 71 are turned on. Also, node NC
The potential of the above becomes a value corresponding to the potential Va, and the transistor 65 and the transistor 68 remain in the ON state. Further, when the potential of the node NA becomes a value corresponding to the potential VSS, the transistor 66 and the transistor 69 are turned off. Therefore, the potential of the node ND becomes a value corresponding to the low level potential of the clock signal CK1. Therefore, the potentials of the output signal OUT and the output signal SROUT become values corresponding to the low level potentials of the clock signal CK1, and the output signal OUT and the output signal SROUT become low level. As a result, the pulse output circuit shown in FIG. 2A is in the reset state.

Next, in the period T5, the reset signal RIN remains at a high level, so that the transistor 72 remains on. Further, the clock signal CK2 becomes low level and the transistor 76 becomes an off state. Also, since the clock signal CK3 remains at a high level, the transistor 75 remains on. Further, since the set signal LIN and the clock signal CK1 remain at the low level, the transistor 61, the transistor 63, and the transistor 74 remain in the off state.

At this time, the potential of the node NB remains a value corresponding to the potential VDD, and the transistor 62,
The transistor 67, the transistor 70, and the transistor 71 remain in the ON state. Further, the potential of the node NC remains at the same value as the potential Va, and the transistor 65 and the transistor 68 remain in the ON state. Further, since the potential of the node NA remains at the same value as the potential VSS, the transistor 66 and the transistor 69 remain in the off state. Therefore, the potential of the node ND becomes a value equivalent to the low level potential of the clock signal CK1. Therefore, the potentials of the output signal OUT and the output signal SROUT become values equivalent to the low level potentials of the clock signal CK1, and the output signal OUT and the output signal SROUT become low level.

Next, in the period T6, the reset signal RIN becomes a low level and the transistor 72 becomes an off state. Further, the clock signal CK1 becomes a high level. Also, the clock signal C
K3 goes low and the transistor 75 goes off. Furthermore, the set signal LI
Since N, the clock signal CK2 remains at a low level, the transistor 61, the transistor 63, and the transistor 74 remain in the off state.

At this time, since the potential of the node NB remains at the same value as the potential VDD, the transistor 6
2. The transistor 67, the transistor 70, and the transistor 71 remain in the ON state.
Further, since the potential of the node NC remains at the same value as the potential Va, the transistor 65 and the transistor 68 remain in the ON state. Further, since the potential of the node NA remains at the same value as the potential VSS, the transistor 66 and the transistor 69 remain in the off state. Further, since the potential of the gate of the transistor 65 is a potential Va lower than the potential VDD, the potential of the node ND becomes Va-Vth65. This is a value higher than the low level potential of the clock signal CK1 and lower than the high level potential. Further, the potentials of the output signal OUT and the output signal SROUT have the same values as the low level of the clock signal CK1. As shown in the period T4 to the period T6, when the output signal OUT and the output signal SROUT are at low level, the potential of the node ND is higher than the potential VSS and the low level potential of the clock signal CK1.
It alternates between Va-Vth65, which is lower than the high level potential. Therefore, the stress on the transistor can be suppressed as compared with the case where the potential of the drain of the transistor 66 changes alternately between the potential VDD and the potential VSS.

The above is the description of the pulse output circuit shown in FIG. 2 (A).

The configuration of the pulse output circuit according to the present embodiment is not limited to the above configuration, and other configurations may be used.

For example, in the pulse output circuit shown in FIG. 3 (A), instead of electrically connecting the gate of the transistor 62 of the pulse output circuit shown in FIG. 2 (B) to the other of the source and drain of the transistor 72, the pulse output circuit of the transistor 62 The configuration is such that a reset signal RIN is input to the gate. As a result, when the pulse output circuit is reset, the speed at which the potential of the node NA is set to a value equivalent to the potential VSS can be increased.

Further, as shown in FIG. 3B, the transistor 64 of the pulse output circuit shown in FIG. 2B,
The transistor 68, the transistor 69, the transistor 70, the transistor 73, the transistor 75, and the transistor 76 do not necessarily have to be provided.

Further, as shown in FIG. 4, a back gate may be provided in each of the transistors 62 to 76, and the threshold voltage of the transistors 62 to 76 may be controlled by controlling the potential of the back gate. For example, when a negative potential is applied to the back gate of the N-channel transistor, the threshold voltage of the N-channel transistor can be shifted in the positive direction. In the pulse output circuit shown in FIG. 4, the transistor 61, the transistor 64, the transistor 72, the transistor 73, the transistor 75, and the transistor 7
A potential BG1 is given to each of the back gates of No. 6, and a potential BG 2 is given to each of the back gates of the transistor 62, the transistor 63, the transistors 65 to 71, and the transistor 74. When a negative potential is used as the potential BG1 and the potential BG2, the value of the potential BG2 is preferably lower than the potential BG1. Potential BG
This is because if the threshold voltage of the transistor to which 1 is supplied is too high, the pulse output circuit is likely to malfunction.

Similarly, in the configuration shown in FIG. 3A or FIG. 3B, a back gate may be provided in the transistor.

Further, an example of a shift register having a plurality of stages of pulse output circuits shown in FIG. 2A will be described with reference to FIG.

The shift register 30 shown in FIG. 5A is a pulse output circuit having a plurality of stages (pulse output circuit 31).
It has _1 to a pulse output circuit 31_N (N is a natural number of 2 or more). FIG. 5A shows a case where N = 4 or more as an example.

Each of the pulse output circuit 31_1 to the pulse output circuit 31_N corresponds to the pulse output circuit shown in FIG. 2 (A). The pulse output circuit 31_1 to the pulse output circuit 31_N are shown in FIG.
As shown in (B), the output signal OUT follows the set signal LIN, the reset signal RIN, the initialization signal RES, the clock signal CK1, the clock signal CK2, and the clock signal CK3.
, Has a function of generating and outputting a plurality of pulse signals as an output signal SROUT.

The start pulse signal SP is input to the pulse output circuit 31_1 as a set signal LIN. Further, the pulse output circuit 31_K (K is a natural number of 2 or more and N or less) has a pulse signal (output signal SROW) output from the pulse output circuit 31_K-1 as a set signal LIN.
T) is input.

A pulse signal (output signal SROUT) output from the pulse output circuit 31_M + 2 is input as a reset signal RIN to the pulse output circuit 31_M (M is a natural number of N-1 or less).

Further, in the pulse output circuit 31_1, the clock signal CLK1 is used as the clock signal CK1.
Is input, the clock signal CLK2 is input as the clock signal CK2, and the clock signal CLK3 is input as the clock signal CK3. Further, with reference to the pulse output circuit 31_1, the clock signal CLK is used as the clock signal CK1 for every three pulse output circuits.
1 is input, the clock signal CLK2 is input as the clock signal CK2, and the clock signal CLK3 is input as the clock signal CK3.

Further, in the pulse output circuit 31_2, the clock signal CLK2 is used as the clock signal CK1.
Is input, the clock signal CLK3 is input as the clock signal CK2, and the clock signal CLK4 is input as the clock signal CK3. Further, with reference to the pulse output circuit 31_2, the clock signal CLK is used as the clock signal CK1 for every three pulse output circuits.
2 is input, the clock signal CLK3 is input as the clock signal CK2, and the clock signal CLK4 is input as the clock signal CK3.

Further, in the pulse output circuit 31_3, the clock signal CLK3 is used as the clock signal CK1.
Is input, the clock signal CLK4 is input as the clock signal CK2, and the clock signal CLK1 is input as the clock signal CK3. Further, with reference to the pulse output circuit 31_3, the clock signal CLK is used as the clock signal CK1 for every three pulse output circuits.
3 is input, the clock signal CLK4 is input as the clock signal CK2, and the clock signal CLK1 is input as the clock signal CK3.

The clock signal CLK4 is input to the pulse output circuit 31_4 as the clock signal CK1, the clock signal CLK1 is input as the clock signal CK2, and the clock signal CLK2 is input as the clock signal CK3. Further, with reference to the pulse output circuit 31_4, the clock signal CLK4 is input as the clock signal CK1 for every three pulse output circuits, the clock signal CLK1 is input as the clock signal CK2, and the clock signal CK3 is used.
The clock signal CLK2 is input as. In FIG. 5A, as an example, the clock signal CK1, the clock signal CK2, and the clock signal CK3 are input to the pulse output circuit 31_4, and the clock signal CK1 and the clock signal CK2 are input to the pulse output circuit 31_4. , And the clock signal CK3.

Further, each of the configurations of the pulse output circuit 31_N + 1 and the pulse output circuit 31_N + 2 is the configuration of the pulse output circuit shown in FIG. 2A without the transistor 72. Pulse signal output from pulse output circuit 31_N + 1 (output signal SROUT_N + 1)
) Is input to the pulse output circuit 31_N-1 as a reset signal RIN. Further, the pulse signal (output signal SROUT_N + 2) output from the pulse output circuit 31_N + 2 is
It is input to the pulse output circuit 31_N as a reset signal RIN. Note that the separately generated pulse signal may be input to the pulse output circuit 31_N-1 and the pulse output circuit 31_N without providing the pulse output circuit 31_N + 1 and the pulse output circuit 31_N + 2. Further, it is not always necessary to output the output signal OUT_N + 1 and the output signal OUT_N + 2.

Further, the initialization signal INI_RES is input as the initialization signal RES to each of the pulse output circuit 31_1 to the pulse output circuit 31_N + 2.

Next, an example of the driving method of the shift register 30 shown in FIG. 5A will be described with reference to the timing chart of FIG. 5C. Here, as an example, it is assumed that the potential VDD is a positive potential, the potential VSS is a negative potential, and the potential Va is (whether + VSS) / 2. Further, as an example, the set signal LIN, the reset signal RIN, and the clock signal CL
It is assumed that the high-level potential of K1 to the clock signal CLK4 is the same as the potential VDD, and the low-level potential is the same as the potential VSS. Also, as an example, the clock signal CLK
It is assumed that the duty ratio of 1 to the clock signal CLK4 is 50%. Also, as an example
It is assumed that the clock signal CLK2 is delayed by 1/4 cycle from the clock signal CLK1, the clock signal CLK3 is delayed by 1/4 cycle from the clock signal CLK2, and the clock signal CLK4 is 1/4 of the clock signal CLK3. It is assumed that it is delayed by the cycle. Further, as an example, it is assumed that the pulse width of the start pulse signal SP is the same as the pulse width of the clock signal CLK1 to the clock signal CLK4. Further, it is assumed that the pulse of the initialization signal INI_RES is input to initialize the pulse output circuit before each pulse output circuit is in the set state.

As shown in FIG. 5C, in the shift register 30 shown in FIG. 5A, the clock signal CLK1 becomes high level at time T12 because the start pulse signal SP becomes high level at time T11. Further, the shift register 30 sequentially outputs the pulses of the output signal SROUT_1 to the output signal SROUT_N according to the clock signal CLK1 to the clock signal CLK4, and sequentially outputs the pulses of the output signal OUT_1 to the output signal OUT_N.

The above is an explanation of an example of the driving method of the shift register 30 shown in FIG. 5 (A).

A protection circuit may be provided in the shift register 30 shown in FIG. 5 (A). For example, FIG. 6 (
In the shift register 30 shown in A), in the shift register shown in FIG. 5A, the protection circuit 32 is electrically connected to the wiring for inputting the initialization signal INI_RES, the clock signal CLK1 to the clock signal CLK4, and the start pulse signal SP. It is a configuration connected to.

Further, the shift register 30 shown in FIG. 6B has a configuration in which the protection circuit 33 is electrically connected to the wiring for outputting the output signal OUT_1 to the output signal OUT_N from the shift register 30 shown in FIG. 6A. Is.

Further, the shift register 30 shown in FIG. 5 (A) has the protection circuit 32 shown in FIG. 6 (A) and FIG. 6 (A).
The protection circuit 33 shown in B) may be provided.

The protection circuit 32 and the protection circuit 33 are circuits that make the wiring and another power line conductive when a potential outside a certain range is applied to the wiring to which the protection circuit 32 is connected. The protection circuit 32 and the protection circuit 33 are configured by using, for example, a diode or the like.

As shown in FIG. 6, by providing a protection circuit, it is possible to increase the electrical resistance of the overvoltage generated by electrostatic discharge (also referred to as ESD) in the shift register.

As described with reference to FIGS. 1 to 6, in an example of the pulse output circuit according to the present embodiment, the transistor 11 is provided, and the transistor 12 is provided with the transistor 12 during the period when the output pulse signal is at a low level. The potential of one of the source and drain is lower than the high level potential of the clock signal. As a result, the stress applied to the transistor 12 can be suppressed, so that the deterioration of the transistor can be suppressed.

(Embodiment 2)
In the present embodiment, an example of the display device using the pulse output circuit according to the first embodiment will be described with reference to FIGS. 7 to 10.

The display device shown in FIG. 7A includes a pixel unit 201 and a drive circuit unit 202.

The pixel unit 201 includes a plurality of pixel circuits 211 arranged in the X row (X is a natural number of 2 or more) and the Y column (Y is a natural number of 2 or more), and the drive circuit unit 202 includes a gate driver 221 and a source driver 223. It is equipped with a drive circuit such as.

The gate driver 221 includes a shift register having a plurality of stages of the pulse output circuits shown in the first embodiment (for example, the shift register 30 shown in FIG. 5A). For example, the gate driver 221 may use the scanning lines GL_1 to GL_ by the pulse signal output from the shift register.
It has a function of controlling the potential of X. A plurality of gate drivers 221 may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 221.

An image signal is input to the source driver 223. The source driver 223 has a function of generating a data signal to be written in the pixel circuit 211 based on the image signal. Further, the source driver 223 has a function of controlling the potentials of the data lines DL_1 to DL_Y.

The source driver 223 is configured by using, for example, a plurality of analog switches. The source driver 223 can output a time-division signal of an image signal as a data signal by sequentially turning on a plurality of analog switches. Further, the source driver 223 may be configured by using a shift register or the like. At this time, as the shift register, a shift register having a plurality of stages of the pulse output circuits shown in the first embodiment (for example, the shift register 30 shown in FIG. 5A) can be used.

In each of the plurality of pixel circuits 211, a pulse signal is input via one of the plurality of scanning lines GL, and a data signal is input via one of the plurality of data line DLs. Multiple pixel circuits 21
In each of 1, the writing and holding of the data of the data signal is controlled by the gate driver 221. For example, in the pixel circuit 211 in the mth row and nth column, a pulse signal is input from the gate driver 221 via the scanning line GL_m (m is a natural number of X or less), and the data line DL_n (n) is input according to the potential of the scanning line GL_m. Is a natural number less than or equal to Y), and a data signal is input from the source driver 223.

Each of the plurality of pixel circuits 211 is, for example, as shown in FIG. 7 (B-1), the liquid crystal element 2
30, a transistor 231_1, and a capacitive element 233_1 are provided.

The potential of one of the pair of electrodes of the liquid crystal element 230 is appropriately set according to the specifications of the pixel circuit 211. The orientation state of the liquid crystal element 230 is set according to the written data. It should be noted that the potential common to one of the pair of electrodes of the liquid crystal element 230 possessed by each of the plurality of pixel circuits 211 (
Common potential) may be given. Further, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 230 for each pixel circuit 211 in each row.

For example, as a display method of a display device including a liquid crystal element, TN (Twisted Nem) is used.
atic) mode, IPS (In Plane Switching) mode, STN (
Super Twisted Nematic mode, VA (Vertical Al)
symmetric) mode, ASM (Axial symmetry Axial symmetry)
d Micro-cell mode, OCB (Optically Compensat)
ed Birefringence) mode, FLC (Ferroelectric L)
quid Crystal) mode, AFLC (AntiFerolectric)
Liquid Crystal) mode, MVA (Multi-Domain Ver)
Tical Alignment mode, PVA (Patterned Vertic)
alSignment) mode, FFS (Fringe Field Switch)
ing) mode, or TBA (Transverse Bend Alignment)
A mode or the like may be used.

Further, the liquid crystal element may be composed of a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. The liquid crystal showing the blue phase has a short response speed of 1 msec or less and is optically isotropic, so that no alignment treatment is required and the viewing angle dependence is small.

In the pixel circuit 211 in the m-th row and n-th column, one of the source and the drain of the transistor 231_1 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 230. Further, the gate of the transistor 231_1 is electrically connected to the scanning line GL_m. The transistor 231_1 has a function of controlling data writing of a data signal by being turned on or off.

One of the pair of electrodes of the capacitive element 233_1 is electrically connected to the potential supply line VL, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 230. The potential value of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 211. The capacitive element 233_1 has a function as a holding capacitance for holding the written data.

In the display device including the pixel circuit 211 of FIG. 7B-1, the pixel circuit 211 of each row is sequentially selected by the gate driver 221, the transistor 231_1 is turned on, and the data of the data signal is written.

The pixel circuit 211 to which the data is written is put into a holding state when the transistor 231_1 is turned off. By doing this sequentially line by line, the image can be displayed.

Further, in the pixel circuit shown in FIG. 7 (B-2), the transistor 231_2 and the capacitive element 233_
2, a transistor 234, and a light emitting element (also referred to as EL) 235 are provided.

One of the source and drain of the transistor 231-2 is electrically connected to the data line DL_n. Further, the gate of the transistor 231-2 is electrically connected to the gate signal line GL_m.

The transistor 231_2 has a function of controlling data writing of a data signal by being turned on or off.

One of the pair of electrodes of the capacitive element 233_2 is electrically connected to the power line VL_a and the other is electrically connected to the other of the source and drain of the transistor 231_2.

The capacitive element 233_2 has a function as a holding capacitance for holding the written data.

One of the source and drain of the transistor 234 is electrically connected to the power line VL_a. Further, the gate of transistor 234 is electrically connected to the other of the source and drain of transistor 231_2.

One of the anode and cathode of the light emitting element 235 is electrically connected to the power supply line VL_b.
The other is electrically connected to the other of the source and drain of the transistor 234.

As the light emitting element 235, for example, an organic electroluminescence element or the like can be used.

The potential VDD is given to one of the power line VL_a and the power line VL_b, and the potential VSS is given to the other.

In the display device including the pixel circuit 211 of FIG. 7B-2, the pixel circuit 211 of each row is sequentially selected by the gate driver 221, the transistor 231_2 is turned on, and the data of the data signal is written.

The pixel circuit 211 to which the data is written is put into a holding state when the transistor 231_2 is turned off. Further, the transistor 234 corresponds to the potential of the written data signal.
The amount of current flowing between the source and drain of the light emitting element 235 is controlled, and the light emitting element 235 emits light with brightness corresponding to the amount of flowing current. By doing this sequentially line by line, the image can be displayed.

Further, an example of a driving method when the display device shown in FIG. 7A can be operated in the low power consumption mode will be described with reference to the timing chart of FIG. Here, as an example, a case where the shift register shown in the first embodiment is used for the gate driver 221 will be described.

The operation of the display device shown in FIG. 7A is divided into a normal mode and a low power consumption mode.

The operation in the normal mode will be described. At this time, as shown in the period 311 of FIG.
When the start pulse signal SP, the power supply voltage PWR, and the clock signals CLK1 to the clock signal CLK4 are input to the shift register, the shift register sequentially outputs the pulses of the output signal SROUT_1 to the output signal SROUT_N according to the pulse of the start pulse signal SP. The pulses of the output signal OUT_1 to the output signal OUT_N are sequentially output. Examples of the power supply voltage PWR include a power supply voltage composed of the potential VDD and the potential VSS, and a power supply voltage composed of the potential Va and the potential VSS.

Next, the operation when the normal mode is changed to the low power consumption mode will be described. At this time,
As shown in the period 312 of FIG. 8, the output of the power supply voltage PWR, the clock signal CLK1 to the clock signal CLK4, and the start pulse signal SP to the shift register is stopped.

At this time, the input of the start pulse signal SP is first stopped in the shift register, then the inputs of the clock signal CLK1 to the clock signal CLK4 are sequentially stopped, and then the power supply voltage P is stopped.
It is preferable to stop the input of WR. As a result, the malfunction of the shift register can be suppressed.

Power supply voltage PWR for shift register, clock signal CLK1 to clock signal CLK
4. When the input of the start pulse signal SP is stopped, the output of the pulse of the output signal SROUT_1 to the output signal SROUT_N is stopped, and the output signal OUT_1 to the output signal OUT
The output of the _N pulse stops. Therefore, the display device is in the low power consumption mode.

After that, when the shift register is returned to the normal mode, the input of the start pulse signal SP, the clock signal CLK1 to the clock signal CLK4, and the power supply voltage PWR to the shift register is restarted as shown in the period 313 of FIG.

At this time, the input of the power supply voltage PWR is first restarted to the shift register, then the input of the clock signal CLK1 to the clock signal CLK4 is restarted, and then the start pulse signal SP is restarted.
Resume input. Further, at this time, the clock signal CLK1 to the clock signal CLK4
It is preferable to sequentially restart the input of the clock signal CLK1 to the clock signal CLK4 after setting the potential of the wiring to which is input to the potential VDD.

When the input of the start pulse signal SP, the clock signal CLK1 to the clock signal CLK4, and the power supply voltage PWR to the shift register is restarted, the shift register sequentially outputs the pulses of the output signal SROUT_1 to the output signal SROUT_N according to the pulse of the start pulse signal SP. It is output, and the pulses of the output signal OUT_1 to the output signal OUT_N are sequentially output. Therefore, the display device returns to the normal mode.

The above is the description of the example of the display device.

As described with reference to FIG. 8, in an example of the display device according to the present embodiment, the operation of the drive circuit including the shift register can be stopped as needed. Therefore, for example, when a transistor having a low off current is used as a transistor of a pixel circuit and it is not necessary to rewrite a data signal in a part or all of the pixel circuits when displaying an image, the operation of the drive circuit is stopped and rewritten. Power consumption can be reduced by increasing the interval.

As shown in FIG. 9, between the gate driver 221 and the pixel circuit 211 (gate signal line G).
The protection circuit 225 may be connected to L). In addition, the source driver 223 and the pixel circuit 211
The protection circuit 225 may be connected between (data signal line DL). The protection circuit 225 is a circuit that makes the wiring and another power line conductive when a potential outside a certain range is applied to the wiring to which the protection circuit 225 is connected. The protection circuit 225 is configured by using, for example, a diode.

As shown in FIG. 9, by providing the protection circuit, the resistance of the display device to the overvoltage generated by ESD or the like can be increased.

As described with reference to FIGS. 1 to 9, in an example of the display device according to the present embodiment, a drive circuit such as a gate driver and a source driver is configured by using the pulse output circuit shown in the first embodiment. .. In the above drive circuit, since the stress on the transistor is small, the reliability of the display device can be improved.

Further, a structural example of the display device according to the present embodiment will be described with reference to FIG.

The display device shown in FIG. 10A is a vertical electric field type liquid crystal display device.

The conductive layers 703a and 703b are provided on one plane of the substrate 700 with the insulating layer 701 interposed therebetween.

The conductive layer 703a is provided in the drive circuit unit 202. The conductive layer 703a has a function as a gate of the transistor of the drive circuit.

The conductive layer 703b is provided in the pixel portion 201. The conductive layer 703b has a function as a gate of the transistor of the pixel circuit.

The insulating layer 704 is provided on the conductive layers 703a and 703b. The insulating layer 704 has a function as a gate insulating layer of the transistor of the drive circuit and a gate insulating layer of the transistor of the pixel circuit.

The semiconductor layer 705a is superimposed on the conductive layer 703a with the insulating layer 704 interposed therebetween. Semiconductor layer 705
a has a function as a layer (also referred to as a channel forming layer) in which a channel of a transistor of a drive circuit is formed.

The semiconductor layer 705b is superimposed on the conductive layer 703b with the insulating layer 704 interposed therebetween. Semiconductor layer 705
b has a function as a channel forming layer of the transistor of the pixel circuit.

The conductive layer 706a is electrically connected to the semiconductor layer 705a. The conductive layer 706a has a function as one of a source and a drain of the transistor of the drive circuit.

The conductive layer 706b is electrically connected to the semiconductor layer 705a. The conductive layer 706b has a function as the other of the source and drain of the transistor of the drive circuit.

The conductive layer 706c is electrically connected to the semiconductor layer 705b. The conductive layer 706c has a function as one of a source and a drain of the transistor of the pixel circuit.

The conductive layer 706d is electrically connected to the semiconductor layer 705b. The conductive layer 706d has a function as the other of the source and the drain of the transistor of the pixel circuit.

The insulating layer 707 is provided on the semiconductor layer 705a and the semiconductor layer 705b, and on the conductive layers 706a to 706d. The insulating layer 707 has a function as an insulating layer (also referred to as a protective insulating layer) that protects the transistor.

The insulating layer 708 is provided on the insulating layer 707. The insulating layer 708 has a function as a flattening layer. By providing the insulating layer 708, it is possible to suppress the generation of parasitic capacitance due to the conductive layer below the insulating layer 708 and the conductive layer above the insulating layer 708.

The conductive layer 709a and the conductive layer 709b1 are provided on the insulating layer 708.

The conductive layer 709a is superimposed on the semiconductor layer 705a with the insulating layer 707 and the insulating layer 708 interposed therebetween. The conductive layer 709a has a function as a gate of the transistor of the drive circuit. for example,
The conductive layer 709a may function as a back gate of the transistor of the drive circuit. For example, in the case of an N-channel transistor, the threshold voltage of the transistor can be shifted in the positive direction by applying a negative potential to the back gate. Further, the back gate may be grounded.

The conductive layer 709b1 has a function as one of a pair of electrodes of the capacitive element of the pixel circuit.

The insulating layer 710 is provided on the surface of the insulating layer 708 and on the conductive layer 709b1. By removing the portion of the insulating layer 710 formed on the transistor of the drive circuit, hydrogen and water in the insulating layer 708 can be discharged to the outside, so that the insulating layer 708 is peeled off from the insulating layer 707. It can be suppressed from being stored. The insulating layer 710 has a function as a protective insulating layer.
Further, the insulating layer 710 has a function as a dielectric layer of the capacitive element of the pixel circuit.

The conductive layer 711 is provided on the insulating layer 710, and is electrically connected to the conductive layer 706d by an opening provided through the insulating layer 707, the insulating layer 708, and the insulating layer 710. Further, the conductive layer 711 is superimposed on the conductive layer 709b1 with the insulating layer 710 interposed therebetween. Conductive layer 711
Has a function as one of a pair of electrodes of the liquid crystal element of the pixel circuit and the other of the pair of electrodes of the capacitive element.

The colored layer 722 is provided on a part of one plane of the substrate 720. The colored layer 722 has a function as a color filter.

The insulating layer 723 is provided on one plane of the substrate 720 with the colored layer 722 interposed therebetween. Insulation layer 723
Has a function as a flattening layer.

The conductive layer 721 is provided on one plane of the insulating layer 723. The conductive layer 721 has a function as the other of the pair of electrodes of the liquid crystal element of the pixel circuit. An insulating layer may be separately provided on the conductive layer 721.

The liquid crystal layer 750 is provided between the conductive layer 711 and the conductive layer 721 using the sealing material 751. Of the insulating layer 707 and the insulating layer 710, the portion located under the sealing material 751 may be removed.

Further, the display device shown in FIG. 10B is a display device of a transverse electric field method (FFS mode), and has a separate conductive layer 703c as compared with the display device shown in FIG. 10A, and has a conductive layer. 70
The difference is that the conductive layer 709b2 is provided instead of 9b1, the conductive layer 712 is provided instead of the conductive layer 711, and the liquid crystal layer 760 is provided instead of the liquid crystal layer 750. For the same part as the display device shown in FIG. 10 (A), the description of the display device shown in FIG. 10 (A) is appropriately referred to.

The conductive layer 703c is provided on the insulating layer 701. At this time, the conductive layer 706d is superimposed on the conductive layer 703c with the insulating layer 704 interposed therebetween.

The conductive layer 709b2 is provided on the insulating layer 708. The conductive layer 709b2 has a function as one of a pair of electrodes of the liquid crystal element of the pixel circuit. Further, the conductive layer 709b2 has a function as one of a pair of electrodes of the capacitive element of the pixel circuit.

The conductive layer 712 is provided on the insulating layer 710 and is electrically connected to the conductive layer 706d by an opening provided through the insulating layer 707, the insulating layer 708, and the insulating layer 710. Further, the conductive layer 712 has a comb tooth portion, and each of the combs of the comb tooth portion sandwiches the insulating layer 710 and superimposes on the conductive layer 709b2. The conductive layer 712 has a function as the other of the pair of electrodes of the liquid crystal element of the pixel circuit. Further, the conductive layer 712 has a function as the other of the pair of electrodes of the capacitive element of the pixel circuit.

The liquid crystal layer 760 is provided on the conductive layer 711 and the conductive layer 712 by the sealing material 751.

In FIGS. 10 (A) and 10 (B), the transistor is a channel etch type transistor, but the transistor is not limited to this, and for example, a channel stop type transistor may be used. Further, it may be a top gate type transistor.

Further, each component of the display device shown in FIGS. 10A and 10B will be described.
In addition, each layer may have a laminated structure.

As the substrates 700 and 720, for example, a glass substrate or a plastic substrate can be applied.

As the insulating layer 701, a layer containing a material such as silicon oxide, silicon nitride, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, or hafnium oxide can be applied.

Examples of the conductive layers 703a to 703c include molybdenum, titanium, chromium, and tantalum.
Layers containing metallic materials such as magnesium, silver, tungsten, aluminum, copper, neodymium, or scandium can be applied.

As the insulating layer 704, a layer containing a material such as silicon oxide, silicon nitride, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, or hafnium oxide can be applied. For example, the insulating layer 70
As No. 4, a laminate of a silicon nitride layer and a silicon oxide nitride layer can be applied. At this time, the silicon nitride layer may be laminated with a plurality of silicon nitride layers having different compositions. Further, an oxide layer may be used as the insulating layer 704. Examples of the oxide layer include In: Ga.
An oxide layer having an atomic ratio of: Zn = 1: 3: 2 can be used.

As the semiconductor layer 705a and the semiconductor layer 705b, for example, an oxide semiconductor layer can be used.

As the oxide semiconductor, as shown in the first embodiment, for example, an In-based metal oxide or Zn.
A metal oxide, an In—Zn metal oxide, an In—Ga—Zn metal oxide, or the like can be applied. Further, a metal oxide containing another metal element may be used instead of a part or all of Ga contained in the In-Ga-Zn-based metal oxide. The oxide semiconductor may have crystals. For example, the oxide semiconductor may be polycrystalline or single crystal. Further, the oxide semiconductor may be amorphous.

As the above-mentioned other metal element, for example, a metal element capable of bonding with more oxygen atoms than gallium may be used, and for example, any one or more elements of titanium, zirconium, hafnium, germanium, and tin may be used. Just do it. Further, as the above-mentioned other metal elements, any one or more elements of lanthanum, cerium, placeodim, neodym, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium may be used. good. These metal elements have a function as a stabilizer. The amount of these metal elements added is such that the metal oxide can function as a semiconductor. Oxygen defects in the metal oxide can be reduced by using a metal element that can have more bonds with oxygen atoms than gallium and by supplying oxygen into the metal oxide.

Further, for example, the first oxide semiconductor layer having an atomic ratio of In: Ga: Zn = 1: 1: 1, I.
A second oxide semiconductor layer having an atomic ratio of n: Ga: Zn = 3: 1: 2, and In: Ga: Z.
The semiconductor layer 705a and the semiconductor layer 705b may be formed by laminating a third oxide semiconductor layer having an atomic ratio of n = 1: 1: 1. Due to the above lamination, the semiconductor layer 705a and the semiconductor layer 7
By configuring 05b, for example, the electric field effect mobility of the transistor can be increased.

Since the transistor containing the oxide semiconductor has a wide bandgap, the leakage current due to thermal excitation is small. Furthermore, the effective mass of holes is as heavy as 10 or more, and the height of the tunnel barrier is 2.8.
It is as high as eV or higher. As a result, the tunnel current is small. Furthermore, there are very few carriers in the semiconductor layer. Therefore, the off current can be lowered. ^{For example, the off-current is 1 × 10 -19} A (100 zA) or less per 1 μm of channel width at room temperature (25 ° C.). More preferably 1
× ^10-22 A (100 yA) or less. The lower the off current of the transistor, the better, but the lower limit of the off current of the transistor is estimated to be ^{about 1 × 10 -30 A / μm.} The semiconductor layer 705a and the semiconductor layer 70 are not limited to the oxide semiconductor layer.
As 5b, a semiconductor layer having a group 14 (silicon or the like) element may be used. For example, as the semiconductor layer containing silicon, a single crystal silicon layer, a polycrystalline silicon layer, an amorphous silicon layer, or the like can be used.

For example, a transistor containing the oxide semiconductor can be produced by removing impurities such as hydrogen or water as much as possible and supplying oxygen to reduce oxygen deficiency as much as possible. At this time,
In the channel formation region, the amount of hydrogen, which is called a donor impurity, is measured by secondary ion mass spectrometry (also called SIMS) at 1 × 10 ¹⁹ / cm ³ or less, preferably 1 × 10 ¹⁸ /.
It is preferable to reduce it to cm ^{3 or less.}

By using the highly purified oxide semiconductor layer for the field effect transistor, the carrier density of the oxide semiconductor layer is reduced to ^{less than 1 × 10 14} / cm ³ , preferably less than 1 × 10 ¹² / cm ³ , and more preferably 1. It can be less than × 10 ¹¹ / cm ^3. By reducing the carrier density in this way, the off-current of the field-effect transistor per 1 μm of channel width is reduced by 1 ×.
10 ^-19 A (100zA) or less, more preferably suppressed to less than ^{1 × 10 -22 A (100yA)} . The lower the off-current of the field-effect transistor, the better, but the lower limit of the off-current of the field-effect transistor is estimated to be ^{about 1 × 10 -30 A / μm.}

The oxide semiconductor may be used as CAAC-OS.

For example, an oxide semiconductor layer which is CAAC-OS can be formed by using a sputtering method.
At this time, sputtering is performed using a target for sputtering an oxide semiconductor which is polycrystalline. When ions collide with the sputtering target, the crystal region contained in the sputtering target may be cleaved from the ab plane and separated as flat plate-shaped or pellet-shaped sputtering particles having a plane parallel to the ab plane. be. At this time, the sputtering particles reach the substrate while maintaining the crystalline state, so that the crystalline state of the sputtering target is transferred to the substrate. As a result, CAAC-OS is formed.

Further, it is preferable to apply the following conditions in order to form CAAC-OS.

For example, by reducing the impurity concentration to form CAAC-OS, it is possible to suppress the collapse of the crystal state of the oxide semiconductor due to the impurities. For example, impurities (hydrogen,) existing in the film formation chamber
It is preferable to reduce water, carbon dioxide, nitrogen, etc.). Further, it is preferable to reduce impurities in the film-forming gas. For example, the dew point of the film forming gas is -80 ° C or less, preferably −
It is preferable to use a film forming gas having a temperature of 100 ° C. or lower.

Further, it is preferable to raise the substrate temperature at the time of film formation. By raising the substrate temperature, when the flat plate-shaped sputtering particles reach the substrate, migration of the sputtering particles occurs, and the sputtering particles can be attached to the substrate with the flat surface facing. For example, the substrate heating temperature is 100 ° C. or higher and 740 ° C. or lower, preferably 200 ° C. or higher and 500 ° C. or higher.
An oxide semiconductor layer is formed by forming an oxide semiconductor film at a temperature of ° C or lower.

Further, it is preferable to increase the oxygen ratio in the film-forming gas and optimize the electric power to suppress plasma damage during film-forming. For example, the oxygen ratio in the film-forming gas is preferably 30% by volume or more, preferably 100% by volume.

Examples of the conductive layer 706a to 706d include molybdenum, titanium, chromium, tantalum, magnesium, silver, tungsten, aluminum, copper, neodymium, and scandium.
Alternatively, a layer containing a metallic material such as ruthenium can be applied.

As the insulating layer 707, a layer containing a material such as silicon oxide, silicon nitride, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, or hafnium oxide can be applied.

As the insulating layer 708, for example, a layer of an organic insulating material or an inorganic insulating material can be applied. For example, the insulating layer 708 may be formed by using an acrylic resin or the like.

As the conductive layer 709a, the conductive layer 709b1, and the conductive layer 709b2, for example, a layer of a metal oxide having a function as a conductor and transmitting light can be applied. For example, indium oxide zinc oxide or indium tin oxide can be applied.

As the insulating layer 710, for example, a material applicable to the insulating layer 704 can be used.

As the conductive layer 711, the conductive layer 712, and the conductive layer 721, for example, a layer of a metal oxide that transmits light can be applied. For example, indium oxide zinc oxide or indium tin oxide can be applied.

The colored layer 722 has a function of transmitting light exhibiting one of, for example, red (R), green (G), and blue (B). As the colored layer 722, a layer containing a dye or a pigment can be used.

As the insulating layer 723, a layer containing a material such as silicon oxide, silicon nitride, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, or hafnium oxide can be applied. In addition, the insulating layer 723
You may use a layer of material applicable to.

As the liquid crystal layer 750, a layer including, for example, a TN liquid crystal, an OCB liquid crystal, an STN liquid crystal, a VA liquid crystal, an ECB type liquid crystal, a GH liquid crystal, a polymer dispersion type liquid crystal, a discotic liquid crystal, or the like can be used.

As the liquid crystal layer 760, for example, a layer containing a liquid crystal showing a blue phase can be applied.

The layer containing a liquid crystal exhibiting a blue phase is composed of, for example, a liquid crystal composition exhibiting a blue phase, a chiral agent, a liquid crystal monomer, a non-liquid crystal monomer, and a liquid crystal composition containing a polymerization initiator. Since the liquid crystal exhibiting the blue phase has a short response time and is optically isotropic, no alignment treatment is required and the viewing angle dependence is small. Therefore, by using a liquid crystal exhibiting a blue phase, the operation of the liquid crystal display device can be speeded up.

The above is a description of the structural example of the display device shown in FIG.

As described with reference to FIG. 10, in an example of the display device according to the present embodiment, the drive circuit is provided on the same substrate as the pixel circuit. As a result, the number of wirings for connecting the pixel circuit and the drive circuit can be reduced.

(Embodiment 3)
In the present embodiment, an example of an electronic device including a panel using the display device of the second embodiment will be described with reference to FIG.

The electronic device shown in FIG. 11A is an example of a portable information terminal.

The electronic devices shown in FIG. 11A are a housing 1011 and a panel 10 provided on the housing 1011.
A twelve, a button 1013, and a speaker 1014 are provided.

The housing 1011 may be provided with a connection terminal and an operation button for connecting to an external device.

Further, the panel 1012 may be configured by using the display device of the second embodiment.

Further, the panel 1012 may be configured by using the touch panel. As a result, panel 1
Touch detection can be performed in 012. As the touch panel, for example, an optical touch panel, a capacitance type touch panel, a resistance film type touch panel, or the like can be applied.

The button 1013 is provided on the housing 1011. For example, if the button 1013 is a power button, the on state of the electronic device can be controlled by pressing the button 1013.

The speaker 1014 is provided in the housing 1011. The speaker 1014 outputs sound.

A microphone may be provided in the housing 1011. By providing the housing 1011 with a microphone, for example, the electronic device shown in FIG. 7A can function as a telephone.

The electronic device shown in FIG. 11A has a function as one or more of, for example, a telephone, an electronic book, a personal computer, and a gaming machine.

The electronic device shown in FIG. 11B is an example of a foldable information terminal.

The electronic devices shown in FIG. 11B include a housing 1021a, a housing 1021b, and a housing 1021a.
The panel 1022a provided in the housing 1022a, the panel 1022b provided in the housing 1021b, the shaft portion 1023, the button 1024, the connection terminal 1025, the recording medium insertion portion 1026, and the speaker 1027 are provided.

The housing 1021a and the housing 1021b are connected by a shaft portion 1023.

Further, the panels 1022a and 1022b may be configured by using the display device of the second embodiment.

Further, the touch panel may be used to configure the panels 1022a and 1022b. As a result, touch detection can be performed on the panels 1022a and 1022b. As the touch panel, for example, an optical touch panel, a capacitance type touch panel, a resistance film type touch panel, or the like can be applied.

Since the electronic device shown in FIG. 11B has a shaft portion 1023, the panel 1022a and the panel 1022b can be folded so as to face each other.

The button 1024 is provided on the housing 1021b. The button 102 is attached to the housing 1021a.
4 may be provided. For example, if the button 1024 is a power button, the on state of the electronic device can be controlled by pressing the button 1024.

The connection terminal 1025 is provided in the housing 1021a. The connection terminal 1 is connected to the housing 1021b.
025 may be provided. Further, the connection terminal 1025 is the housing 1021a and the housing 10.
A plurality of them may be provided on one or both of 21b. The connection terminal 1025 is shown in FIG. 11 (B).
It is a terminal for connecting an electronic device shown in (1) to another device.

The recording medium insertion unit 1026 is provided in the housing 1021a. The recording medium insertion portion 1026 may be provided in the housing 1021b. Further, the recording medium insertion portion 1026 is the housing 1021a.
And one or both of the housing 1021b may be provided in a plurality. For example, by inserting the card-type recording medium into the recording medium insertion unit, the data of the card-type recording medium can be read out to the electronic device, or the data in the electronic device can be written to the card-type recording medium.

The speaker 1027 is provided in the housing 1021b. The speaker 1027 outputs sound. The speaker 1027 may be provided in the housing 1021a.

A microphone may be provided in the housing 1021a or the housing 1021b. By providing the microphone in the housing 1021a or the housing 1021b, for example, the electronic device shown in FIG. 11B can be made to function as a telephone.

The electronic device shown in FIG. 11B has a function as one or more of, for example, a telephone, an electronic book, a personal computer, and a gaming machine.

The electronic device shown in FIG. 11C is an example of a stationary information terminal. The electronic devices shown in FIG. 11C include a housing 1031, a panel 1032 provided on the housing 1031, and a button 10.
33 and a speaker 1034 are provided.

Further, the panel 1032 may be configured by using the display device of the second embodiment.

Further, the panel 1032 may be configured by using the touch panel. As a result, panel 1
Touch detection can be performed at 032. As the touch panel, for example, an optical touch panel, a capacitance type touch panel, a resistance film type touch panel, or the like can be applied.

A panel similar to the panel 1032 may be provided on the deck portion 1035 of the housing 1031.

Further, the housing 1031 may be provided with a ticket output unit for outputting a ticket or the like, a coin insertion unit, a bill insertion unit, or the like.

The button 1033 is provided on the housing 1031. For example, if the button 1033 is a power button, the on state of the electronic device can be controlled by pressing the button 1033.

The speaker 1034 is provided in the housing 1031. The speaker 1034 outputs audio.

The electronic device shown in FIG. 11C has a function as, for example, an automated teller machine, an information communication terminal (also referred to as a multimedia station) for ordering tickets, or a gaming machine.

FIG. 11D is an example of a stationary information terminal. The electronic devices shown in FIG. 11D include a housing 1041, a panel 1042 provided in the housing 1041, a support base 1043 for supporting the housing 1041, a button 1044, a connection terminal 1045, and a speaker 1046. , Equipped with.

The housing 1041 may be provided with a connection terminal for connecting to an external device.

Further, the panel 1042 may be configured by using the display device of the second embodiment.

Further, the panel 1042 may be configured by using the touch panel. As a result, panel 1
Touch detection can be performed in 042. As the touch panel, for example, an optical touch panel, a capacitance type touch panel, a resistance film type touch panel, or the like can be applied.

The button 1044 is provided in the housing 1041. For example, if the button 1044 is a power button, the on state of the electronic device can be controlled by pressing the button 1044.

The connection terminal 1045 is provided in the housing 1041. The connection terminal 1045 is a terminal for connecting the electronic device shown in FIG. 11D to another device. For example, when the electronic device shown in FIG. 11D is connected to the personal computer by the connection terminal 1045, an image corresponding to the data signal input from the personal computer can be displayed on the panel 1042. For example, if the panel 1042 of the electronic device shown in FIG. 11D is larger than the panel of the other electronic device to which the panel 1042 is connected, the display image of the other electronic device can be enlarged, and it is easy for a plurality of people to visually recognize at the same time. Become.

The speaker 1046 is provided in the housing 1041. The speaker 1046 outputs audio.

The electronic device shown in FIG. 11D has a function as one or more of, for example, an output monitor, a personal computer, and a television device.

The above is the description of the example of the electronic device shown in FIG.

As described with reference to FIG. 11, in the electronic device according to the present embodiment, a highly reliable electronic device can be provided by providing the panel with the panel using the display device of the second embodiment.

11 Transistor 12 Transistor 13 Transistor 14 Transistor 15 Transistor 31 Pulse output circuit 32 Protection circuit 33 Protection circuit 61 Transistor 62 Transistor 63 Transistor 64 Transistor 65 Transistor 66 Transistor 67 Transistor 68 Transistor 69 Transistor 70 Transistor 71 Transistor 72 Transistor 73 Transistor 74 Transistor 75 Transistor 76 Transistor 201 Pixel 202 Drive circuit 211 Pleist circuit 221 Gate driver 223 Source driver 225 Protection circuit 230 Liquid crystal element 231_1 Transistor 231_1 Transistor 233_1 Transistor 233_1 Transistor 234 Transistor 235 Light emitting element 311 Period 312 Period 313 Period 700 Substrate 701 Insulation layer 703a Conductive layer 703b Conductive layer 703c Conductive layer 704 Insulation layer 705a Semiconductor layer 705b Semiconductor layer 706a Conductive layer 706b Conductive layer 706c Conductive layer 706d Conductive layer 707 Insulation layer 708 Insulation layer 709a Conductive layer 709b1 Conductive layer 709 Layer 712 Conductive layer 720 Substrate 721 Conductive layer 722 Colored layer 723 Insulation layer 750 Liquid crystal layer 751 Sealing material 760 Liquid crystal layer 1011 Housing 1012 Panel 1013 Button 1014 Speaker 1021a Housing 1021b Housing 1022a Panel 1022b Panel 1023 Shaft 1024 Button 1025 Connection Terminal 1026 Recording medium insertion part 1027 Speaker 1031 Housing 1032 Panel 1033 Button 1034 Speaker 1035 Deck 1041 Housing 1042 Panel 1043 Support stand 1044 Button 1045 Connection terminal 1046 Speaker

Claims (1)

It has the same conductive type 1st to 5th transistors and has
One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor.
The other of the source or drain of the first transistor is electrically connected to the wiring to which the clock signal is supplied.
The other of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor.
The other of the source or drain of the second transistor is electrically connected to the wiring from which the output signal is output.
The other of the source or drain of the third transistor is electrically connected to the wiring to which the first potential (VSS) is supplied.
One of the source or drain of the fourth transistor is electrically connected to the gate of the first transistor.
One of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor.
The other of the source or drain of the fourth transistor is electrically connected to the wiring to which the second potential (SiO) is supplied.
One of the source or drain of the fifth transistor is electrically connected to the gate of the first transistor.
The other of the source or drain of the fifth transistor is electrically connected to the wiring to which the third potential (( VDD + VSS) / 2) is supplied.
The gate of the fifth transistor is an output circuit electrically connected to the gate of the third transistor.

Images