JP2019075579A5 - - Google Patents
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- JP2019075579A5 JP2019075579A5 JP2019002112A JP2019002112A JP2019075579A5 JP 2019075579 A5 JP2019075579 A5 JP 2019075579A5 JP 2019002112 A JP2019002112 A JP 2019002112A JP 2019002112 A JP2019002112 A JP 2019002112A JP 2019075579 A5 JP2019075579 A5 JP 2019075579A5
- Authority
- JP
- Japan
- Prior art keywords
- film
- mask
- substrate
- isocyanate
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 description 13
- IQPQWNKOIGAROB-UHFFFAOYSA-N [N-]=C=O Chemical compound [N-]=C=O IQPQWNKOIGAROB-UHFFFAOYSA-N 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 150000001412 amines Chemical class 0.000 description 6
- 229920000642 polymer Polymers 0.000 description 4
- XSQUKJJJFZCRTK-UHFFFAOYSA-N Urea Natural products NC(N)=O XSQUKJJJFZCRTK-UHFFFAOYSA-N 0.000 description 3
- 125000003277 amino group Chemical group 0.000 description 3
- 239000004202 carbamide Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 230000000379 polymerizing Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
Description
本発明の半導体装置の製造方法は、基板に対して処理を行い、半導体装置を製造する方法において、
被エッチング膜が形成された基板の表面に重合用の原料であるイソシアネートとアミンとを供給して、尿素結合を有する重合体からなるマスク用の膜を形成する工程と、
前記マスク用の膜にエッチング用のパターンを形成する工程と、
次いで前記パターンを用いて前記被エッチング膜を処理ガスによりエッチングする工程と、
その後、前記基板を加熱して前記重合体を解重合して前記マスク用の膜を除去する工程と、
を含み、
前記イソシアネートはイソシアネート基を１つのみ有する一官能性分子であるか、あるいは前記アミンはアミノ基を１つのみ有する一官能性分子であることを特徴とする。
A method of manufacturing a semiconductor device according to the present invention is a method of processing a substrate to manufacture a semiconductor device,
Supplying isocyanate and amine, which are raw materials for polymerization, to the surface of a substrate on which a film to be etched is formed, to form a film for a mask made of a polymer having a urea bond;
Forming an etching pattern on the mask film;
And then etching the film to be etched with a processing gas using the pattern;
Thereafter, the substrate is heated to depolymerize the polymer to remove the film for the mask;
Including
The isocyanate is a monofunctional molecule having only one isocyanate group, or the amine is a monofunctional molecule having only one amino group.
本発明の真空処理装置は、イソシアネートとアミンとを重合させて形成された尿素結合を有する重合体からなるマスク用の膜が被エッチング膜の上に形成され、前記マスク用の膜の上にマスクパターンを形成している膜が積層されている基板を、真空容器内にて処理ガスによりエッチングして前記マスクパターンを前記マスク用の膜に転写するための第１のエッチング処理モジュールと、
第１のエッチング処理モジュールにてエッチングされた基板を、真空容器内にて前記マスク用の膜をマスクとして処理ガスにより被エッチング膜をエッチングするための第２のエッチング処理モジュールと、
前記第２のエッチング処理モジュールにてエッチングされた後の基板を真空容器内にて加熱して前記マスク用の膜を解重合して除去するための除去モジュールと、
を備え、
前記イソシアネートはイソシアネート基を１つのみ有する一官能性分子であるか、あるいは前記アミンはアミノ基を１つのみ有する一官能性分子であることを特徴とする。
In the vacuum processing apparatus of the present invention, a film for a mask made of a polymer having a urea bond formed by polymerizing an isocyanate and an amine is formed on a film to be etched, and a mask is formed on the film for the mask A first etching processing module for etching a substrate on which a film forming a pattern is laminated with a processing gas in a vacuum vessel to transfer the mask pattern to a film for the mask;
A second etching module for etching a film to be etched by a processing gas using a substrate etched by the first etching module as a mask in the vacuum vessel using the film for the mask as a mask;
A removal module for heating the substrate after being etched by the second etching module in a vacuum vessel to depolymerize and remove the film for the mask;
Equipped with
The isocyanate is a monofunctional molecule having only one isocyanate group, or the amine is a monofunctional molecule having only one amino group .
本発明の基板処理装置は、被エッチング膜が形成された基板の表面に、イソシアネート、アミンを各々液体またはミストとして供給して尿素結合を有する重合体からなるマスク用の膜を形成するための成膜部と、
前記マスク用の膜が成膜された基板にレジストを塗布するためのレジスト塗布部と、
レジストが塗布された基板を加熱処理する露光前の加熱処理部と、
露光後の基板を加熱処理する露光後の加熱処理部と、
加熱処理された基板を現像するための現像処理部と、
基板を処理する各部の間の搬送を行うための搬送機構と、を備え、
前記イソシアネートはイソシアネート基を１つのみ有する一官能性分子であるか、あるいは前記アミンはアミノ基を１つのみ有する一官能性分子であることを特徴とする。
The substrate processing apparatus of the present invention, the surface of the substrate film to be etched is formed, Lee isocyanate, amine to form a film for mask made of polymer supplied to having a urea bond as each liquid or mist A deposition unit,
A resist application unit for applying a resist to the substrate on which the film for the mask is formed;
A heat processing unit before exposure which heats a substrate coated with a resist;
A post-exposure heat treatment section for subjecting the exposed substrate to heat treatment;
A development processing unit for developing the heat-treated substrate;
A transport mechanism for transporting between the units for processing the substrate;
The isocyanate is a monofunctional molecule having only one isocyanate group, or the amine is a monofunctional molecule having only one amino group.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016143265 | 2016-07-21 | ||
| JP2016143265 | 2016-07-21 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017206391A Division JP6465189B2 (en) | 2016-07-21 | 2017-10-25 | Semiconductor device manufacturing method and vacuum processing apparatus |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019075579A JP2019075579A (en) | 2019-05-16 |
| JP2019075579A5 true JP2019075579A5 (en) | 2019-06-20 |
| JP6610812B2 JP6610812B2 (en) | 2019-11-27 |
Family
ID=61165976
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017206391A Active JP6465189B2 (en) | 2016-07-21 | 2017-10-25 | Semiconductor device manufacturing method and vacuum processing apparatus |
| JP2019002112A Active JP6610812B2 (en) | 2016-07-21 | 2019-01-09 | Semiconductor device manufacturing method, vacuum processing apparatus, and substrate processing apparatus |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017206391A Active JP6465189B2 (en) | 2016-07-21 | 2017-10-25 | Semiconductor device manufacturing method and vacuum processing apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (2) | JP6465189B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6910319B2 (en) * | 2018-04-23 | 2021-07-28 | 東京エレクトロン株式会社 | How to etch the organic region |
| JP7058545B2 (en) * | 2018-04-25 | 2022-04-22 | 東京エレクトロン株式会社 | Gas supply pipe cleaning method and processing system |
| JP7045929B2 (en) * | 2018-05-28 | 2022-04-01 | 東京エレクトロン株式会社 | Manufacturing method of semiconductor equipment and substrate processing equipment |
| US20200203150A1 (en) * | 2018-06-05 | 2020-06-25 | Tokyo Electron Limited | Composition for film deposition and film deposition apparatus |
| JP2019212776A (en) * | 2018-06-05 | 2019-12-12 | 東京エレクトロン株式会社 | Composition for deposition and deposition apparatus |
| JP2019212777A (en) * | 2018-06-05 | 2019-12-12 | 東京エレクトロン株式会社 | Composition for deposition and deposition apparatus |
| JP7169910B2 (en) * | 2019-03-11 | 2022-11-11 | 東京エレクトロン株式会社 | Semiconductor device manufacturing method |
| JP7192588B2 (en) * | 2019-03-12 | 2022-12-20 | 東京エレクトロン株式会社 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD |
| JP7193731B2 (en) * | 2019-03-29 | 2022-12-21 | 東京エレクトロン株式会社 | Etching method and etching apparatus |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4810601A (en) * | 1984-12-07 | 1989-03-07 | International Business Machines Corporation | Top imaged resists |
| JPH0335239A (en) * | 1989-06-30 | 1991-02-15 | Toshiba Corp | Production of semiconductor device |
| JPH0517285A (en) * | 1991-07-12 | 1993-01-26 | Fuji Xerox Co Ltd | Formation of multilayered resist |
| JPH07258370A (en) * | 1994-03-28 | 1995-10-09 | Ulvac Japan Ltd | Production of polyurea film |
| JP3863934B2 (en) * | 1995-11-14 | 2006-12-27 | 株式会社アルバック | Method for forming polymer thin film |
| JP2005292528A (en) * | 2004-04-01 | 2005-10-20 | Jsr Corp | Composition for forming resist lower layer film, resist lower film and method for forming pattern |
| JP5360416B2 (en) * | 2008-01-11 | 2013-12-04 | 日産化学工業株式会社 | Silicon-containing resist underlayer film forming composition having urea group |
| JP5860668B2 (en) * | 2011-10-28 | 2016-02-16 | 東京エレクトロン株式会社 | Manufacturing method of semiconductor device |
| JP6226142B2 (en) * | 2012-07-02 | 2017-11-08 | 日産化学工業株式会社 | Method of manufacturing semiconductor device using organic underlayer film forming composition for solvent development lithography process |
| JP2014056884A (en) * | 2012-09-11 | 2014-03-27 | Konica Minolta Inc | Electronic device and manufacturing method of the same |
| JP6239466B2 (en) * | 2014-08-15 | 2017-11-29 | 東京エレクトロン株式会社 | Manufacturing method of semiconductor device |
-
2017
- 2017-10-25 JP JP2017206391A patent/JP6465189B2/en active Active
-
2019
- 2019-01-09 JP JP2019002112A patent/JP6610812B2/en active Active
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