JP2019071769A - Drive circuit for output transistor, semiconductor device, and automobile - Google Patents

Abstract

To reduce an on-resistance of an output transistor Min such a situation that an input voltage Vis low.SOLUTION: A drive circuit 200 drives an output transistor Mdepending on a control signal S. A gate of a first transistor Mis biased, and a source thereof is connected with an internal line 201. A control electrode of the output transistor Mis applied with a voltage Vof the internal line 201 during an ON period of the output transistor M. A voltage correction circuit 270 acts on the internal line 201 to gently reduce the voltage Vof the internal line 201 with time.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a driving technology of a P-channel or PNP transistor.

  A drive circuit of a switching regulator, an inverter, a converter, and a relay includes a switching output circuit such as a half bridge circuit or a full bridge (H bridge) circuit.

FIG. 1 is a circuit diagram showing a configuration of an output circuit 1 examined by the present inventor. The output circuit 1 includes an output transistor M _H and a drive circuit 2. The output transistor M _H is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the source is connected to the input terminal IN, and the drain is connected to the output terminal OUT. The drive circuit 2 controls the gate voltage V _G of the output transistor M _H in response to the control signal S _CTRL .

In applications where the input voltage V _IN is relatively low, it is common to switch the gate voltage V _G between the input voltage V _IN and the ground voltage V _GND . However, in applications where the input voltage V _IN is high, the gate voltage V _G is set between the input voltage V _IN and the predetermined voltage V _REGB (= V _IN −ΔV) in consideration of the gate withstand voltage of the output transistor M _{H and} the like. It is common to switch. ΔV is the output transistor corresponds to the amplitude of the gate-source voltage of _{M H,} defined greater than the output transistor _{M H} of the gate-source threshold _{V GS (th).} For example, ΔV = 5 V or so.

The drive circuit 2 includes a driver 4, a voltage source 6, and a level shifter 8. The voltage source 6 generates a power supply voltage (also referred to as an internal power supply voltage) V _REGB lower than the input voltage V _IN by a predetermined voltage ΔV. The input voltage V _IN is supplied to the upper power supply terminal of the driver 4, and the internal power supply voltage V _REGB is supplied to the lower power supply terminal. The level shifter 8 shifts the level of the control signal S _CTRL that makes the power supply voltage V _REG high and the ground voltage V _GND low to a control signal S _CTRL 'that makes V _IN high and V _REGB low, and supplies the driver 4 Do. The driver 4 generates a gate voltage V _G which changes in the range of high (V _IN ) and low (V _REGB ) in response to the control signal S _CTRL '.

The voltage source 6 is configured of a source follower type clamp circuit. Specifically, a bias voltage V _BIAS lower than the input voltage V _IN by a predetermined voltage (V _Z ) is supplied to the gate of the first transistor M ₁ . When the first gate-source voltage of the transistor M ₁ and V _TH, the following relationship holds.
V _REGB = V _IN −V _Z + V _TH = V _BIAS + V _TH
That is, the amplitude ΔV of the voltage V _GS between the gate and the source of the output transistor M _H is ΔV = (V _Z −V _TH ).

JP, 2017-77145, A

(First issue)
The above is the configuration of the output circuit 1. As a result of examining the output circuit 1 of FIG. 1, the present inventors came to recognize the following problems.

FIG. 2 is a diagram showing input / output characteristics of the voltage source 6 of FIG. The horizontal axis indicates the input voltage V _IN . FIG. 2 shows the input voltage V _IN and the bias voltage V _BIAS in addition to the internal power supply voltage V _REGB .

In order for the voltage source 6 to operate properly, the potential V _BIAS of the gate of the first transistor M ₁ must be higher than the saturation voltage V _SAT of the current source 7.
V _BIAS > V _SAT
That is, in the low voltage region where V _IN <V _SAT + V _Z , the difference ΔV between V _IN and V _REGB , that is, the gate-source voltage V _{GS of the} output transistor M _H becomes small. When the voltage V _GS between the gate and the source of the output transistor M _H is small, the on resistance R _ON becomes large and the loss becomes large.

The inventor examined the drive circuit of FIG. 3 in order to solve this problem. FIG. 3 is a circuit diagram of a drive circuit 2R according to a comparison technique. The drive circuit 2R includes a voltage reduction detection circuit 10 and a switch SW1. The reduced voltage detection circuit 10 compares the input voltage V _IN with a predetermined threshold to detect a reduced voltage state. Switch SW1 is provided between the line on which internal power supply voltage V _REGB is generated and the ground. When the reduced voltage state switch SW is turned on, the internal power supply voltage _{V REGB} can provide lowered to the ground voltage _V GND (= 0V), the ground voltage _{V GND} to the gate voltage _{V G} of the output transistor _{M H.}

As another approach, a switch SW2 may be provided between the gate of the output transistor M _H and the ground instead of the switch SW1, and the switch SW2 may be turned on in the low voltage state.

In the drive circuit 2R of FIG. 3, even when the input voltage V _IN is low, the on resistance of the output transistor M _H can be kept small. However, if the switch SW1 or SW2 is turned on even though the input voltage V _IN is sufficiently high due to the malfunction of the reduced voltage detection circuit 10, an overvoltage will be applied between the gate and source of the output transistor M _H. Unreliable.

Although one aspect of the problem is described here focusing on a state in which the input voltage V _IN is low, the application of the present invention is not limited to the state in which the input voltage V _IN is low.

(Second issue)
FIG. 4 is a circuit diagram showing a configuration of the output circuit 1 examined by the present inventor. The output circuit 1 includes an output transistor M _H and a drive circuit 2. The output transistor M _H is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the source is connected to the input terminal IN, and the drain is connected to the output terminal OUT. The drive circuit 2 controls the gate voltage V _G of the output transistor M _H in response to the control signal S _CTRL .

In applications where the input voltage V _IN is relatively low, it is common to switch the gate voltage V _G between the input voltage V _IN and the ground voltage V _GND . However, in applications where the input voltage V _IN is high, the gate voltage V _G is set between the input voltage V _IN and the predetermined voltage V _REGB (= V _IN −ΔV) in consideration of the gate withstand voltage of the output transistor M _{H and} the like. It is common to switch. However, ΔV is approximately 4 to 5 V, and is determined to be larger than the threshold voltage V _{GS (th)} between the gate and the source of the output transistor M _H.

The drive circuit 2 includes a driver 4, a voltage source 6, and a level shifter 8. The voltage source 6 generates a power supply voltage V _REGB lower than the input voltage V _IN by a predetermined voltage ΔV. The input voltage V _IN is supplied to the upper power supply terminal of the driver 4, and the power supply voltage V _REGB is supplied to the lower power supply terminal. The level shifter 8 shifts the level of the control signal S _CTRL that makes the power supply voltage V _DD high and the ground voltage V _GND low to a control signal S _CTRL 'that makes V _IN high and V _REGB low, and supplies it to the driver 4 Do. The driver 4 generates a gate voltage V _G which changes in the range of high (V _IN ) and low (V _REGB ) in response to the control signal S _CTRL '.

The above is the configuration of the output circuit 1. As a result of examining the output circuit 1 of FIG. 4, the present inventors came to recognize the following problem. When turning off the output transistor M _H , the driver 4 sources a current I ₁ to the gate of the output transistor M _H. As a result, the gate capacitance of the output transistor M _H is charged, and the gate voltage V _G rises to near V _IN .

Conversely, when turning on the output transistor M _H , the driver 4 sinks a current I ₂ from the gate of the output transistor M _H. As a result, the gate capacitance of the output transistor M _H is discharged, and the gate voltage V _G falls to near the power supply voltage V _REGB .

Current _{I 2} driver 4 sinks, since flows into the internal power supply line 11 for generating the power supply voltage _{V REGB,} becomes a factor to vary the power supply voltage _{V REGB.} To suppress supply voltage V _REGB, between the input terminal IN and the internal power supply line 11, it is necessary to provide a large capacitor C ₁ of the relatively capacity. If inside integration of the capacitor C ₁ IC (Integrated Circuit), the chip area increases, cost increases. In the case where a configuration for an external capacitor C ₁ to the IC (Integrated the Circuit), number of parts increases, and in order to connect the capacitor C ₁ of the external to the internal power supply line 11, requires additional pins on the IC Become.

The present invention has been made in view of such problems, and one of the exemplary objects of an aspect thereof is to provide a drive circuit that can reduce the on resistance of the output transistor M _H. One of the exemplary objects of another aspect is to provide an output circuit which reduces the capacitance of the capacitor or does not require the capacitor.

1. One embodiment of the present invention relates to a drive circuit which drives an output transistor provided between an input terminal receiving an input voltage and an output terminal according to a control signal. In the drive circuit, an internal line and a control electrode which is a gate or a base are biased, and a first electrode which is a source or an emitter is connected to the internal line and acts on the internal line; And V. a voltage correction circuit that gradually decreases temporally. The voltage of the internal line is applied to the control electrode which is the gate or base of the output transistor during its on period.

  Another aspect of the present invention is also a drive circuit. The drive circuit includes an internal line connected to a control electrode that is the gate or base of the output transistor, a control electrode that is the gate or base biased, and a first electrode that is the source or emitter connected to the internal line. A second transistor which is provided between one transistor and a second electrode which is the drain or collector of the first transistor and the ground, and which turns on and off according to the control signal, and a current source which sinks an auxiliary current from an internal line; And an impedance element provided between the input terminal and the internal line.

  Yet another aspect of the present invention is also a drive circuit. The drive circuit includes an internal line and a first transistor in which a control electrode which is a gate or a base is biased and a first electrode which is a source or an emitter is connected to the internal line, and an upper power supply terminal connected to an input terminal. It has a lower power supply terminal connected to the internal line, an output terminal connected to the control electrode which is the gate or base of the output transistor, and drives the output transistor according to the control signal, and the auxiliary current from the internal line A sink current source and an impedance element provided between an input terminal and an internal line.

2. One embodiment of the present invention relates to a drive circuit that drives an output transistor provided between an input terminal and an output terminal. The drive circuit is provided between the first transistor whose first electrode is connected to the control electrode of the output transistor and whose control electrode is biased, the second electrode of the first transistor and the ground, and the on period of the output transistor And a third transistor provided between the input terminal and the control electrode of the output transistor, and a sub driver for turning on the third transistor in the off period of the output transistor. The sub-driver includes a second resistor provided between the input terminal and the control electrode of the third transistor, and a fourth transistor whose first electrode is connected to the control electrode of the third transistor and whose control electrode is biased And a fifth transistor provided between the second electrode of the fourth transistor and the ground and turned on in the off period of the output transistor. The control electrode of the first transistor and the control electrode of the fourth transistor are biased by separate voltage sources.

  Another aspect of the present invention relates to a semiconductor device. The semiconductor device may include an output transistor and any of the above driver circuits for driving the output transistor.

  Another aspect of the invention relates to a motor vehicle. An automobile may include a mechanical relay and a semiconductor device that drives the mechanical relay.

  It is to be noted that any combination of the above-described constituent elements, or one in which the constituent elements and expressions of the present invention are mutually replaced among methods, apparatuses, systems, etc. is also effective as an aspect of the present invention.

  According to an aspect of the present invention, the on resistance of the output transistor can be reduced. Further, according to an aspect, the capacitance of the capacitor can be reduced or the capacitor can be omitted.

It is a circuit diagram which shows the structure of the output circuit which this inventor examined. It is a figure which shows the input-output characteristic of the voltage source of FIG. It is a circuit diagram of the drive circuit concerning a comparison art. It is a circuit diagram which shows the structure of the output circuit which this inventor examined. FIG. 1 is a circuit diagram of an output circuit according to a first embodiment. FIG. 6 is a diagram for explaining the operation when the input voltage V _IN of the output circuit of FIG. 5 is high (non-low voltage state). It is a figure explaining the operation | movement when the input voltage _VIN of the output circuit of FIG. 5 is low (low voltage area | region). It is a figure explaining the operation | movement when the input voltage _VIN of the output circuit of FIG. 5 is low (low voltage area | region). FIG. 7 is a circuit diagram of an output circuit according to a second embodiment. It is a figure explaining operation _| movement when the input voltage _VIN of the output circuit of FIG. 9 is high. It is a figure explaining the operation _| movement when the input voltage _{VIN of} FIG. 9 is low. FIG. 10 is a circuit diagram of an output circuit according to a third embodiment. It is a block diagram of a relay apparatus. 1 is a perspective view of a motor vehicle provided with a relay device. FIG. 16 is a circuit diagram of an output circuit according to a fourth embodiment. It is a circuit diagram of a semiconductor device provided with an output circuit concerning Example 4.1. FIG. 17 is an operation waveform diagram of the output circuit of FIG. It is a circuit diagram of a semiconductor device provided with the output circuit concerning Example 4.2. FIG. 19 is a circuit diagram of a specific configuration example of the output circuit of FIG. 18; It is a circuit diagram of a semiconductor device provided with the output circuit concerning Example 4.3. FIG. 21 is an operation waveform diagram of the output circuit of FIG. 20. It is a circuit diagram of a semiconductor device provided with the output circuit concerning Example 4.4. 51 is a circuit diagram of a semiconductor device including an output circuit according to Example 4.5.

(Overview of the embodiment)
1. One embodiment disclosed in the present specification relates to a drive circuit that drives an output transistor provided between an input terminal receiving an input voltage and an output terminal according to a control signal. In the drive circuit, an internal line and a control electrode which is a gate or a base are biased, and a first electrode which is a source or an emitter is connected to the internal line and acts on the internal line; And V. a voltage correction circuit that gradually decreases temporally. The voltage of the internal line is applied to the control electrode which is the gate or base of the output transistor during its on period.

  By lowering the voltage of the internal line by the voltage correction circuit, the low level of the gate voltage of the output transistor can be reduced, and the on-resistance can be reduced.

  The voltage correction circuit may include a current source that sinks the auxiliary current from the internal line. By drawing out the charge of the internal line by the auxiliary current, the voltage of the internal line can be gently decreased at a slope corresponding to the amount of current.

  In one embodiment, the drive circuit has an upper power supply terminal connected to the input terminal, a lower power supply terminal connected to the internal line, and an output terminal connected to the control electrode which is the gate or base of the output transistor. And a driver for driving the output transistor in accordance with the control signal.

  In one embodiment, the auxiliary current may be less than the current that the driver sinks from the control electrode of the output transistor during the on period of the output transistor. The auxiliary current thereby does not adversely affect the turn-off during normal switching operation.

  In one embodiment, the drive circuit may further include a second transistor provided between the second electrode which is the drain or the collector of the first transistor and the ground, and turned on / off according to the control signal.

  In one embodiment, the auxiliary current may be less than the current sunk from the control electrode of the output transistor through the second transistor during the on period of the output transistor. The auxiliary current thereby does not adversely affect the turn-off during normal switching operation.

  In one embodiment, the drive circuit may further include a third transistor provided between the input terminal and the control electrode of the output transistor and turned on during a period when the output transistor is to be turned off. The auxiliary current may be smaller than the current flowing to the third transistor in the off period of the output transistor. As a result, the auxiliary current does not adversely affect the turn-off of the normal switching operation.

  In one embodiment, the auxiliary current may be larger than the current flowing into the internal line during the off period of the output transistor in the low voltage state.

  Another aspect of the present disclosure is also a drive circuit. The drive circuit includes an internal line connected to a control electrode that is the gate or base of the output transistor, a control electrode that is the gate or base biased, and a first electrode that is the source or emitter connected to the internal line. A second transistor which is provided between one transistor and a second electrode which is the drain or collector of the first transistor and the ground, and which turns on and off according to the control signal, and a current source which sinks an auxiliary current from an internal line; And an impedance element provided between the input terminal and the internal line.

  In one embodiment, the auxiliary current may be larger than the current flowing through the impedance element and smaller than the current flowing through the first transistor.

  In one embodiment, the driving circuit may further include a third transistor provided between the input terminal and the internal line, and turned on and off complementarily to the second transistor according to the control signal.

  Yet another aspect of the present disclosure is also a drive circuit. The drive circuit includes an internal line and a first transistor in which a control electrode which is a gate or a base is biased and a first electrode which is a source or an emitter is connected to the internal line, and an upper power supply terminal connected to an input terminal. It has a lower power supply terminal connected to the internal line, an output terminal connected to the control electrode which is the gate or base of the output transistor, and drives the output transistor according to the control signal, and the auxiliary current from the internal line A sink current source and an impedance element provided between an input terminal and an internal line.

  In one embodiment, the auxiliary current may be larger than the current flowing through the impedance element and smaller than the current flowing from the lower power supply terminal of the driver to the internal line.

  In one embodiment, the drive circuit may further include a clamp circuit that clamps the voltage of the internal line so that the potential difference with the input voltage does not exceed a predetermined value. The clamp circuit may include a zener diode provided between the input terminal and the internal line.

  In one embodiment, the control signal may be a pulse signal in the normal state of the input voltage, and may be a DC signal that indicates ON in a fixed manner in the reduced voltage state in which the input voltage decreases.

  In one embodiment, the control signal is a pulse signal, and the on-level time of the control signal may be longer as the input voltage decreases.

  The auxiliary current may be turned on or off according to the control signal. The auxiliary current may be fixed on regardless of the level of the control signal.

  In one embodiment, the drive circuit may further include a bias circuit that supplies a bias voltage lower than the input voltage by a predetermined voltage width to the control electrode of the first transistor. The bias circuit may include a first Zener diode provided between the input terminal and the control electrode of the first transistor, and a current source provided between the control electrode of the first transistor and the ground.

  The drive circuit may be integrated on one semiconductor substrate. "Integrated integration" includes the case where all of the circuit components are formed on a semiconductor substrate, and the case where the main components of the circuit are integrally integrated. A resistor, a capacitor or the like may be provided outside the semiconductor substrate. By integrating the circuit as one IC, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

2. One embodiment disclosed herein relates to a drive circuit that drives an output transistor provided between an input terminal and an output terminal. The drive circuit includes a turn-off circuit for supplying a current to a control electrode of the output transistor, a first transistor whose control electrode is connected to a control electrode of the output transistor and whose control electrode is biased, and a second electrode of the first transistor. And a second transistor that is turned on during the on period of the output transistor.

  The first transistor functions as a source follower or emitter follower type voltage clamp circuit, and the voltage of the control electrode of the output transistor when the second transistor is on is stabilized to a predetermined voltage. When the first transistor is turned on, the discharge current drawn from the gate capacitance (base capacitance) of the first transistor flows through the first transistor and the second transistor to the ground. Therefore, the voltage fluctuation of the control electrode of the output transistor can be suppressed.

In one embodiment, the turn-off circuit may include a third transistor provided between the input terminal and the control electrode of the output transistor, and a sub-driver for turning on the third transistor during the off period of the output transistor.
The turn-off speed can be increased by charging the capacity of the control electrode of the output transistor through the third transistor when the output transistor is turned on.

In one embodiment, the sub-driver is connected to the second resistor provided between the input terminal and the control electrode of the third transistor, and the first electrode thereof to the control electrode of the third transistor, and the control electrode is biased. And a fifth transistor provided between the second electrode of the fourth transistor and the ground and turned on in the off period of the output transistor.
According to this aspect, the low level of the drive voltage of the third transistor can be stabilized to a predetermined voltage.

  In one embodiment, the control electrodes of the first and fourth transistors may be biased by a common voltage source. When the second transistor is turned off, the potential of the control electrode of the first transistor and hence the control electrode of the fourth transistor fluctuates due to the gate capacitance of the first transistor. At this time, when the fifth transistor is turned on, fluctuation of the control electrode of the fourth transistor appears as voltage fluctuation of the control electrode of the third transistor. Fluctuations in the voltage at the control electrode of the third transistor adversely affect the turn-off operation of the output transistor. On the other hand, when the fifth transistor is turned off, the potential of the control electrode of the fourth transistor, that is, the control electrode of the first transistor fluctuates due to the gate capacitance of the fourth transistor. At this time, when the second transistor is turned on, fluctuation of the control electrode of the first transistor appears as voltage fluctuation of the control electrode of the output transistor. In order to suppress this voltage fluctuation, a smoothing capacitor may be connected to a common voltage source.

  In one embodiment, the control electrode of the first transistor and the control electrode of the fourth transistor may be biased by separate voltage sources. In this case, the fluctuation of the control electrodes of the first and fourth transistors does not affect each other, so that the fluctuation of the control electrode of the output transistor can be suppressed even without the smoothing capacitor.

  In one embodiment, the drive circuit may further comprise a first resistor provided between the input terminal and the control electrode of the output transistor.

  In one embodiment, the drive circuit is configured to supply a first voltage source that supplies a first bias voltage to a control electrode of a first transistor, and a second voltage that supplies a second bias voltage to a control electrode of a fourth transistor. And a second voltage source independent of the source. The first voltage source and the second voltage source may have the same circuit configuration.

  The first voltage source includes a constant voltage element provided between the input terminal and the control electrode of the first transistor, and the second voltage source is a constant voltage provided between the input terminal and the control electrode of the fourth transistor An element may be included.

  In one embodiment, a plurality of third transistors and sub drivers may be provided. The fifth transistors of the plurality of sub drivers may switch complementarily in each stage. The third transistor in the final stage is provided between the input terminal and the control electrode of the output transistor, and the third transistor in the previous stage is provided between the input terminal and the control electrode of the third transistor in the subsequent stage It is also good. The control electrodes of the fourth transistor adjacent to the first transistor and the first transistor in one step are biased by the common first voltage source, and the control electrodes of the remaining fourth transistors are separated by the common second voltage source. It may be biased.

  The drive circuit may be integrated on one semiconductor substrate. "Integrated integration" includes the case where all of the circuit components are formed on a semiconductor substrate, and the case where the main components of the circuit are integrally integrated. A resistor, a capacitor or the like may be provided outside the semiconductor substrate. By integrating the circuit as one IC, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

Embodiment
Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and duplicating descriptions will be omitted as appropriate. In addition, the embodiments do not limit the invention and are merely examples, and all the features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In the present specification, “the state in which the member A is connected to the member B” means that the members A and B are electrically connected in addition to the case where the members A and B are physically and directly connected. It also includes the case of indirect connection via other members that do not substantially affect the connection state of the connection or do not impair the function or effect provided by the connection.

  Similarly, "a state where the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, and It also includes the case of indirect connection via other members that do not substantially affect the connection state of the connection or do not impair the function or effect provided by the connection.

Embodiment 1
FIG. 5 is a circuit diagram of the output circuit 100 according to the first embodiment. The output circuit 100 includes an output transistor M _H and a drive circuit 200. In the present embodiment, the output circuit 100 is a part of a functional IC (semiconductor device 300) integrated on one semiconductor substrate.

The output transistor M _H may be an upper arm of a half bridge circuit (single phase inverter). Alternatively, the output transistor M _H may be the upper arm of one leg of a full bridge circuit or a three-phase inverter. An inductive element such as an inductor, a transformer, a motor coil, or a coil of a relay may be connected to the output terminal OUT. Alternatively, the output transistor M _H may be a switching transistor of a buck converter.

The output transistor M _H is provided between the input terminal IN and the output terminal OUT. The output transistor M _H is a P-channel MOSFET, the source is connected to the input terminal IN, and the drain is connected to the output terminal OUT. The output transistor _MH may be a GaN FET, an IGBT (Insulated Gate Bipolar Transistor), or a PNP bipolar transistor.

The drive circuit 200 drives the output transistor M _H in response to the control signal S _CTRL . Specifically, the control signal _{S CTRL} is turned on the output transistor _{M H} when on level (e.g. high), the control signal _{S CTRL} turns off the output transistor _{M H} when the off-level (e.g., low). The control signal S _CTRL is typically a pulse signal, but it may be a DC signal as well. The output terminal OUT, and the output voltage _{V OUT} is generated in response to the control signal _{S CTRL,} the output voltage _{V OUT,} the output transistor _{M H} is an input voltage _{V IN} When on, when the output transistor _{M H} is off , Ground voltage V _GND or high impedance state.

The driving circuit 200 mainly includes an internal line 201, a first transistor M ₁ , and a voltage correction circuit 270. First, portions other than the voltage correction circuit 270 will be described.

The first transistor M ₁ is a P-channel MOSFET, the gate (control electrode) is biased by a predetermined bias voltage (reference voltage) V _BIAS , and the source (first electrode) is connected to the internal line 201. The impedance element R ₁ is provided between the input terminal IN and the internal line 201. Impedance element R ₁ may be a resistor, it may be a current source, may be suitably biased transistors.

The bias circuit 240 generates a bias voltage V _BIAS that is lower than the input voltage V _IN by a predetermined voltage. For example, the bias circuit 240 includes a zener diode which is a constant voltage element 242, and a current source 244. At a connection node between constant voltage element 242 and current source 244, a bias voltage V _BIAS represented by V _BIAS = V _IN -V _Z is generated.

The first transistor _{M 1} acts as a source follower circuit, the internal power supply voltage _{V REGB} internal line 201 _is stabilized to _{V REGB = V BIAS + V TH} = V IN -V Z + V TH.

The drive circuit 200 is configured to apply the internal power supply voltage V _REGB of the internal line 201 to the gate of the output transistor M _{H in} the on period (S _CTRL = H).

In the first embodiment, the driver 204 is provided. The upper power supply terminal of the driver 204 is connected to the input terminal IN, the lower power supply terminal is connected to the internal line 201, and the output is connected to the gate (control electrode) of the output transistor M _H.

  Up to this point, the description has been based on the voltage correction circuit 270 being ignored. Subsequently, the voltage correction circuit 270 will be described.

The voltage correction circuit 270 acts on the internal line 201 and slowly reduces the voltage of the internal line 201 in time. The voltage correction circuit 270 is active at least in the on period (S _CTRL is high) of the output transistor M _H. In the off period, the voltage correction circuit 270 may be disabled (high impedance state) or may be maintained in the active state.

Voltage correction circuit 270 includes a current source 272 that draws auxiliary current I _AUX from internal line 201. The configuration of current source 272 is not particularly limited, but may include appropriately biased transistors. The voltage correction circuit 270 can be configured by a resistor instead of the current source.

  It is desirable that the amount of auxiliary current be defined so as to satisfy the following conditions.

(Condition 1)
The amount of current of auxiliary current I _AUX is set to be small enough not to affect normal switching operation in the non-low voltage state of input voltage V _IN . Therefore, the auxiliary current I _AUX is sufficiently smaller than the current I _B which the driver 204 sinks from the gate of the output transistor M _{H in} the on period (S _CTRL = H) of the output transistor M _H.
I _AUX << I _B
For example, I _AUX is preferably about 1/1000 to 1/200 of I _B.

(Condition 2)
In addition, the amount of the auxiliary current I _AUX is set to a large value such that the internal power supply voltage V _REGB of the internal line 201 can be gradually reduced in time in the low voltage state of the input voltage V _IN . For example, when the switching period in normal operation and _{T P,} the internal power supply voltage _{V REGB} is at _{T P} or longer _than, to decrease _{V TH,} it may define the amount of current of the auxiliary current _{I AUX.}

Specifically, it is desirable that the auxiliary current I _AUX be larger than the current I _R flowing into the internal line 201 during the off period of the output transistor M _H. The current I _R is mainly a current flowing to the impedance element R ₁ .
I _AUX > I _R
For example, I _AUX is preferably 1.1 or more times I _R.

The output circuit 100 may further include a clamp circuit 280. The clamp circuit 280 is configured to clamp the internal power supply voltage V _REGB of the internal line 201 so that the potential difference with the input voltage V _IN does not exceed a predetermined value. But construction of the clamp circuit 280 is limited, it can be composed of a constant voltage element such as a Zener diode ZD _1, for example provided between the input terminal IN and the internal line 201.

The above is the configuration of the output circuit 100. Subsequently, the operation will be described.
1. High Input Voltage State FIG. 6 is a diagram for explaining the operation when the input voltage V _IN of the output circuit 100 of FIG. 5 is high (non-low voltage state). Here, the auxiliary current I _AUX is switched in accordance with the control signal S _CTRL . When the input voltage V _IN is high, the internal power supply voltage V _REGB of the internal line 201 is stabilized to the following voltage level by the first transistor M ₁ . ΔV is larger than the gate-source threshold V _{GS (th)} of the output transistor M _H.
V _REGB = V _IN −ΔV = V _IN − (V _Z −V _TH )

When the control signal _{S CTRL} transitions high, the gate of the output transistor _{M H} by a current _{I B} is discharged, the gate voltage _{V G} is decreased to the internal power supply voltage _{V REGB,} to full-on.

Then, while the control signal S _CTRL is high (ON time T _ON ), the charge of the internal line 201 is discharged by the auxiliary current I _AUX , and the voltage V _REGB of the internal line 201 is gradually discharged with time. However, since I _AUX << I _B , I _AUX does not affect the turn-on operation of the output transistor M _H.

When the input voltage V _IN is high, the control signal S _CTRL is a pulse signal, and the reduction width of the internal power supply voltage V _REGB during the on time T _ON is not so large. _Therefore , the gate-source voltage V _{GS of the} output transistor M _H Does not exceed its pressure resistance.

2. Low input voltage condition (low voltage condition)
FIG. 7 is a diagram for explaining the operation when the input voltage V _IN of the output circuit 100 of FIG. 5 is low (low voltage region). In this example, it is assumed that the control signal S _CTRL is fixed at the on level (high) in the low voltage region.

As shown in FIG. 2, when the input voltage V _IN enters the low voltage region, the difference ΔV between V _IN and V _REGB decreases.

When the control signal S _CTRL transitions high, the current I _B discharges the gate of the output transistor M _H , and the gate voltage V _G falls to the internal power supply voltage V _REGB . However, since ΔV, that is, the voltage between the gate and the source is small, the output transistor _MH can not be fully turned on immediately after turn-on, and the output voltage V _OUT becomes lower than the input voltage V _IN .

Then, while the control signal S _CTRL is high (ON time T _ON ), the charge of the internal line 201 is discharged by the auxiliary current I _AUX , and the internal power supply voltage V _REGB gradually decreases with time. In the low voltage state, since the on time T _ON is long, the internal power supply voltage V _REGB decreases to near 0 V (or a level clamped by the clamp circuit 280), and the potential difference ΔV increases. As a result, the output gate voltage _{V G} of the transistor _{M H} is gradually reduced, the output on-resistance of the transistor _{M H} decreases, the output voltage _{V OUT} approaches the input voltage _{V IN.}

FIG. 8 is a diagram for explaining the operation when the input voltage V _IN of the output circuit 100 of FIG. 5 is low (low voltage region). In this example, the control signal S _CTRL is a pulse signal having a large duty ratio in the low voltage region. Since the discharge time by the auxiliary current I _AUX becomes long as the duty ratio of the control signal S _CTRL increases, the internal power supply voltage V _REGB can be maintained at around 0 V. The operation of FIG. 7 can also be understood as fixing the duty ratio of the control signal S _CTRL in FIG. 6 to 100%.

When the duty ratio of the control signal S _CTRL is d, the effective voltage level of V _OUT is given by the following equation.
V _OUT = V _IN × d
On platforms where effective voltage level V _OUT is taking control such that the constant, by decreasing input voltage V _IN, the duty ratio d is increased.

The above is the operation of the output circuit 100. According to this output circuit 100, in the situation where the input voltage V _IN is low, the on resistance of the output transistor M _H can be reduced, and hence the power loss can be reduced.

Furthermore, the reduced voltage detection circuit 10 for determining the low voltage state and the non-low voltage state shown in FIG. 3 is unnecessary. Therefore, false detection of the low voltage state does not cause a problem that an overvoltage is applied between the gate and the source of the output transistor M _H.

Note that the low voltage state and the non-low voltage state may occur dynamically on one platform. That is, as a result of the fluctuation of the input voltage V _IN , the low voltage state and the non-low voltage state may be switched.

Alternatively, the semiconductor device 300 may be used for platforms with different input voltages V _IN . In this case, one platform may always operate in the low voltage state, and another platform may always operate in the non-low voltage state. The present invention also includes such an aspect.

Second Embodiment
FIG. 9 is a circuit diagram of an output circuit 100B according to the second embodiment. Drive circuit 200B, instead of the driver 204 of FIG. 5, a second transistor _{M 2.} In this embodiment, the first transistor M ₁ of the source (first electrode), i.e. the internal line 201 is connected to the gate of the output transistor M _H.

The second transistor _{M 2,} the first transistor _{M 1} of the drain is provided between the (second electrode) and the ground, on and off in response to the control signal _{S CTRL.} More specifically, the second transistor _{M 2} is an N-channel MOSFET, is provided between the ground and the drain of the first transistor _{M 1.} The second transistor _{M 2,} the control signal _{S CTRL} is when it is on level (high), is controlled to be turned on.

Current source 272 sinks auxiliary current I _AUX from internal line 201. The impedance element R ₁ is provided between the input terminal IN and the internal line 201.

The amount of current of the auxiliary current I _AUX is preferably defined to satisfy the following conditions.
(Condition 1)
Auxiliary current _{I AUX} is in the on period of the output transistor _{M H (S CTRL = H)} , from the discharge current _{I B} which is sunk from the gate of the output transistor _{M H} through the first transistor _{M 1} and the second transistor _{M 2} Even small enough.
I _AUX << I _B
For example, I _AUX is preferably about 1/1000 to 1/200 of I _B.

(Condition 2)
The auxiliary current I _AUX is defined to be smaller than the charging current I _{R (HIGH)} flowing into the internal line 201 in the off period of the output transistor M _H in the non-low voltage state. The current I _{R (HIGH)} is mainly a current flowing to the impedance element R ₁ . As a result, the auxiliary current I _AUX does not affect the turn-off operation.
I _AUX <I _{R (HIGH)}

In addition, the auxiliary current I _AUX is determined to be larger than the current I _{R (LOW)} flowing into the internal line 201 in the on period of the output transistor M _H in the low voltage state. The current I _{R (LOW)} is mainly a current flowing to the impedance element R ₁ .
I _AUX > I _{R (LOW)}

  The above is the configuration of the output circuit 100B. Subsequently, the operation will be described.

FIG. 10 is a diagram for explaining the operation when the input voltage V _IN of the output circuit 100B of FIG. 9 is high. When the control signal _{S CTRL} is high, the second transistor _{M 2} is turned on. As a result, the discharge current _{I B} flows through the first transistor _{M 1} and the second transistor _{M 2,} the charge from the internal line 201 (gate capacitance of the output transistor _{M H)} is discharged, the gate voltage _{V G} is decreased. The first transistor _{M 1} functions as a clamp circuit of a source follower type, the low level of the gate voltage _{V G is,} V _REGB = V IN _- is clamped to (V Z _{-V TH).}

Then, while the control signal S _CTRL is high (on time T _ON ), the charge of the internal line 201 is discharged by the auxiliary current I _AUX , and the voltage V _G of the internal line 201 is gradually discharged with time. However, since I _AUX << I _B , I _AUX does not affect the turn-on operation of the output transistor M _H.

When the input voltage V _IN is high, the control signal S _CTRL is a pulse signal, and the reduction width of the internal power supply voltage V _REGB during the on time T _ON is not so large. _Therefore , the gate-source voltage V _{GS of the} output transistor M _H Does not exceed its pressure resistance.

When the control signal _{S CTRL} is low, the second transistor _{M 2} is turned off. The gate capacitance of the output transistor M _H is charged by the charging current I _R flowing through the resistor R ₁ , the gate voltage V _G rises, and the output transistor M _H turns off.

FIG. 11 is a diagram for explaining the operation when the input voltage V _{IN of} FIG. 9 is low. Here, the duty ratio of the control signal S _CTRL in the low voltage state is 100%. When the control signal S _CTRL transitions high, the current I _B discharges the gate of the output transistor M _H , and the gate voltage V _G falls to the internal power supply voltage V _REGB . However, since ΔV, that is, the voltage between the gate and the source is small, the output transistor _MH can not be fully turned on immediately after turn-on, and the output voltage V _OUT becomes lower than the input voltage V _IN .

Then, while the control signal S _CTRL is high (ON time T _ON ), the charge of the internal line 201 is discharged by the auxiliary current I _AUX , and the gate voltage V _G gradually decreases with time. In the low voltage state, since the on time T _ON is long, the gate voltage V _G decreases to around 0 V (or a level clamped by the clamp circuit 280), and the potential difference ΔV increases. As a result, the output gate voltage _{V G} of the transistor _{M H} is gradually reduced, the output on-resistance of the transistor _{M H} decreases, the output voltage _{V OUT} approaches the input voltage _{V IN.}

Also in the second embodiment, as in the first embodiment, the on resistance of the output transistor M _H in the low voltage state can be reduced, and power consumption can be reduced.

Third Embodiment
FIG. 12 is a circuit diagram of an output circuit 100C according to the third embodiment. Driving circuit 200C, in addition to the output circuit 100B of FIG. 9, a third transistor _{M 3} and the sub-driver 220.

The third transistor _{M 3} are provided between the input terminal IN and the internal line 201, complementarily turned on and the second transistor _{M 2} according to the control signal _{S CTRL,} off. More particularly the third transistor _{M 3} is a P-channel MOSET, is provided between the input terminal IN and the gate line 202.

Sub-driver 220 is in the off period of the output transistor _{M H (S CTRL} is low) to turn on the third transistor _{M 3.} For example, sub driver 220 level shifts control signal S _CTRL switching between V _{DD and} V _GND to gate signal V _G3 switching between an appropriate high voltage and a low voltage (for example, between V _{IN and} V _REGB ). . The low voltage V _REGB may be the same as the low voltage of the gate voltage V _G of the output transistor M _H.

The above is the configuration of the output circuit 100C. In the output circuit 100C, the control signal _{S CTRL} is the third transistor _{M 3} is turned becomes low, the gate capacitance of the output transistor _{M H} is charged by the current _{I A} flowing through the third transistor _{M 3.} Thus, the turn-off time of the output transistor M _H can be shortened as compared with the output circuit 100 B of FIG. 9, and high speed switching can be performed.

In the third embodiment, it is preferable that the following relationship be established.
(Condition 1)
Auxiliary current _{I AUX} is in the on period of the output transistor _{M H (S CTRL = H)} , from the discharge current _{I B} which is sunk from the gate of the output transistor _{M H} through the first transistor _{M 1} and the second transistor _{M 2} Even small enough.
I _AUX << I _B
For example, I _AUX is preferably about 1/1000 to 1/200 of I _B.

(Condition 2)
The auxiliary current I _AUX is specified to be smaller than the charging current I _A flowing into the internal line 201 in the off period of the output transistor M _H in the non-low voltage state. The current _{I A} is the current mainly flows through the third transistor _{M 3.} As a result, the auxiliary current I _AUX does not affect the turn-off operation.
I _AUX <I _A

In addition, the auxiliary current I _AUX is determined to be larger than the current I _{R (LOW)} flowing into the internal line 201 in the on period of the output transistor M _H in the low voltage state. The current I _{R (LOW)} is mainly a current flowing to the impedance element R ₁ .
I _AUX > I _{R (LOW)}

(Use)
Subsequently, the application of the output circuit 100 will be described. The above-described semiconductor device (output circuit) can be used as a drive circuit of a mechanical relay. FIG. 13 is a block diagram of the relay device 400. As shown in FIG. The relay device 400 is used, for example, in automobiles, home appliances, industrial devices, transport devices, and agricultural devices, and is mainly used to control the interruption and conduction of a large current power line.

  The relay device 400 includes a mechanical relay 410 and a drive circuit 500 thereof. The relay device 400 may be jagged.

The mechanical relay 410 includes a coil 412 and a switch 414. The drive circuit 500 corresponds to the above-described semiconductor device 300, and includes a high side transistor M _H , a low side transistor M _L , a high side driver 502, a low side driver 504, and a controller 506. The high side transistor M _H and the low side transistor M _L form a half bridge circuit. The controller 506 generates control signals S _CTRLH and S _CTRLL of the high side transistor M _H and the low side transistor M _L based on the control signal EN from the outside. The high side transistor M _H and the high side driver 502 correspond to the output circuit 100 described above. High-side driver 502 corresponds to the driving circuit 200 described above, to drive the high-side transistor _{M H} on the basis of the control signal _{S CTRLH.} Low-side driver 504 drives the low-side transistor _{M L} based on the control signal _{S CTRLL.}

  FIG. 14 is a perspective view of a car 600 provided with the relay device 400. As shown in FIG. A car 600 comprises a plurality of relays 602, 604, 606. One relay 602 is used for a wiper or a washer. Another relay 604 is used for a power window, a door lock, a power seat, and a power slide door. Yet another relay 606 is used for headlights, starters and the like.

  The present invention has been described above based on the embodiments. It is understood by those skilled in the art that this embodiment is an exemplification, and that various modifications can be made to the combination of each component and each processing process, and such a modification is also within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(Modification 1.1)
In the first to third embodiments, the semiconductor device configured by the MOSFETs has been described. However, any MOSFET can be replaced with a bipolar transistor or the like. In this case, in the above description, the gate may be replaced with the base, the drain as the collector, and the source as the emitter.

(Modification 1.2)
In the first to third embodiments, the case where the output transistor _MH is integrated in the semiconductor device 300 has been described. However, the present invention is not limited thereto. A discrete element may be used as the output transistor _MH .

(Modification 1.3)
The application of the semiconductor device 300 is not limited to the drive circuit of the relay, and switching power supply such as DC / DC converter, motor drive circuit (inverter), AC / DC converter, DC / AC converter (inverter), secondary battery It can also be used for charge and discharge systems and power conditioners.

(Modification 1.4)
In the first to third embodiments, one aspect of the present invention has been described as a technique for suppressing an increase in on-resistance in a low voltage state (voltage reduction state), but the application of the present invention is not limited thereto. The invention is also useful in applications where _IN is high (non-low voltage state). That is, in the source follower type voltage source 6 as shown in FIG.
V _REGB = V _BIAS + V _TH
Is true. Therefore, regardless of the level of the input voltage V _IN, a voltage higher than the bias voltage V _BIAS by the gate-source voltage V _{TH of the} transistor M ₁ is the gate voltage V _G of the output transistor M _H in the on period. In other words, it can be understood that the voltage V _GS between the gate and the source of the output transistor M ₁ is reduced by V _TH . According to the present invention, when it is desired to reduce the influence of V _TH regardless of whether the input voltage V _IN is high or low (for example, a constant voltage V _Z sufficiently larger than the threshold V _{GS (th) of the} output transistor can not be generated ₎ ), Can be used widely.

Embodiment 4
FIG. 15 is a circuit diagram of an output circuit 100 according to the fourth embodiment. The output circuit 100 includes an output transistor M _H and a drive circuit 200. In the present embodiment, the output circuit 100 is a part of a functional IC (semiconductor device 300) integrated on one semiconductor substrate.

The output transistor M _H may be an upper arm of a half bridge circuit (single phase inverter). Alternatively, the output transistor M _H may be the upper arm of one leg of a full bridge circuit or a three-phase inverter. An inductive element such as an inductor, a transformer, a motor coil, or a coil of a relay may be connected to the output terminal OUT. Alternatively, the output transistor M _H may be a switching transistor of a buck converter.

The output transistor M _H is provided between the input terminal IN and the output terminal OUT. The output transistor M _H is a P-channel MOSFET, the source is connected to the input terminal IN, and the drain is connected to the output terminal OUT. The output transistor _MH may be a GaN FET, an IGBT (Insulated Gate Bipolar Transistor), or a PNP bipolar transistor.

The drive circuit 200 drives the output transistor M _H in response to the control signal S _CTRL . Specifically, the control signal _{S CTRL} is turned on the output transistor _{M H} when on level (e.g. high), the control signal _{S CTRL} turns off the output transistor _{M H} when the off-level (e.g., low). The control signal S _CTRL is typically a pulse signal, but it may be a DC signal as well. The output terminal OUT, and the output voltage _{V OUT} is generated in response to the control signal _{S CTRL,} the output voltage _{V OUT,} the output transistor _{M H} is an input voltage _{V IN} When on, when the output transistor _{M H} is off , Ground voltage V _GND or high impedance state.

Drive circuit 200 includes turn-off circuit 210 and turn-on circuit 230. Turn-off circuit 210, in the off period of the output transistors M _H, supplies a charging current to the control electrode of the output transistor M _H (gate), to increase the gate voltage V _G of the output transistor M _H to the vicinity of the input voltage V _IN , Turn off the output transistor M _H.

Turn-on circuit 230 includes a first transistor _{M 1} and the second transistor _{M 2.} The first transistor _{M 1} is a P-channel MOSFET, and a first electrode (source) is connected to the control electrode of the output transistor _{M H} (gate), the bias voltage _{V BIAS1} is supplied to the control electrode (gate) . The bias voltage V _BIAS1 may be a constant voltage. In this case, the first transistor _{M 1} operates as a clamp circuit of a source follower type, the potential _{V G} of the gate line 202 _is clamped as the lower limit of the _{V L = V BIAS1 + V TH} . V _L is referred to as the clamp level. Here, V _L <V _IN −V _{GS (th)} holds.

The second transistor _{M 2} is an N-channel MOSFET, is provided between the ground and the second electrode of the first transistor _{M 1} (drain). The second transistor _{M 2,} the control signal _{S CTRL} is when it is on level (high), is controlled to be turned on.

  The above is the configuration of the output circuit 100. Subsequently, the operation will be described.

When the control signal _{S CTRL} is off level, the second transistor _{M 2} turn-on circuit 230 is off, thus the discharge current _{I 2} flowing to the ground from the gate line 202 is zero. The gate of the output transistor _{M H,} is supplied charging current _{I 1} from the turn-off circuit 210, the gate voltage _{V G} rises to near the input voltage _{V IN,} the output transistor _{M H} is turned off.

When the control signal _{S CTRL} is on level, the second transistor _{M 2} the turn-on circuit 230 is turned on. At this time, a discharge current I ₂ flows from the gate line 202 through the first transistor M ₁ and the second transistor M ₂ . When the gate capacitance by the discharge current _{I 2} is discharged gradually reduces the gate voltage _{V G,} the gate-source voltage _{V GS} exceeds the threshold _{V GS (th),} the output transistor _{M H} is turned on. The gate voltage V _G is clamped by the first transistor M ₁ when it has dropped to the clamp level V _L.

The above is the operation of the output circuit 100. According to this output circuit 100, the discharge current I _{2 at the} time of turning on the output transistor M _H flows to the ground and does not flow to the generation node of the bias voltage V _BIAS1 , so a bias corresponding to the power supply voltage V _REGB of FIG. It does not _swing the voltage V _BIAS1 and hence the clamp level V _L. Therefore, a capacitor for stabilizing bias voltage V _BIAS1 (clamp level V _L ) is not necessary, or its capacitance value can be reduced.

Example 4.1
FIG. 16 is a circuit diagram of a semiconductor device 300A provided with an output circuit 100A according to Embodiment 4.1. Turn-off circuit 210A includes a first resistor _{R 1} provided between the input terminal IN and an output transistor _{M H} gate (gate line 202).

The drive circuit 200A further includes a first voltage source 250. The first voltage source 250, the first gate of the transistor _{M 1,} supplies a bias voltage _{V BIAS1.} The bias voltage V _BIAS1 is a voltage lower than the input voltage V _IN by a predetermined voltage width ΔV, and ΔV> V _{GS (th)} + V _TH holds. First voltage source 250 includes, for example, a first constant voltage element 252 and a first current source 254. The first constant voltage element 252 includes a Zener diode or a diode, and the voltage ΔV across the terminal takes a constant value.

  The above is the configuration of the output circuit 100A. Subsequently, the operation will be described. FIG. 17 is an operation waveform diagram of the output circuit 100A of FIG.

Control signal _{S CTRL} is high interval, the second transistor _{M 2} is turned on, the second transistor _{M 2} voltage _{V A} at the connection node _{N 1} of the first transistor _{M 1} becomes the ground voltage _{V GND.} When the second transistor _{M 2} is turned on, the gate of the output transistor _{M H,} the discharge current _{I 2} is withdrawn through the first transistor _{M 1} and the second transistor _{M 2.} As a result, the gate voltage _{V G} of the output transistor _{M H is, V L = V IN -ΔV +} V TH , and the output transistor _{M H} is turned on. In FIG. 17, it is shown as ΔV = 5V.

Control signal _{S CTRL} is low period, the second transistor _{M 2} is turned off, the discharge current _{I 2} is zero. Gate voltage _{V G} of the output transistor _{M H} is pulled up by the first resistor _{R 1,} the gate capacitance of the output transistor _{M H} by the charging current _{I 1} flowing through the first resistor _{R 1} is charged, the input voltage _{V IN} And the output transistor M _H turns off. At this time, the potential V _A of the node N ₁ approaches the input voltage V _IN . Variation of the first transistor _{M 1} of the drain voltage _{V A,} the first gate voltage of the transistor _{M 1,} i.e. cause variations in the bias voltage _{V BIAS1.} However, the bias voltage _{V BIAS1,} since only utilized in the ON period of the output transistors _{M H,} fluctuation of the bias voltage _{V BIAS1} It should be noted that that does not affect the circuit operation.

Embodiment 4.1 has an advantage that the output circuit 100 of FIG. 15 can be embodied with a simple configuration. On the other hand, the output circuit 100A of FIG. 16 has the following problems. Slew rate of the gate voltage V _G at the time of turning off the first transistor M ₁ (gradient) is defined by a first resistance value of the resistor R _1.

In applications where high speed switching is required, it is necessary to reduce the first resistance value of the resistor R _1. However the first resistor R _1, also the charging current I ₁ continues to flow in the ON period of the output transistor M _H. The charging current I _1, via the first transistor M ₁ and the second transistor M ₂ is discarded to the ground, wasteful power consumption.

That Example 4.1 is in relation of the first transistor M ₁ of the turn-on slew rate and power consumption trade-off, is sometimes difficult to employ in applications balance the high speed and low power consumption are required . In the following embodiments, an output circuit capable of achieving both high speed and low power consumption will be described.

(Example 4.2)
FIG. 18 is a circuit diagram of a semiconductor device 300B provided with an output circuit 100B according to a 4.2. Turn-off circuit 210B, in addition to the first resistor _{R 1,} including a third transistor _{M 3} and the sub-driver 220. The third transistor _{M 3} represents a P-channel MOSET, is provided between the input terminal IN and the gate line 202.

Sub-driver 220 is in the off period of the output transistor _{M H (S CTRL} is low) to turn on the third transistor _{M 3.} For example, sub driver 220 level shifts control signal S _CTRL switching between V _{DD and} V _GND to gate signal V _G3 switching between an appropriate high voltage and a low voltage (for example, between V _{IN and} V _REGB ). . The low voltage V _REGB may be the same as the low voltage of the gate voltage V _G of the output transistor M _H.

Accordingly, the charging current I ₁ of the gate capacitance of the output transistor M _H, since it generated by the third transistor M _3, it turns off the output transistor M _H at a high speed. Since the first resistor R ₁ is capable of sufficiently high, during the ON period of the output transistors M _H, a current flowing through the first resistor R ₁ can be reduced, thereby reducing wasteful power consumption. Thus, according to the output circuit 100B of FIG. 18, both high speed and low power consumption can be achieved.

  FIG. 19 is a circuit diagram of a specific configuration example of the output circuit 100B of FIG. The sub driver 220 is configured similarly to the drive circuit 200 of FIG. 15, and can specifically include a turn-off circuit 222 and a turn-on circuit 224.

More specifically, the sub driver 220 can be configured in the same manner as the drive circuit 200A of FIG. That is, the sub driver 220 includes a second resistor R ₂ corresponding to the turn-off circuit 222, and a fourth transistor M ₄ and a fifth transistor M ₅ forming the turn-on circuit 224. The gate of the fourth transistor _{M 4,} the bias voltage _{V BIAS1} is supplied. The bias voltage V _BIAS1 is generated by the first constant voltage element 252 and the first current source 254, as in FIG.

The inverted signal #S _CTRL of the control signal S _CTRL is input to the gate of the fifth transistor M ₅ , and is turned on in the off period of the output transistor M _H (S _CTRL is low). Operation of the sub-driver 220 of FIG. 19 is similar to the operation of the drive circuit 200A in FIG. 16, the gate voltage _{V G3} of the third transistor _{M 3} are _high the _{V IN,} and the low and _{V L =} V BIAS1 ₊ V _TH Switch by two values.

As described with reference to FIG. 17, the control signal _{S CTRL} is becomes low, the second transistor _{M 2} is turned off. Turn-off of the second transistor _{M 2} is varied the drain voltage _{V A,} further under the influence of the gate capacitance of the first transistor _{M 1,} cause variations in the bias voltage _{V BIAS1.} The bias voltage _{V BIAS1} is supplied to the gate of the fourth transistor _{M 4.} When turning on the fifth transistor _{M 5} this time, the variation of the gate voltage _{V BIAS1} of the fourth transistor _{M 4} is a variation of the gate voltage _{V G3} of the third transistor _{M 3,} the turn-off operation of the output transistor _{M H} (slew rate, etc.) Adversely affect

Conversely, when turning off the fifth transistor _{M 5,} the influence of the gate capacitance of the fourth transistor _{M 4,} the gate voltage of the fourth transistor _{M 4} (i.e. bias voltage _{V BIAS1)} fluctuates. In this case to turn on the second transistor _{M 2,} variation of the gate voltage _{V BIAS1} of the first transistor _{M 1} becomes the fluctuation of the gate voltage _{V G} of the output transistor _{M H,} adversely affect the turn-on operation of the output transistor _{M H.}

Therefore, when the fluctuation of the bias voltage V _BIAS1 is unacceptably large, add a capacitor C ₂ for smoothing, it is necessary to reduce the fluctuation band.

(Example 4.3)
FIG. 20 is a circuit diagram of a semiconductor device 300C provided with an output circuit 100C according to Embodiment 4.3. In Example 4.2 (Fig. 19), the first transistor _{M 1} and the fourth transistor _{M 4} has been biased by a common voltage source. In Example 4.3 the contrary, the first transistor _{M 1} and the fourth transistor _{M 4} is biased by a separate voltage source. Specifically, drive circuit 200C includes a first voltage source 250 and a second voltage source 260. The second voltage source 260 is configured similarly to the first voltage source 250, and includes a second constant voltage element 262 and a second current source 264.

The above is the configuration of the output circuit 100C. Subsequently, the operation will be described. FIG. 21 is an operation waveform diagram of output circuit 100C of FIG. The turn-on circuit 230 and the sub driver 220 operate in a complementary manner in response to the control signal _SCTRL . Therefore, voltages V _A and V _A ′ at two corresponding nodes N ₁ and N ₂ change complementarily, and bias voltages V _BIAS1 and V _BIAS2 also change complementarily. The bias voltage _{V BIAS1} is utilized, the period in which the second transistor _{M 2} is turned on, i.e. is the control signal _{S CTRL} is on time is high, the bias voltage _{V BIAS1} at the on period is stable. Similarly, the bias voltage V _BIAS2 is used during the on period of the fifth transistor M ₅ , that is, the off period during which the control signal S _CTRL is low, but the bias voltage V _BIAS2 is stable in this off period. .

According to the output circuit 100C, the variation in the bias voltage _{V BIAS1, V BIAS2,} the output transistor _{M H,} the third transistor _{M 3} each gate voltage _{V G,} does not affect the row _{V G3.} Thus for capacitor C ₂ as shown in FIG. 19 is not required, it is possible to reduce the circuit area.

(Example 4.4)
FIG. 22 is a circuit diagram of a semiconductor device 300D including an output circuit 100D according to a 4.4. In the circuit of FIG. 19 and FIG. 20, the gate capacitance of the third transistor _{M 3} are, is charged by the second resistor _{R 2.} Thus the third when the size of the transistor M ₃ (W / L) is large, a problem similar to the drive circuit 200A in FIG. 16, i.e., with respect to the drive of the third transistor M _3, both high speed and low power consumption The problem of not being able to occur may occur.
In this embodiment, the third transistor M ₃ and the sub-driver 220 bunk, are connected in series. The third transistor M 3 _{_ 2} of the latter stage is provided between the input terminal IN and the gate of the output transistor M _H. The third transistor M 3 _{_ 1} of the preceding stage is provided between the input terminal IN and the gate of the third transistor M 3 _{_ 2} of one subsequent stage.

The sub driver 220_1 turns on the third transistor M _{3_1} when the control signal S _CTRL is high, and turns off the third transistor M _{3_1} when the control signal S _CTRL is low. The sub drivers 220_1 and 220_2 are similarly configured. The gate of the fourth transistor M _{4 _ 1} of the sub driver 220 _{_ 1} is commonly biased with the gate of the first transistor M ₁ .

Fifth Embodiment
FIG. 23 is a circuit diagram of a semiconductor device 300E provided with an output circuit 100E according to the fifth embodiment. In the fifth embodiment, the output circuit 100D of FIG. 22 is further multistaged. The output circuit 100E, the sub-driver 220_1~220_N is provided a plurality third transistors _M 3_1 _{~M 3_N} and multiple stages (N stages) of (N number), they are connected in a cascade. The sizes (driving capabilities) of the constituent elements of the plurality of third transistors M3 and the sub driver 220 are larger toward the later stages.

The plurality of sub drivers 220_1 to 220_N are similarly configured. i-th sub-driver 220_i (1 ≦ i ≦ N) drives the corresponding third transistor _{M 3_i.} The third transistor M 3 _{_N} of the final stage is provided between the input terminal IN and the gate of the output transistor M _H. The third transistor M 3 _{_j} of the preceding stage (1 ≦ j ≦ N−1) is provided between _the input terminal IN and the gate of the third transistor M _{3 _ (j + 1)} of one _subsequent stage.

The fourth transistor _M 4_N adjacent in skipping the first transistor _{M 1} and the first transistor _{M 1} and one _{stage, M 4_ (N-2)} , the gate of ... is biased by a common voltage source 250. The gates of the remaining fourth transistors M 4 _{_ (N−1)} , M 4 _{_ (N 3),} ... _Are biased by another common voltage source 260.

(Use)
Subsequently, the application of the output circuit 100 will be described. The above-described semiconductor device (output circuit) can be used as a drive circuit of a mechanical relay. The relay device and the automobile equipped with the same are as described with reference to FIGS.

(Modification 4.1)
In the fourth embodiment, a semiconductor device configured by MOSFETs has been described. However, any MOSFET can be replaced with a bipolar transistor or the like. In this case, in the above description, the gate may be replaced with the base, the drain as the collector, and the source as the emitter.

(Modification 4.2)
Although the case where the output transistor _MH is integrated in the semiconductor device 300 has been described in the fourth embodiment, it is not limited thereto, and a discrete element may be used as the output transistor _MH .

(Modification 4.3)
The application of the semiconductor device 300 is not limited to the drive circuit of the relay, and switching power supply such as DC / DC converter, motor drive circuit (inverter), AC / DC converter, DC / AC converter (inverter), secondary battery It can also be used for charge and discharge systems and power conditioners.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only show the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement can be made without departing from the concept of the present invention.

100 output circuit M _H output transistor 200 drive circuit 201 internal line 202 gate line 210 turn-off circuit 204 driver 220 sub-driver 222 turn-off circuit 224 turn-on circuit 230 turn-on circuit 240 bias circuit 242 constant voltage element 244 current source 250 first voltage source 252 1 constant voltage element 254 first current source 260 second voltage source 262 second current source 270 second current source 270 voltage correction circuit 272 current source 280 clamp circuit 300 semiconductor device R ₁ impedance element, first resistance R ₂ second Resistor M ₁ 1st transistor M ₂ 2nd transistor M ₃ 3rd transistor M ₄ 4th transistor M ₅ 5th transistor 400 Relay device 410 Mechanical relay 500 Drive circuit

Claims (28)

A driving circuit that drives an output transistor provided between an input terminal receiving an input voltage and an output terminal according to a control signal,
With the internal line
A first transistor in which a control electrode which is a gate or a base is biased, and a first electrode which is a source or an emitter is connected to the internal line;
A voltage correction circuit that acts on the internal line and causes the voltage of the internal line to decrease gradually in time;
Equipped with
A drive circuit characterized in that a voltage of the internal line is applied to a control electrode which is a gate or a base of the output transistor during the on period.   The drive circuit according to claim 1, wherein the voltage correction circuit includes a current source that sinks an auxiliary current from the internal line.   It has an upper power supply terminal connected to the input terminal, a lower power supply terminal connected to the internal line, and an output terminal connected to a control electrode which is a gate or a base of the output transistor, according to the control signal. The drive circuit according to claim 2, further comprising a driver for driving the output transistor.   The drive circuit according to claim 3, wherein the auxiliary current is smaller than the current sunk from the control electrode of the output transistor by the driver during the on period of the output transistor.   The drive circuit according to claim 1, further comprising: a second transistor provided between a second electrode which is a drain or a collector of the first transistor and the ground, and turned on / off according to the control signal. .   The drive circuit according to claim 5, wherein the auxiliary current is smaller than the current sunk from the control electrode of the output transistor through the second transistor during the on period of the output transistor. And a third transistor provided between the input terminal and the control electrode of the output transistor and turned on during a period when the output transistor is to be turned off.
3. The drive circuit according to claim 2, wherein the auxiliary current is smaller than the current flowing through the third transistor during the off period of the output transistor. A driving circuit that drives an output transistor provided between an input terminal receiving an input voltage and an output terminal according to a control signal,
An internal line connected to a control electrode which is the gate or base of the output transistor;
A first transistor in which a control electrode which is a gate or a base is biased, and a first electrode which is a source or an emitter is connected to the internal line;
A second transistor provided between a second electrode which is a drain or a collector of the first transistor and the ground, and turned on / off according to the control signal;
A current source for sinking an auxiliary current from the internal line;
An impedance element provided between the input terminal and the internal line;
A drive circuit comprising:   The drive circuit according to claim 8, wherein the auxiliary current is larger than a current flowing through the impedance element and smaller than a current flowing through the first transistor.   10. The device according to claim 8, further comprising: a third transistor provided between the input terminal and the internal line, and turned on and off complementarily to the second transistor according to the control signal. Drive circuit. A driving circuit that drives an output transistor provided between an input terminal receiving an input voltage and an output terminal according to a control signal,
With the internal line
A first transistor in which a control electrode which is a gate or a base is biased, and a first electrode which is a source or an emitter is connected to the internal line;
It has an upper power supply terminal connected to the input terminal, a lower power supply terminal connected to the internal line, and an output terminal connected to a control electrode which is a gate or a base of the output transistor, according to the control signal. A driver for driving the output transistor;
A current source for sinking an auxiliary current from the internal line;
An impedance element provided between the input terminal and the internal line;
A drive circuit comprising:   12. The drive circuit according to claim 11, wherein the auxiliary current is larger than the current flowing through the impedance element and smaller than the current flowing from the lower power supply terminal of the driver to the internal line.   The drive circuit according to any one of claims 1 to 12, further comprising a clamp circuit that clamps the voltage of the internal line so that the potential difference with the input voltage does not exceed a predetermined value.   The drive circuit according to claim 13, wherein the clamp circuit includes a Zener diode provided between the input terminal and the internal line.   15. The control signal according to claim 1, wherein the control signal is a pulse signal in a normal state of the input voltage, and is a DC signal which instructs fixedly on in a reduced voltage state in which the input voltage decreases. The drive circuit according to any one.   The drive circuit according to any one of claims 1 to 14, wherein the control signal is a pulse signal, and a time of an on level of the control signal becomes longer in a reduced voltage state in which the input voltage decreases.   The drive circuit according to any one of claims 2 to 12, wherein the auxiliary current is turned on or off in response to the control signal.   The driving circuit according to any one of claims 2 to 12, wherein the auxiliary current is fixed on regardless of the level of the control signal.   The drive circuit according to any one of claims 1 to 18, further comprising a bias circuit that supplies a bias voltage having a predetermined voltage width lower than the input voltage to the control electrode of the first transistor. The bias circuit
A first Zener diode provided between the input terminal and the control electrode of the first transistor;
A current source provided between the control electrode of the first transistor and the ground;
20. The drive circuit of claim 19 including: A driving circuit for driving an output transistor provided between an input terminal and an output terminal, the driving circuit comprising:
A first transistor whose first electrode is connected to a control electrode of the output transistor, the control electrode being biased;
A second transistor provided between the second electrode of the first transistor and the ground and turned on during the on period of the output transistor;
A third transistor provided between the input terminal and the control electrode of the output transistor;
A sub driver that turns on the third transistor during an off period of the output transistor;
Equipped with
The subdriver is
A second resistor provided between the input terminal and the control electrode of the third transistor;
A fourth transistor whose first electrode is connected to the control electrode of the third transistor and whose control electrode is biased;
A fifth transistor provided between the second electrode of the fourth transistor and the ground and turned on in the off period of the output transistor;
Including
A control circuit characterized in that the control electrode of the first transistor and the control electrode of the fourth transistor are biased by different voltage sources.   22. The drive circuit of claim 21, further comprising a first resistor provided between the input terminal and the control electrode of the output transistor. A first voltage source for supplying a first bias voltage to a control electrode of the first transistor;
Supplying a second bias voltage to a control electrode of the fourth transistor, and a second voltage source independent of the first voltage source,
And further
23. The drive circuit according to claim 21, wherein the first voltage source and the second voltage source have the same circuit configuration. The first voltage source includes a constant voltage element provided between the input terminal and the control electrode of the first transistor,
The drive circuit according to claim 23, wherein the second voltage source includes a constant voltage element provided between the input terminal and the control electrode of the fourth transistor. A plurality of the third transistors and the sub drivers are provided, and fifth transistors of the plurality of sub drivers perform complementary switching in each stage,
The third transistor in the final stage is provided between the input terminal and the control electrode of the output transistor, and the third transistor in the previous stage is between the input terminal and the control electrode of the third transistor in the subsequent stage Provided
The control electrodes of the fourth transistor adjacent to the first transistor and the first transistor in one-step skipping are biased by a common first voltage source,
25. A drive circuit according to any of claims 21 to 24, wherein the control electrodes of the remaining fourth transistors are biased by another common second voltage source. A driving circuit for driving an output transistor provided between an input terminal and an output terminal, the driving circuit comprising:
A first transistor whose first electrode is connected to the control electrode of the output transistor;
A second transistor provided between the second electrode of the first transistor and the ground;
A plurality of third transistors,
A plurality of sub drivers corresponding to the plurality of third transistors;
Equipped with
The third transistor in the final stage is provided between the input terminal and the control electrode of the output transistor, and the third transistor in the previous stage is between the input terminal and the control electrode of the third transistor in the subsequent stage Provided
The subdriver is
A second resistor provided between the control terminal of the third transistor corresponding to the input terminal;
A fourth transistor whose first electrode is connected to the control electrode of the corresponding third transistor;
A fifth transistor provided between the second electrode of the fourth transistor and the ground;
Including
The control electrodes of the fourth transistor adjacent to the first transistor and the first transistor in one-step skipping are biased by a common first voltage source,
Driving circuit characterized in that the control electrodes of the remaining fourth transistors are biased by another common second voltage source. An output transistor,
The drive circuit according to any one of claims 1 to 26, which drives the output transistor.
A semiconductor device comprising: Mechanical relay,
The semiconductor device according to claim 27, which drives the mechanical relay.
An automobile characterized by comprising.

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