JP7132063B2 - Driver circuits for output transistors, semiconductor devices, automobiles - Google Patents

Description

The present invention relates to driving techniques for P-channel or PNP type transistors.

Driving circuits for switching regulators, inverters, converters, and relays include switching output circuits such as half-bridge circuits and full-bridge (H-bridge) circuits.

FIG. 1 is a circuit diagram showing the configuration of an output circuit 1 studied by the inventors. The output circuit 1 comprises an output transistor _MH and a drive circuit 2 . The output transistor _MH is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source connected to the input terminal IN and a drain connected to the output terminal OUT. The drive circuit 2 controls the gate voltage _VG of the output transistor _MH according to the control signal _SCTRL .

In applications where the input voltage V _IN is relatively low, it is common to have the gate voltage V _G switch between the input voltage V _IN and ground voltage V _GND . However, in applications where the input voltage V _IN is high, the gate voltage V _G is set between the input voltage V _IN and a predetermined voltage V _REGB (=V _IN -ΔV) in consideration of the gate withstand voltage of the output transistor _MH . Switching is common. ΔV corresponds to the amplitude of the gate-source voltage of the output transistor _MH , and is determined to be larger than the gate-source threshold _VGS(th) of the output transistor _MH . For example, ΔV is about 5V.

Drive circuit 2 includes driver 4 , voltage source 6 and level shifter 8 . A voltage source 6 generates a power supply voltage (also called an internal power supply voltage) V _REGB that is lower than the input voltage _VIN by a predetermined voltage ΔV. An input voltage V _IN is supplied to the upper power supply terminal of the driver 4, and an internal power supply voltage V _REGB is supplied to the lower power supply terminal. The level shifter 8 level-shifts the control signal S _CTRL that sets the power supply voltage V _REG to high and the ground voltage V _GND to low to the control signal S _CTRL ' that sets V _IN to high and V _REGB to low, and supplies it to the driver 4 . do. The driver 4 generates a gate voltage V _G that varies between high (V _IN ) and low (V _REGB ) in accordance with the control signal S _CTRL '.

The voltage source 6 is composed of a source follower type clamp circuit. Specifically, the gate of the _first transistor M1 is supplied with a bias voltage V _BIAS that is lower than the input voltage V _IN by a predetermined voltage (V _Z ). When the gate-source voltage of the _first transistor M1 is _VTH , the following relationship holds.
V _REGB =V _IN -V _Z +V _TH =V _BIAS +V _TH
That is, the amplitude ΔV of the gate-source voltage V _GS of the output transistor M _H is ΔV=(V _Z −V _TH ).

JP 2017-77145 A

(First issue)
The configuration of the output circuit 1 is as described above. As a result of studying the output circuit 1 of FIG. 1, the inventors have come to recognize the following problems.

FIG. 2 is a diagram showing input/output characteristics of the voltage source 6 of FIG. The horizontal axis indicates the input voltage V _IN . FIG. 2 shows the input voltage V _IN and the bias voltage V _BIAS in addition to the internal power supply voltage V _REGB .

In order for the voltage source 6 to operate normally, the potential V _BIAS at the gate of the first transistor M ₁ must be higher than the saturation voltage V _SAT of the current source 7 .
V _BIAS >V _SAT
That is, in the low voltage region where V _IN <V _SAT +V _Z , the difference ΔV between V _IN and V _REGB , that is, the gate-source voltage V _GS of the output transistor M _H becomes small. When the gate-source voltage _VGS of the output transistor _MH is small, its _on -resistance RON becomes large and the loss becomes large.

In order to solve this problem, the inventor studied the drive circuit of FIG. FIG. 3 is a circuit diagram of a drive circuit 2R according to a comparative technique. The drive circuit 2R includes a voltage drop detection circuit 10 and a switch SW1. The voltage drop detection circuit 10 compares the input voltage _VIN with a predetermined threshold to detect a voltage drop state. The switch SW1 is provided between the line generating the internal power supply voltage _{V_REGB} and the ground. When the switch SW is turned on in the reduced voltage state, the internal power supply voltage V _REGB is lowered to the ground voltage V _GND (=0 V), and the ground voltage V _GND can be applied to the gate voltage V _G of the output transistor _MH .

As another approach, instead of the switch SW1, a switch SW2 may be provided between the gate of the output transistor _MH and the ground, and the switch SW2 may be turned on in the reduced voltage state.

In the drive circuit 2R of FIG. 3, the on-resistance of the output transistor _MH can be kept small even when the input voltage _VIN is low. However, if the switch SW1 or SW2 is turned on due to a malfunction of the voltage reduction detection circuit 10 even though the input voltage _VIN is sufficiently high, an overvoltage will be applied between the gate and source of the output transistor _MH , causing the circuit to malfunction. undermining the credibility of

Here, one aspect of the problem has been described by focusing on the state where the input voltage _VIN is low, but the application of the present invention is not limited to the state where the input voltage _VIN is low.

(Second issue)
FIG. 4 is a circuit diagram showing the configuration of the output circuit 1 examined by the inventors. The output circuit 1 comprises an output transistor _MH and a drive circuit 2 . The output transistor _MH is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source connected to the input terminal IN and a drain connected to the output terminal OUT. The drive circuit 2 controls the gate voltage _VG of the output transistor _MH according to the control signal _SCTRL .

In applications where the input voltage V _IN is relatively low, it is common to have the gate voltage V _G switch between the input voltage V _IN and ground voltage V _GND . However, in applications where the input voltage V _IN is high, the gate voltage V _G is set between the input voltage V _IN and a predetermined voltage V _REGB (=V _IN -ΔV) in consideration of the gate withstand voltage of the output transistor _MH . Switching is common. However, ΔV is approximately 4 to 5 V, and is determined to be larger than the gate-source threshold V _{GS (th)} of the output transistor _MH .

Drive circuit 2 includes driver 4 , voltage source 6 and level shifter 8 . A voltage source 6 generates a power supply voltage V _REGB that is lower than the input voltage V _IN by a predetermined voltage ΔV. An input voltage V _IN is supplied to the upper power supply terminal of the driver 4, and a power supply voltage V _REGB is supplied to the lower power supply terminal. The level shifter 8 level-shifts the control signal S _CTRL that sets the power supply voltage V _DD to high and the ground voltage V _GND to low to the control signal S _CTRL ' that sets V _IN to high and V _REGB to low, and supplies it to the driver 4 . do. The driver 4 generates a gate voltage V _G that varies between high (V _IN ) and low (V _REGB ) in accordance with the control signal S _CTRL '.

The configuration of the output circuit 1 is as described above. As a result of studying the output circuit 1 of FIG. 4, the inventors have come to recognize the following problems. In turning off output transistor _MH , driver ₄ sources current I1 to the gate of output transistor _MH . As a result, the gate capacitance of the output transistor _MH is charged, and the gate voltage _VG rises to near _VIN .

Conversely, in turning on output transistor _MH , driver 4 sinks current _I2 from the gate of output transistor _MH . As a result, the gate capacitance of the output transistor _MH is discharged, and the gate voltage _{VG drops to near the power supply voltage VREGB .}

The current _I2 that the driver 4 sinks flows into the internal power supply line 11 in which the power supply voltage _VREGB is generated, and thus causes the power supply voltage _VREGB to fluctuate. In order to suppress fluctuations in the power supply voltage _VREGB , it is necessary to provide _a capacitor C1 with a relatively large capacity between the internal power supply line 11 and the input terminal IN. Integrating the capacitor C1 inside _an IC (Integrated Circuit) increases the chip area and the cost. If the capacitor C1 is externally attached to _an IC (Integrated Circuit), the number of parts increases and an additional pin is required on the IC in order to connect the external capacitor C1 to the internal power supply line ₁₁ . Become.

The present invention has been made in view of the above problems, and one exemplary purpose of certain aspects thereof is to provide a drive circuit capable of reducing the on-resistance of an output transistor _MH . An exemplary object of another aspect is to provide an output circuit that reduces the capacitance of a capacitor or eliminates the need for a capacitor.

1. One aspect of the present invention relates to a drive circuit that drives an output transistor provided between an input terminal that receives an input voltage and an output terminal according to a control signal. The driving circuit includes an internal line, a first transistor biased at a control electrode, which is a gate or base, and a first electrode, which is a source or emitter, connected to the internal line, and acts on the internal line to generate a voltage on the internal line. and a voltage correction circuit that gradually lowers the voltage over time. The voltage of the internal line is applied to the control electrode, which is the gate or base of the output transistor, during its ON period.

Another aspect of the invention is also a drive circuit. This drive circuit includes an internal line connected to the control electrode, which is the gate or base of the output transistor, and a second line, to which the control electrode, which is the gate or base, is biased and the first electrode, which is the source or emitter, is connected to the internal line. 1 transistor, a second transistor provided between a second electrode, which is the drain or collector of the first transistor, and ground, and turned on and off according to a control signal, a current source for sinking an auxiliary current from an internal line; and an impedance element provided between the input terminal and the internal line.

Yet another aspect of the invention is also a drive circuit. The drive circuit includes an internal line, a first transistor biased at a control electrode that is a gate or base and a first electrode that is a source or emitter connected to the internal line, an upper power supply terminal connected to an input terminal, A driver that has a lower power supply terminal connected to the internal line, an output terminal connected to the control electrode that is the gate or base of the output transistor, drives the output transistor according to the control signal, and draws an auxiliary current from the internal line. A sinking current source and an impedance element provided between the input terminal and the internal line.

2. One aspect of the present invention relates to a drive circuit that drives an output transistor provided between an input terminal and an output terminal. A drive circuit is provided between a first transistor whose first electrode is connected to the control electrode of the output transistor and whose control electrode is biased, and between the second electrode of the first transistor and the ground, and the ON period of the output transistor is a third transistor provided between the input terminal and the control electrode of the output transistor; and a sub-driver that turns on the third transistor during the off period of the output transistor. The sub-driver includes a second resistor provided between the input terminal and the control electrode of the third transistor, and a fourth transistor whose first electrode is connected to the control electrode of the third transistor and whose control electrode is biased. , a fifth transistor provided between the second electrode of the fourth transistor and the ground and turned on during the off period of the output transistor. A control electrode of the first transistor and a control electrode of the fourth transistor are biased by separate voltage sources.

Another aspect of the present invention relates to a semiconductor device. A semiconductor device may include an output transistor and any of the drive circuits described above for driving the output transistor.

Another aspect of the invention relates to automobiles. The automobile may include a mechanical relay and a semiconductor device that drives the mechanical relay.

It should be noted that arbitrary combinations of the above-described constituent elements and mutually replacing the constituent elements and expressions of the present invention in methods, devices, systems, etc. are also effective as aspects of the present invention.

According to one aspect of the present invention, the ON resistance of the output transistor can be reduced. Further, according to another aspect, the capacity of the capacitor can be reduced, or the capacitor can be eliminated.

1 is a circuit diagram showing a configuration of an output circuit studied by the inventor; FIG. 2 is a diagram showing input/output characteristics of the voltage source of FIG. 1; FIG. It is a circuit diagram of a drive circuit according to a comparative technique. 1 is a circuit diagram showing a configuration of an output circuit studied by the inventor; FIG. 2 is a circuit diagram of an output circuit according to Embodiment 1; FIG. 6 is a diagram for explaining the operation of the output circuit of FIG. 5 when the input voltage _VIN is high (non-low voltage state); FIG. 6 is a diagram for explaining the operation of the output circuit of FIG. 5 when the input voltage _VIN is low (low voltage region); FIG. 6 is a diagram for explaining the operation of the output circuit of FIG. 5 when the input voltage _VIN is low (low voltage region); FIG. 8 is a circuit diagram of an output circuit according to Embodiment 2; FIG. 10 is a diagram for explaining the operation of the output circuit of FIG. 9 when the input voltage V _IN is high; FIG. 10 is a diagram for explaining the operation when the input voltage _VIN of FIG. 9 is low; FIG. 10 is a circuit diagram of an output circuit according to Embodiment 3; FIG. It is a block diagram of a relay device. 1 is a perspective view of a motor vehicle equipped with a relay device; FIG. 10 is a circuit diagram of an output circuit according to Embodiment 4; FIG. FIG. 13 is a circuit diagram of a semiconductor device including an output circuit according to Example 4.1; 17 is an operation waveform diagram of the output circuit of FIG. 16; FIG. FIG. 13 is a circuit diagram of a semiconductor device including an output circuit according to Example 4.2; 19 is a circuit diagram of a specific configuration example of the output circuit of FIG. 18; FIG. FIG. 14 is a circuit diagram of a semiconductor device including an output circuit according to Example 4.3; 21 is an operation waveform diagram of the output circuit of FIG. 20; FIG. FIG. 20 is a circuit diagram of a semiconductor device including an output circuit according to Example 4.4; FIG. 20 is a circuit diagram of a semiconductor device including an output circuit according to Example 4.5;

(Overview of Embodiment)
1. An embodiment disclosed in this specification relates to a drive circuit that drives an output transistor provided between an input terminal that receives an input voltage and an output terminal according to a control signal. The driving circuit includes an internal line, a first transistor biased at a control electrode, which is a gate or base, and a first electrode, which is a source or emitter, connected to the internal line, and acts on the internal line to generate a voltage on the internal line. and a voltage correction circuit that gradually lowers the voltage over time. The voltage of the internal line is applied to the control electrode, which is the gate or base of the output transistor, during its ON period.

By lowering the voltage of the internal line with the voltage correction circuit, the low level of the gate voltage of the output transistor can be lowered, and the on-resistance can be reduced.

The voltage correction circuit may include a current source that sinks auxiliary current from internal lines. By extracting the charge of the internal line with the auxiliary current, the voltage of the internal line can be gently lowered with a slope corresponding to the amount of current.

In one embodiment, the drive circuit has an upper power supply terminal connected to the input terminal, a lower power supply terminal connected to the internal line, and an output terminal connected to the control electrode which is the gate or base of the output transistor. , a driver for driving the output transistor according to the control signal.

In one embodiment, the auxiliary current may be less than the current that the driver sinks from the control electrode of the output transistor during the ON period of the output transistor. The auxiliary current thus does not adversely affect turn-off during normal switching operation.

In one embodiment, the drive circuit may further include a second transistor that is provided between the second electrode, which is the drain or collector of the first transistor, and the ground, and that is turned on and off according to the control signal.

In one embodiment, the auxiliary current may be less than the current sunk from the control electrode of the output transistor via the second transistor during the ON period of the output transistor. The auxiliary current thus does not adversely affect turn-off during normal switching operation.

In one embodiment, the drive circuit may further include a third transistor which is provided between the input terminal and the control electrode of the output transistor and which is turned on during the period when the output transistor should be turned off. The auxiliary current may be smaller than the current flowing through the third transistor during the OFF period of the output transistor. The auxiliary current thus does not adversely affect the turn-off of normal switching operation.

In one embodiment, the auxiliary current may be greater than the current flowing into the internal line during the off period of the output transistor in a low voltage condition.

Another aspect of the present disclosure is also a drive circuit. This drive circuit includes an internal line connected to the control electrode, which is the gate or base of the output transistor, and a second line, to which the control electrode, which is the gate or base, is biased and the first electrode, which is the source or emitter, is connected to the internal line. 1 transistor, a second transistor provided between a second electrode, which is the drain or collector of the first transistor, and ground, and turned on and off according to a control signal, a current source for sinking an auxiliary current from an internal line; and an impedance element provided between the input terminal and the internal line.

In one embodiment, the auxiliary current may be greater than the current flowing through the impedance element and less than the current flowing through the first transistor.

In one embodiment, the drive circuit may further include a third transistor that is provided between the input terminal and the internal line and turns on and off complementarily to the second transistor according to the control signal.

Yet another aspect of the present disclosure is also a drive circuit. The drive circuit includes an internal line, a first transistor biased at a control electrode that is a gate or base and a first electrode that is a source or emitter connected to the internal line, an upper power supply terminal connected to an input terminal, A driver that has a lower power supply terminal connected to the internal line, an output terminal connected to the control electrode that is the gate or base of the output transistor, drives the output transistor according to the control signal, and draws an auxiliary current from the internal line. A sinking current source and an impedance element provided between the input terminal and the internal line.

In one embodiment, the auxiliary current may be greater than the current flowing through the impedance element and less than the current flowing from the lower power supply terminal of the driver to the internal line.

In one embodiment, the drive circuit may further include a clamp circuit that clamps the voltage of the internal line so that the potential difference from the input voltage does not exceed a predetermined value. The clamp circuit may include a Zener diode provided between the input terminal and the internal line.

In one embodiment, the control signal may be a pulse signal in the normal state of the input voltage, and may be a DC signal that instructs to turn on fixedly in the low voltage state in which the input voltage drops.

In one embodiment, the control signal is a pulse signal, and the on-level time of the control signal may increase as the input voltage decreases.

The auxiliary current may be turned on and off according to the control signal. The auxiliary current may be fixedly on regardless of the level of the control signal.

In one embodiment, the drive circuit may further include a bias circuit that supplies a bias voltage lower than the input voltage by a predetermined voltage width to the control electrode of the first transistor. The bias circuit may include a first Zener diode provided between the input terminal and the control electrode of the first transistor, and a current source provided between the control electrode of the first transistor and ground.

The drive circuit may be monolithically integrated on one semiconductor substrate. "Integrated integration" includes the case where all circuit components are formed on a semiconductor substrate, and the case where the main components of a circuit are integrated. A resistor, capacitor, or the like may be provided outside the semiconductor substrate. By integrating the circuits as one IC, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

2. An embodiment disclosed in this specification relates to a drive circuit that drives an output transistor provided between an input terminal and an output terminal. The drive circuit includes a turn-off circuit that supplies a current to the control electrode of the output transistor, a first transistor whose control electrode is connected to the control electrode of the output transistor and biased at the control electrode, and a second electrode of the first transistor. and a second transistor that is provided between the output transistor and the ground and that is turned on during the on period of the output transistor.

The first transistor functions as a source follower or emitter follower type voltage clamp circuit, and the voltage of the control electrode of the output transistor is stabilized at a predetermined voltage when the second transistor is on. When turning on the first transistor, the discharge current drawn from the gate capacitance (base capacitance) of the first transistor flows through the first and second transistors to ground. Therefore, voltage fluctuation of the control electrode of the output transistor can be suppressed.

In one embodiment, the turn-off circuit may include a third transistor provided between the input terminal and the control electrode of the output transistor, and a sub-driver that turns on the third transistor during the off period of the output transistor.
When the output transistor is turned on, the turn-off speed can be increased by charging the capacitance of the control electrode of the output transistor via the third transistor.

In one embodiment, the sub-driver includes a second resistor provided between the input terminal and the control electrode of the third transistor, a first electrode of which is connected to the control electrode of the third transistor, and the control electrode of which is biased. and a fifth transistor provided between the second electrode of the fourth transistor and the ground and turned on during the off period of the output transistor.
According to this aspect, the low level of the driving voltage of the third transistor can be stabilized at the predetermined voltage.

In one embodiment, the control electrodes of the first transistor and the fourth transistor may be biased by a common voltage source. When the second transistor is turned off, the potential of the control electrode of the first transistor, and thus the control electrode of the fourth transistor, fluctuates under the influence of the gate capacitance of the first transistor. At this time, when the fifth transistor is turned on, the fluctuation of the control electrode of the fourth transistor appears as the voltage fluctuation of the control electrode of the third transistor. Fluctuations in the voltage of the control electrode of the third transistor adversely affect the turn-off behavior of the output transistor. Conversely, when the fifth transistor is turned off, the gate capacitance of the fourth transistor causes the potential of the control electrode of the fourth transistor, and thus the potential of the control electrode of the first transistor, to fluctuate. When the second transistor is turned on at this time, the fluctuation of the control electrode of the first transistor appears as the voltage fluctuation of the control electrode of the output transistor. In order to suppress this voltage fluctuation, a smoothing capacitor may be connected to the common voltage source.

In one embodiment, the control electrode of the first transistor and the control electrode of the fourth transistor may be biased by separate voltage sources. In this case, fluctuations in the control electrodes of the first transistor and the fourth transistor do not affect each other, so fluctuations in the control electrode of the output transistor can be suppressed without a smoothing capacitor.

In one embodiment, the drive circuit may further include a first resistor provided between the input terminal and the control electrode of the output transistor.

In one embodiment, the drive circuit includes a first voltage source that provides a first bias voltage to the control electrode of the first transistor and a first voltage source that provides a second bias voltage to the control electrode of the fourth transistor. and a second voltage source independent of the source. The first voltage source and the second voltage source may have the same circuit configuration.

The first voltage source includes a constant voltage element provided between the input terminal and the control electrode of the first transistor, and the second voltage source includes a constant voltage element provided between the input terminal and the control electrode of the fourth transistor. element.

In one embodiment, a plurality of third transistors and sub-drivers may be provided. The fifth transistors of the plurality of sub-drivers may be complementarily switched for each stage. The final-stage third transistor is provided between the input terminal and the control electrode of the output transistor, and the preceding-stage third transistor is provided between the input terminal and the control electrode of the subsequent-stage third transistor. good too. The control electrodes of the first transistor and the fourth transistor adjacent to the first transistor are biased by a common first voltage source, and the control electrodes of the remaining fourth transistors are biased by a common separate second voltage source. May be biased.

The drive circuit may be monolithically integrated on one semiconductor substrate. "Integrated integration" includes the case where all circuit components are formed on a semiconductor substrate, and the case where the main components of a circuit are integrated. A resistor, capacitor, or the like may be provided outside the semiconductor substrate. By integrating the circuits as one IC, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

(Embodiment)
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplication of description will be omitted as appropriate. Moreover, the embodiments are illustrative rather than limiting the invention, and not all features and combinations thereof described in the embodiments are necessarily essential to the invention.

In this specification, "a state in which member A is connected to member B" refers to a case in which member A and member B are physically directly connected, as well as a case in which member A and member B are electrically connected to each other. It also includes the case of being indirectly connected through other members that do not substantially affect the physical connection state or impair the functions and effects achieved by their combination.

Similarly, "the state in which member C is provided between member A and member B" refers to the case where member A and member C or member B and member C are directly connected, as well as the case where they are electrically connected. It also includes the case of being indirectly connected through other members that do not substantially affect the physical connection state or impair the functions and effects achieved by their combination.

(Embodiment 1)
FIG. 5 is a circuit diagram of the output circuit 100 according to the first embodiment. The output circuit 100 includes an output transistor _MH and a drive circuit 200 . In this embodiment, the output circuit 100 is part of a functional IC (semiconductor device 300) integrated on one semiconductor substrate.

The output transistor _MH may be the upper arm of a half-bridge circuit (single-phase inverter). Alternatively, the output transistor _MH may be the upper arm of one leg of a full bridge circuit or a three-phase inverter. Inductive elements such as inductors, transformers, motor coils, and relay coils may be connected to the output terminal OUT. Alternatively, the output transistor _MH may be the switching transistor of a Buck Converter.

The output transistor _MH is provided between the input terminal IN and the output terminal OUT. The output transistor _MH is a P-channel MOSFET, and has a source connected to the input terminal IN and a drain connected to the output terminal OUT. The output transistor _MH may be a GaNFET, an IGBT (Insulated Gate Bipolar Transistor), or a PNP bipolar transistor.

The drive circuit 200 drives the output transistor _MH according to the control signal _SCTRL . Specifically, the output transistor MH is turned on when the control signal _SCTRL is on level (eg high), and the output transistor _MH is turned off when the control signal _SCTRL is off _level (eg low). The control signal S _CTRL is typically a pulse signal, but is not limited to this and may be a DC signal. An output voltage _VOUT corresponding to the control signal _SCTRL is generated at the output terminal OUT. The output voltage _VOUT is the input voltage VIN when the output transistor _MH is on, and is the input voltage _VIN when the output transistor _MH is off. , the ground voltage _VGND or high impedance state.

The driving circuit 200 mainly includes an internal line 201 , a first transistor M ₁ and a voltage correction circuit 270 . First, portions other than the voltage correction circuit 270 will be described.

The first transistor M ₁ is a P-channel MOSFET with a gate (control electrode) biased by a predetermined bias voltage (reference voltage) V _BIAS and a source (first electrode) connected to the internal line 201 . Impedance element R ₁ is provided between input terminal IN and internal line 201 . Impedance element _R1 may be a resistor, a current source, or an appropriately biased transistor.

A bias circuit 240 generates a bias voltage V _BIAS that is a predetermined voltage lower than the input voltage _VIN . For example, bias circuit 240 includes a constant voltage element 242 , a Zener diode, and a current source 244 . A bias voltage V _BIAS represented by V _BIAS =V _IN -V _Z is generated at the connection node between the constant voltage element 242 and the current source 244 .

The _first transistor M1 functions as a source follower circuit, and the internal power supply voltage V _REGB on the internal line 201 is regulated to V _REGB =V _BIAS +V _TH =V _IN -V _Z +V _TH .

The drive circuit 200 is configured to apply the internal power supply voltage V _REGB on the internal line 201 to the gate of the output transistor M _H during the ON period (S _CTRL =H).

In Embodiment 1, a driver 204 is provided. The driver 204 has an upper power supply terminal connected to the input terminal IN, a lower power supply terminal connected to the internal line 201, and an output connected to the gate (control electrode) of the output transistor _MH .

The description so far has ignored the voltage correction circuit 270 . Next, the voltage correction circuit 270 will be explained.

The voltage correction circuit 270 acts on the internal line 201 to gradually reduce the voltage of the internal line 201 over time. Voltage correction circuit 270 is active at least during the on period of output transistor M _H (S _CTRL is high). In the OFF period, the voltage correction circuit 270 may be disabled (high impedance state) or maintained in an active state.

Voltage correction circuit 270 includes current source 272 that draws auxiliary current I _AUX from internal line 201 . The configuration of current source 272 is not particularly limited, but may include an appropriately biased transistor. The voltage correction circuit 270 can also be configured with a resistor instead of the current source.

It is desirable to define the amount of auxiliary current so as to satisfy the following conditions.

(Condition 1)
The current amount of the auxiliary current I _AUX is set to be small enough not to affect the normal switching operation when the input voltage V _IN is in a non-low voltage state. Therefore, the auxiliary current I _AUX is much smaller than the current I _B that the driver 204 sinks from the gate of the output transistor M _H during the ON period of the output transistor M _H (S _CTRL =H).
I _AUX << I _B
For example, I _AUX is preferably about 1/1000 to 1/200 of I _B.

(Condition 2)
Further, the amount of the auxiliary current I _AUX is set large enough to allow the internal power supply voltage V _REGB of the internal line 201 to be gradually lowered over time when the input voltage V _IN is in a low voltage state. For example, when the switching period during normal operation is T _P , the amount of auxiliary current I _AUX may be defined such that the internal power supply voltage V _REGB drops by V _TH in T _P or longer.

Specifically, it is desirable that the auxiliary current I _AUX be greater than the current I _R flowing into the internal line 201 during the OFF period of the output transistor _MH . This current I _R is the current that mainly flows through the impedance element _R1 .
I _AUX >I _R
For example, I _AUX is _preferably at least 1.1 times IR.

Output circuit 100 may further comprise clamp circuit 280 . Clamp circuit 280 is configured to clamp internal power supply voltage V _REGB on internal line 201 such that the potential difference from input voltage V _IN does not exceed a predetermined value. Although the configuration of the clamp circuit 280 is not particularly limited, it can be composed of a constant voltage element such as _a Zener diode ZD1 provided between the input terminal IN and the internal line 201, for example.

The above is the configuration of the output circuit 100 . Next, the operation will be explained.
1. High Input Voltage State FIG. 6 is a diagram for explaining the operation of the output circuit 100 of FIG. 5 when the input voltage _VIN is high (non-low voltage state). Here, it is assumed that the auxiliary current I _AUX switches according to the control signal S _CTRL . When the input voltage V _IN is high, the internal power supply voltage V _REGB on internal line 201 is regulated by the _first transistor M1 to the following voltage levels: ΔV is greater than the gate-to-source threshold V _GS(th) of the output transistor _MH .
V _REGB =V _IN -ΔV=V _IN -(V _Z -V _TH )

When the control signal S _CTRL transitions high, the current I _B discharges the gate of the output transistor _MH , causing the gate voltage V _G to drop to the internal power supply voltage V _REGB and turn it full on.

While the control signal S _CTRL is high (ON time T _ON ), the internal line 201 is discharged by the auxiliary current I _AUX , and the voltage V _REGB of the internal line 201 is slowly discharged with time. However, since I _AUX <<IB, I _AUX does not affect the turn _- on operation of the output transistor _MH .

Further, when the input voltage V _IN is high, the control signal S _CTRL is a pulse signal, and the drop width of the internal power supply voltage _{V REGB} during the _ON time T _ON is not so large. does not exceed its withstand voltage.

2. Low input voltage state (low voltage state)
FIG. 7 is a diagram for explaining the operation of the output circuit 100 of FIG. 5 when the input voltage _VIN is low (low voltage region). In this example, it is assumed that the control signal _SCTRL is fixed at the on level (high) in the low voltage region.

As shown in FIG. 2, when the input voltage V _IN enters the low voltage region, the difference ΔV between V _IN and V _REGB becomes smaller.

When the control signal S _CTRL transitions high, the current I _B discharges the gate of the output transistor M _H and the gate voltage V _G drops to the internal power supply voltage V _REGB . However, since ΔV, that is, the gate-source voltage is small, the output transistor _MH cannot be fully turned on immediately after turn-on, and the output voltage _VOUT becomes lower than the input voltage _VIN .

While the control signal S _CTRL is high (ON time T _ON ), the auxiliary current I _AUX discharges the internal line 201, and the internal power supply voltage V _REGB gradually decreases over time. In the low voltage state, the ON time T _ON is long, so the internal power supply voltage V _REGB drops to near 0V (or the level clamped by the clamp circuit 280), and the potential difference ΔV increases. As a result, the gate voltage _VG of the output transistor _MH decreases, the ON resistance of the output transistor _MH decreases, and the output voltage _VOUT approaches the input voltage _VIN .

FIG. 8 is a diagram for explaining the operation of the output circuit 100 of FIG. 5 when the input voltage _VIN is low (low voltage region). In this example, the control signal S _CTRL is a pulse signal having a large duty ratio in the low voltage region. By increasing the duty ratio of the control signal S _CTRL , the discharge time by the auxiliary current I _AUX becomes longer, so that the internal power supply voltage V _REGB can be maintained near 0V. The operation of FIG. 7 can also be understood as fixing the duty ratio of the control signal _SCTRL in FIG. 6 to 100%.

When the duty ratio of the control signal S _CTRL is d, the effective voltage level of V _OUT is given by the following equation.
V _OUT =V _IN ×d
In platforms where the effective voltage level of _VOUT is controlled to be constant, a decrease in the input voltage _VIN will increase the duty ratio d.

The above is the operation of the output circuit 100 . According to this output circuit 100, the on-resistance of the output transistor _MH can be reduced when the input voltage _VIN is low, and power loss can be reduced.

Furthermore, the reduced voltage detection circuit 10 for determining the low voltage state and the non-low voltage state shown in FIG. 3 is not required. Therefore, the problem of applying an overvoltage between the gate and source of the output transistor _MH due to erroneous detection of a low voltage state does not occur.

Note that the low voltage state and non-low voltage state may occur dynamically in one platform. That is, variations in the input voltage V _IN may result in switching between low and non-low voltage states.

Alternatively, semiconductor device 300 may be used in platforms with different input voltages _VIN . In this case, one platform may always operate in a low voltage state and another platform may always operate in a non-low voltage state. The present invention also includes such aspects.

(Embodiment 2)
FIG. 9 is a circuit diagram of an output circuit 100B according to the second embodiment. The drive circuit 200B includes a _second transistor M2 instead of the driver 204 of FIG. In this embodiment, the source (first electrode) of the _first transistor M1, ie internal line 201, is connected to the gate of the output transistor _MH .

The second transistor M2 is provided between the drain ( _second electrode) of the _first transistor M1 and the ground, and is turned on and off according to the control signal _SCTRL . More specifically, the _second transistor M2 is an N-channel MOSFET and is provided between the drain of the _first transistor M1 and ground. The _second transistor M2 is controlled to be on when the control signal S _CTRL is on level (high).

Current source 272 sinks auxiliary current I _AUX from internal line 201 . Impedance element R ₁ is provided between input terminal IN and internal line 201 .

It is desirable that the current amount of the auxiliary current I _AUX is specified so as to satisfy the following conditions.
(Condition 1)
The auxiliary current _IAUX is more than the discharge current IB that is sunk from the gate of the output transistor _MH via the _first transistor M1 and the _second transistor M2 during the ON period of the output transistor _MH (S _CTRL = _H ). is also small enough.
I _AUX << I _B
For example, I _AUX is preferably about 1/1000 to 1/200 of I _B.

(Condition 2)
The auxiliary current _{I_AUX} is defined to be less than the charging current _{I_R(HIGH)} flowing into the internal line 201 during the off period of the output transistor _MH in a non-low voltage state. This current I _{R (HIGH)} is a current that mainly flows through the impedance element _R1 . The auxiliary current I _AUX thus has no effect on the turn-off operation.
I _AUX <IR _(HIGH)

Also, the auxiliary current I _AUX is determined to be larger than the current I _{R (LOW)} flowing into the internal line 201 during the ON period of the output transistor _MH in the low voltage state. This current I _{R (LOW)} is the current that mainly flows through the impedance element _R1 .
I _AUX >I _{R (LOW)}

The above is the configuration of the output circuit 100B. Next, the operation will be explained.

FIG. 10 is a diagram for explaining the operation of the output circuit 100B of FIG. 9 when the input voltage _VIN is high. When the control signal S _CTRL goes high, the _second transistor M2 is turned on. As a result, the discharge current _IB flows through the _first transistor M1 and the _second transistor M2, the charge is discharged from the internal line 201 (the gate capacitance of the output transistor _MH ), and the gate voltage _VG is lowered. The first transistor M ₁ functions as a source-follower type clamp circuit, and the low level of the gate voltage V _G is clamped to V _REGB =V _IN -(V _Z -V _TH ).

Then, while the control signal S _CTRL is high (ON time T _ON ), the internal line 201 is discharged by the auxiliary current I _AUX , and the voltage V _G of the internal line 201 is gradually discharged with time. However, since I _AUX <<IB, I _AUX does not affect the turn _- on operation of the output transistor _MH .

Further, when the input voltage V _IN is high, the control signal S _CTRL is a pulse signal, and the drop width of the internal power supply voltage _{V REGB} during the _ON time T _ON is not so large. does not exceed its withstand voltage.

When the control signal S _CTRL goes low, the _second transistor M2 is turned off. The gate capacitance of the output transistor _MH is charged by the charging current _IR flowing through the resistor _R1 , the gate voltage _VG rises, and the output transistor _MH is turned off.

FIG. 11 is a diagram for explaining the operation when the input voltage _VIN of FIG. 9 is low. Here, it is assumed that the duty ratio of the control signal _SCTRL in the low voltage state is 100%. When the control signal S _CTRL transitions high, the current I _B discharges the gate of the output transistor M _H and the gate voltage V _G drops to the internal power supply voltage V _REGB . However, since ΔV, that is, the gate-source voltage is small, the output transistor _MH cannot be fully turned on immediately after turn-on, and the output voltage _VOUT becomes lower than the input voltage _VIN .

During the period when the control signal S _CTRL is high (ON time T _ON ), the charge in the internal line 201 is discharged by the auxiliary current I _AUX , and the gate voltage V _G gradually decreases with time. In the low voltage state, the _ON time TON is long, so the gate voltage _VG drops to near 0V (or the level clamped by the clamp circuit 280), and the potential difference ΔV increases. As a result, the gate voltage _VG of the output transistor _MH decreases, the ON resistance of the output transistor _MH decreases, and the output voltage _VOUT approaches the input voltage _VIN .

According to the second embodiment, similarly to the first embodiment, the on-resistance of the output transistor _MH in the low voltage state can be reduced, and the power consumption can be reduced.

(Embodiment 3)
FIG. 12 is a circuit diagram of an output circuit 100C according to the third embodiment. The drive circuit 200C includes a _third transistor M3 and a sub-driver 220 in addition to the output circuit 100B of FIG.

A _third transistor M3 is provided between the input terminal IN and the internal line 201, and is turned on/off complementarily to the _second transistor M2 according to the control signal _SCTRL . More specifically, the _third transistor M3 is a P-channel MOSFET and is provided between the input terminal IN and the gate line 202 .

The sub-driver 220 turns on the _third transistor M3 during the off period of the output transistor _MH ( _SCTRL is low). For example, sub-driver 220 level shifts a control signal S _CTRL that switches between V _DD -V _GND to a gate signal V _G3 that switches between appropriate high and low voltages (eg, between V _IN -V _REGB ). . This low voltage _VREGB may be the same as the low voltage of the gate voltage _VG of the output transistor _MH .

The above is the configuration of the output circuit 100C. In this output circuit 100C, when the control signal _SCTRL becomes low, the _third transistor M3 is turned on, and the gate capacitance of the output transistor _MH is charged by the current _IA flowing through the _third transistor M3. As a result, compared to the output circuit 100B of FIG. 9, the turn-off time of the output transistor _MH can be shortened, enabling high-speed switching.

In addition, in Embodiment 3, it is preferable that the following relationship holds.
(Condition 1)
The auxiliary current _IAUX is more than the discharge current IB that is sunk from the gate of the output transistor _MH via the _first transistor M1 and the _second transistor M2 during the ON period of the output transistor _MH (S _CTRL = _H ). is also small enough.
I _AUX << I _B
For example, I _AUX is preferably about 1/1000 to 1/200 of I _B.

(Condition 2)
Auxiliary current I _AUX is defined to be less than charging current I _A flowing into internal line 201 during the off period of output transistor _MH in a non-low voltage condition. This current _IA is the current that mainly flows through the _third transistor M3. The auxiliary current I _AUX thus has no effect on the turn-off operation.
I _AUX < I _A

Also, the auxiliary current I _AUX is determined to be larger than the current I _{R (LOW)} flowing into the internal line 201 during the ON period of the output transistor _MH in the low voltage state. This current I _{R (LOW)} is the current that mainly flows through the impedance element _R1 .
I _AUX >I _{R (LOW)}

(Application)
Next, the application of the output circuit 100 will be described. The semiconductor device (output circuit) described above can be used in a drive circuit for a mechanical relay. FIG. 13 is a block diagram of the relay device 400. As shown in FIG. The relay device 400 is used, for example, in automobiles, home appliances, industrial equipment, transportation equipment, and agricultural equipment, and is mainly used to control the interruption and conduction of large current power lines.

The relay device 400 includes a mechanical relay 410 and its drive circuit 500 . The relay device 400 may be modularized.

Mechanical relay 410 includes coil 412 and switch 414 . The drive circuit 500 corresponds to the semiconductor device 300 described above, and includes a high side transistor M _H , a low side transistor M _L , a high side driver 502 , a low side driver 504 and a controller 506 . High side transistor _MH and low side transistor _ML form a half bridge circuit. The controller 506 generates control signals S _CTRLH and S _CTRL for the high-side transistor M _H and low-side transistor M _L based on an external control signal EN. High side transistor _MH and high side driver 502 correspond to output circuit 100 described above. The high side driver 502 corresponds to the drive circuit 200 described above, and drives the high side transistor _MH based on the control signal _SCTRLH . The low side driver 504 drives the low side transistor _{M_L} based on the control signal _{S_CTRL} .

FIG. 14 is a perspective view of automobile 600 having relay device 400 . Vehicle 600 comprises a plurality of relays 602,604,606. Some relays 602 are used for wipers and washers. Other relays 604 are used for power windows, door locks, power seats and power sliding doors. Still other relays 606 are used for headlights, starters, and the like.

The present invention has been described above based on the embodiments. It should be understood by those skilled in the art that this embodiment is merely an example, and that various modifications can be made to the combination of each component and each treatment process, and that such modifications are within the scope of the present invention. be. Such modifications will be described below.

(Modification 1.1)
In the first to third embodiments, the semiconductor device composed of MOSFETs has been described, but the present invention is not limited to this, and arbitrary MOSFETs can be replaced with bipolar transistors or the like. In this case, in the above description, the gate should be read as the base, the drain as the collector, and the source as the emitter.

(Modification 1.2)
In the first to third embodiments, the case where the output transistor _MH is integrated in the semiconductor device 300 has been described, but the present invention is not limited to this, and a discrete element may be used as the output transistor _MH .

(Modification 1.3)
Applications of the semiconductor device 300 are not limited to a relay drive circuit, but can also be used as a switching power supply such as a DC/DC converter, a motor drive circuit (inverter), an AC/DC converter, a DC/AC converter (inverter), and a secondary battery. It can also be used for charging/discharging systems, power conditioners, and the like.

(Modification 1.4)
In the first to third embodiments, one aspect of the present invention has been described as a technique for suppressing an increase in on-resistance in a low voltage state (reduced voltage state). The present invention is also useful in applications where _IN is used in a high state (non-low voltage state). That is, in the source follower type voltage source 6 as shown in FIG.
V _REGB =V _BIAS +V _TH
holds. Therefore, regardless of whether the input voltage _VIN is high or low, a voltage higher than the bias voltage _VBIAS by the gate _- source voltage _VTH of the transistor M1 is the gate voltage _VG of the output transistor _MH during the ON period. In other words, it can be understood that the gate-to _- source voltage _VGS of the output transistor M1 is reduced by _VTH . The present invention is useful when it is desired to reduce the effect of _VTH regardless of whether the input voltage _VIN is high or low (for example, in situations where a constant voltage _VZ sufficiently larger than the threshold _VGS(th) of the output transistor cannot be generated). ), can be widely used.

(Embodiment 4)
FIG. 15 is a circuit diagram of the output circuit 100 according to the fourth embodiment. The output circuit 100 includes an output transistor _MH and a drive circuit 200 . In this embodiment, the output circuit 100 is part of a functional IC (semiconductor device 300) integrated on one semiconductor substrate.

The output transistor _MH may be the upper arm of a half-bridge circuit (single-phase inverter). Alternatively, the output transistor _MH may be the upper arm of one leg of a full bridge circuit or a three-phase inverter. Inductive elements such as inductors, transformers, motor coils, and relay coils may be connected to the output terminal OUT. Alternatively, the output transistor _MH may be the switching transistor of a Buck Converter.

The output transistor _MH is provided between the input terminal IN and the output terminal OUT. The output transistor _MH is a P-channel MOSFET, and has a source connected to the input terminal IN and a drain connected to the output terminal OUT. The output transistor _MH may be a GaNFET, an IGBT (Insulated Gate Bipolar Transistor), or a PNP bipolar transistor.

The drive circuit 200 drives the output transistor _MH according to the control signal _SCTRL . Specifically, the output transistor MH is turned on when the control signal _SCTRL is on level (eg high), and the output transistor _MH is turned off when the control signal _SCTRL is off _level (eg low). The control signal S _CTRL is typically a pulse signal, but is not limited to this and may be a DC signal. An output voltage _VOUT corresponding to the control signal _SCTRL is generated at the output terminal OUT. The output voltage _VOUT is the input voltage VIN when the output transistor _MH is on, and is the input voltage _VIN when the output transistor _MH is off. , the ground voltage _VGND or high impedance state.

Drive circuit 200 comprises a turn-off circuit 210 and a turn-on circuit 230 . The turn-off circuit 210 supplies a charging current to the control electrode (gate) of the output transistor _MH to raise the gate voltage _VG of the output transistor _MH to near the input voltage _VIN during the OFF period of the output transistor _MH . , turn off the output transistor _MH .

The turn-on circuit 230 includes a _first transistor M1 and a _second transistor M2. The _first transistor M1 is a P-channel MOSFET, the first electrode (source) of which is connected to the control electrode (gate) of the output transistor _MH , the control electrode (gate) of which is supplied with a bias voltage V _BIAS1 . . The bias voltage V _BIAS1 may be a constant voltage. In this case, the _first transistor M1 operates as a source follower type clamp circuit, and the potential VG of the gate line 202 is _clamped with _VL = _VBIAS1 + _VTH as the lower limit. _VL is called the clamp level. Here, V _L <V _IN -V _GS(th) holds.

The second transistor M2 is an N-channel MOSFET and is provided between the _second electrode (drain) of the _first transistor M1 and ground. The _second transistor M2 is controlled to be on when the control signal S _CTRL is on level (high).

The above is the configuration of the output circuit 100 . Next, the operation will be explained.

When the control signal S _CTRL is off level, the _second transistor M2 of the turn-on circuit 230 is off, so the discharge current _I2 flowing from the gate line 202 to ground is zero. The charging current I1 from the turn _- off circuit 210 is supplied to the gate of the output transistor _MH , the gate voltage _VG rises to near the input voltage _VIN , and the output transistor _MH is turned off.

When the control signal S _CTRL is on level, the _second transistor M2 of the turn-on circuit 230 is turned on. At this time, a discharge current _I2 flows from the gate line 202 through the _first transistor M1 and the _second transistor M2. When the gate capacitance is discharged by the discharge current _I2 , the gate voltage _VG decreases, and when the gate-source voltage _VGS exceeds the threshold value _VGS(th) , the output transistor _MH is turned on. The gate voltage _VG is clamped by the _first transistor M1 when it drops to the clamp level _VL .

The above is the operation of the output circuit 100 . According to this output circuit 100, the discharge current _I2 when turning on the output transistor _MH flows to the ground and does not flow to the node where the bias voltage _{V BIAS1} is generated. It does not fluctuate the voltage V _BIAS1 and thus the clamp level V _L . Therefore, a capacitor for stabilizing the bias voltage V _BIAS1 (clamp level V _L ) becomes unnecessary, or its capacitance value can be reduced.

(Example 4.1)
FIG. 16 is a circuit diagram of a semiconductor device 300A including an output circuit 100A according to Example 4.1. The turn-off circuit 210A includes a _first resistor R1 provided between the input terminal IN and the gate of the output transistor _MH (gate line 202).

Drive circuit 200A further includes a first voltage source 250 . A first voltage source 250 provides a bias voltage V _BIAS1 to the gate of the _first transistor M1. The bias voltage V _BIAS1 is lower than the input voltage _VIN by a predetermined voltage width ΔV, and ΔV>V _GS(th) +V _TH is established. First voltage source 250 includes, for example, first constant voltage element 252 and first current source 254 . The first constant voltage element 252 includes a Zener diode or a diode, and has a constant voltage ΔV across both ends thereof.

The above is the configuration of the output circuit 100A. Next, the operation will be explained. FIG. 17 is an operation waveform diagram of the output circuit 100A of FIG.

When the control signal S _CTRL is high, the second transistor M2 is on, and the voltage V _A of the connection node N1 between the _second transistor _M2 and the _first transistor M1 becomes the ground voltage _{V GND} . When the _second transistor M2 is on, a discharge current _I2 is drawn from the gate of the output transistor _MH through the _first transistor M1 and the _second transistor M2. As a result, the gate voltage V _G of the output transistor M _H becomes V _L =V _IN -ΔV+V _TH and the output transistor M _H is turned on. In FIG. 17, it is shown as ΔV=5V.

When the control signal S _CTRL is low, the _second transistor M2 is off and the discharge current _I2 is zero. The gate voltage _VG of the output transistor _MH is pulled up by the _first resistor R1, the gate capacitance of the output transistor _MH is charged by the charging current I1 flowing through the _first resistor _R1 , and the input voltage V _IN to turn off the output transistor _MH . _At this time, the potential _VA of the node N1 approaches the input voltage _VIN . Variations in the drain voltage V _A of the _first transistor M1 cause variations in the gate voltage of the _first transistor M1, ie, the bias voltage V _BIAS1 . However, since the bias voltage V _BIAS1 is used only during the ON period of the output transistor _MH , it should be noted that variations in the bias voltage V _BIAS1 do not affect circuit operation.

Embodiment 4.1 has the advantage that the output circuit 100 of FIG. 15 can be implemented with a simple configuration. On the other hand, the output circuit 100A of FIG. 16 has the following problems. The slew rate (slope) of the gate voltage _VG when turning off the _first transistor M1 is defined by the resistance value of the _first resistor R1.

Applications that require fast switching require a small resistance value for the _first resistor R1. However, the charging current I1 continues to flow through the _first resistor _R1 even during the ON period of the output transistor _MH . This charging current I1 is dumped to ground via the _first transistor M1 and the _second transistor _M2 , wasting power.

That is, in Example 4.1, there is a trade-off relationship between the turn-on slew rate of the _first transistor M1 and power consumption, and it may be difficult to adopt it for applications that require both high speed and low power consumption. . In the following embodiments, an output circuit capable of achieving both high speed and low power consumption will be described.

(Example 4.2)
FIG. 18 is a circuit diagram of a semiconductor device 300B including an output circuit 100B according to Example 4.2. The turn-off circuit 210B includes a _third transistor M3 and a sub-driver 220 in addition to the _first resistor R1. The _third transistor M3 is a P-channel MOSFET and is provided between the input terminal IN and the gate line 202 .

The sub-driver 220 turns on the _third transistor M3 during the off period of the output transistor _MH ( _SCTRL is low). For example, sub-driver 220 level shifts a control signal S _CTRL that switches between V _DD -V _GND to a gate signal V _G3 that switches between appropriate high and low voltages (eg, between V _IN -V _REGB ). . This low voltage _VREGB may be the same as the low voltage of the gate voltage _VG of the output transistor _MH .

As a result, since the charging current I1 for the gate capacitance of the output transistor _MH can be generated by the _third transistor M3 _, the output transistor _MH can be turned off at high speed. Since the first resistor _R1 can be made sufficiently high, the current flowing through the _first resistor R1 can be reduced during the ON period of the output transistor _MH , and wasteful power consumption can be reduced. Thus, according to the output circuit 100B of FIG. 18, it is possible to achieve both high speed and low power consumption.

FIG. 19 is a circuit diagram of a specific configuration example of the output circuit 100B of FIG. Sub-driver 220 is configured in the same manner as drive circuit 200 of FIG.

More specifically, the sub-driver 220 can be configured similarly to the drive circuit 200A of FIG. That is, the sub-driver 220 includes a _second resistor R2 corresponding to a turn-off circuit 222 and a _fourth transistor M4 and a _fifth transistor M5 forming a turn-on circuit 224. FIG. A bias voltage V _BIAS1 is supplied to the gate of the _fourth transistor M4. The bias voltage V _BIAS1 is generated by the first constant voltage element 252 and the first current source 254 as in FIG.

An inverted signal #S _CTRL of the control signal S _CTRL is input to the gate of the _fifth transistor M5, and the fifth transistor M5 is turned on during the off period of the output transistor _MH (S _CTRL is low). The operation of the _{sub -} driver ₂₂₀ of FIG. 19 is similar to the operation of the _{drive circuit 200A} of FIG. Switching between two values.

As described with reference to FIG. 17, when the control signal S _CTRL goes low, the _second transistor M2 is turned off. The turn-off of the _second transistor M2 causes variations in its drain voltage V _A and, under the influence of the gate capacitance of the _first transistor M1, variations in the bias voltage V _BIAS1 . This bias voltage V _BIAS1 is also supplied to the gate of the _fourth transistor M4. At this time, when the _fifth transistor M5 is turned on, the fluctuation of the gate voltage _VBIAS1 of the _fourth transistor M4 becomes the fluctuation of the gate voltage _VG3 of the _third transistor M3, and the turn-off operation of the output transistor _MH (slew rate, etc.) adversely affect

Conversely, when the _fifth transistor M5 is turned off, the gate voltage of the _fourth transistor M4 (ie, the bias voltage V _BIAS1 ) fluctuates under the influence of the gate capacitance of the _fourth transistor M4. At this time, when the second transistor M2 is turned on, the variation of the gate voltage _VBIAS1 of the _first transistor M1 _results in the variation of the gate voltage _VG of the output transistor _MH , adversely affecting the turn-on operation of the output transistor _MH .

Therefore, if the fluctuation of the bias voltage V _BIAS1 is unacceptably large, it is necessary to add a smoothing capacitor _C2 to reduce the fluctuation range.

(Example 4.3)
FIG. 20 is a circuit diagram of a semiconductor device 300C including an output circuit 100C according to Example 4.3. In example 4.2 (Fig. 19) the _first transistor M1 and the _fourth transistor M4 were biased by a common voltage source. In contrast, in embodiment 4.3, the _first transistor M1 and the _fourth transistor M4 are biased by separate voltage sources. Specifically, drive circuit 200C includes first voltage source 250 and second voltage source 260 . Second voltage source 260 is configured similarly to first voltage source 250 and includes a second constant voltage element 262 and a second current source 264 .

The above is the configuration of the output circuit 100C. Next, the operation will be explained. FIG. 21 is an operation waveform diagram of the output circuit 100C of FIG. The turn-on circuit 230 and the sub-driver 220 operate complementarily according to the control signal _SCTRL . Therefore, the voltages V _A and V _A ' at the two corresponding nodes N ₁ and N ₂ fluctuate complementarily, and the bias voltages V _BIAS1 and V _BIAS2 also fluctuate complementarily. The bias voltage V _BIAS1 is used during the ON period when the _second transistor M2 is ON, ie, when the control signal S _CTRL is high, and the bias voltage V _BIAS1 is stable during this ON period. Similarly, the bias voltage V _BIAS2 is utilized during the period when the _fifth transistor M5 is on, that is, during the off period when the control signal S _CTRL is low, during which the bias voltage V _BIAS2 is stable. .

According to this output circuit 100C, variations in the bias voltages V _BIAS1 and V _BIAS2 do not affect the low gate voltages V _G and V _G3 of the output transistor M _H and third transistor M ₃ , respectively. Therefore, since the capacitor _C2 shown in FIG. 19 is not required, the circuit area can be reduced.

(Example 4.4)
FIG. 22 is a circuit diagram of a semiconductor device 300D including an output circuit 100D according to Example 4.4. In the circuits of FIGS. 19 and 20, the gate capacitance of the _third transistor M3 is charged by the _second resistor R2. Therefore, when the size (W/L) of the _third transistor M3 is large _, the same problem as in the drive circuit 200A of FIG. The problem can arise that you can't.
In this embodiment, the _third transistor M3 and the sub-driver 220 are connected in series in two stages. A third transistor _{M3_2} in the latter stage is provided between the input terminal IN and the gate of the output transistor _MH . The front-stage third transistor _{M3_1} is provided between the input terminal IN and the gate of the rear-stage third transistor _{M3_2} .

The sub-driver 220_1 turns on the third transistor _{M3_1} when the control signal _{S_CTRL} is high, and turns off the third transistor _{M3_1} when it is low. The sub-drivers 220_1 and 220_2 are similarly configured. The gate of the fourth transistor _{M4_1} of the sub-driver 220_1 is commonly biased with the gate of the _first transistor M1.

(Fifth embodiment)
FIG. 23 is a circuit diagram of a semiconductor device 300E including an output circuit 100E according to the fifth embodiment. The fifth embodiment further multistages the output circuit 100D of FIG. The output circuit 100E is provided with a plurality (N) of third transistors _{M3_1} to _{M3_N} and a plurality of stages (N stages) of sub-drivers 220_1 to 220_N, which are connected in cascade. The sizes (driving capabilities) of the constituent elements of the plurality of third transistors M3 and the sub-driver 220 are larger in the later stages.

A plurality of sub-drivers 220_1-220_N are similarly configured. The i-th sub-driver 220_i (1≤i≤N) drives the corresponding third transistor _{M3_i} . The final-stage third transistor _{M3_N} is provided between the input terminal IN and the gate of the output transistor _MH . The third transistor _{M3_j in the previous stage (1≤j≤N-1) is provided between the} input terminal IN and the gate of the third transistor M3_ _(j+1) in the subsequent stage.

The gates of the _{first transistor M 1 and} the fourth transistors M 4 — _N , M 4 _{— (N−2)} , . The gates of the remaining fourth transistors M _{4_(N-1)} , M _{4_(N-3)} . . . are biased by a common further voltage source 260 .

(Application)
Next, the application of the output circuit 100 will be described. The semiconductor device (output circuit) described above can be used in a drive circuit for a mechanical relay. The relay device and the vehicle equipped with it are as described with reference to FIGS.

(Modification 4.1)
In the fourth embodiment, a semiconductor device composed of MOSFETs has been described, but the present invention is not limited to this, and arbitrary MOSFETs can be replaced with bipolar transistors or the like. In this case, in the above description, the gate should be read as the base, the drain as the collector, and the source as the emitter.

(Modification 4.2)
In the fourth embodiment, the case where the output transistor _MH is integrated in the semiconductor device 300 has been described, but the present invention is not limited to this, and a discrete element may be used as the output transistor _MH .

(Modification 4.3)
Applications of the semiconductor device 300 are not limited to a relay drive circuit, but can also be used as a switching power supply such as a DC/DC converter, a motor drive circuit (inverter), an AC/DC converter, a DC/AC converter (inverter), and a secondary battery. It can also be used for charging/discharging systems, power conditioners, and the like.

Although the present invention has been described using specific terms based on the embodiments, the embodiments merely show the principles and applications of the present invention, and the embodiments are defined in the scope of claims. Many modifications and changes in arrangement are permitted without departing from the spirit of the present invention.

100 output circuit _MH output transistor 200 drive circuit 201 internal line 202 gate line 210 turn-off circuit 204 driver 220 sub-driver 222 turn-off circuit 224 turn-on circuit 230 turn-on circuit 240 bias circuit 242 constant voltage element 244 current source 250 first voltage source 252 second 1 constant voltage element 254 first current source 260 second voltage source 262 second constant voltage element 264 second current source 270 voltage correction circuit 272 current source 280 clamp circuit 300 semiconductor device R ₁ impedance element, first resistor R ₂ second Resistor M1 _First transistor M2 _Second transistor M3 _Third transistor M4 _Fourth transistor M5 _Fifth transistor 400 Relay device 410 Mechanical relay 500 Drive circuit

Claims (17)

A drive circuit for driving a P-channel or PNP-type output transistor provided between an input terminal receiving an input voltage and an output terminal according to a control signal,
internal line and
a first transistor having a control electrode, gate or base, biased and a first electrode, source or emitter, connected to said internal line;
a voltage correction circuit that acts on the internal line to gradually reduce the voltage of the internal line over time;
with
A driving circuit, wherein the voltage of the internal line is applied to the control electrode, which is the gate or base of the output transistor, during its ON period. 2. The drive circuit of claim 1, wherein said voltage correction circuit includes a current source for sinking auxiliary current from said internal line. an upper power supply terminal connected to the input terminal, a lower power supply terminal connected to the internal line, and an output terminal connected to a control electrode, which is the gate or base of the output transistor, according to the control signal. 3. The drive circuit according to claim 2, further comprising a driver for driving said output transistor. 4. A drive circuit according to claim 3, wherein said auxiliary current is less than the current sunk by said driver from said control electrode of said output transistor during the ON period of said output transistor. 3. The driving circuit according to claim 2 , further comprising a second transistor provided between the second electrode, which is the drain or collector of the first transistor, and ground, and turned on and off according to the control signal. . 6. The drive circuit according to claim 5, wherein the auxiliary current is smaller than the current sunk from the control electrode of the output transistor through the second transistor during the ON period of the output transistor. further comprising a third transistor provided between the input terminal and the control electrode of the output transistor and turned on during a period in which the output transistor should be turned off;
3. The drive circuit according to claim 2, wherein the auxiliary current is smaller than the current flowing through the third transistor during the OFF period of the output transistor. 8. The drive circuit according to claim 1 , further comprising a clamp circuit for clamping the voltage of said internal line so that the potential difference from said input voltage does not exceed a predetermined value. 9. The drive circuit according to claim 8 , wherein said clamp circuit includes a Zener diode provided between said input terminal and said internal line. 10. The control signal according to claim 1 , wherein the control signal is a pulse signal in a normal state of the input voltage, and a DC signal that instructs to turn on fixedly in a reduced voltage state in which the input voltage drops. A drive circuit according to any one of the preceding claims. 10. The drive circuit according to claim 1 , wherein said control signal is a pulse signal, and the ON level time of said control signal becomes longer in a reduced voltage state in which said input voltage drops. 8. The driving circuit according to claim 2 , wherein said auxiliary current is turned on and off according to said control signal. 8. The driving circuit according to claim 2 , wherein said auxiliary current is fixedly on regardless of the level of said control signal. 14. The drive circuit according to any one of claims 1 to 13 , further comprising a bias circuit that supplies a bias voltage lower than the input voltage by a predetermined voltage width to the control electrode of the first transistor. The bias circuit is
a first Zener diode provided between the input terminal and the control electrode of the first transistor;
a current source provided between the control electrode of the first transistor and ground;
15. The drive circuit of claim 14 , comprising: a P-channel or PNP output transistor;
a driving circuit according to any one of claims 1 to 15 , which drives the output transistor;
A semiconductor device comprising: a mechanical relay,
17. The semiconductor device according to claim 16 , which drives the mechanical relay;
An automobile characterized by comprising:

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