JP2019064873A - Semiconductor growth substrate, semiconductor element, semiconductor light emitting element and method for manufacturing semiconductor growth substrate - Google Patents

Abstract

To provide: a semiconductor growth substrate capable of reducing crystal defects even while using an inexpensive heterogeneous substrate to grow a semiconductor layer excellent in crystal quality ; a semiconductor element; a semiconductor light emitting element; and a method for manufacturing the semiconductor growth substrate.SOLUTION: A semiconductor growth substrate comprises: a heterogeneous substrate 1 having a crystal structure different from that of a semiconductor layer 3 to be grown; a nanowire layer 2a including a plurality of nanowires formed on the heterogeneous substrate 1 and having a columnar crystal of a nano size to a micron size; a diameter expansion layer 2b in which the diameter of the nanowire is expanded and varied; and a ground layer 2c constituted to bond adjacent nanowires. The heterogeneous substrate 1 is one of a sapphire substrate, a Si substrate and a SiC substrate; the nanowire layer 2a, the diameter expansion layer 2b and the ground layer 2c are GaN single crystals; and the GaN single crystal uses a c plane as a main growth surface.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method of manufacturing a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting device, and a semiconductor growth substrate.

  Heretofore, as semiconductor light emitting devices such as LEDs (Light Emitting Diodes) and semiconductor lasers, those using compound semiconductor materials such as GaN-based and SiC-based having a large band gap have been proposed. In addition, since these materials have high breakdown electric field strength and high electron mobility, their application to semiconductor devices such as high electron mobility transistors (HEMTs) which are power devices is also being studied.

  In order to improve the performance of semiconductor elements and semiconductor light emitting elements using these compound semiconductor materials, it is necessary to improve the crystal quality of the semiconductor layers constituting the functional layer and the active layer, and a substrate of the same material system as the semiconductor layer It is preferable to use However, since low-defect GaN and SiC substrates are very expensive and the substrate size is also small, it is often used to use a different type of material substrate different from the semiconductor layer.

  When sapphire or the like is used as the dissimilar substrate, the semiconductor layer is grown through the buffer layer for reducing the lattice mismatch because the lattice constant and the crystal structure are different between the semiconductor layer to be grown and the dissimilar substrate. Is common. In addition, techniques for selectively forming a mask on different types of substrates, and forming grooves in different types of substrates to reduce crystal defects caused by lattice mismatch, linear expansion coefficient difference, etc. by lateral growth are also used. (See, for example, Patent Documents 1 and 2).

Japanese Patent Application Publication No. 11-130597 JP 2000-106455 A

  However, in the above-described conventional lateral growth, the size of the growth region of the dissimilar substrate is several μm to several hundreds μm, and to reduce the density of crystal defects and threading dislocations, the number of semiconductor layers grown in the lateral direction is also several. It was necessary to grow with a thickness of μm to several hundreds of μm. In addition, it is difficult to sufficiently reduce crystal defects and threading dislocations even if a semiconductor layer having a sufficient thickness is laterally grown.

  Therefore, the present invention provides a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting device, and a semiconductor growth substrate capable of growing a semiconductor layer of good crystal quality by reducing crystal defects while using an inexpensive heterogeneous substrate. An object is to provide a manufacturing method.

  In order to solve the above problems, the substrate for semiconductor growth of the present invention is a heterogeneous substrate having a crystal structure different from that of the semiconductor layer to be grown, and a nanowire which is a nanosized to micron sized columnar crystal formed on the heterogeneous substrate. A plurality of nanowire layers each including a plurality of nanowire layers, a diameter expansion layer in which the diameter of the nanowires is expanded and changed, and an underlayer formed by combining the adjacent nanowires.

  In such a substrate for semiconductor growth of the present invention, a nanowire layer provided with a plurality of nanowires is formed on a heterogeneous substrate, and a diameter expansion layer and an underlayer are grown from the nanowire layer. The influence can be suppressed by the nanowires, and it is possible to grow a semiconductor layer of good crystal quality by reducing crystal defects while using an inexpensive dissimilar substrate.

  In one aspect of the present invention, the heterogeneous substrate is any one of a sapphire substrate, a Si substrate, and a SiC substrate.

  In one aspect of the present invention, the nanowire layer, the diameter expansion layer, and the base layer are GaN single crystals, and the GaN single crystals have a c-plane as a main growth surface.

  In order to solve the above-mentioned subject, a semiconductor device of the present invention is characterized by providing a functional layer on a substrate for semiconductor growth given in any one of the above.

  In order to solve the above-mentioned subject, a semiconductor light emitting element of the present invention is characterized by providing an active layer on a substrate for semiconductor growth given in any one of the above.

  Further, in order to solve the above problems, according to the method for manufacturing a substrate for semiconductor growth of the present invention, a plurality of nanowires which are columnar crystals of nano size to micron size are provided on a foreign substrate different in crystal structure from the semiconductor layer to be grown. Characterized by comprising a nanowire formation step of forming a nanowire layer, a diameter enlargement step of continuing the growth by expanding the diameter of the nanowire, and an underlayer formation step of continuing the growth by combining adjacent nanowires. Do.

  In the present invention, manufacturing of a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element and a substrate for semiconductor growth capable of growing a semiconductor layer of good crystal quality by reducing crystal defects while using an inexpensive heterogeneous substrate We can provide a way.

It is process drawing which shows the manufacturing method of the board | substrate for semiconductor growth in 1st Embodiment of this invention, FIG. 1 (a) is a mask process, FIG.1 (b) is a nanowire formation process, FIG.1 (c) is a diameter expansion process. 1 (d) shows a base layer forming process, and FIG. 1 (e) shows a semiconductor layer forming process. It is sectional drawing which shows typically the structure of the semiconductor light-emitting device 10 in 2nd Embodiment of this invention. It is sectional drawing which shows typically the structure of the semiconductor element 20 in 3rd Embodiment of this invention.

First Embodiment
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and duplicative descriptions will be omitted as appropriate. FIG. 1 is a process drawing showing a method of manufacturing a substrate for semiconductor growth in the first embodiment of the present invention, and FIG. 1 (a) is a mask process, FIG. 1 (b) is a nanowire formation process, FIG. FIG. 1 (d) shows a base layer forming step, and FIG. 1 (e) shows a semiconductor layer forming step.

  First, in the mask process shown in FIG. 1A, the dissimilar substrate 1 is prepared, the mask 1a is formed over the entire main surface, and the opening 1b is formed in a predetermined region using a known patterning method. Here, the heterosubstrate 1 is a single crystal substrate having a crystal structure different from that of the semiconductor layer to be grown. For example, when the material system of the semiconductor layer to be grown is GaN, sapphire substrate, Si substrate and SiC substrate are listed. Be Further, as described later, the main surface of the heterosubstrate 1 is a crystal surface on which the nanowires of the growing semiconductor layer can be grown. For example, in the case of a GaN-based semiconductor layer, the c plane of the sapphire substrate is mainly used. It can be used as a surface.

  The material which comprises the mask 1a is not specifically limited, Well-known materials, such as a resist, can be apply | coated by a spin coat method etc. Further, the type of the resist film is not limited, and may be a thermosetting type or a UV curing type as long as nano-sized patterning is possible.

  The opening 1 b is a region in which the mask 1 a is partially removed to expose the main surface of the dissimilar substrate 1, and the plurality of openings 1 b are two-dimensionally arranged on the main surface of the dissimilar substrate 1. . The size of the opening 1 b is nano size or micron size. The shape of the opening 1 b is not limited, but a regular polygonal shape such as a circle, a quadrangle, or a hexagon is preferable. The two-dimensional arrangement of the openings 1b on the main surface of the heterosubstrate 1 is not particularly limited, and a known arrangement such as a square lattice shape or a triangular lattice shape can be used.

  Here, nanosize refers to a range of 1 nm or more and less than 1 μm, and the nanowire which is a columnar crystal of nanosize refers to the size in the width direction in a cross section parallel to the c-plane being 1 nm or more and less than 1 μm. Here, the micron size indicates a range of 1 μm to less than 10 μm, and the nanowire which is a columnar crystal of micron size means that the size in the width direction in a cross section parallel to the c-plane is 1 μm to less than 10 μm. A more preferable micron size is 1 μm or more and less than 5 μm, and more preferably 1 μm or more and less than 3 μm.

  Examples of the patterning method of the mask 1a include known methods such as transfer of a pattern by nanoimprint technology using a mold on which a predetermined pattern is formed, photolithography, and etching.

Next, in the nanowire formation step shown in FIG. 1 (b), nanosize or micron size is formed on the dissimilar substrate 1 exposed from the opening 1b using metal organic chemical vapor deposition (MOCVD method: Metal Organic Chemical Vapor Deposition). A plurality of nanowires, which are columnar crystals, are grown to form a nanowire layer 2a. As a growth method of the nanowire layer 2a by the specific MOCVD method, when the material of the semiconductor layer grown on the heterogeneous substrate 1 is a GaN-based material, for example, hydrogen or nitrogen is used as a carrier gas and ammonia is used as a V group material The growth temperature is 900 to 1200 ° C., the growth pressure is 400 mbar or less, the V / III ratio is 1,500, and the like using (NH ₃ ) and TMG (Trimethyl Gallium) as a group III raw material.

  Here, in the nanowire layer 2a, columnar crystals are selectively grown on the region of the opening 1b as shown in FIG. 1 (b). This is because, for example, in the case of a GaN-based material, a GaN single crystal having a c-plane main surface is grown on a c-plane sapphire heterogeneous substrate 1, but six m-planes perpendicular to the c-plane are formed as facets and c-plane direction Growth is a priority. Therefore, in the case of a GaN-based material, the plurality of nanowires included in the nanowire layer 2a are in a hexagonal column shape perpendicular to the c-plane and having the m-plane as a side surface. Although FIG. 1B shows an example in which a columnar crystal is grown vertically from the opening 1b, an m-plane may cover the mask 1a slightly in the lateral growth in the vicinity of the opening 1b. In addition, although a flat c-plane is shown in FIG. 1 (b) as the upper surface of the columnar crystal included in the nanowire layer 2a, a specific crystal plane such as an a-plane may be formed as a facet.

  Next, in the diameter expansion step shown in FIG. 1C, the semiconductor layer is continuously grown from the plurality of columnar crystals included in the nanowire layer 2a using the MOCVD method. At this time, by adjusting the growth conditions, it is possible to grow the semiconductor layer while expanding the diameter of the columnar crystal, and the diameter expanded layer 2b is formed. The diameter expansion step is continued until the diameter expansion layers 2b grown from the adjacent columnar crystals are bonded to each other.

The growth conditions for growing the diameter expansion layer 2b include lowering the growth temperature and increasing the growth pressure and raising the V / III ratio as compared to the nanowire formation step. Specifically, for example, using hydrogen and nitrogen as a carrier gas, using ammonia (NH ₃ ) as a group V source, and using TMG as a group III source, a growth temperature of 700 to 900 ° C., a growth pressure of 400 mbar or more, V / III ratio 3000-5000 etc. are mentioned.

  Next, in the base layer forming step shown in FIG. 1D, the semiconductor layer is continuously grown from the diameter expansion layer 2b using the MOCVD method, and nanowires which are adjacent columnar crystals are bonded to each other to form the dissimilar substrate 1 Underlayer 2c is formed over the entire surface of Here, as shown in FIG. 1D, the nanowire layer 2a which is a columnar crystal is not grown in the region on the mask 1a, and the diameter expansion layer 2b and the base layer 2c cover the upper side of the mask 1a with an overhang. An air gap is formed on the mask 1a. By the steps of forming the underlayer shown in FIG. 1D, the method for manufacturing a substrate for semiconductor growth in the present invention is completed, and the substrate for semiconductor growth in the present invention is obtained.

  Finally, in the semiconductor layer forming step shown in FIG. 1 (e), GaN 3 is grown on the underlayer 2c by MOCVD. The semiconductor layer forming step may be carried out by the same MOCVD apparatus continuously from the base layer forming step, and the semiconductor growth substrate obtained after completion of the base layer forming step is taken out of the MOCVD device and stored. It may be implemented by another MOCVD apparatus as a post process.

  The substrate for semiconductor growth obtained by the method for manufacturing a substrate for semiconductor growth in the present embodiment is a nanowire layer 2a including a plurality of nanowires that are columnar crystals of nano size to micron size formed on the dissimilar substrate 1 and the diameter of the nanowires. And the base layer 2c formed by combining adjacent nanowires with each other.

  The nanowires included in the nanowire layer 2a are nano-sized to micron-sized columnar crystals, so the area of the interface with the main surface of the dissimilar substrate 1 is extremely small, and crystal defects due to lattice mismatch or linear expansion coefficient difference Is sufficiently reduced. In addition, in the nanowire layer 2a, crystal defects are reduced by nano-sized to micron-sized columnar crystals, so the total thickness of the nanowire layer 2a, the diameter expansion layer 2b, and the underlayer 2c is smaller than defect reduction using conventional lateral growth. Thus, it is possible to reduce the growth time and to reduce the raw materials used.

  The smaller the size in the width direction of the cross section parallel to the c-plane of the columnar crystal is, the larger the size of the nanowire is, preferably 1 μm to 10 μm, and more preferably 1 μm to 5 μm. Or less, more preferably 1 μm or more and less than 3 μm, and most preferably nano-sized.

  Further, since the diameter expansion layer 2b and the base layer 2c are continuously grown from the nanowire layer 2a, crystal defects are similarly sufficiently reduced. Furthermore, in the diameter expansion layer 2b continuously grown from the nanowire layer 2a, the crystal defect is bent in the lateral direction by the lateral growth, so that the crystal defect penetrating to the base layer 2c can be further reduced. Thereby, in the substrate for semiconductor growth of the present embodiment, the crystal defects of the base layer 2c are sufficiently reduced, and the crystal defects are reduced while using an inexpensive foreign substrate to grow a semiconductor layer of good crystal quality. It is possible to

Second Embodiment
Next, a second embodiment of the present invention will be described with reference to FIG. The same contents as the first embodiment will not be described. FIG. 2 is a cross-sectional view schematically showing the structure of a semiconductor light emitting device 10 according to a second embodiment of the present invention.

  The semiconductor light emitting device 10 shown in FIG. 2 includes the heterosubstrate 1, the nanowire layer 2a, the diameter expansion layer 2b, the underlayer 2c, the GaN layer 3, the n-type semiconductor layer 4, the active layer 5, the p-type semiconductor layer 6, the n-side electrode 7 has a p-side electrode 8. Here, an example of an LED is shown as the semiconductor light emitting element 10, but a known semiconductor laser structure may be formed.

  Similar to the first embodiment, the heterosubstrate 1 is prepared to form the mask 1a, and the nanowire layer 2a, the diameter expansion layer 2b, and the base layer 2c are grown by the MOCVD method. Subsequently, a GaN layer 3, an n-type semiconductor layer 4, an active layer 5, and a p-type semiconductor layer 6 are sequentially grown by the MOCVD method.

  Next, part of the p-type semiconductor layer 6 and the active layer 5 are removed by photolithography and etching using a predetermined mask pattern to expose part of the n-type semiconductor layer 4. Next, an electrode material is formed on the exposed surfaces of the n-type semiconductor layer 4 and the p-type semiconductor layer 6 by evaporation or the like, and dicing is performed to form an individual chip, whereby the semiconductor light emitting device 10 is obtained.

  Although the n-type semiconductor layer 4 and the p-type semiconductor layer 6 are each described here as a single layer, they may include a plurality of layers having different materials and compositions, for example, the n-type semiconductor layer 4 and the p-type semiconductor The layer 6 may include a cladding layer, a contact layer, a current diffusion layer, an electron blocking layer, a waveguide layer, and the like. In addition, although the active layer 5 has been described as a single layer, it may be configured of multiple layers such as a multi quantum well (MQW) structure.

  The n-type semiconductor layer 4 is epitaxially grown on the GaN layer 3 and is a semiconductor layer doped with an n-type impurity whose main surface is c-plane, and electrons are injected from the n-side electrode 7 to the active layer 5. It is a layer to supply. As a material which comprises the n-type semiconductor layer 4, GaN, AlGaN, InGaN, AlInGaN etc. are mentioned as a III-V group compound semiconductor layer, for example, Si etc. are mentioned as an n-type impurity.

  The active layer 5 is epitaxially grown on the n-type semiconductor layer 4 and is a semiconductor layer having the c-plane as a main surface, and the semiconductor light emitting element 10 emits light by recombination of electrons and holes in the layer. The active layer 5 is made of a material having a smaller band gap than the n-type semiconductor layer 4 and the p-type semiconductor layer 6, and examples thereof include InGaN and AlInGaN. The active layer 5 may be intentionally non-doped without containing an impurity, or may be n-type containing an n-type impurity or p-type containing a p-type impurity.

  The p-type semiconductor layer 6 is a semiconductor layer epitaxially grown on the active layer 5 and having the c-plane as the main surface, and a layer which injects holes from the p-side electrode 8 and supplies holes to the active layer 5. . As a material which comprises the p-type semiconductor layer 6, GaN, AlGaN, InGaN, AlInGaN etc. are mentioned as a III-V group compound semiconductor layer, for example, Zn, Mg etc. are mentioned as a p-type impurity.

  Also in the present embodiment, the semiconductor light emitting device 10 has the nanowire layer 2a, the diameter expansion layer 2b, and the base layer 2c formed on the dissimilar substrate 1, and the GaN layer 3, the n-type semiconductor layer 4, the active layer 5, the p-type semiconductor layer 6 is epitaxially grown. Therefore, as described in the first embodiment, the crystal defects and threading dislocations can be sufficiently suppressed by the nanowires, and the n-type semiconductor layer 4, the active layer 5, and the p-type semiconductor layer 6 grown thereon are also favorable. Become crystalline. As a result, the characteristics of the n-type semiconductor layer 4, the active layer 5, and the p-type semiconductor layer 6 also become good, and improvement of the external quantum efficiency of the semiconductor light emitting device 10 and the like are expected.

Third Embodiment
Next, a third embodiment of the present invention will be described. The same contents as the first embodiment will not be described. FIG. 3 is a cross-sectional view schematically showing the structure of the semiconductor device 20 in the present embodiment. The semiconductor device using the semiconductor growth substrate in the present invention is not limited to the semiconductor light emitting device 10 such as an LED or a semiconductor laser, but may be a semiconductor device such as a HEMT provided with a functional layer on the semiconductor growth substrate.

  As shown in FIG. 3, the semiconductor device 30 includes the heterosubstrate 1, the nanowire layer 2 a, the diameter expansion layer 2 b, the underlayer 2 c, the electron transit layer 23, the electron supply layer 24, the protective film 25, the source electrode 26, the gate electrode 27, It has a drain electrode 28p. Although an example of a HEMT is shown here as the semiconductor device 20, the device structure is not limited as long as it is a known semiconductor device. In addition, a structure known as HEMT may be provided in each layer, or a p-type layer or an n-type layer may be added.

  The electron transit layer 23 is a layer which is epitaxially grown on the base layer 2c and moves electrons, and is made of, for example, GaN. The electron supply layer 24 is an n-type semiconductor layer having a larger band gap than the electron transit layer 23 epitaxially grown on the electron transit layer 23, and is made of, for example, n-type AlGaN. A two-dimensional electron gas layer is formed in the vicinity of the interface between the electron transit layer 23 and the electron supply layer 24. Therefore, the combination of the electron transit layer 23 and the electron supply layer 24 corresponds to the functional layer in the present invention.

  The protective film 25 is an insulating film formed in a predetermined region on the electron supply layer 24, and a region where the protective film 25 is not formed is a region where the source electrode 26, the gate electrode 27, and the drain electrode 28 are formed. . The source electrode 26 and the drain electrode 28 are electrodes made of a metal material formed on the electron supply layer 24 and make ohmic contact with the electron supply layer 24. The gate electrode 27 is an electrode made of a metal material formed on the electron supply layer 24 and has a Schottky junction with the electron supply layer 24.

  In the electron supply layer 24, a depletion layer is formed in the vicinity of the interface with the electron transit layer 23 by the formation of the two-dimensional electron gas layer, and a depletion layer is formed by the Schottky junction at the interface with the gate electrode 27. Therefore, by changing the voltage applied to gate electrode 27, the thickness of the depletion layer is adjusted by the field effect to control the concentration of the two-dimensional electron gas, and the current flowing between source electrode 26 and drain electrode 28 is controlled. can do.

  Also in the present embodiment, in the semiconductor device 20, the nanowire layer 2a, the diameter expansion layer 2b, and the base layer 2c are formed on the dissimilar substrate 1, and the electron transit layer 23 and the electron supply layer 24 are epitaxially grown. Therefore, as described in the first embodiment, the crystal defects and threading dislocations can be sufficiently suppressed by the nanowires, and the electron transit layer 23 and the electron supply layer 24 grown thereon also have good crystallinity. As a result, the characteristics of the electron transit layer 23 and the electron supply layer 24 also become good, and the performance improvement of the semiconductor element 20 is expected.

Fourth Embodiment
Next, a fourth embodiment of the present invention will be described. The same contents as the first embodiment will not be described. In the second embodiment, the semiconductor light emitting device 10 has a structure including the dissimilar substrate 1, the nanowire layer 2a, the diameter expansion layer 2b, and the base layer 2c, but polishing, etching, laser ablation, etc. from the back side of the substrate The dissimilar substrate 1, the nanowire layer 2a, and the diameter expansion layer 2b may be removed using a technique. Alternatively, the n-side electrode 7 may be provided on the side from which the dissimilar substrate 1 is removed, and the p-side electrode 8 and the n-side electrode 7 may be opposed to each other.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Is also included in the technical scope of the present invention.

DESCRIPTION OF SYMBOLS 10 Semiconductor light emitting element 1 Heterogeneous substrate 1a Mask 1b Opening 2a Nanowire layer 2b Diameter expansion layer 2c Underlayer 3 GaN layer 4 n-type semiconductor layer 5 Active layer 6 p-type semiconductor layer 7 ... n-side electrode 8 ... p-side electrode 20 ... semiconductor element 23 ... electron traveling layer 24 ... electron supply layer 25 ... protective film 26 ... source electrode 27 ... gate electrode 28 ... drain electrode

Claims (6)

A different kind of substrate different in crystal structure from the semiconductor layer to be grown;
A nanowire layer comprising a plurality of nanowires, which are nano-sized to micron-sized columnar crystals formed on the heterogeneous substrate, and a diameter-expanding layer in which the diameter of the nanowire is expanded and changed;
A substrate for semiconductor growth, comprising: an underlayer formed by bonding the adjacent nanowires to each other. The substrate for semiconductor growth according to claim 1, wherein
The substrate for semiconductor growth is any one of a sapphire substrate, a Si substrate, and a SiC substrate. The semiconductor growth substrate according to claim 1 or 2, wherein
The substrate for semiconductor growth, wherein the nanowire layer, the diameter expansion layer, and the base layer are GaN single crystals, and the GaN single crystal has a c-plane as a main growth surface.   A semiconductor device comprising a functional layer on the semiconductor growth substrate according to any one of claims 1 to 3.   A semiconductor light emitting device comprising an active layer on the semiconductor growth substrate according to any one of claims 1 to 3. Forming a nanowire layer comprising a plurality of nanowires of nano-sized to micron-sized columnar crystals on a foreign substrate having a crystal structure different from that of the semiconductor layer to be grown;
An expanding step of expanding the diameter of the nanowire to continue the growth;
A method for manufacturing a substrate for semiconductor growth, comprising a base layer forming step of combining adjacent nanowires and continuing growth.