JP2019050501A - General-purpose bus control method, general-purpose bus controller and general-purpose bus control program - Google Patents

Abstract

To optimize a waveform of a general-purpose bus during the operation of an apparatus.SOLUTION: The general-purpose bus controller, controlling a general-purpose bus connected with a device, includes: a drive circuit for driving a general-purpose bus; a memory table for previously storing an optimum waveform at the general-purpose bus; and a waveform check circuit for checking a waveform of the general-purpose bus. Acquisition means acquires a checked waveform. Comparison means compares the acquired waveform to the previously stored optimum waveform. Change/setting means can execute setting to change an optimum value of a drive circuit according to a comparison result.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a general-purpose bus control method for controlling a general-purpose bus for connecting a drive (device) such as a hard disk drive (HDD) or memory to a computer main body, a general-purpose bus control device, and a general-purpose bus control program.

  Various are known as being standards for a universal bus interface defining a universal bus. For example, ATA (advanced technology attachment) is one of connection standard standards for communication by connecting a storage device (external storage device) such as a hard disk drive (HDD) to a computer main body.

  Further, SATA (Serial ATA) is an interface standard for connecting a hard disk drive (HDD), a solid state drive (SSD) or an optical drive to a computer main body. SATA is a connection interface standard for recording drives, which has replaced mainstream SCSI (small computer system interface) and parallel ATA. Here, a solid state drive (SSD) is a device that can be treated as a storage (in particular, a disk drive) using a semiconductor element memory as a storage device.

  Universal Serial Bus (USB) is one of serial bus standards for connecting peripheral devices to information devices such as computers.

  Here, the HDD, the SSD, the optical drive, the recording drive, the peripheral devices and the like as described above are collectively referred to simply as “device”.

  In a general-purpose bus interface such as SATA / USB as described above, a drive circuit (a bus controller or a bus controller that controls data input / output according to the line length / signal characteristics of the general-purpose bus and the characteristics of the connected hard disk / memory). The waveform in the driver changes. The bus controller is also called a bus controller IC (integrated circuit) or a driver chip, and the redriver is also called a redriver IC or a redriver chip.

  From this, with regard to the control value set in the drive circuit that controls the signal strength of the general-purpose bus, the waveform is measured in advance evaluation, the optimum value is determined, and the control value of the drive circuit is determined It is common to operate with a fixed value. In that case, the optimum value of the drive circuit (bus controller / redriver) may change due to changes in signal characteristics of the general-purpose bus due to aged deterioration / temperature change, changes in devices used (HDD or SSD), or the like. In such a case, there is a possibility of an error.

  In other words, in the general-purpose bus interface, when the optimum value of the control value for setting the signal strength and the like of the drive circuit for bus control changes due to some influence during device operation, the control value is fixed as a fixed value. I can not cope with that.

  Various techniques have been proposed to overcome such problems.

  For example, Patent Document 1 discloses a method in which access is performed with a plurality of setting values when the apparatus is started, and in some cases, an error is repeated to select a value that does not cause an error.

  Patent Document 2 actively utilizes the fact that the waveform of the signal output on the bus line changes in accordance with the load capacitance component of the bus line, and based on this, appropriately controls the drive capability of the output signal. Disclosure of technical ideas. The bus drive circuit unit disclosed in Patent Document 2 determines the current bus state based on the voltage level of the feedback signal on the line, and the drive capability of the variable capability drive circuit based on the determination result. And d) determining drive capability.

  Patent Document 3 solves the limitations on the number of connected function expansion devices, transfer speed, and transfer width when aligning a bus at the time of design, and can minimize the effect of bus mismatching. And “apparatus” are disclosed.

  In Patent Document 3, the waveforms in the transmitting unit and the receiving unit of the card are observed, and it is determined from the waveforms whether or not matching is achieved. If matched, if it is confirmed that the current impedance value is also matched for data transfer in all other sections, the CPU accesses slot and termination impedance control, and the card attached is Load the ID and termination impedance values. Then, the card ID and the terminal impedance value are stored in the non-volatile memory. The value of the termination impedance is read from the non-volatile memory, and the read value is sent to the termination impedance control unit. Then, the switch control unit performs on / off control of the switch so that the value of the termination impedance becomes the sent value.

JP, 2010-092384, A Unexamined-Japanese-Patent No. 2000-261464 Japanese Patent Application Laid-Open No. 07-264218

  However, Patent Documents 1 to 3 have the following problems, respectively.

  In Patent Document 1, it is not possible to avoid the occurrence of an error in the process of selecting the optimum value.

  Since the patent document 2 measures a voltage level (only a voltage value), it becomes difficult to make the signal waveform of a general purpose bus close to the state of an optimal waveform. Further, in Patent Document 2, it is necessary to provide a dedicated circuit (drive capability determination means) for determining the drive capability of the drive circuit.

  Patent Document 3 can only cope with changes due to differences in the bus connection state at the time of device startup. In other words, Patent Document 3 can not cope with changes in operation of the device (waveform change).

  An object of the present invention is to provide a general-purpose bus control method, a general-purpose bus control device, and a general-purpose bus control program that solve the problems described above.

  The general-purpose bus control method of the present invention is a method of controlling a general-purpose bus connected to a device, comprising: a check step of checking a waveform of the general-purpose bus; an acquisition step of acquiring the checked waveform; And comparing and comparing the waveform with the pre-stored optimum waveform; and changing and setting the optimum value of the drive circuit for driving the general-purpose bus when the comparison results do not match; including.

  The general-purpose bus control device according to the present invention is a general-purpose bus control device for controlling a general-purpose bus connected to a device, comprising: a drive circuit for driving the general-purpose bus; A waveform check circuit for checking the waveform of the general-purpose bus; acquisition means for acquiring the checked waveform; comparison means for comparing the acquired waveform with the previously stored optimum waveform; and according to the comparison result And change / setting means settable to change the optimum value of the drive circuit.

  The general-purpose bus control program of the present invention is a general-purpose bus control program that causes a computer to control a general-purpose bus connected to a device, and the computer acquires the waveform of the general-purpose bus checked by a waveform check circuit. Setting a procedure to change the optimum value of the drive circuit for driving the general-purpose bus when the comparison result compares the obtained waveform with the previously stored optimum waveform; Execute change / setting procedure and

  According to the present invention, it is possible to optimize the waveform of the general purpose bus during the operation of the device.

FIG. 1 is a block diagram showing a configuration of a general-purpose bus control device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing an internal configuration of a bus controller used in the general-purpose bus control device shown in FIG. 1. It is a block diagram which shows the internal structure of the redriver used for the general purpose bus control apparatus shown by FIG. FIG. 7 is a diagram showing an example of optimum waveforms stored in a memory table in a bus control circuit used in the general-purpose bus control device shown in FIG. 1. It is a table | surface which shows an example of the content memorize | stored in the memory table as a parameter with the shape of the optimal waveform shown in FIG. It is a block diagram which shows the structure of CPU (control part) in the bus control circuit used for the general purpose bus control apparatus shown by FIG. It is a flowchart for demonstrating the operation | movement of the general purpose bus control apparatus shown in FIG. It is a block diagram showing composition of a general-purpose bus control device concerning a 2nd embodiment of the present invention. It is a block diagram which shows the structure of the general purpose bus control apparatus which concerns on the 3rd Embodiment of this invention.

  First, the features of the present invention will be described.

  In the general-purpose bus control device according to the present invention, a waveform check circuit is mounted on the general-purpose bus, and optimum values for the general-purpose bus are set in each drive circuit from the waveform information sampled by the waveform check circuit. By this, the signal strength of the general-purpose bus is changed to cope with the change of the optimum value.

  Hereinafter, embodiments of the present invention will be described.

First Embodiment
FIG. 1 is a block diagram showing the configuration of a general-purpose bus control device 1 according to a first embodiment of the present invention.

  The illustrated general-purpose bus control device 1 includes a bus control circuit 11, a bus controller 12, a redriver 13, a waveform check circuit 14, and a device 15.

  The bus control circuit 11 incorporates a bus controller 12. The illustrated bus control circuit 11 is configured by integrating a CPU (central processing unit) and a chip set into one chip. Therefore, the bus control circuit 11 is also called a CPU / chipset. The bus controller 12 is provided inside the chipset.

  As described above, the bus controller 12 is also called a bus controller IC or a driver chip, and the redriver 13 is also called a redriver IC or a redriver chip.

  The bus controller 12 and the redriver 13 are connected by a first general-purpose bus B1. The redriver 13 and the device 15 are connected by a second general-purpose bus B2.

  Each of the first general-purpose bus B1 and the second general-purpose bus B2 is a serial bus defined by a serial bus interface standard selected from the group of serial advanced technology attachment (SATA) and universal serial bus (USB) Good.

  The device 15 may also be a drive selected from the group of hard disk drives (HDDs), solid state drives (SSDs), optical drives, recording drives, and peripherals.

  The bus control circuit 11 incorporates a memory table 111 composed of non-volatile memory. A CPU (described later), which is a control unit of the bus control circuit 11, is connected to the bus controller 12 by a first local bus B3. Further, the bus control circuit 11 is connected to the redriver 13 by the second local bus B4. Furthermore, the bus control circuit 11 is connected to the waveform check circuit 14 by a third local bus B5.

  FIG. 2 is a block diagram showing an internal configuration of the bus controller 12. The bus controller 12 comprises a driver / equalizer C1 and a receiver / equalizer C2.

  The driver / equalizer C1 adjusts the amplitude / intensity or the like of the signal waveform of the input signal from the internal bus according to an instruction from the CPU via the first local bus B3, and transmits the adjusted signal to the first general-purpose bus B1. Send out. Similarly, the receiver / equalizer C2 adjusts the amplitude / intensity of the signal waveform of the input signal from the first general-purpose bus B1 according to an instruction from the CPU via the first local bus B3, and internally adjusts the adjusted signal. Tell the bus.

  FIG. 3 is a block diagram showing an internal configuration of the redriver 13. The redriver 13 includes a first receiver / equalizer C3, a first driver C4, a second receiver / equalizer C5, and a second driver C6.

  The first receiver / equalizer C3 adjusts the amplitude / intensity and the like of the signal waveform of the input signal from the first general-purpose bus B1 according to an instruction from the CPU via the second local bus B4. The adjusted signal is sent to the second general-purpose bus B2 after passing through the first driver C4.

  Similarly, the second receiver / equalizer C5 adjusts the amplitude / intensity of the signal waveform of the input signal from the second general-purpose bus B2 according to an instruction from the CPU via the second local bus B4. The adjusted signal is transmitted to the first general-purpose bus B1 after passing through the second driver C6.

  The waveform check circuit 14 shown in the figure measures the waveform of the second general-purpose bus B2 for a certain period, obtains time and voltage level information, and then takes waveform information indicating the obtained (checked) waveform to the third local bus It transfers to the bus control circuit 11 via B5. Thus, the waveform check circuit 14 sends the waveform information of the checked waveform to the bus control circuit 11 via the third local bus B5.

  Next, with reference to FIGS. 4 and 5, the memory table 111 built in the bus control circuit 11 will be described.

  The bus control circuit 11 measures an optimum waveform in the general-purpose bus control device 1 in advance as shown in FIG. In FIG. 4, the horizontal axis represents a time axis, and the vertical axis represents a voltage level.

  Then, the bus control circuit 11 stores the contents as shown in FIG. 5 in the memory table 111 as parameters indicating the shape of the optimum waveform. The value of voltage shown in FIG. 5 may have a width to some extent. As described above, the memory table 111 stores in advance optimum waveform information indicating the optimum waveform.

  FIG. 6 is a block diagram showing an internal configuration of a CPU (control unit) 110 included in the bus control circuit 11.

  As shown in FIG. 6, the CPU (control unit) 110 includes an acquisition unit 113, a comparison unit 115, and a change / setting unit 117.

  The acquisition unit 113 acquires waveform information of the waveform checked by the waveform check circuit 14 via the third local bus B5.

  The comparison unit 115 compares the waveform information of the waveform acquired by the acquisition unit 113 with the optimum waveform information indicating the optimum waveform stored in advance in the memory table 111.

  The change / setting unit 117 can be set to change the optimum values of the bus controller 12 and the redriver 13 according to the comparison result in the comparison unit 115, as described later.

  More specifically, if the comparison result in the comparison unit 115 does not match, the change / setting unit 117 sets the optimum values of the bus controller 12 and the redriver 13 to be changed. Change / setting unit 117 includes a register 119 for holding the changed drive strength setting value.

  Note that the acquisition unit 113, the comparison unit 115, and the change / setting unit 117 repeat the operation until the comparison result in the comparison unit 115 matches.

  As described above, in the first embodiment, the waveform states of the general-purpose buses B1 and B2 are confirmed with respect to the general-purpose bus control device 1 in which the device 15 is connected to the general-purpose buses B1 and B2 such as SATA / USB. A built-in waveform check circuit 14 is provided. Thereby, the signal strengths of the general purpose buses B1 and B2 are changed to cope with the change of the optimum value.

  Next, with reference to FIG. 7, the operation of the general-purpose bus control device 1 according to the first embodiment of the present invention will be described.

  First, the waveform check circuit 14 records the amplitude information of the waveform of the second general-purpose bus B2 as a numerical value, and transmits it as "waveform information" to the bus control circuit 11 via the third local bus B5.

  In the bus control circuit 11, the acquisition unit 113 acquires this "waveform information" (step S1).

  Next, in the bus control circuit 11, the comparison unit 115 compares the acquired "waveform information" with "optimum waveform information" stored in advance in the memory table 111 (step S2).

  As a result of comparison by the comparison unit 115, when the acquired "waveform information" and "optimum waveform information" match (step S3; YES), the change / setting unit 117 does not change the setting, and the operation is It will end.

  Here, that the acquired "waveform information" and "optimum waveform information" coincide not only when strictly (without error) both information coincide, but also within a predetermined tolerance. Note that this also includes the case where both pieces of information match.

  On the other hand, when the comparison result in the comparison unit 115 shows that the acquired “waveform information” and “optimum waveform information” do not match (step S3; NO), the change / setting unit 117 sets “drive strength setting” of the register 119. By changing and rewriting the value of “value”, the amplitude / intensity of the signal waveform in the bus controller 12 is adjusted via the first local bus B3. Further, the change / setting unit 117 performs the same process on the redriver 13 via the second local bus B4 (step S4).

  The bus controller 12 and the redriver 13 in which the value of “drive strength setting value” is rewritten in step S4 change drive waveforms of the first general-purpose bus B1 and the second general-purpose bus B2, respectively (step S5). .

  After step S5, the bus control circuit 11 performs the process again in the order of step S1, step S2, and step S3. If the acquired “waveform information” and the “optimum waveform information” coincide with each other in step S3 (step S3; YES), the operation ends. If the acquired “waveform information” and the “optimum waveform information” do not match in step S3 (step S3; NO), the bus control circuit 11 again performs steps S4, S5, S1, S2, S3 and S3. And repeat the series of processes until the acquired "waveform information" and "optimum waveform information" match.

  The operation of the general-purpose bus control device 1 described above is always performed when the device 15 is replaced. In addition, the operation of the general-purpose bus control device 1 is periodically performed even during the operation of the device. However, the operation of the general-purpose bus control device 1 may be performed irregularly during the operation of the device.

  Next, the effects of the first embodiment will be described.

  The first effect is that the first embodiment is not a method for judging whether or not an error occurs in waveform optimization. Therefore, not only at the start of the device but also during the operation of the device, the general purpose is generally used regularly. It is possible to optimize the setting of the bus waveform.

  The second effect is that, in the first embodiment, by performing adjustment until it matches the optimum waveform value, it is possible to always maintain the state of the ideal waveform with more margin.

  In the first embodiment, an example in which the bus controller 12 and the redriver 13 are provided as the drive circuit is described, but the present invention is not limited to this. That is, the present invention may include only the bus controller 12 as a drive circuit.

  As described above, each part of the bus control circuit 11 can be realized using a combination of hardware and software. In the combination of hardware and software, a general-purpose bus control program is expanded on a random access memory (RAM), and hardware such as the control unit (CPU) 110 is operated based on the general-purpose bus control program. Implement each part as various means. Also, the general-purpose bus control program may be recorded on a recording medium and distributed. The general-purpose bus control program recorded in the recording medium is read into the memory via a wired, wireless, or recording medium itself to operate the control unit and the like. Incidentally, examples of the recording medium include an optical disk, a magnetic disk, a semiconductor memory device, a hard disk and the like.

  Describing the first embodiment in another expression, the computer (CPU 110) operated as the bus control circuit 11 is changed by the acquisition unit 113, the comparison unit 115, and the change based on the general-purpose bus control program developed in the RAM. This can be realized by causing the setting unit 117 to operate.

Second Embodiment
FIG. 8 is a block diagram showing a configuration of a general-purpose bus control device 1A according to a second embodiment of the present invention.

  The illustrated general-purpose bus control device 1A has the same configuration as the general-purpose bus control circuit 1 shown in FIG. 1 except that it further includes another waveform check circuit 16, and operates. Therefore, components having the same function are denoted by the same reference numerals, and the description thereof will be omitted to simplify the description. Only the differences will be described below.

  The waveform check circuit 16 is a circuit that checks the waveform of the first general-purpose bus B1. The waveform information indicating the waveform checked by the waveform check circuit 16 is sent to the bus control circuit 11 via the fourth local bus B6.

  The bus control circuit 11 includes a switch (switching circuit) (not shown), and performs selection of the optimum value for each of the first general purpose bus B1 and the second general purpose bus B2 in order. Further, the bus control circuit 11 includes two registers 119 (FIG. 6) for each of the first general purpose bus B1 and the second general purpose bus B2.

  For example, first, in order to set an optimum value to the first general-purpose bus B1, the bus control circuit 11 acquires waveform information of the waveform checked by the waveform check circuit 16 via the fourth local bus B6. . Then, the bus control circuit 11 controls the bus controller 12 by the above-described operation to adjust the amplitude / intensity or the like of the signal waveform of the first general-purpose bus B1.

  After the adjustment is completed, the bus control circuit 11 sets the third local bus B5 to the waveform information of the waveform checked by the waveform check circuit 14 in order to set the optimum value to the second general-purpose bus B2. Get through. Then, the bus control circuit 11 controls the redriver 13 by the above-described operation to adjust the amplitude / intensity or the like of the signal waveform of the second general-purpose bus B2.

  The order of selection of the optimum value is not limited to this, and it goes without saying that the second general-purpose bus B2 may be selected first, and then the first general-purpose bus B1 may be selected.

  As described above, in the second embodiment, since the two waveform check circuits 14 and 16 are arranged, it is possible to check the waveform state of the general-purpose bus in more detail.

  The number of waveform check circuits is not limited to two, and may of course be three or more.

Third Embodiment
FIG. 9 is a block diagram showing a configuration of a universal bus control device 1B according to a third embodiment of the present invention.

  The illustrated general-purpose bus control device 1 B includes a bus controller 12, a redriver 13, a waveform check device 14 A, and a device 15.

  That is, from the general-purpose bus control device 1 according to the first embodiment, the general-purpose bus control circuit 1B according to the third embodiment omits the bus control circuit 11 and replaces the waveform check circuit 14 with the waveform check device 14A. Has a configuration. Hereinafter, only differences from the first embodiment will be described.

  The waveform check device 14A incorporates the memory table 111 and includes the waveform check circuit 14, an acquisition unit 113, a comparison unit 115, and a change / setting unit 115.

  By adopting such a configuration, in the third embodiment, the settings of the bus controller 12 and the redriver 13 can be changed directly from the waveform check device 14A.

  As mentioned above, although this invention was demonstrated with reference to embodiment, this invention is not limited to the said embodiment. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  Some or all of the above embodiments may be described as in the following appendices, but is not limited to the following.

(Supplementary Note 1) A method of controlling a general-purpose bus connected to a device,
Checking the waveform of the general-purpose bus;
An acquisition step of acquiring the checked waveform;
A comparison step of comparing the acquired waveform with the optimum waveform stored in advance;
A change / setting step of setting to change an optimal value of a drive circuit for driving the general-purpose bus when the comparison results do not match;
General purpose bus control method including:

(Supplementary note 2) The general-purpose bus control method according to Supplementary note 1, repeating the acquisition step, the comparison step, and the change / setting step until the comparison results match.

(Supplementary Note 3) A general-purpose bus control device that controls a general-purpose bus connected to a device,
A drive circuit for driving the general purpose bus;
A memory table for storing in advance an optimum waveform on the general-purpose bus;
A waveform check circuit that checks the waveform of the general-purpose bus;
Acquisition means for acquiring the checked waveform;
Comparing means for comparing the acquired waveform with the previously stored optimum waveform;
Change / setting means settable to change the optimum value of the drive circuit according to the comparison result;
Universal bus controller comprising:

(Supplementary Note 4) The universal bus control device according to Supplementary Note 3, comprising a control unit having the acquisition means, the comparison means, and the change / setting means.

(Supplementary Note 5) The universal bus control device according to Supplementary Note 3, further comprising: a waveform check device having the waveform check circuit, the acquisition means, the comparison means, and the change / setting means.

(Supplementary Note 6) The universal bus control device according to Supplementary Note 3, comprising a plurality of the waveform check circuits.

(Supplementary note 7) In any one of supplementary notes 3 to 6, the device comprises a drive selected from the group of a hard disk drive (HDD), a solid state drive (SSD), an optical drive, a recording drive, and a peripheral device. Generic bus controller as described.

(Supplementary note 8) Any one of supplementary notes 3 to 7, wherein the general-purpose bus is a serial bus defined by a serial bus interface standard selected from the group of serial advanced technology attachment (SATA) and universal serial bus (USB). Universal bus controller according to

(Supplementary note 9) The universal bus control device according to any one of supplementary notes 3 to 8, wherein the drive circuit includes a bus controller that adjusts the amplitude and strength of the signal waveform of the universal bus.

(Supplementary note 10) The universal bus control according to supplementary note 9, wherein the drive circuit further includes a redriver provided between the device and the bus controller to adjust the amplitude and strength of the signal waveform of the universal bus. apparatus.

(Supplementary note 11) A general-purpose bus control program that causes a computer to control a general-purpose bus connected to a device, the computer including:
An acquisition procedure for acquiring the waveform of the general-purpose bus checked by a waveform check circuit;
A comparison procedure for comparing the acquired waveform with the optimum waveform stored in advance;
A change / setting procedure of setting to change an optimum value of a drive circuit for driving the general-purpose bus when the comparison results do not match;
General purpose bus control program to execute.

(Supplementary note 12) The general-purpose bus control program according to supplementary note 11, causing the computer to repeatedly execute the acquisition procedure, the comparison procedure, and the change / setting procedure until the comparison results match.

  The present invention can be applied to improving the reliability of a computer device in general.

1, 1A, 1B General-purpose bus control device 11 Bus control circuit (CPU / chip set)
110 CPU (control unit)
111 Memory table 113 Acquisition unit 115 Comparison unit 117 Change / setting unit 119 Register 12 Bus controller (driver chip)
13 Redriver (Redriver chip)
14 waveform check circuit 14A waveform check device 15 device 16 waveform check circuit B1, B2 general purpose bus B3 to B6 local bus C1 driver / equalizer C2 receiver / equalizer C3 receiver / equalizer C4 driver C5 receiver / equalizer C6 driver

Claims (10)

A method of controlling a general purpose bus connected to a device, comprising:
Checking the waveform of the general-purpose bus;
An acquisition step of acquiring the checked waveform;
A comparison step of comparing the acquired waveform with the optimum waveform stored in advance;
A change / setting step of setting to change an optimal value of a drive circuit for driving the general-purpose bus when the comparison results do not match;
General purpose bus control method including:   The general-purpose bus control method according to claim 1, wherein the acquisition step, the comparison step, and the change / setting step are repeated until the comparison results match. A general purpose bus control device for controlling a general purpose bus connected to a device,
A drive circuit for driving the general purpose bus;
A memory table for storing in advance an optimum waveform on the general-purpose bus;
A waveform check circuit that checks the waveform of the general-purpose bus;
Acquisition means for acquiring the checked waveform;
Comparing means for comparing the acquired waveform with the previously stored optimum waveform;
Change / setting means settable to change the optimum value of the drive circuit according to the comparison result;
Universal bus controller comprising:   The universal bus control device according to claim 3, further comprising: a control unit having the acquisition unit, the comparison unit, and the change / setting unit.   4. The universal bus control device according to claim 3, further comprising: a waveform check device having the waveform check circuit, the acquisition means, the comparison means, and the change / setting means.   The device according to any one of claims 3 to 5, wherein the device comprises a drive selected from the group of a hard disk drive (HDD), a solid state drive (SSD), an optical drive, a recording drive and a peripheral device. Bus controller.   A bus according to any one of claims 3 to 6, wherein said universal bus comprises a serial bus defined by a serial bus interface standard selected from the group of Serial Advanced Technology Attachment (SATA) and Universal Serial Bus (USB). Universal bus controller.   The universal bus control device according to any one of claims 3 to 7, wherein the drive circuit includes a bus controller that adjusts the amplitude and strength of the signal waveform of the universal bus.   The universal bus control device according to claim 8, wherein the drive circuit further includes a redriver provided between the device and the bus controller to adjust an amplitude and strength of a signal waveform of the universal bus. A general-purpose bus control program that causes a computer to control a general-purpose bus connected to a device, the computer comprising:
An acquisition procedure for acquiring the waveform of the general-purpose bus checked by a waveform check circuit;
A comparison procedure for comparing the acquired waveform with the optimum waveform stored in advance;
A change / setting procedure of setting to change an optimum value of a drive circuit for driving the general-purpose bus when the comparison results do not match;
General purpose bus control program to execute.

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