TW201706846A - Information processing device, method, and program - Google Patents

Abstract

An information processing device in an embodiment of the present invention controls access to the shared memory of n MPUs (n being an integer greater than or equal to 2). A control unit analyzes an access pattern to the shared memory on the basis of requests for access to the shared memory accepted in parallel from the n MPUs in the same access phase, and processes m accepted access requests (m being a natural number less than or equal to n) sequentially in the access phase in an order based on the analyzed access pattern. Therefore, even when there is an increase in the number of master MPUs that perform the delivery of input/output data via the shared memory of intelligent input/output devices, it is possible to deliver data without lowering the effective processing speed of each of the master MPUs.

Description

Information processing device, method and program

Embodiments of the present invention relate to an information processing apparatus, method, and program.

An intelligent input/output device is known, for example, in a system for process control, in which a plurality of main MPUs (micro processing units) pass through shared memory. (shared memory) access.

The smart input/output device includes: one or a plurality of main MPUs, respectively performing processing of input and output data corresponding to the controlled device; and shared memory for inputting and outputting with the main MPU of the upper control device The transfer of data; and the circuit, the main MPU that performs the processing of the input and output data and the main MPU of the upper control device are connected to the shared memory. Japanese Patent Laid-Open Publication No. 2000-20491 (hereinafter referred to as Patent Document 1).

In the above-mentioned smart input/output device, when a plurality of master MPUs access the shared memory at the same time, before one master MPU finishes processing, one or more other master MPUs must wait for access, resulting in access. The processing speed of the actual MPU that is forced to wait for processing is reduced. In particular, if the number of primary MPUs increases, the reduction in the effective processing speed of each primary MPU may become significant.

The present invention has been developed in view of the above circumstances, and an object of the present invention is to provide an information processing apparatus, method, and program that can not even increase the number of primary MPUs for transferring input and output data through a shared memory of a smart input/output device. The processing speed of each master MPU can be reduced to transfer data.

The information processing device according to the embodiment is an information processing device that controls access to shared memory of n (n: 2 or more integers) MPU (micro processing unit).

Moreover, in the same access phase, the control unit analyzes the access mode to the shared memory according to the access request for the shared memory received from the n MPUs in parallel, and in the order based on the analyzed access mode. In the access phase, m (m: n or less natural number) access requests are processed in order.

10‧‧‧Processing Control System

11‧‧‧Upper controller

11A, 23-1~23-n‧‧‧Main MPU

12‧‧‧Smart input and output device

13‧‧‧ face

14‧‧‧Communication network

21‧‧‧ shared memory

22‧‧‧Mediation control circuit

31‧‧‧1st access temporary latch processing unit

32‧‧‧2nd access temporary latch processing unit

33‧‧‧Access Mode Analysis Department

34‧‧‧Address switching processing unit

35‧‧‧Command Output Processing Department

36‧‧‧Data Switching Processing Department

A0‧‧‧1st stage

A1‧‧‧2nd stage

A2‧‧‧3rd stage

DEV1~DEVn‧‧‧ controlled device

T1~T3‧‧‧ phase (access phase)

Fig. 1 is a block diagram showing a schematic configuration of a process control system 10 having an information processing device according to an embodiment.

FIG. 2 is a schematic block diagram showing the upper controller 11 and the smart input/output device 12.

[Fig. 3] Fig. 3 is a timing chart showing a case where the main MPU 11A and the main MPU 23-1 perform data reading processing in the T2 phase with the smart input/output device in the T2 phase.

[Fig. 4] Fig. 4 is a timing chart showing a case where the main input MPU 11A and the main MPU 23-1 perform data writing processing in the T2 phase with the smart input/output device in the T2 phase.

FIG. 5 is an explanatory diagram of an access mode analysis table. FIG.

FIG. 6 is a flowchart showing the processing of the smart input/output device 12.

Next, an embodiment will be described in detail with reference to the drawings.

Fig. 1 is a block diagram showing a schematic configuration of a process control system 10 having an information processing device according to an embodiment.

The processing control system 10 includes: a higher-level controller 11 that performs overall control of the processing control system 10; and a smart input/output device 12 that performs input/output control under the control of the upper controller 11; The input/output interfaces I11 to I1n and the controlled devices DEV1 to DEVn are connected to the interface 13 through the corresponding dielectric surfaces I21 to I2n and the communication network 14.

Here, as the controlled devices DEV1 to DEVn, a sensor unit that senses various states (current, voltage, temperature, flow rate, pressure, etc.) in addition to the controlled device such as a motor or a valve is also included.

In the following description, for the sake of understanding, the case where the smart input/output device 12 includes one main MPU 23-1 will be described as an example. In addition, in the following description, the read address/write address in the shared memory 21 is subscribed to each of the controlled devices DEV1 to DEVn in advance, and the access sequence is also in a cyclic manner. It is specified that for the same controlled device DEV1~DEVn, the read address or the write address will not be repeatedly specified.

FIG. 2 is a schematic block diagram of the upper controller 11 and the smart input/output device 12.

The host controller 11 includes a main MPU 11A that controls the entire upper controller 11 and prepares a pulse-time terminal CLK, a Ready terminal RDY for inputting the first ready signal RDY1, a wafer selection terminal CS, an address terminal ADR, The terminal RD, the write terminal WT, and the data terminal DATA are read.

The smart input/output device 12 includes: a shared memory 21 that memorizes input and output data; and a control unit (hereinafter referred to as a mediation control circuit 22) that adjusts when the main MPU competes for access to the shared memory 21; And the main MPUs 23-1 to 23-n perform control for data input and output with the controlled device DEV1.

The mediation control circuit 22 includes a first access temporary latch processing unit 31 that stores shared memory from the master MPU 11A of the upper controller 11 The access data of the body 21 is temporarily latched; and the second access temporary latch processing unit 32 temporarily latches the access data of the shared memory 21 from the main MPUs 23-1 to 23-n; The access mode analysis unit 33 analyzes the shared memory based on the access data latched in the first access temporary latch processing unit 31 and the access data latched in the second access temporary latch processing unit 32. The access pattern of the body 21; and the address switching processing unit 34 switches the read address or the write address of the shared memory 21 to the first memory based on the analysis result of the access pattern analyzing unit 33. The address data stored in the temporary latch processing unit 31 or the address data stored in the second access temporary latch processing unit 32; and the command output processing unit 35 are output based on the analysis result of the access pattern analyzing unit 33. The write command, the read command, or the wafer select command of the shared memory 21; and the data switching processing unit 36 switches the main MPU of the input object of the data or the main MPU of the output target in accordance with the analysis result of the access mode analysis unit 33.

The main MPU 23-1 includes a clock terminal CLK, a ready (Ready) terminal RDY for inputting the second ready signal RDY2, a wafer selection terminal CS, an address terminal ADR, a read terminal RD, a write terminal WT, and a data terminal DATA.

Next, the operation of the embodiment will be described.

The access mode of the smart input/output device 12 has three consecutive access phases, namely, a T1 phase to a T3 phase.

3 is a case where the main MPU 11A and the main MPU 23-1 perform data reading processing in the T2 phase with the smart input/output device in the T2 phase. Example processing timing diagram.

In addition, FIG. 4 is a processing sequence diagram in which the main MPU 11A and the main MPU 23-1 perform data writing processing in the T2 phase in the smart input/output device.

In the T1 phase to the T3 phase, there are three sub-stages, namely, the first sub-stage A0 to the third sub-stage A2, which are arranged in accordance with the time series. Further, it is designed to analyze the access mode in the first sub-stage A0, and to perform shared memory access processing corresponding to one of the main MPUs in the second sub-stage A1, and to perform the other main MPU in the third sub-stage A2. Corresponding shared memory access processing. Further, in the sub-stage, in addition to at least one sub-stage (one in the present embodiment) for performing the analysis of the access mode, at least one of the main MPUs that can simultaneously access the shared memory 21 is provided. The secondary stage of the number (two in this embodiment).

First, the operation of the access mode analysis unit will be described.

FIG. 5 is an explanatory diagram of an access mode analysis table.

In Figure 5, the situation in which the access mode is analyzed in the T2 phase is disclosed.

As the access mode of the shared memory 21, in the case of the device configuration of Fig. 2, the following nine modes exist.

Here, the access mode analysis unit 33 responds to the state of the wafer selection terminal CS, the read terminal RD, and the write terminal WT of the main MPU 11A and the main MPU 23-1 (positive logic [high active]). Next, the combination of the "H" level shown by "1" in Fig. 3 or the "L" level shown by "0" in Fig. 3 is used to analyze the access pattern.

(1) Access mode No. 1

Both the main MPU 11A and the main MPU 23-1 read data from the shared memory 21.

Specifically, in the stage of analysis (in the T2 stage in the present description, the same applies hereinafter), the access mode analysis unit 33 reads the terminal RD = "L" when the wafer selection terminal CS of the main MPU 11A is "L". When the write terminal WT is "H" and the wafer selection terminal CS of the main MPU 23-1 is "L", the read terminal RD is "L", and the write terminal WT is "H", it is determined that the memory is present. Take mode No.1.

(2) Access mode No. 2

Both the main MPU 11A and the main MPU 23-1 write data to the shared memory 21.

Specifically, in the stage of analyzing, the access mode analysis unit 33 reads the terminal RD = "H" and the write terminal WT = "L" when the wafer selection terminal CS of the main MPU 11A = "L", and The wafer selection terminal CS of the main MPU 23-1 is "L", the read terminal RD is "H", and when the write terminal WT is "L", it is determined to be the access mode No. 2.

(3) Access mode No. 3

The main MPU 11A reads data from the shared memory 21, and the main MPU 23-1 writes data to the shared memory 21.

Specifically, the access mode analysis unit 33 reads out the wafer selection terminal CS of the main MPU 11A = "L" at the stage of analysis. Terminal RD = "L", write terminal WT = "H", and wafer select terminal CS of the main MPU 23-1 = "L", read terminal RD = "H", write terminal WT = "L" In this case, it is determined as access mode No. 3.

(4) Access mode No. 4

The main MPU 11A writes data to the shared memory 21, and the main MPU 23-1 reads data from the shared memory 21.

Specifically, in the stage of analyzing, the access mode analysis unit 33 reads the terminal RD = "H" and the write terminal WT = "L" when the wafer selection terminal CS of the main MPU 11A = "L", and The wafer selection terminal CS of the main MPU 23-1 is "L", the read terminal RD is "L", and when the write terminal WT is "H", it is determined to be the access mode No. 4.

(5) Access mode No. 5

The main MPU 11A reads data from the shared memory 21, and the main MPU 23-1 does not perform anything on the shared memory 21.

Specifically, in the stage of analyzing, the access mode analysis unit 33 reads the terminal RD = "L" and the write terminal WT = "H" when the wafer selection terminal CS of the main MPU 11A is "L", and The wafer selection terminal CS of the main MPU 23-1 is "H", the read terminal RD is "H", and when the write terminal WT is "H", it is determined to be the access mode No. 5.

Further, in the stage of analyzing, the access mode analysis unit 33 reads the terminal RD = "L", the write terminal WT = "H", and the write terminal WT = "H" when the wafer selection terminal CS of the main MPU 11A is "L". MPU23-1 wafer When the terminal CS=“L” is selected, the read terminal RD=“H”, and the write terminal WT=“H”, it is determined to be the access mode No. 5.

(6) Access mode No. 6

The main MPU 23-1 reads data from the shared memory 21, and the main MPU 11A does not perform anything on the shared memory 21.

Specifically, in the stage of analyzing, the access mode analysis unit 33 reads the terminal RD = "H" and the write terminal WT = "H" when the wafer selection terminal CS of the main MPU 11A is "H", and The wafer selection terminal CS of the main MPU 23-1 is "L", the read terminal RD is "L", and when the write terminal WT is "H", it is determined to be the access mode No. 6.

Further, in the stage of analyzing, the access mode analysis unit 33 reads the terminal RD = "H", the write terminal WT = "H", and the write terminal WT = "H" when the wafer selection terminal CS of the main MPU 11A is "L", and the main mode The wafer selection terminal CS of the MPU 23-1 is "L", the read terminal RD is "L", and when the write terminal WT is "H", it is determined to be the access mode No. 6.

(7) Access mode No. 7

The main MPU 11A writes data to the shared memory 21, and the main MPU 23-1 does not perform anything to the shared memory 21.

Specifically, in the stage of analyzing, the access mode analysis unit 33 reads the terminal RD = "H" and the write terminal WT = "L" when the wafer selection terminal CS of the main MPU 11A = "L", and , the chip selection terminal CS=“H” of the main MPU23-1, the readout terminal RD=“H”, the write terminal In the case of WT = "H", it is determined as access mode No. 7.

Further, in the stage of analyzing, the access mode analyzing unit 33 reads the terminal RD = "H", the write terminal WT = "L", and the write terminal WT = "L" when the wafer selection terminal CS of the main MPU 11A is "L", and the main mode The wafer selection terminal CS of the MPU 23-1 is "L", the read terminal RD is "H", and when the write terminal WT is "H", it is determined to be the access mode No. 7.

(8) Access mode No. 8

The main MPU 23-1 writes data to the shared memory 21, and the main MPU 11A does not perform anything to the shared memory 21.

Specifically, in the stage of analyzing, the access mode analysis unit 33 reads the terminal RD = "H" and the write terminal WT = "H" when the wafer selection terminal CS of the main MPU 11A is "H", and The wafer selection terminal CS of the main MPU 23-1 is "L", the read terminal RD is "H", and when the write terminal WT is "L", it is determined to be the access mode No. 8.

Further, in the stage of analyzing, the access mode analysis unit 33 reads the terminal RD = "H", the write terminal WT = "H", and the write terminal WT = "H" when the wafer selection terminal CS of the main MPU 11A is "L", and the main mode The wafer selection terminal CS of the MPU 23-1 is "L", the read terminal RD is "H", and when the write terminal WT is "L", it is determined to be the access mode No. 8.

(9) Access mode No. 9

Both the main MPU 23-1 and the main MPU 11A do not perform anything on the shared memory 21.

Specifically, in the stage of analyzing, the access mode analysis unit 33 reads the terminal RD = "H" and the write terminal WT = "H" when the wafer selection terminal CS of the main MPU 11A is "H", and The wafer selection terminal CS of the main MPU 23-1 is "H", the read terminal RD is "H", and when the write terminal WT is "H", it is determined to be the access mode No. 9.

Further, in the stage of analyzing, the access mode analysis unit 33 reads the terminal RD = "H", the write terminal WT = "H", and the write terminal WT = "H" when the wafer selection terminal CS of the main MPU 11A is "L", and the main mode The wafer selection terminal CS of the MPU 23-1 is "L", the read terminal RD is "H", and when the write terminal WT is "H", it is determined to be the access mode No. 9.

FIG. 6 is a process flow diagram of the smart input/output device 12. In FIG. 6, for simplicity of illustration, the main MPU 11A is referred to as "MPU1", and the main MPU 23-1 is referred to as "MPU2".

First, the first access temporary latch processing unit 31 of the mediation control circuit 22 outputs the address from the address terminal ADR of the main MPU 11A in the first sub-stage A0 (indicated by T2_A0 in FIG. 4) in the T2 phase. The data and the data written from the data terminal DATA are latched.

On the other hand, the second access temporary latch processing unit 32 of the mediation control circuit 22 latches the address data output from the address terminal ADR of the main MPU 23-1 and the write data output from the data terminal DATA ( Step S11).

Next, the access pattern analysis unit 33 analyzes the access mode based on the combination of the state of each of the wafer selection terminal CS, the read terminal RD, and the write terminal WT of the main MPU 11A and the main MPU 23-1 (step S12).

Next, the access mode analysis unit 33 determines whether or not the analyzed access mode is the access mode No. 1 in the case where both the main MPU 11A and the main MPU 23-1 read data from the shared memory 21 ( Step S13).

In the determination of step S13, when the analyzed access mode is the access mode No. 1 (step S13; Yes), the access mode analyzing unit 33, in the second sub-stage A1 of the T2 phase (in FIG. 4) In the case of T2_A1, the control address switching processing unit 34 switches the address bus bar to the main MPU 11A side (step S14).

In this manner, the access mode analysis unit 33 issues (outputs) the shared memory read command corresponding to the main MPU 11A as the shared memory command output process (step S15). As a result, the first access temporary latch processing unit 31 reads and reads the data corresponding to the address from the shared memory 21 and latches it (step S16).

Next, in the third sub-stage A2 (indicated by T2_A2 in FIG. 4) of the T2 stage, the access mode analysis unit 33 controls the address switching processing unit 34 to switch the address bus to the main MPU23-1 side ( Step S17).

In this manner, the access mode analysis unit 33 issues (outputs) the shared memory read command corresponding to the main MPU 23-1 as the shared memory command output process (step S18). As a result, the second access temporary latch processing unit 32 reads and reads the data corresponding to the address from the shared memory 21 and latches it (step S19).

Then, the main MPU 11A reads the data to be read from the first access temporary latch processing unit 31, and the main MPU 23-1 reads the data to be read from the second access temporary latch processing unit 32, and ends the T2 phase. Processing in (step S20).

Here, the case of the access mode No. 1 will be described as an example, and the material reading process will be described in detail with reference to FIG. 3.

The mediation control circuit 22 sets the first ready signal RDY1 to the "H" level across the T1 phase to the T3 phase as shown in FIG. 3 to permit access to the shared memory 21 for the master MPU 11A. Similarly, the mediation control circuit 22 sets the second ready signal RDY2 to the "H" level across the T1 phase to the T3 phase as shown in FIG. 3 to permit access to the shared memory 21 for the master MPU 23-1. .

In this way, the master MPU 11A understands that the access to the shared memory 21 by the master MPU 11A is currently permitted according to the first ready signal RDY1, and is output from the address terminal ADR across the T1 phase to the T3 phase as shown in FIG. The read address 110 of the shared memory.

Next, the main MPU 11A sets the read signal R to the "L" level during the period of the T2 phase to notify the mediation control circuit 22 that the read preparation has been completed.

On the other hand, the main MPU 23-1, based on the second ready signal RDY2, understands that the access to the shared memory 21 is currently permitted for the primary MPU 23-1, as shown in FIG. 3, spanning from the T1 phase to the T3 phase. The address terminal ADR outputs the read address 210 of the shared memory.

Next, the main MPU23-1 will read during the T2 phase. The signal R is set to the "L" level to notify the mediation control circuit 22 that the readout preparation has been completed.

On the other hand, the first access temporary latch processing unit 31 of the mediation control circuit 22 outputs the address from the address terminal ADR of the main MPU 11A in the first sub-stage A0 (indicated by T2_A0 in FIG. 6) in the T2 phase. The address data 110 is latched. Further, the second access temporary latch processing unit 32 of the mediation control circuit 22 latches the address data 210 output from the address terminal ADR of the main MPU 23-1.

Next, the access mode analysis unit 33 analyzes the access mode based on the combination of the state of each of the wafer selection terminal CS, the read terminal RD, and the write terminal WT of the main MPU 11A and the main MPU 23-1.

Next, the access pattern analysis unit 33 reads out the respective wafer selection terminals CS of the main MPU 11A and the main MPU 23-1 in the T2 stage, the "L" level, and the read terminal RD. Since the signal R is at the "L" level, it is determined that both the main MPU 11A and the main MPU 23-1 read the data from the shared memory 21, that is, the access mode No. 1.

Then, the access mode analysis unit 33 controls the address switching processing unit 34 to switch the address bus and the data bus to the main MPU 11A side in the second sub-stage A1 (indicated by T2_A1 in FIG. 6) in the T2 phase. .

In this manner, the access mode analysis unit 33 issues (outputs) the shared memory read command corresponding to the main MPU 11A as the shared memory command output process (step S15). As a result, the first access The temporary latch processing unit 31 reads out and latches and reads the read data 112 corresponding to the address 111 from the shared memory 21, and outputs the read data 112 to the data bus.

As a result, in the data bus of the main MPU 11A, the read latch data 113 is outputted in the second sub-stage A1 to the third sub-stage A2 (indicated by T2_A1 to T2_A2 in FIG. 6) in the T2 stage.

In this case, the data reading time point 114 of the main MPU 11A, that is, the end time of the T2 phase, is longer than the period of the predetermined data reading/setting time DRS (Data Read/Setup). The data bus of the main MPU 11A continuously outputs the read latch data 113. In this way, the main MPU 11A can surely capture the read latch data 113.

Further, in the third sub-stage A2 (indicated by T2_A2 in FIG. 6) of the T2 stage, the access mode analysis unit 33 controls the address switching processing unit 34 to switch the address bus and the data bus to the main MPU 23- 1 side.

In this manner, the access mode analyzing unit 33 issues (outputs) the shared memory read command corresponding to the main MPU 23-1 as the shared memory command output process. As a result, the second access temporary latch processing unit 32 reads out and reads and reads the read data 212 corresponding to the address 211 from the shared memory 21, and outputs the read data 212 to the data bus.

As a result, in the data bus of the main MPU23-1, in the third sub-stage A2 of the T2 stage (in the figure T2_A1~T2_A2 in Figure 6) In the display, the read latch data 213 is output.

In this case as well, the data read time point 214 of the main MPU 23-1, that is, the end time of the T2 phase, is longer than the predetermined data read/build time DRS (Data Read Setup). During this period, the data bus in the main MPU 23-1 continues to output the read latch data 213. In this way, the main MPU 23-1 can surely capture the read latch data 213.

Here again, return to the description of FIG. 6.

In the determination of step S13, when the analyzed access mode is not the access mode No. 1 (step S13; No), the access mode analyzing unit 33 determines whether the analyzed access mode is the main MPU 11A or not. In the case where both of the main MPUs 23-1 write data to the shared memory 21, that is, access mode No. 2 (step S21).

In the determination of step S21, when the analyzed access mode is the access mode No. 2 (step S21; Yes), the access mode analyzing unit 33, in the second sub-stage A1 of the T2 phase, the control bit The address switching processing unit 34 switches the address bus and the data bus to the main MPU 11A side (step S22).

In this way, the access mode analysis unit 33 issues (outputs) the shared memory write command corresponding to the main MPU 11A to the shared memory 21 as the shared memory command output process (step S23).

As a result, the first access temporary latch processing unit 31 writes the data of the main MPU 11A to the area of the shared memory 21 corresponding to the write address (step S24).

Next, the access mode analysis unit 33 controls the address switching processing unit 34 to switch the address bus and the data bus to the main MPU 23-12 side in the third sub-stage A2 of the T2 stage (step S25).

Then, the access mode analysis unit 33 issues (outputs) the shared memory write command corresponding to the main MPU 23-1 to the shared memory 21 as the shared memory command output process (step S26).

As a result, the second access temporary latch processing unit 32 writes the data of the main MPU 23-1 to the area of the shared memory 21 corresponding to the write address (step S27).

Here, the case where the access mode No. 2 is taken as an example, the data writing process will be described in detail with reference to FIG.

The mediation control circuit 22 sets the first ready signal RDY1 to the "H" level across the T1 phase to the T3 phase as shown in FIG. 4 to permit access to the shared memory 21 for the master MPU 11A. Similarly, the mediation control circuit 22 sets the second ready signal RDY2 to the "H" level across the T1 phase to the T3 phase as shown in FIG. 4 to permit access to the shared memory 21 for the master MPU 23-1. .

In this way, the master MPU 11A understands that the access to the shared memory 21 by the master MPU 11A is currently permitted according to the first ready signal RDY1, and is output from the address terminal ADR across the T1 phase to the T3 phase as shown in FIG. The write address of the shared memory is 120.

Next, the main MPU 11A sets the write signal W to the "L" level during the period of the T2 phase to notify the mediation control circuit 22 that the write preparation has been completed.

On the other hand, the master MPU 23-1 understands that the access to the shared memory 21 by the master MPU 23-1 is currently permitted according to the second ready signal RDY2, as shown in FIG. 4, spanning from the T1 phase to the T3 phase. The address terminal ADR outputs the write address 220 of the shared memory.

Next, the main MPU 23-1 sets the write signal W to the "L" level during the period of the T2 phase to notify the mediation control circuit 22 that the write preparation has been completed. On the other hand, the first access temporary latch processing unit 31 of the mediation control circuit 22 outputs the address from the address terminal ADR of the main MPU 11A in the first sub-stage A0 (indicated by T2_A0 in FIG. 6) in the T2 phase. The address data 120 is latched. Further, the second access temporary latch processing unit 32 of the mediation control circuit 22 latches the address data 220 output from the address terminal ADR of the main MPU 23-1.

Next, the access mode analysis unit 33 analyzes the access mode based on the combination of the state of each of the wafer selection terminal CS, the read terminal RD, and the write terminal WT of the main MPU 11A and the main MPU 23-1.

Next, the access mode analysis unit 33 writes the respective chip selection terminals CS of the main MPU 11A and the main MPU 23-1 in the T2 stage to the "L" level and writes the write terminal WT. Since the signal W is at the "L" level, it is determined that both the main MPU 11A and the main MPU 23-1 write data from the shared memory 21, that is, the access mode No. 2.

Then, the access mode analysis unit 33 controls the address switching processing unit 34 to switch the address bus and the data bus to the main MPU 11A in the second sub-stage A1 (indicated by T2_A1 in FIG. 6) in the T2 phase. side.

In this manner, the access mode analyzing unit 33 issues (outputs) a shared memory write command corresponding to the main MPU 11A as a shared memory command output process. The first access temporary latch processing unit 31 outputs the write address 120 and the corresponding write data 122 to the shared memory 21 as the write address 121 and the write data 123.

Along with this, the write signal W of the shared memory 21 becomes the "L" level, and in the second sub-stage A1 of the T2 stage (indicated by T2_A1 in FIG. 6), the write data 123 is written and written. The area corresponding to address 121.

Then, the access mode analysis unit 33 controls the address switching processing unit 34 to switch the address bus and the data bus to the main MPU 23 in the third sub-stage A2 (indicated by T2_A2 in FIG. 6) in the T2 phase. 1 side.

In this manner, the access mode analyzing unit 33 issues (outputs) a shared memory write command corresponding to the main MPU 23-1 as a shared memory command output process. The second access temporary latch processing unit 32 outputs the write address 220 and the corresponding write data 222 to the shared memory 21 as the write address 221 and the write data 223.

Along with this, the write signal W of the shared memory 21 becomes the "L" level, and in the third sub-stage A2 of the T2 stage (indicated by T2_A2 in FIG. 6), the write data 223 is written and written. The area corresponding to address 221.

Here again, return to the description of FIG. 6.

In the determination of step S21, when the analyzed access mode is not the access mode No. 2 (step S21; No), the access mode analyzing unit 33 determines whether or not the analyzed access mode is the master MPU 11A. The shared memory 21 reads the data, and the main MPU 23-1 writes the data to the shared memory 21, that is, the access mode No. 3 (step S31).

In the determination of step S31, when the analyzed access mode is the access mode No. 3 (step S31; Yes), the access mode analyzing unit 33, in the second sub-stage A1 of the T2 phase, the control bit The address switching processing unit 34 switches the address bus and the data bus to the main MPU 11A side (step S32).

In this manner, the access mode analysis unit 33 issues (outputs) the shared memory read command corresponding to the main MPU 11A as the shared memory command output process (step S33). As a result, the first access temporary latch processing unit 31 reads and reads the data corresponding to the address from the shared memory 21 and latches it (step S34).

Next, the access mode analysis unit 33 controls the address switching processing unit 34 to switch the address bus and the data bus to the second access on the main MPU 23-1 side in the third sub-stage A2 of the T2 phase. The processing unit 32 is temporarily latched (step S35).

Then, the access mode analysis unit 33 issues (outputs) the shared memory write command corresponding to the main MPU 23-1 to the shared memory 21 as the shared memory command output process (step S36).

As a result, the second access temporary latch processing unit 32 writes the data of the main MPU 23-1 to the area corresponding to the write address of the shared memory 21 and the write address. (Step S37).

Then, the main MPU 11A reads the data to be read from the first access temporary latch processing unit 31, and ends the processing in the T2 phase (step S38).

In the determination of step S31, when the analyzed access mode is not the access mode No. 3 (step S31; No), the access mode analyzing unit 33 determines whether or not the analyzed access mode is the master MPU 11A pair. The shared memory 21 writes data, and the main MPU 23-1 reads the data from the shared memory 21, that is, the access mode No. 4 (step S41).

In the determination of step S41, when the analyzed access mode is the access mode No. 4 (step S41; Yes), the access mode analyzing unit 33, in the second sub-stage A1 of the T2 phase, the control bit The address switching processing unit 34 switches the address bus and the data bus to the main MPU 23-1 side (step S42).

In this way, the access mode analyzing unit 33 issues (outputs) the shared memory read command corresponding to the main MPU 23-1 as the shared memory command output process (step S43).

As a result, the second access temporary latch processing unit 32 reads and reads the data corresponding to the address from the shared memory 21 and latches it (step S44).

Next, the access mode analysis unit 33 controls the address switching processing unit 34 to switch the address bus and the data bus to the first access temporary lock on the main MPU 11A side in the third sub-stage A2 of the T2 phase. Deposit The control unit 31 (step S45).

Then, the access mode analysis unit 33 issues (outputs) the shared memory write command corresponding to the main MPU 11A to the shared memory 21 as the shared memory command output process (step S46).

As a result, the first access temporary latch processing unit 31 writes the data of the main MPU 11A to the area of the shared memory 21 corresponding to the write address (step S47).

Then, the main MPU 11A reads the data to be read from the second access temporary latch processing unit 32, and ends the processing in the T2 phase (step S48).

In the determination of step S41, when the analyzed access mode is not the access mode No. 4 (step S41; No), the access mode analyzing unit 33 determines whether or not the analyzed access mode is the master MPU 11A. The shared memory 21 reads the data, and the main MPU 23-1 does not perform any operation on the shared memory 21, that is, the access mode No. 5 (step S51).

In the determination of step S51, when the analyzed access mode is the access mode No. 5 (step S51; Yes), the access mode analyzing unit 33, in the second sub-stage A1 of the T2 phase, the control bit The address switching processing unit 34 switches the address bus and the data bus to the main MPU 11A side (step S52).

In this way, the access mode analysis unit 33 issues (outputs) the shared memory read command corresponding to the main MPU 11A as the shared memory command output process (step S53).

As a result, the first access temporary latch processing unit 31 reads and reads the data corresponding to the address from the shared memory 21 and latches it (step S54).

Then, the main MPU 11A reads the data to be read from the first access temporary latch processing unit 31, and ends the processing in the T2 phase (step S55).

In the determination of step S51, when the analyzed access mode is not the access mode No. 5 (step S51; No), the access mode analyzing unit 33 determines whether or not the analyzed access mode is the main MPU 23- (1) The data is read from the shared memory 21, and the main MPU 11A does not perform any operation on the shared memory 21, that is, access mode No. 6 (step S61).

In the determination of step S61, when the analyzed access mode is the access mode No. 6 (step S61; Yes), the access mode analyzing unit 33, in the second sub-stage A1 of the T2 phase, the control bit The address switching processing unit 34 switches the address bus and the data bus to the main MPU 23-1 side (step S62).

In this manner, the access mode analyzing unit 33 issues (outputs) the shared memory read command corresponding to the main MPU 23-1 as the shared memory command output process (step S63).

As a result, the second access temporary latch processing unit 32 reads and reads the data corresponding to the address from the shared memory 21 and latches it (step S64).

Next, the main MPU 23-1 temporarily latches the processing from the second access. The unit 32 reads the data to be read and ends the processing in the T2 phase (step S65).

In the determination of step S61, when the analyzed access mode is not the access mode No. 6 (step S61; No), the access mode analyzing unit 33 determines whether or not the analyzed access mode is the master MPU 11A pair. The shared memory 21 writes data, and the main MPU 23-1 does not perform any operation on the shared memory 21, that is, access mode No. 7 (step S71).

In the determination of step S71, when the analyzed access mode is the access mode No. 7 (step S71; Yes), the access mode analyzing unit 33, in the second sub-stage A1 of the T2 phase, the control bit The address switching processing unit 34 switches the address bus and the data bus to the main MPU 11A side (step S72).

In this way, the access mode analysis unit 33 issues (outputs) the shared memory write command corresponding to the main MPU 11A to the shared memory 21 as the shared memory command output process (step S73).

As a result, the first access temporary latch processing unit 31 writes the data of the main MPU 11A to the area corresponding to the write address of the shared memory 21, and ends the processing in the T2 stage (step S74).

In the determination of step S71, when the analyzed access mode is not the access mode No. 7 (step S71; No), the access mode analyzing unit 33 determines whether or not the analyzed access mode is the main MPU 23- 1 data is written to the shared memory 21, and the main MPU 11A does not perform anything on the shared memory 21, that is, access mode No. 8 (step S81).

In the determination of step S81, when the analyzed access mode is the access mode No. 8 (step S81; Yes), the access mode analyzing unit 33, in the second sub-stage A1 of the T2 phase, the control bit The address switching processing unit 34 switches the address bus and the data bus to the main MPU 23-1 side (step S82).

In this manner, the access mode analysis unit 33 issues (outputs) the shared memory write command corresponding to the main MPU 23-1 to the shared memory 21 as the shared memory command output process (step S83).

As a result, the second access temporary latch processing unit 32 writes the data of the main MPU 23-1 to the area corresponding to the write address of the shared memory 21, and ends the processing in the T2 stage (step S84).

In the determination of step S81, when the analyzed access mode is not the access mode No. 8 (step S81; No), the access mode analyzing unit 33 determines that the analyzed access mode is the main MPU23- 1 and both of the main MPUs 11A do not perform any operation on the shared memory 21, that is, access mode No. 9, and do nothing, and the processing in the T2 phase is terminated (step S91).

As described above, according to the present embodiment, in the same access phase (T1 to T3 phase), a plurality of master MPUs are equivalently accessed simultaneously to the shared memory 21, and a plurality of master MPUs are not forced to stand by. So that it will not lead to a reduction in the effective processing speed.

The program executed in the information processing apparatus of the present embodiment records the CD in an archive form in an installable form or in an executable form. A ROM, a floppy disk (FD), a CD-R, a DVD (Digital Versatile Disk), or the like can be provided by a recording medium read by a computer.

Further, the program executed in the information processing apparatus of the present embodiment may be stored in a computer connected to a network such as the Internet, and provided by downloading it via the Internet. Further, the program executed in the information processing device of the present embodiment may be configured to be provided or distributed via a network such as the Internet.

Further, the program of the information processing device of the present embodiment may be configured to be incorporated in a ROM or the like in advance.

The embodiments of the present invention have been described above, but are not intended to limit the scope of the invention. The present invention may be embodied in various other forms, and various omissions, substitutions and changes can be made without departing from the scope of the invention. The invention and its modifications are intended to be included within the scope of the invention and the scope of the invention.

10‧‧‧Processing Control System

11‧‧‧Upper controller

11A, 23-1~23-n‧‧‧Main MPU

12‧‧‧Smart input and output device

13‧‧‧ face

14‧‧‧Communication network

21‧‧‧ shared memory

22‧‧‧Mediation control circuit

DEV1~DEVn‧‧‧ controlled device

I11~I1n‧‧‧Import interface

I21~I2n‧‧‧ (corresponding to the controlled devices DEV1~DEVn)

Claims (7)

An information processing device is an information processing device that controls access to shared memory of n (n: 2 or more integers) MPU (micro processing unit), and includes a control unit at the same access stage. And analyzing an access mode to the shared memory according to an access request for the shared memory received from the n MPUs in parallel, and in the order of the access mode based on the analysis, in the access phase The m (m:n or less natural number) access requests accepted as described above are processed in order. The information processing device according to claim 1, wherein the control unit includes: a plurality of latch processing units that store the access request from the MPU and data corresponding to the access request; And the access mode analysis unit analyzes an access mode of the plurality of MPUs to the shared memory based on an access request for the shared memory received from the n MPUs in parallel; and an instruction output processing unit according to the foregoing As a result of the analysis of the access mode, an output of the access command is output to the shared memory. The information processing device according to claim 2, wherein the control unit includes: an address switching processing unit that performs processing with the n MPUs based on an analysis result of the access mode An MPU access And obtaining the corresponding address data and outputting to the shared memory; and the data switching processing unit is configured to correspond to an access request of any MPU that is the processing target among the n MPUs according to the analysis result of the access mode The data is written to the shared memory, or the read data corresponding to the access request of any MPU that is the processing target among the n MPUs is read from the shared memory. The information processing device according to any one of claims 1 to 3, wherein the access stage includes at least (n+1) sub-stages, and the control unit is in the access stage. The initial sub-stage analyzes the access patterns and processes the m access requests sequentially in the remaining n sub-stages. The information processing device according to any one of the preceding claims, wherein at least one of the n MPUs is an MPU constituting a higher-level controller, and among the n MPUs, The MPUs other than the MPU of the host controller are configured to control the MPU of the corresponding controlled device under the control of the upper controller. A method for controlling an information processing device for controlling access to shared memory of n (n: 2 or more integers) MPUs, comprising: simultaneously accepting from the n MPUs in parallel in the same access phase The process of sharing access requirements for memory; and And analyzing, according to the foregoing access requirement, a process of accessing the shared memory; and processing, in the order of the access mode according to the foregoing, the m received in the access phase (m:n The following natural number) process of access requirements. A program for controlling an information processing device for accessing shared memory of n (n: 2 or more integers) MPUs by a computer, so that the computer functions as: in the same access phase, Means for concurrently accepting access requests for the shared memory from the n MPUs; and means for analyzing an access mode to the shared memory according to the access request; and using an access mode based on the analysis In the order, the means for accepting m (m: n or less natural number) access requests are sequentially processed in the access phase.