TW201503158A - Data storage device and FLASH memory control method - Google Patents

Abstract

An overclocking method for a data storage device which includes a FLASH memory. A controller, coupled to the FLASH memory, tests the FLASH memory by test clocks of several frequencies, to determine at least one proper clock for the FLASH memory and thereby the FLASH memory is operated according to the at least one proper clock. In an exemplary embodiment, multiple clocks are regarded proper. The proper clocks may be of different frequencies. The FLASH memory may be switched between the proper clocks to disperse the EMI into different frequency bands.

Description

Data storage device and flash memory control method

The present invention relates to a data storage device implemented by flash memory, and to a method for controlling a flash memory.

Today's data storage devices often use FLASH memory as a storage medium, which is often used as a memory card, a USB flash device, a solid state drive (SSD), and the like. Another application is to package a multi-chip package and package the flash memory chip with the control chip - called the embedded flash memory module (eMMC).

Flash memory is not only widely used, but its capacity has also increased significantly with the development of process technology. However, the process yield of such a large-capacity flash memory is not necessarily ideal. Undesirable flash memory, the general manufacturer is defaulted to operate with a low clock.

The invention discloses a data storage device implemented by flash memory, and discloses a control method of a flash memory, wherein an overclocking design is provided.

A data storage device implemented in accordance with an embodiment of the present invention includes a flash memory and a controller coupled to the flash memory. The The controller tests the flash memory with test clock signals of various frequencies to determine a clock signal suitable for the flash memory, so that the flash memory operates according to the applicable clock signal.

A flash memory control method implemented according to an embodiment of the present invention includes the steps of: testing a flash memory with a test clock signal of a plurality of frequencies; and authenticating the flash memory according to the test clock signals of the plurality of frequencies The result of the test performed by the body determines the clock signal to which the flash memory is applied; and causes the flash memory to operate in accordance with the applicable clock signal.

One embodiment determines that a plurality of clock candidates are clock signals to which the flash memory is applied. The clock candidate frequencies may be different. The flash memory can switch operations among the clock candidates such that the electromagnetic interference effect is dispersed into a plurality of frequency bands.

The present invention will be described in detail below with reference to the accompanying drawings.

100‧‧‧ data storage device

102‧‧‧Flash memory

104‧‧‧ Controller

106‧‧‧Host

BLK1, BLK2‧‧‧ blocks

S202...S224, S302...S320, S402...S406‧‧‧ steps

1 is a data storage device 100 implemented in accordance with an embodiment of the present invention; FIG. 2 is a flowchart illustrating an overclocking test of a flash memory according to an embodiment of the present invention; and FIG. 3 is a diagram illustrating fast in different modes. Flash memory frequency conversion operation; FIG. 4 is a flow chart illustrating how the "overclocking test" and "frequency conversion operation" described above are arranged in the operation of the flash memory 102 in accordance with an embodiment of the present invention.

The following description sets forth various embodiments of the invention. The following description sets forth the basic concepts of the invention and is not intended to limit the invention. The scope of the actual invention shall be defined in accordance with the scope of the patent application.

1 is a data storage device 100 implemented in accordance with an embodiment of the present invention, including a flash memory 102 and a controller 104 coupled to the flash memory 102. The controller 104 can operate the flash memory 102 in response to a request from the host 106. As shown in the embodiment, the storage space of the flash memory 102 is divided into a plurality of blocks BLK1, BLK2, etc. Each block includes a plurality of pages. The space of a block needs to be erased together to release it for use as an idle block. The write operation of the flash memory 102 is generally more complicated than the read operation and is a major factor in determining the operating clock.

In addition to being responsible for processing data transfers between the host 106 and the flash memory 102, the controller 104 can also overclock the flash memory 102. When the overclocking test is successful, the controller 104 can control the flash memory 102 to operate with a specific clock signal having a frequency higher than the frequency of the highest clock signal supported by the flash memory 102. For example, the manufacturer sets the highest frequency clock (for example, 300 MHz) that the flash memory 102 specifies to support when the flash memory 102 is shipped. The controller 104 of the present invention can perform an overclocking test on the flash memory 102. When the overclocking test is successful, the controller 104 can control the flash memory 102 to operate at a particular clock signal (e.g., 333 MHz) above the highest frequency clock. In one embodiment, the controller 104 tests the flash memory 102 with test clock signals of various frequencies to determine a clock signal to which the flash memory 102 is applied, so that the flash memory 102 is based on the flash memory 102. Applicable Clock signal operation.

In an embodiment, the controller 104 can couple the flash memory 102 through a data transmission line. When the controller 104 tests the flash memory 102 with one of the plurality of test clock signals described above, the flash memory 102 can respond to a response signal on the data transmission line. The controller 104 can determine, according to the response signal, whether the clock signal is a clock signal to which the flash memory 102 is applied. In one embodiment, the controller 104 can determine the flash memory 102 from the test clock signals by adjusting a sampling time point of reading the response signal corresponding to each test clock signal. Applicable clock signal. For example, the sampling time point is advanced or delayed, so that the controller 104 reads the correct response signal or the bit error rate of the response signal is lower than a specific value. When the controller 104 can read the response signal with the correct or bit error rate lower than the specific value, it is determined that the test clock signal corresponding to the response signal passes the overclocking test. In one embodiment, the controller 104 begins overclocking the flash memory 102 with the clock signal having the highest frequency among the test clock signals. When the highest frequency clock signal cannot pass the overclocking test, the controller 104 may start overclocking the flash memory 102 by using the clock signal having the second highest frequency among the test clock signals, and thereby analogy. That is, the controller 104 can be gradually down-converted from the highest frequency test clock signal to test the flash memory 102.

The drive of the data transfer line between the controller 104 and the flash memory 102 is based on a set of drive parameters. In addition to adjusting the sampling time point of the response signal, in the above overclocking test, the driving parameters of the data transmission line between the controller 104 and the flash memory 102 can also be adjusted. In one embodiment, the controller 104 further adjusts (eg, boosts or reduces) the set of drive parameters such that the data is transmitted via the above data. The response signal of the line response is correctly captured by the controller 104. In another embodiment, the controller 104 operates at a single data rate (SDR) by switching the flash memory 102 such that the response signal responsive to the data transmission line is correctly captured by the controller 104.

Figure 2 is a flow chart illustrating an overclocking test of a flash memory in accordance with an embodiment of the present invention. Step S202 is responsible for initializing the driving parameters of the data transmission line between the controller 104 and the flash memory 102. Step S204 is responsible for initializing the clock signal to the highest frequency. Step S206 is responsible for initializing the sampling time point of the clock signal. Step S208 is responsible for determining whether the flash memory 102 operates correctly under such a clock signal; for example, writing test data and reading it correctly. In one embodiment, the test data can be a set of test data pre-stored in the controller 104. If the test is passed, the flow proceeds to step S210 to determine the clock signal to which the flash memory 102 is applied.

If it is determined in step S208 that the flash memory 102 is not functioning properly, the flow proceeds to step S212, and it is determined whether the test clock signal of the current frequency has been tested at all sampling time points. In one embodiment, there are 32 sampling time points for testing. If there are still other sampling time points to be tested, the flow proceeds to step S214, the sampling time point is changed, and then step S208 is performed again.

If the step S212 determines that the current frequency clock signal has no other sampling time points to be tested, the flow proceeds to step S216 to determine whether the clock signal is the lowest frequency. If there is still a lower frequency clock signal to be tested, the flow proceeds to step S218, downclocking the clock signal, and then proceeds to step S206.

If all the testable frequencies have been tested, the process proceeds to step S220 to determine whether there is an unused data transmission line drive parameter setting. If Yes, the flow proceeds to step S222, adjusting or using other drive parameter settings, and then proceeds to step S204.

If all of the testable drive parameter settings are not applicable, the process proceeds to step S224, and the flash memory 102 is switched from double data rate (DDR) to single data rate (SDR) operation, and then step S202 is performed again. .

With the procedure shown in Fig. 2, the frequency of the clock signal to which the flash memory 102 is applied and the sampling time point can be determined. In addition, if there is a need to adjust the data transmission line driving parameters or switch the flash memory 102 to the SDR mode, it can also be achieved by the program shown in FIG. 2, and the flash memory 102 is correctly operated in accordance with the most suitable clock signal. .

In some embodiments, the clock signals to which different operations of the flash memory 102 are applied may be obtained separately for overclocking testing.

In one embodiment, the controller 104 may determine, by using the test clock signals, a plurality of clock candidates as clock signals applicable to the flash memory 102, and the flash memory 102 is tied to the clock candidates. Medium frequency operation. For example, after determining a maximum frequency clock (hereinafter referred to as CLK_Max) in which the flash memory 102 is properly operated, the controller 104 will down-clock to find a high-frequency clock in which the flash memory 102 is properly operated (below) Call it CLK_Alt). The highest frequency clock CLK_Max and the secondary high frequency clock CLK_Alt can be used as clock candidates for the flash memory 102. The flash memory 102 switches operations in the clock candidates (the highest frequency clock CLK_Max and the secondary high frequency clock CLK_Alt). Such variable frequency operation can spread electromagnetic interference (EMI) effects into multiple frequency bands. In particular, the number of clock candidates is not limited to two, and is not limited to the above-mentioned highest frequency clock CLK_Max and the second high frequency clock CLK_Alt; the user can design according to the needs.

The frequency conversion operation of the clock signal can have multiple modes. Figure 3 illustrates the flash memory conversion operation in different modes.

If it is determined in step S302 that the flash memory 102 is operating in mode 1, the program proceeds to step S304, and the controller 104 sends an instruction to the flash memory 102 to perform the step S306 to switch the flash memory 102. Pulse signal. For example, corresponding to the first command issued by the controller 104, the flash memory 102 is operated with the highest frequency clock CLK_Max; corresponding to the second command issued by the controller 104, the flash memory 102 is connected to the sub-high frequency clock. CLK_Alt operation; corresponding to the third command issued by the controller 104, the flash memory 102 operates with the highest frequency clock CLK_Max... and so on.

If it is determined in step S302 that the flash memory 102 is operating in mode 2, the program proceeds to step S308, where it is determined that the controller 104 issues the command type. If it is a read command, the flow proceeds to step S310 to cause the flash memory 102 to operate at the highest frequency clock CLK_Max. If it is a write command, the flow proceeds to step S312, and it is further determined whether the previous command is also a write command. If it is determined that the write command occurs continuously, the process proceeds to step S314, and the clock signal is converted to switch between the highest frequency clock CLK_Max and the second high frequency clock CLK_Alt when the flash memory 102 performs the write operation. action. Since the write operation of the flash memory 102 is time consuming compared to the read operation, such a frequency conversion operation can effectively prevent electromagnetic interference (EMI) effects from being concentrated in a specific frequency band. In an embodiment, if it is determined that the write command occurs discontinuously, the flow proceeds to step S315 to cause the flash memory 102 to operate with a fixed clock signal. In one embodiment, the fixed clock signal is the secondary high frequency clock CLK_Alt. Still other embodiments are such that the flash memory 102 is fixedly down-converted when writing data to a clock operation that is lower than the secondary high-frequency clock CLK_Alt.

If it is determined in step S302 that the flash memory 102 is operating in mode 3, the program proceeds to step S316 to determine the type of data requested and read by the controller 104. If it is sequential read/sequential write, the program proceeds to step S318 to control the flash memory 102 to use the above-mentioned highest frequency clock CLK_Max. If it is a random read/random write, the program proceeds to step S320 to cause the flash memory 102 to down-convert the high-frequency clock CLK_Alt. Since the reading and writing of the discrete data of the flash memory 102 is more complicated than the sequential reading and writing, the frequency conversion design can effectively prevent the electromagnetic interference (EMI) effect from being concentrated in a specific frequency band. In other embodiments, the flash memory 102 switches between the highest frequency clock CLK_Max and the secondary high frequency clock CLK_Alt during reading and writing of discrete data, and the electromagnetic interference is dispersed.

4 is a flow chart illustrating how the "overclocking test" and "frequency conversion operation" described above are arranged in the operation of the flash memory 102 in accordance with an embodiment of the present invention. After the flash memory 102 is powered on, the step S402 is responsible for initializing the flash memory 102; the clock parameter set by the vendor normal state is written into the associated register in the flash memory 102, so that the flash memory 102 can be Low-standard clock signal action. In step S404, the flash memory 102 is overclocked (refer to the program shown in FIG. 2), and a plurality of clock candidates suitable for the flash memory 102 are determined. Step S406 is to perform a frequency conversion operation on the flash memory 102 (such as mode 1, 2 or 3 in FIG. 3), so that the flash memory 102 switches between the clock candidates, so that the electromagnetic interference (EMI) effect is dispersed. Frequency bands. The above overclocking test can also cause the operating clock to dynamically adjust with the aging problem of the flash memory 102.

The controller 104 described in the above embodiment may be a combination of an arithmetic unit and a read-only processor (ROM) in addition to a specially designed chip. It. The technical steps disclosed above can be implemented in firmware, and the related code is carried in the read-only memory in the controller, and is executed by the arithmetic unit in the controller. In addition, all techniques that use the same concept to control a flash memory are within the scope of this case. The case is more related to the control method of the flash memory, and is not limited to the implementation of the controller of a specific architecture.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧ data storage device

102‧‧‧Flash memory

104‧‧‧ Controller

106‧‧‧Host

BLK1, BLK2‧‧‧ blocks

Claims (18)

A data storage device includes: a flash memory; and a controller coupled to the flash memory, the controller tests the flash memory with test clock signals of various frequencies to determine the flash The clock signal applied to the memory causes the flash memory system to operate in accordance with the applicable clock signal. The data storage device of claim 1, wherein the controller further determines, by the test clock signals, a plurality of clock candidates as clock signals to which the flash memory is applied, so that the clock signal is applied to the flash memory. The flash memory system performs frequency conversion operations among the clock candidates. The data storage device of claim 2, wherein: the controller is the highest frequency clock and the high frequency clock that the flash memory is correctly operated as the clock candidate; and the control The device switches the clock signal used by the flash memory every time an instruction is given to the flash memory. The data storage device of claim 2, wherein: the controller is a clock candidate of the highest frequency clock and a high frequency clock that are correctly operated by the flash memory; the controller Controlling the flash memory to operate at the highest frequency clock when the read command is issued to the flash memory; and the controller controls the flash memory when a write command is issued to the flash memory The operation is performed by the above-described secondary high-frequency clock operation or between the above-mentioned highest frequency clock and the above-described secondary high-frequency clock. The data storage device of claim 2, wherein: the controller is a clock candidate of the highest frequency clock and a high frequency clock that are correctly operated by the flash memory; the controller When the flash memory is sequentially read and written, the flash memory is controlled to operate at the highest frequency clock; and the controller controls the flash memory to be the second highest when randomly reading and writing the flash memory. The frequency clock operation, or the above-mentioned highest frequency clock and the above-mentioned secondary high frequency clock switching operation. The data storage device of claim 1, wherein the controller gradually down-converts from the highest frequency test clock signal to test the flash memory. The data storage device of claim 1, wherein: the flash memory system responds to a response signal when the controller tests the flash memory with one of the test clock signals; The controller determines a clock signal applicable to the flash memory from the test clock signals by adjusting a sampling time point of reading the response signals corresponding to the test clock signals. The data storage device of claim 1, wherein: the driving of the data transmission line between the controller and the flash memory is based on a set of driving parameters; and when the controller uses the testing When one of the pulse signals tests the flash memory, the controller further adjusts the set of driving parameters so that the signal transmitted through the data transmission line is correctly captured by the controller. For example, the data storage device described in claim 1 wherein: A data transmission line is coupled between the controller and the flash memory; and the controller operates at a single data rate by switching the flash memory so that the signal transmitted through the data transmission line is correctly corrected by the controller. Capture. A flash memory control method comprising: testing a flash memory with a test clock signal of a plurality of frequencies; determining the result of the test of the flash memory according to the test frequency signals of the plurality of frequencies described above; The clock signal to which the flash memory is applied; and the flash memory to operate in accordance with the applicable clock signal. The flash memory control method of claim 10, further comprising: determining, by the test clock signals, a plurality of clock candidates as clock signals applicable to the flash memory, so that The flash memory system performs frequency conversion operations among the clock candidates. The flash memory control method of claim 11, wherein: the highest frequency clock and the high frequency clock system of the flash memory functioning correctly as the clock candidate; and the flashing The clock signal used by the memory is switched every time there is a new command. The flash memory control method according to claim 11, wherein: the highest frequency clock and the high frequency clock system that the flash memory is correctly operated as the clock candidate; The flash memory system operates at the highest frequency clock described above; In the case of a write operation, the flash memory system operates in the above-described secondary high frequency clock, or between the above-described highest frequency clock and the above-described secondary high frequency clock. The flash memory control method of claim 11, wherein: the highest frequency clock and the high frequency clock system of the flash memory are correctly operated as the clock candidate; In flash memory, the flash memory system operates at the highest frequency clock; and when the flash memory is randomly read and written, the flash memory system operates at the above-mentioned secondary high frequency clock or at the highest frequency Pulse and the above-mentioned secondary high-frequency clock switching operation. The flash memory control method of claim 10, wherein the test clock signal is gradually down-converted from the highest frequency to test the flash memory. The flash memory control method of claim 10, further comprising: when the flash memory is tested by one of the test clock signals, the flash memory system responds with a response signal; And determining, by adjusting a sampling time point of the response signal corresponding to the test clock signals, determining a clock signal applicable to the flash memory from the test clock signals. The flash memory control method of claim 10, further comprising: transmitting the signal to the flash memory via the data transmission line based on a set of driving parameter driving signals; When the flash memory is tested with one of the test clock signals, the set of drive parameters is adjusted such that the signal transmitted via the data transmission line is correctly captured. The flash memory control method of claim 10, further comprising: transmitting a signal to the flash memory via a data transmission line; and operating the data by a single data rate by switching the flash memory The signal transmitted by the transmission line is correctly captured by the flash memory.