CN116069387A - Storage device adaptation method, adaptation device, storage device and readable storage medium - Google Patents
Storage device adaptation method, adaptation device, storage device and readable storage medium Download PDFInfo
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Abstract
The disclosure provides a storage device adapting method, an adapting device, a storage device and a computer readable storage medium, and relates to the technical field of storage devices. The adaptation method of the storage device comprises the following steps: in the development process of the storage device, presetting development codes for adapting to the flash memory chip; acquiring characteristic parameters of the flash memory chip to be adapted based on an adaptation rule; and carrying out adaptation processing on the preset development codes based on the characteristic parameters so as to generate an application strategy applicable to the flash memory chip based on processing results. Through the technical scheme of the disclosure, the adaptation operation between the main control chip and the flash memory chips of different types in the storage device is realized, so that the adaptation processing efficiency can be improved, the adaptation performance can be ensured, and the development efficiency of the SSD solid state disk is improved while the performance of the SSD solid state disk is ensured.
Description
Technical Field
The present disclosure relates to the field of storage devices, and in particular, to a method and apparatus for adapting a storage device, and a computer readable storage medium.
Background
The solid state disk (SSD, solid State Drive) is a nonvolatile data storage device, and mainly comprises a main control chip and a flash memory chip (i.e. a storage unit), wherein the main control chip needs to be subjected to adaptation processing with the storage units of different manufacturers in a development stage, and in the development and adaptation process, the time and the adaptation degree consumed by the adaptation directly influence the development progress of the main control chip and the performance of the SSD solid state disk.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
It is an object of the present disclosure to provide a method, an apparatus, a storage device and a computer-readable storage medium for adapting a storage device, which overcome, at least to some extent, the problem that the addressing efficiency of a storage chip in the related art is still to be improved.
Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.
According to one aspect of the present disclosure, there is provided a method of adapting a storage device, comprising: in the development process of the storage device, presetting development codes for adapting to the flash memory chip; acquiring characteristic parameters of the flash memory chip to be adapted based on an adaptation rule; and carrying out adaptation processing on the preset development codes based on the characteristic parameters so as to generate an application strategy applicable to the flash memory chip based on processing results.
In one embodiment of the present disclosure, the adapting rule includes an operation rule, and the obtaining, based on the adapting rule, the characteristic parameter of the flash memory chip to be adapted includes: acquiring operation characteristic parameters suitable for operation of the flash memory chip based on the operation rule; the adapting processing is carried out on the preset development codes based on the characteristic parameters, so that an application strategy applicable to the flash memory chip is generated based on processing results, and the running conditions to be configured of the flash memory chip are determined based on the running characteristic parameters; determining parameters to be adjusted corresponding to the running conditions in the development codes; and adjusting the parameters to be adjusted to be matched with the flash memory chip, and generating the application strategy.
In one embodiment of the present disclosure, the operation feature parameter includes an interface feature of the flash memory chip, and the determining an operation condition to be configured of the flash memory chip based on the operation feature parameter includes: and identifying an interface protocol supported by the flash memory chip based on the interface characteristics of the flash memory chip, and taking an identification result as the operation condition to be configured, wherein the interface protocol comprises a first type interface protocol and a second type interface protocol.
In one embodiment of the disclosure, the determining the parameters to be adjusted in the development code corresponding to the operating conditions includes: inquiring code parameters related to the interface features in the development codes as the parameters to be adjusted so as to adjust the parameters to be adjusted into an operation instruction sequence matched with the interface protocol based on the identification result, wherein the operation instruction sequence is configured based on clock signals for the first type of interface protocol, and the operation instruction sequence is configured based on jump edges of differential signals for the second type of interface protocol.
In one embodiment of the present disclosure, the operation feature parameter includes an instruction feature of the flash memory chip, and the determining, based on the operation feature parameter, an operation condition to be configured of the flash memory chip includes: and detecting an execution function of the flash memory chip based on the instruction characteristic of the flash memory chip, wherein the execution function is used as the running condition to be configured, and the execution function comprises operation time required by executing an operation instruction, and the operation instruction comprises at least one of a read instruction, a write instruction and an erase instruction.
In one embodiment of the disclosure, the determining the parameters to be adjusted in the development code corresponding to the operating conditions includes: inquiring a delay parameter which needs to be waited for completing the operation instruction from the development code as the corresponding parameter to be adjusted so as to adjust the delay parameter to be matched with the operation time.
In one embodiment of the present disclosure, the adapting rule includes a performance rule, and the obtaining, based on the adapting rule, the characteristic parameter of the flash memory chip to be adapted includes: acquiring performance characteristic parameters suitable for optimizing operation of the flash memory chip based on the performance rule; the adapting the preset development code based on the characteristic parameters to generate an application policy applicable to the flash memory chip based on the processing result includes: determining the operation performance of the flash memory chip to be optimized based on the performance characteristic parameters; and configuring corresponding performance optimization parameters for the operation performance in the development code to generate the application strategy.
In one embodiment of the present disclosure, the performance characteristic parameter includes a read-write performance characteristic of the flash memory chip, and the determining, based on the performance characteristic parameter, an operation performance to be adapted to the flash memory chip includes: detecting whether the flash memory chip supports a parallel processing mode or not based on the read-write performance characteristics of the flash memory chip, and taking a detection result as the running performance to be optimized, wherein the parallel processing mode comprises at least one of a multi-stage read-write technology Multiplane, an external cross read-write technology Interleave, an internal cross read-write technology and two-step programming operation.
In one embodiment of the disclosure, the configuring, in the development code, corresponding performance optimization parameters for the running performance to generate the application policy includes: if the parallel processing mode is determined to be supported based on the detection result, configuring an instruction code for starting a parallel processing instruction in the development code, and distributing corresponding calculation and storage resources for the parallel processing instruction to generate the application strategy; and if the parallel processing mode is not supported based on the detection result, configuring a specified code for shielding the parallel processing instruction in the development code to generate the application strategy.
In one embodiment of the present disclosure, the performance characteristic parameter includes a physical characteristic of the flash memory chip, and the determining, based on the performance characteristic parameter, an operating performance of the flash memory chip to be optimized includes: identifying the number of storage units in the flash memory chip to serve as the performance characteristic parameters; and determining the operation performance to be optimized of the flash memory chip based on the number of the storage units.
In one embodiment of the disclosure, the configuring, in the development code, corresponding performance optimization parameters for the running performance to generate the application policy includes: optimizing the storage resource allocation of the flash memory chip based on the number of the storage units to obtain allocation optimization parameters; the allocation optimization parameters are configured in the development code to generate the application policy.
In one embodiment of the present disclosure, the adapting rule includes a reliability rule, and the obtaining, based on the adapting rule, the characteristic parameter of the flash memory chip to be adapted includes: acquiring reliability characteristic parameters of the flash memory chip based on the reliability rule; the adapting the preset development code based on the characteristic parameters to generate an application policy applicable to the flash memory chip based on the processing result includes: inquiring a reliability basic strategy in the development code; and carrying out adaptation processing on the reliability basic strategy based on the reliability characteristic parameters to obtain a reliability strategy as the application strategy, wherein the reliability basic strategy comprises a processing strategy for reading a retry lookup table and/or a temperature control strategy for the flash memory chip.
In one embodiment of the present disclosure, the adapting the reliability base policy based on the reliability feature parameter, to obtain a reliability policy includes: adjusting a processing capacity and/or a processing parameter value in the processing strategy based on the storage quality parameter; and/or adjusting rule parameters of the temperature control strategy based on the temperature characteristic parameters to obtain the application strategy.
In an embodiment of the present disclosure, the adapting the preset development code based on the feature parameter to generate an application policy applicable to the flash memory chip based on a processing result further includes: executing test operation on the flash memory chip based on the application strategy so as to detect whether the processing result of the development code meets the development requirement or not; and if the development requirement is not met, performing repair operation on the development code.
According to another aspect of the present disclosure, there is provided an adapting apparatus of a storage device, including: the presetting module is used for presetting development codes for adapting to the flash memory chip in the development process of the storage equipment; the acquisition module is used for acquiring characteristic parameters of the flash memory chip to be adapted based on the adaptation rule; and the processing module is used for carrying out adaptation processing on the preset development codes based on the characteristic parameters so as to generate an application strategy applicable to the flash memory chip based on a processing result.
According to still another aspect of the present disclosure, there is provided a storage device including: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the method of adapting the storage device of any of the above via execution of the executable instructions.
According to yet another aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of adapting a storage device of any of the above.
According to the adaptation scheme of the storage device, in the development stage of the flash memory chip, development codes for controlling the operation of the flash memory chip are pre-stored in the main control chip, the configured development codes with general characteristics are subjected to adaptation processing based on the acquired characteristic parameters of the flash memory chip to be adapted, so that relevant parameter values in the preset development codes are configured to be special parameter values matched with the characteristic parameters, an application strategy applicable to the flash memory chip is generated based on processing results, the adaptation operation between the main control chip and the flash memory chips of different types in the storage device is realized, the adaptation processing efficiency can be improved, the adaptation performance can be ensured, and the development efficiency of the SSD solid state disk is improved while the performance of the SSD solid state disk is ensured.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
FIG. 1 shows a schematic diagram of a computer system in an embodiment of the present disclosure;
FIG. 2 illustrates a flow chart of a method of adapting a storage device in an embodiment of the present disclosure;
FIG. 3 illustrates a flow chart of another method of adapting a storage device in an embodiment of the present disclosure;
FIG. 4 illustrates a flow chart of a method of adapting a further storage device in an embodiment of the present disclosure;
FIG. 5 illustrates a flow chart of a method of adapting a further storage device in an embodiment of the present disclosure;
FIG. 6 illustrates a flow chart of a method of adapting a further storage device in an embodiment of the present disclosure;
FIG. 7 illustrates a flow chart of a method of adapting a further storage device in an embodiment of the present disclosure;
FIG. 8 illustrates a flow chart of a method of adapting a further storage device in an embodiment of the present disclosure;
FIG. 9 illustrates a flow chart of a method of adapting a further storage device in an embodiment of the present disclosure;
fig. 10 shows a schematic diagram of an adapting apparatus of a storage device in an embodiment of the disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.
For ease of understanding, several terms referred to in this application are first explained below.
Solid State Disk (Solid State Disk): information is stored in units of bytes in memory, and each byte unit is given a unique memory address, called a physical address, in order to properly store or retrieve information.
The scheme provided by the embodiment of the application relates to storage and other technologies, and is specifically described through the following embodiments.
FIG. 1 shows a schematic block diagram of a computer system according to an embodiment of the present disclosure. The computer system 100 includes a host 110 and a solid state disk, the solid state disk includes a main control chip 120 and a flash memory chip 130, and a storage medium of the flash memory chip 130 may be a flash memory chip array.
The host interface 122 of the main control chip 120 is connected to the host 110 to transmit instructions. The processor 124 may be a front-end processor of a solid state disk, and is connected to the host interface 122, the memory controller 126, and the cache module 128, where the cache module 128 is used to store an address mapping table and the like.
The memory controller 126 of the main control chip 120 is connected to the flash memory chip 130, and performs data access operation on corresponding memory cells of the flash memory chip 130 according to the physical address provided by the processor 124.
Flash memory chip 130 includes an array of flash memory chips. In order to improve the data read/write performance, the memory controller 126 of the main control chip 120 may read/write the flash memory chip of the flash memory chip 130 through the multiple channels CH0 and CH 1. Each channel connects a set of flash memory chips, each flash memory chip including a plurality of physical blocks (e.g., physical block 131 and physical block 132 in fig. 1, etc.), each physical block including a plurality of physical pages, and data access operations to the flash memory chips including read, write, and erase. Because of the physical characteristics of the flash memory chip, the basic unit of data operation is, for example, a physical page, the basic unit of erase operation is, for example, a physical block, one physical page size is 8KB or 4KB, one physical block has 256 physical pages, and one logical unit number LUN has 4096 physical blocks.
When the host 110 performs a data operation, the main control chip 120 receives an instruction from the host 110. The host chip 120 maps logical addresses in the instructions to physical addresses that are used to characterize locations in the flash chip 130.
In the development process of storage equipment such as solid state disk SSDs, aiming at the development operation of solid state disk SSDs with different capacities and different standards (consumption level/enterprise level/military level/PCIE gen4/PCIE gen 5), aiming at the main control chip of the SSD, the running codes of all modules in the main control chip of the SSD are different, and the calling conditions of NAND related parameters are also different, so that the situation that multiple flash memory chips are used by the main control chip of multiple SSDs exists. The invoking condition of the NAND related parameters is more complicated.
In the development process of the main control chip, the operation strategies and the calling parameters of different modules of the SSD are affected by different flash memory chips, and if a SSD developer adjusts the corresponding parameters in each module of the SSD according to the characteristics of each chip, the development workload of the main control chip is increased dramatically, and the development progress of the SSD and the final stability of the main control operation are affected.
Therefore, the parameters required to be called by the running codes of all modules of the SSD are automatically generated by using the automatic script according to different flash memory chips, so that the SSDDE development workload of the SSD is saved, and the stability of the main control chip is improved.
The steps of the adaptation method of the storage device in this exemplary embodiment will be described in more detail with reference to the accompanying drawings and examples.
Fig. 2 shows a flowchart of an adaptation method of a storage device in an embodiment of the present disclosure. The method provided by the embodiments of the present disclosure may be performed by any storage device having computing processing capabilities.
As shown in fig. 2, the main control chip executes an adaptation method of the storage device, including the following steps:
step S202, in the development process of the storage device, a development code for adapting to the flash memory chip is preset.
The preset development codes are specifically development codes with universal formats, and through the preset development codes, when the development codes are matched with flash memory chips of different manufacturers and/or different models, the adaptation operation between the main control chip and the flash memory chips can be completed only by modifying a small part of parameters through macro processing operation.
Specifically, the development code with the general format may be a development code suitable for a class a flash memory chip, and in a class B flash memory chip, based on characteristic parameters of the class a flash memory chip, the class B parameters in the development code are adjusted to class a parameters in combination with macro processing operation.
Step S204, obtaining the characteristic parameters of the flash memory chip to be adapted based on the adaptation rule.
The development instruction of the main control chip can obtain the characteristic parameters of the flash memory chip to be adapted, and the development instruction can be an adaptation instruction of the main control chip and the flash memory chip, a test instruction of the main control chip, or a special instruction configured for adaptation operation between the main control chip and the flash memory chip.
The adaptation rules may include operation rules, performance rules, and reliability rules to implement normal operation of the flash memory chip based on the operation rules, performance optimization of the flash memory chip based on the performance rules, and reliability assurance of the flash memory chip based on the reliability rules, respectively.
Specifically, the characteristic parameters are obtained based on the adaptation rules, which may be specifically obtained based on the operation rules, the performance rules and the reliability rules in sequence, and further adapted, or may be randomly adapted based on different adaptation rules, or may further select part of the adaptation rules for adaptation.
In addition, the characteristic parameters of the flash memory chip can also include the type of the flash memory chip, the model of the flash memory chip, the manufacturer identification of the flash memory chip, and the like.
Further, the characteristic parameters of the flash memory chip may further include interface characteristics, instruction characteristics, read-write performance characteristics, physical characteristics, reliability indexes, and the like of the flash memory chip.
Specifically, the characteristic parameters of the flash memory chip include interface characteristics, instruction characteristics, read-write performance characteristics, physical characteristics, reliability indexes and the like of the flash memory chip, so that the normal operation of the flash memory chip can be ensured based on the interface characteristics and the instruction characteristics, the optimization of the performance of the flash memory chip can be realized according to the read-write performance characteristics and the physical characteristics, and the reliability of the flash memory chip can be ensured according to the reliability indexes.
Step S206, carrying out adaptation processing on the preset development codes based on the characteristic parameters to generate an application strategy applicable to the flash memory chip based on the processing result.
And carrying out adaptation processing on preset development codes, including, but not limited to, parameter adjustment, parameter model call, specific instruction configuration, parameter calculation, code configuration, relevant parameter module shielding and other operations in the development codes.
The foregoing adaptation processing on the preset development code may be specifically implemented by performing macro processing on the development code.
And carrying out adaptation processing on the preset development codes, and particularly, adopting an inline function for processing.
In addition, the preset development code is subjected to the adaptation processing, and in particular, the development parameters can be subjected to the adaptation processing by developing a special adaptation model.
Specifically, taking macro processing as an example, the macro processing specifically replaces a certain text mode according to a series of predefined rules, by adopting replacement to extract editable parameters related to characteristic parameters in preset development codes, based on macro processing operation, no matter where a macro name appears in source codes, a preprocessor can replace the macro name with a text designated in definition, and application codes matched with the characteristic parameters can be written in the preset development codes so as to obtain an application strategy of a flash memory chip.
In the disclosure, macro processing is performed on a preset development code based on a feature parameter, specifically, a code matching the feature parameter may be selected from a preset plurality of groups of codes based on macro processing, or specifically, a parameter value a in the code may be adjusted to a parameter value B matching the feature parameter based on macro processing.
In this embodiment, in the development stage of the flash memory chip, by pre-storing a development code for controlling the operation of the flash memory chip in the main control chip, based on the obtained feature parameter of the flash memory chip to be adapted, the configured development code with general features is subjected to adaptation processing, so that relevant parameter values in the preset development code are configured into special parameter values matched with the feature parameter, and an application policy applicable to the flash memory chip is generated based on the processing result, so that the adaptation operation between the main control chip and the flash memory chips of different types in the storage device is realized, the adaptation processing efficiency is improved, the adaptation performance is ensured, and the development efficiency of the SSD solid state disk is improved while the performance of the SSD solid state disk is ensured.
As shown in fig. 3, in an embodiment of the present disclosure, in step S204, a specific implementation manner of obtaining, based on an adaptation rule, a characteristic parameter of a flash memory chip to be adapted includes:
step S302, operation characteristic parameters suitable for operation of the flash memory chip are obtained based on operation rules.
The adaptation rules comprise operation rules, namely rules capable of enabling the flash memory chip to normally operate.
In step S204, the adapting process is performed on the preset development code based on the feature parameter, so as to generate a specific implementation manner of the application policy applicable to the flash memory chip based on the processing result, which includes:
step S304, determining the operation condition of the flash memory chip to be configured based on the operation characteristic parameters.
Step S306, determining parameters to be adjusted corresponding to the operation conditions in the development code.
Step S308, the parameters to be adjusted are adjusted to be matched with the flash memory chip based on macro processing, and an application strategy is generated.
The parameters to be adjusted are adjusted to be matched with the flash memory chip, and the parameters to be adjusted can be adjusted based on macro processing.
The method comprises the steps of determining parameters to be adjusted corresponding to running conditions to be configured of the flash memory chip in development codes, specifically inquiring parts to be adjusted from all preset development codes, and further determining the parameters to be adjusted.
If the target code matched with the characteristic parameter is selected from the preset multiple groups of codes based on macro processing, the parameter to be adjusted can be an adaptive parameter between the flash memory chip and the target code.
And if the parameter value A in the code is adjusted to be the parameter value B matched with the characteristic parameter based on macro processing, the parameter to be adjusted is the parameter value A.
In this embodiment, in order to ensure normal operation of the flash memory chip, an operation characteristic parameter required by operation of the flash memory chip is determined based on an operation rule, so as to further determine an operation condition satisfying the operation characteristic parameter, and determine a parameter to be adjusted in a development code, and the development code adapted to the current flash memory chip is obtained by performing macro processing on the parameter to be adjusted based on the characteristic parameter of the flash memory chip, so as to realize normal operation of the flash memory chip after adaptation, and the development code adapted to the flash memory chip is used as an application policy of a storage device including the main control chip, so that when the storage device is operated, the adjusted development code can be ensured to be reliably invoked.
Specifically, taking an SSD solid state disk as an example, when a main control chip of the SSD solid state disk is developed, the main control chip needs to be adapted to different types of flash memory chips produced by different manufacturers, and the time consumed by the adapting work and the accuracy of the adapting work directly affect the development progress of the main control chip and the performance of the SSD solid state disk.
In order to ensure normal operation of the flash memory chip, as shown in fig. 4, one implementation manner of adapting the main control chip to the flash memory chip, in one embodiment of the present disclosure, the main control chip performs an adapting method of the storage device, including the following steps:
Step S402, in the development process of the storage device, a development code for adapting to the flash memory chip is preset.
Step S404, obtaining operation characteristic parameters suitable for operation of the flash memory chip based on the operation rule, wherein the operation characteristic parameters comprise interface characteristics of the flash memory chip.
Step S406, the interface protocol supported by the flash memory chip is identified based on the interface characteristics of the flash memory chip, and the identification result is used as the operation condition to be configured.
Wherein the interface protocols include a first type of interface protocol and a second type of interface protocol.
Specifically, the first type of interface protocol may be a ONFI (Open NAND Flash Interface) protocol, the operation command sequence is configured based on a clock signal, that is, in the ONFI protocol, the ONFI synchronization mode has a clock signal, data, commands and addresses all need to be synchronized with the clock signal, the second type of interface protocol may be a Toggle protocol, the operation command sequence is configured based on a transition edge of a differential signal, that is, in the Toggle protocol, writing data to the flash memory chip is triggered based on a transition edge of a DQS (data selection pulse) differential signal, reading data from the flash memory chip is triggered by a REN differential signal transition edge sent from a master device of the memory device, and outputting data based on the transition edge of the DQS.
In step S408, the code parameters related to the interface features in the development code are queried as parameters to be adjusted.
Step S410, adjusting the parameters to be adjusted to an operation instruction sequence matched with the interface protocol based on the identification result, and generating an application strategy.
Specifically, the parameter adjustment for the interface protocol is specifically: and if the identification result is the first type interface protocol, associating the operation instruction sequence corresponding to the first type interface protocol with the flash memory chip, and if the identification result is the second type interface protocol, associating the operation instruction sequence corresponding to the second type interface protocol with the flash memory chip.
In this embodiment, because different flash memory chips support ONFI protocols or Toggle protocols respectively, based on different interface protocols, the operation instruction sequences supported by the flash memory chips are different, and by storing different instruction codes in the main control chip and combining with the identification result of the interface protocol supported by the interface of the flash memory chip, the corresponding operation instruction sequences are determined, thereby ensuring efficient adaptation between the main control chip and the interface of the flash memory chip.
In order to ensure normal operation of the flash memory chip, another implementation manner of adapting the main control chip to the flash memory chip is shown in fig. 5, in one embodiment of the present disclosure, the main control chip performs an adapting method of the storage device, including the following steps:
In step S502, in the development process of the storage device, a development code for adapting to the flash memory chip is preset.
Step S504, obtaining operation characteristic parameters suitable for operation of the flash memory chip based on the operation rule, wherein the operation characteristic parameters comprise instruction characteristics of the flash memory chip.
In step S506, the execution function of the flash memory chip is detected based on the instruction feature of the flash memory chip, so as to serve as the running condition to be configured, and the execution function includes the operation time required for executing the operation instruction.
Wherein the operation instruction includes at least one of a read instruction, a write instruction, and an erase instruction.
The execution function is specifically the completion degree, completion efficiency, and the like of executing the above-described various instructions.
Step S508, inquiring the delay parameter to be waited for completing the operation instruction from the development code as the corresponding parameter to be adjusted.
The flash memory chip comprises a pin R/B for outputting a Ready/Busy signal, wherein the Ready/Busy signal is used for indicating a target state, namely an execution state of an operation instruction of the flash memory chip, when the flash memory chip is in a low level, the flash memory chip is identified to have operation in progress, and the state of the Ready signal after the low level is changed into a high level can be obtained based on a delay parameter so as to execute the operation of the next step.
Step S510, adjusting the delay parameter to match the operation time based on the macro processing, and generating an application policy.
In this embodiment, since response operation times of received read instructions, write instructions, erase instructions and the like are different in different flash memory chips, delay parameters required to wait when the main control chip detects whether instructions are completed are different, so that by acquiring operation time required for the flash memory chip to execute the operation instructions, delay parameters required to wait for the operation instructions corresponding to development codes are adjusted to match with the operation time, timely response when interaction with the flash memory chip is ensured, and development efficiency of the main control chip is improved.
As shown in fig. 6, in an embodiment of the present disclosure, in step S204, a specific implementation manner of obtaining, based on an adaptation rule, a characteristic parameter of a flash memory chip to be adapted includes:
step S602, obtaining performance characteristic parameters suitable for optimizing operation of the flash memory chip based on the performance rules.
The adaptation rules comprise performance rules, namely rules capable of optimizing the operation performance of the flash memory chip.
In step S204, the adapting process is performed on the preset development code based on the feature parameter, so as to generate a specific implementation manner of the application policy applicable to the flash memory chip based on the processing result, which includes:
Step S604, determining the operation performance of the flash memory chip to be optimized based on the performance characteristic parameters.
Step S606, corresponding performance optimization parameters are configured for the operation performance in the development code based on macro processing to generate an application strategy.
In this embodiment, in order to realize performance optimization of the flash memory chip, performance characteristic parameters required by operation of the flash memory chip are determined based on performance rules, so as to further determine operation performance to be optimized which meets the performance characteristic parameters, and corresponding performance optimization parameters are configured for the operation performance in development codes, and the performance optimization parameters are subjected to macro processing based on the characteristic parameters of the flash memory chip to obtain an adjusted development code suitable for the current flash memory chip, so that performance optimization after the flash memory chip is adapted is realized, and the development code is used as an application strategy of storage equipment comprising the main control chip, so that the performance optimization after the flash memory chip is adapted can be realized based on automatic adaptation operation on the basis of normal operation of the storage equipment.
In order to achieve performance improvement of the flash memory chip, as shown in fig. 7, one implementation manner of adapting the main control chip to the flash memory chip, in one embodiment of the present disclosure, the main control chip performs an adapting method of the storage device, including the following steps:
In step S702, in the development process of the storage device, a development code for adapting to the flash memory chip is preset.
In step S704, performance characteristic parameters suitable for optimizing operation of the flash memory chip are obtained based on the performance rule, wherein the performance characteristic parameters include read-write performance characteristics of the flash memory chip.
Step S706, whether the flash memory chip supports the parallel processing mode is detected based on the read-write performance characteristics of the flash memory chip, and the detection result is used as the running performance to be optimized.
The parallel processing mode comprises at least one of a multi-level read-write technology Multiplane, an external cross read-write technology interleave, an internal cross read-write technology and two-step programming operation.
In step S708, if it is determined that the parallel processing mode is supported based on the detection result, an instruction code for starting the parallel processing instruction is configured in the development code based on the macro processing, and corresponding computing and storage resources are allocated to the parallel processing instruction to generate the application policy.
In step S710, if it is determined that the parallel processing mode is not supported based on the detection result, a specified code for masking the parallel processing instruction is configured in the code based on the macro processing to generate an application policy.
Specifically, the configuration and masking of instruction codes may also be implemented in a macro-processing based manner.
In this embodiment, since the instruction ranges supported by the different types of flash memory chips are different, for example, a part of types of flash memory chips support multiplane, interleave and other parallel operations, a part of types of flash memory chips do not support parallel operations, and another part of types of flash memory chips support two-step programming operations, for example, a part of types of flash memory chips do not support two-step programming operations, the main control chip identifies whether the chip to be adapted supports the above parallel processing manner, so that when the chip to be adapted supports the above parallel processing manner, corresponding processing instructions are started, and when the chip to be adapted does not support the above parallel processing manner, the corresponding processing instructions are shielded, so that reliable support of the main control chip on the above functions of the flash memory chip is ensured, and further, the operation efficiency and stability of the storage device are ensured.
In order to achieve performance improvement of the flash memory chip, another implementation manner of adapting the main control chip to the flash memory chip is shown in fig. 8, in one embodiment of the present disclosure, the main control chip performs an adapting method of the storage device, including the following steps:
step S802, in the development process of the storage device, a development code for adapting to the flash memory chip is preset.
In step S804, performance characteristic parameters suitable for the optimized operation of the flash memory chip are obtained based on the performance rule, wherein the performance characteristic parameters include physical characteristics of the flash memory chip.
In step S806, the number of memory cells in the flash memory chip is identified as the performance characteristic parameter.
I.e. the physical characteristics of the flash memory chip include the number of memory cells.
Wherein, a flash memory chip has several DIEs (or LUNs), each DIE has several planes, each Plane has several blocks, each Block has several pages, each Page corresponds to several memory cells.
Step S808, determining the operation performance of the flash memory chip to be optimized based on the number of the memory cells.
Step S810, optimizing the storage resource allocation of the flash memory chip based on the number of the storage units to obtain allocation optimization parameters.
In step S812, allocation optimization parameters are configured in the development code to generate an application policy.
The allocation optimization parameters are configured in the development code, and can be specifically configured in the development code based on macro processing.
In this embodiment, the number of the memory units is different for different flash memory chips, so that the host chip needs to allocate different memory resources to process the flash memory chip operation instruction, thereby enabling the memory device to have better performance.
In order to ensure the reliability of the operation of the flash memory chip, as shown in fig. 9, one implementation manner of adapting the main control chip to the flash memory chip, in one embodiment of the present disclosure, the main control chip performs an adapting method of the storage device, including the following steps:
In step S902, in the development process of the storage device, a development code for adapting to the flash memory chip is preset.
Step S904, obtaining the reliability characteristic parameters of the flash memory chip based on the reliability rule.
The adaptation rules comprise reliability rules, namely rules which enable the flash memory chip to guarantee operation reliability.
Step S906, query the reliability base policy in the development code.
The reliability basic strategy comprises a processing strategy for reading the retry lookup table and/or a temperature control strategy for the flash memory chip.
Step S908 adjusts the processing capacity and/or the processing parameter values in the processing strategy based on the storage quality parameter.
Specifically, read Retry is an error correction mechanism that attempts to correctly Read data by attempting to find the closest threshold voltage from the normal threshold voltage when a page presents an uncorrectable Read error of ECC (Error Checking and Correcting, error checking and correction).
Therefore, the read retry lookup table matched with the flash memory chip is configured to perform reliable read retry operation based on the query result time.
In step S910, rule parameters of the temperature control policy are adjusted based on the temperature characteristic parameters to obtain an application policy.
In addition, by detecting the temperature control reliability index of the flash memory chip, the corresponding temperature control strategy is determined based on the index, and reliable temperature control of the flash memory chip is realized.
In this embodiment, since specific index values of chip reliability of different flash memory chips are different, in order to ensure operation reliability of the flash memory chips, the master control chip needs to configure different strategies to cope with the operation reliability of the flash memory chips, so that the reliability of the flash memory chips is in an optimal state, for example, the built-in read retry table (read retry table) of the different flash memory chips is different, the master control chip needs to perform corresponding adapting operation when in use, in addition, the temperature characteristics of the different flash memory chips are different, the master control chip needs to store different temperature control strategy parameters, and the reliability index of the flash memory chips is obtained to call the corresponding temperature control strategy parameters, so that efficient and reliable adaptation between the application reliability of the master control chip and the flash memory chips is ensured.
In one embodiment of the present disclosure, the adapting processing is performed on the preset development code based on the feature parameter, so as to generate an application policy applicable to the flash memory chip based on the processing result, and the method further includes: executing test operation on the flash memory chip based on the application strategy so as to detect whether the processing result of the development code meets the development requirement or not; and if the development requirement is not met, repairing the developed code.
It is noted that the above-described figures are only schematic illustrations of processes involved in a method according to an exemplary embodiment of the invention, and are not intended to be limiting. It will be readily appreciated that the processes shown in the above figures do not indicate or limit the temporal order of these processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, for example, among a plurality of modules.
Those skilled in the art will appreciate that the various aspects of the invention may be implemented as a system, method, or program product. Accordingly, aspects of the invention may be embodied in the following forms, namely: an entirely hardware embodiment, an entirely software embodiment (including firmware, micro-code, etc.) or an embodiment combining hardware and software aspects may be referred to herein as a "circuit," module "or" system.
An adaptation means 1000 of a storage device according to this embodiment of the invention is described below with reference to fig. 10. The adapting apparatus 1000 of the storage device shown in fig. 10 is only an example, and should not impose any limitation on the functions and the scope of use of the embodiment of the present invention.
The adaptation means 1000 of the storage device is embodied in the form of a hardware module. The components of the adaptation means 1000 of the storage device may include, but are not limited to: a preset module 1002, configured to preset a development code for adapting to the flash memory chip in a development process of the storage device; an obtaining module 1004, configured to obtain a characteristic parameter of a flash memory chip to be adapted based on an adaptation rule; the processing module 1006 is configured to perform an adaptation process on a preset development code based on the feature parameter, so as to generate an application policy applicable to the flash memory chip based on the processing result.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a server, a terminal device, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.
In an exemplary embodiment of the present disclosure, a computer-readable storage medium having stored thereon a program product capable of implementing the method described above in the present specification is also provided. In some possible embodiments, the aspects of the invention may also be implemented in the form of a program product comprising program code for causing a terminal device to carry out the steps according to the various exemplary embodiments of the invention as described in the "exemplary method" section of this specification, when the program product is run on the terminal device.
A program product for implementing the above-described method according to an embodiment of the present invention may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The computer readable signal medium may include a data signal propagated in baseband or as part of a carrier wave with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).
It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.
Furthermore, although the steps of the methods in the present disclosure are depicted in a particular order in the drawings, this does not require or imply that the steps must be performed in that particular order or that all illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a server, a mobile terminal, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (17)
1. An adaptation method of a memory device, which is characterized by being applied to a main control chip of the memory device, wherein the memory device further comprises a flash memory chip, the adaptation method comprising:
in the development process of the storage device, presetting development codes for adapting to the flash memory chip;
acquiring characteristic parameters of the flash memory chip to be adapted based on an adaptation rule;
and carrying out adaptation processing on the preset development codes based on the characteristic parameters so as to generate an application strategy applicable to the flash memory chip based on processing results.
2. The method of adapting a memory device according to claim 1,
the adapting rule comprises an operation rule, and the obtaining the characteristic parameters of the flash memory chip to be adapted based on the adapting rule comprises the following steps:
acquiring operation characteristic parameters suitable for operation of the flash memory chip based on the operation rule;
the adapting the preset development code based on the characteristic parameters to generate an application policy applicable to the flash memory chip based on the processing result includes:
determining the operation condition to be configured of the flash memory chip based on the operation characteristic parameters;
Determining parameters to be adjusted corresponding to the running conditions in the development codes;
and adjusting the parameters to be adjusted to be matched with the flash memory chip, and generating the application strategy.
3. The method of adapting a memory device according to claim 2, wherein the operating characteristic parameter comprises an interface characteristic of the flash memory chip, and wherein determining an operating condition of the flash memory chip to be configured based on the operating characteristic parameter comprises:
identifying an interface protocol supported by the flash memory chip based on the interface characteristics of the flash memory chip, taking the identification result as the operation condition to be configured,
wherein the interface protocol includes a first type of interface protocol and a second type of interface protocol.
4. A method of adapting a storage device according to claim 3, wherein said determining parameters to be adjusted in said development code corresponding to said operating conditions comprises:
inquiring code parameters related to the interface characteristics in the development code as the parameters to be adjusted so as to adjust the parameters to be adjusted into an operation instruction sequence matched with the interface protocol based on the identification result,
the operation instruction sequence is configured based on a clock signal for the first type of interface protocol, and the operation instruction sequence is configured based on a jump edge of a differential signal for the second type of interface protocol.
5. The method of adapting a memory device according to claim 2, wherein the operating characteristic parameter comprises an instruction characteristic of the flash memory chip, and wherein determining an operating condition of the flash memory chip to be configured based on the operating characteristic parameter comprises:
detecting an execution function of the flash memory chip based on the instruction feature of the flash memory chip, taking the execution function as the operation condition to be configured, wherein the execution function comprises operation time required by executing operation instructions,
wherein the operation instruction includes at least one of a read instruction, a write instruction, and an erase instruction.
6. The method of adapting a storage device according to claim 5, wherein said determining parameters to be adjusted in said development code corresponding to said operating conditions comprises:
inquiring a delay parameter which needs to be waited for completing the operation instruction from the development code as the corresponding parameter to be adjusted so as to adjust the delay parameter to be matched with the operation time.
7. The method of adapting a memory device according to claim 1,
the adapting rule comprises a performance rule, and the obtaining the characteristic parameters of the flash memory chip to be adapted based on the adapting rule comprises the following steps:
Acquiring performance characteristic parameters suitable for optimizing operation of the flash memory chip based on the performance rule;
the adapting the preset development code based on the characteristic parameters to generate an application policy applicable to the flash memory chip based on the processing result includes:
determining the operation performance of the flash memory chip to be optimized based on the performance characteristic parameters;
and configuring corresponding performance optimization parameters for the operation performance in the development code to generate the application strategy.
8. The method of adapting a memory device according to claim 7, wherein the performance characteristic parameter includes a read-write performance characteristic of the flash memory chip, and wherein determining, based on the performance characteristic parameter, an operational performance of the flash memory chip to be adapted includes:
detecting whether the flash memory chip supports a parallel processing mode based on the read-write performance characteristics of the flash memory chip, taking the detection result as the running performance to be optimized,
the parallel processing mode comprises at least one of a multi-stage read-write technology Multiplane, an external cross read-write technology interleave, an internal cross read-write technology and two-step programming operation.
9. The method of adapting a storage device according to claim 8, wherein configuring corresponding performance optimization parameters for the operating performance in the development code to generate the application policy comprises:
if the parallel processing mode is determined to be supported based on the detection result, configuring instruction codes for starting the parallel processing instructions in the development codes, and distributing corresponding calculation and storage resources for the parallel processing instructions to generate the application strategy;
and if the parallel processing mode is not supported based on the detection result, configuring a specified code for shielding the parallel processing instruction in the development code to generate the application strategy.
10. The method of adapting a memory device of claim 7, wherein the performance characteristic parameter comprises a physical characteristic of the flash memory chip, and wherein determining, based on the performance characteristic parameter, an operational performance of the flash memory chip to be optimized comprises:
identifying the number of storage units in the flash memory chip to serve as the performance characteristic parameters;
and determining the operation performance to be optimized of the flash memory chip based on the number of the storage units.
11. The method of adapting a storage device according to claim 10, wherein configuring corresponding performance optimization parameters for the operating performance in the development code to generate the application policy comprises:
optimizing the storage resource allocation of the flash memory chip based on the number of the storage units to obtain allocation optimization parameters;
the allocation optimization parameters are configured in the development code to generate the application policy.
12. The method of adapting a memory device according to claim 1,
the adapting rule includes a reliability rule, and the obtaining, based on the adapting rule, the characteristic parameters of the flash memory chip to be adapted includes:
acquiring reliability characteristic parameters of the flash memory chip based on the reliability rule;
the adapting the preset development code based on the characteristic parameters to generate an application policy applicable to the flash memory chip based on the processing result includes:
inquiring a reliability basic strategy in the development code;
performing adaptation processing on the reliability basic strategy based on the reliability characteristic parameters to obtain a reliability strategy which is used as the application strategy,
The reliability basic strategy comprises a processing strategy for reading a retry lookup table and/or a temperature control strategy for the flash memory chip.
13. The method for adapting a storage device according to claim 12, wherein said adapting the reliability base policy based on the reliability feature parameter to obtain a reliability policy includes, as the application policy:
adjusting a processing capacity and/or a processing parameter value in the processing strategy based on the storage quality parameter; and/or
And adjusting rule parameters of the temperature control strategy based on the temperature characteristic parameters to obtain the application strategy.
14. The adapting method of a storage device according to any one of claims 1 to 13, wherein the adapting processing is performed on the preset development code based on the feature parameter to generate an application policy applicable to the flash memory chip based on a processing result, further comprising:
executing test operation on the flash memory chip based on the application strategy so as to detect whether the processing result of the development code meets the development requirement or not;
and if the development requirement is not met, performing repair operation on the development code.
15. An adaptation device of a storage device, characterized by being applied to a main control chip of the storage device, the storage device further comprising a flash memory chip, the adaptation device comprising:
the presetting module is used for presetting development codes for adapting to the flash memory chip in the development process of the storage equipment;
the acquisition module is used for acquiring characteristic parameters of the flash memory chip to be adapted based on the adaptation rule;
and the processing module is used for carrying out adaptation processing on the preset development codes based on the characteristic parameters so as to generate an application strategy applicable to the flash memory chip based on a processing result.
16. A memory device, comprising:
a main control chip;
the flash memory chip is electrically connected with the main control chip,
wherein the main control chip is configured to execute the adaptation method of the storage device according to any one of claims 1 to 14.
17. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements a method of adapting a storage device according to any of claims 1-14.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040083464A1 (en) * | 2002-10-25 | 2004-04-29 | Cwalina Krzysztof J. | Non-invasive rule-based binary analysis of software assemblies |
| US20140136809A1 (en) * | 2012-11-15 | 2014-05-15 | Bank Of America Corporation | Storage black box |
| US20160269317A1 (en) * | 2015-03-09 | 2016-09-15 | International Business Machines Corporation | Policy driven storage hardware allocation |
| CN108133732A (en) * | 2017-12-20 | 2018-06-08 | 北京京存技术有限公司 | Performance test methods, device, equipment and the storage medium of flash chip |
| US10445229B1 (en) * | 2013-01-28 | 2019-10-15 | Radian Memory Systems, Inc. | Memory controller with at least one address segment defined for which data is striped across flash memory dies, with a common address offset being used to obtain physical addresses for the data in each of the dies |
| CN110727437A (en) * | 2019-09-10 | 2020-01-24 | 平安普惠企业管理有限公司 | Code optimization item acquisition method and device, storage medium and electronic equipment |
| CN114254301A (en) * | 2021-12-21 | 2022-03-29 | 建信金融科技有限责任公司 | PaC-based security policy management method and device |
-
2023
- 2023-03-03 CN CN202310207122.7A patent/CN116069387B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040083464A1 (en) * | 2002-10-25 | 2004-04-29 | Cwalina Krzysztof J. | Non-invasive rule-based binary analysis of software assemblies |
| US20140136809A1 (en) * | 2012-11-15 | 2014-05-15 | Bank Of America Corporation | Storage black box |
| US10445229B1 (en) * | 2013-01-28 | 2019-10-15 | Radian Memory Systems, Inc. | Memory controller with at least one address segment defined for which data is striped across flash memory dies, with a common address offset being used to obtain physical addresses for the data in each of the dies |
| US20160269317A1 (en) * | 2015-03-09 | 2016-09-15 | International Business Machines Corporation | Policy driven storage hardware allocation |
| CN108133732A (en) * | 2017-12-20 | 2018-06-08 | 北京京存技术有限公司 | Performance test methods, device, equipment and the storage medium of flash chip |
| CN110727437A (en) * | 2019-09-10 | 2020-01-24 | 平安普惠企业管理有限公司 | Code optimization item acquisition method and device, storage medium and electronic equipment |
| CN114254301A (en) * | 2021-12-21 | 2022-03-29 | 建信金融科技有限责任公司 | PaC-based security policy management method and device |
Non-Patent Citations (1)
| Title |
|---|
| 马久跃;余子濠;包云岗;孙凝晖;: "体系结构内可编程数据平面方法", 计算机研究与发展, no. 01 * |
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