JP2019016710A - Electronic device and electronic device manufacturing method - Google Patents

Abstract

To provide: an electronic device which has reduced resistance and reduced parasitic capacitance to achieve excellent sensitivity and excellent high-frequency properties; and provide a manufacturing method of the electronic device.SOLUTION: An electronic device has: a semi-insulating semiconductor substrate; an insulation film which is arranged on the semiconductor substrate and has an opening region where a plurality of submicron-size openings are formed and a hole formed at an end of the opening region; a conductive thin film arranged on the insulation film and in the opening region; and a first nanowire which extends from a surface of the semiconductor substrate in the hole into a direction perpendicular to the substrate surface. The first nanowire has the same conductivity type and the same composition with the conductive thin film; and the conductive thin film fills up the inside of the openings and connected with the first nanowire on the insulation film.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an electronic device and a method for manufacturing the electronic device.

  A backward diode using a compound semiconductor heterojunction is expected as a high-sensitivity high-frequency receiving device for environmental radio wave power generation and wireless communication. A technique for increasing the sensitivity of the backward diode by optimizing the doping concentration of the GaAsSb heterojunction is known (see Non-Patent Document 1, for example). Here, the GaAsSb heterojunction is formed on a lattice-matched InP substrate.

  On the other hand, the growth of compound semiconductor nanowires on a lattice-mismatched substrate is known (see, for example, Non-Patent Document 2). Here, it has been reported that InP nanowires grow on a GaAs substrate with a critical diameter of 96 nm.

  In order to take advantage of the high sensitivity and high-frequency characteristics of compound semiconductor nanowires, it is desirable to reduce resistance and parasitic capacitance as much as possible with components other than nanowires.

T. Takahashi et al. “Sensitivity Improvement in GaAsSb-Based Heterojunction Backward Diodes by Optimized Doping Concentration,” IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 62, No. 6, June 2015 Chuang et al. , “Critical diameter for III-V nanowires grown on Lattice-mismatched substrates,” Appl. Phys. Lett. 90, 043115 (2007)

  Since the conventional GaAsSb-based backward diode is manufactured by a lattice matching system, a general-purpose GaAs substrate cannot be used, and an expensive InP substrate is used. When a backward diode is made of a compound semiconductor material on a semi-insulating GaAs substrate, a conductive thin film is formed on the GaAs substrate to make electrical contact. In this case, there is a problem that it is difficult to reduce the resistance because InAs having a narrow band gap cannot be used due to the lattice matching restriction of the semiconductor material. In addition, the parasitic capacitance cannot be sufficiently reduced due to processing restrictions on the conductive thin film.

  An object of the present invention is to provide an electronic device with reduced resistance and parasitic capacitance, excellent sensitivity and high frequency characteristics, and a method for manufacturing the same.

In one aspect of the present invention, the electronic device is
A semi-insulating semiconductor substrate;
An insulating film disposed on the semiconductor substrate and having an opening region in which a plurality of submicron-sized openings are formed; and a hole provided at an end of the opening region;
A conductive thin film disposed in the opening region on the insulating film;
A first nanowire extending from the surface of the semiconductor substrate in the hole in a direction perpendicular to the substrate surface;
Have
The first nanowire has the same conductivity type and the same composition as the conductive thin film,
The conductive thin film fills the opening and is connected to the first nanowire on the insulating film.

  Resistors and parasitic capacitance are reduced, and an electronic device having excellent sensitivity and high frequency characteristics is realized.

It is a figure explaining the problem when forming a conductive thin film and nanowire on a semi-insulating semiconductor substrate. It is a figure explaining the effect | action of the electronic device of embodiment. 1 is a diagram illustrating a configuration example of an electronic device according to Example 1. FIG. 6 is a manufacturing process diagram of the electronic device of Example 1. FIG. 6 is a manufacturing process diagram of the electronic device of Example 1. FIG. It is a figure which shows the example of the opening shape of the opening part area | region which forms a conductive thin film. It is a figure which shows the modification for a capacity reduction. 6 is a diagram illustrating a configuration of an electronic device of Example 2. FIG. 6 is a diagram illustrating a configuration of an electronic device of Example 3. FIG. It is a schematic diagram of the radio wave receiver used with a radio | wireless communications system as an application example of the electronic device of embodiment. It is a schematic diagram of the generator of an IoT (Internet of Things) sensor as an application example of the electronic device of the embodiment.

  In the embodiment, an electronic device using nanowires and a manufacturing method thereof are provided. The electronic device of the embodiment is useful for devices that handle low power and / or high frequency, and is particularly effective in improving high frequency reception (detection) performance in wireless communication and radio wave power generation.

  FIG. 1 is a diagram for explaining problems when the conductive thin film 105 and the nanowire diode 200 are formed on a semi-insulating semiconductor substrate. A case where a GaAs substrate 101 which is a general-purpose compound semiconductor substrate is used as a semi-insulating semiconductor substrate will be described.

  In order to electrically connect the nanowire diode 200 to the lower electrode 103, a conductive thin film 105 is formed on the semi-insulating GaAs substrate 101. The conductive thin film 105 connected to the nanowire diode 200 is required to be a semiconductor thin film having good crystallinity and free from defects such as dislocations. InGaAs is a material that is close in nature to GaAs and has a narrow band gap. For example, an n-type InGaAs thin film is grown as the conductive thin film 105. The nanowire diode 200 is formed of a nanowire 201 of n-type InAs (may be labeled “n-InAs”) connected to the conductive thin film 105 and a nanowire 202 of a p-type compound semiconductor.

  From the viewpoint of reducing the resistance of the device, it is desirable to use InGaAs having a composition ratio of indium (In) as large as possible as the conductive thin film 105. However, due to the effect of lattice mismatch between InGaAs and GaAs, there is a limit between the film thickness that can be stacked while maintaining good crystallinity and the composition of In. For example, in order to obtain a film thickness of about 100 nm required for the conductive thin film 105, it is a limit to use InGaAs having an In composition of at most 5%. When InGaAs having an In composition higher than 5% is used, dislocations for releasing strain are generated at a high density during film formation, and the crystallinity is deteriorated, so that device performance is impaired.

  In terms of capacity, when the conductive thin film 105 is processed to remove unnecessary portions by etching, etching is performed sufficiently away from the nanowires 201 and 202 from the viewpoint of protection of the nanowires 201 and 202 and lithography accuracy. . For this reason, it is difficult to sufficiently reduce the parasitic capacitance. Further, since the epitaxial substrate on which the conductive thin film 105 is formed is prepared prior to the growth of the nanowire 201, the process becomes complicated.

  FIG. 2 is a diagram for explaining the operation of the electronic device using the nanowire element 20 of the embodiment. The nanowire element 20 extends from the surface of the semi-insulating semiconductor substrate 11 in a longitudinal direction (a direction perpendicular to the substrate surface), and is disposed on the semiconductor substrate 11 with an insulating film 12 interposed therebetween. Electrically connected. The insulating film 12 has an opening region 14 in which a plurality of submicron-sized openings 13 are formed, and a single hole 132 having a submicron diameter formed at an end of the opening region 14. The opening 13 and the hole 132 penetrate the insulating film 12 and reach the semiconductor substrate 11. The diameter of the hole 132 is, for example, 100 nm to 500 nm from the viewpoint of securing a space for arranging the nanowire growth catalyst and obtaining the mechanical strength of the nanowire. The opening 13 may have a diameter or a maximum width in at least one direction that is a submicron size.

  The conductive thin film 15 grows in the opening region 14 starting from the surface of the semiconductor substrate 11 in the opening 13 and spreads in the lateral direction (in-plane direction) on the surface of the insulating film 12. A portion of the conductive thin film 15 that fills the opening 13 is a leg 151 connected to the semiconductor substrate 11.

  The nanowire element 20 extends in the direction (longitudinal direction) perpendicular to the substrate surface, starting from the surface of the semiconductor substrate 11 inside the single hole 132. The nanowire element 20 includes a nanowire 21 and a nanowire 22 that are bonded in a direction perpendicular to the substrate surface of the semiconductor substrate 11. The nanowire 21 has the same composition and the same conductivity type as the conductive thin film 15 and is connected to the conductive thin film 15. The nanowire 22 has a composition different from that of the nanowire 21 and a different conductivity type. The interface between the nanowire 21 and the nanowire 22 is a heterojunction.

  By disposing the catalyst inside the hole 132, the growth of the nanowire 21 in the vertical direction is promoted when the conductive thin film 15 and the nanowire 21 are simultaneously formed by crystal growth. Due to the lateral growth of the conductive thin film 15 on the insulating film 12, the conductive thin film 15 and the nanowire 21 are electrically connected at the end of the opening region 14. A metal electrode pad or lower electrode 27 is disposed on a part of the conductive thin film 15 and serves as a connection terminal to the outside.

  According to this configuration, even when an inexpensive GaAs substrate is used as the semi-insulating semiconductor substrate 11 and InGaAs having a large In composition is used as the conductive thin film 15, the conductive thin film 15 and the nanowire element 20 having good crystallinity are used. Can be obtained. Further, the conductive thin film 15 can be grown in a desired area and shape. As a result, electric resistance and parasitic capacitance can be reduced.

  Here, the crystal growth mechanism in the formation region of the conductive thin film 15, that is, the opening region 14 in which the plurality of openings 13 are formed will be described. Inside the submicron-diameter opening 13, the semiconductor crystal can release the strain in the lateral direction. For this reason, even with a lattice mismatch material, crystal growth proceeds upward (in a direction perpendicular to the substrate surface) while suppressing the occurrence of dislocations due to strain accumulation. Thereafter, when the open space on the insulating film 12 is reached, the crystal grows not only in the direction perpendicular to the substrate surface but also in the horizontal direction (lateral direction or in-plane direction). By appropriately selecting the growth conditions, it is possible to change the growth rate ratio between the upward direction and the lateral direction, and to make the lateral growth dominant.

  The growth on the insulating film 12 proceeds without dislocation because there is no element to be constrained. By further promoting the lateral growth, the crystals grown from the openings 13 are connected to each other. At this time, the crystal material grown from each opening 13 is the same material, and the base GaAs substrate is a single crystal, and the crystal from each opening 13 portion inherits its crystal orientation. A single crystal conductive thin film 15 can be obtained.

On the other hand, in the inside of the single hole 132 subjected to the gold (Au) catalyst, the growth rate is higher than that of the other openings 13 by the effect of the Au catalyst. Also on the insulating film 12, the nanowire 21 can be formed because the growth selectively proceeds upward due to the effect of the Au catalyst. The nanowire 21 and the conductive thin film 15 are connected when the growth of the conductive thin film 15 proceeds in the lateral direction.
The condition that the plurality of openings 13 have a submicron size may be a submicron order in at least one direction. For example, a slit-like opening 13 having a submicron width or a lattice-like opening 13 may be used. In the case where the opening 13 is formed by a hole such as a circle or a polygon, the size of the opening 13 is limited over the entire circumference, which is more preferable in that a dislocation-free conductive thin film 15 is formed. The specific shape of the opening 13 will be described later.
The reason why the crystal releases the strain laterally in the submicron diameter opening 13 will be described. The release of strain in the lateral direction is a phenomenon characteristic of crystal growth in submicron diameter openings. First, a thin film growth on a substrate whose opening is not limited will be described microscopically.

  When the growth raw material is supplied onto the substrate, an atomic layer disk having a bottom surface size of about 30 nm to 50 nm is formed as an initial nucleus for growth. Thereafter, step flow growth is caused to the initial nucleus (atomic layer disk), and the terrace is widened to form a thin film. At this time, the thin film is bonded so as to be restrained by atoms of the underlying substrate. Therefore, when the thin film is a strained material, an amount of strain corresponding to lattice mismatch with the substrate is accumulated in the lateral direction (in-plane direction of the substrate).

  Next, the growth in the submicron-diameter opening 13 will be viewed microscopically. The atomic layer disk of the initial nucleus is formed in the opening 13, and the same is true until the thin film disk expands until it approaches the diameter of the opening 13. However, due to the presence of the insulating film 12 forming the inner wall of the opening 13, the lateral growth of the thin film disk stops before contacting the insulating film 12. At this time, there is no bond between the thin film and the wall of the insulating film 12, and no force is applied from the insulating film 12 to the thin film. Therefore, the periphery of the disk acts as a strain free end. Further, since the element itself that is subjected to strain is also limited to a small contact surface with the substrate, the total strain energy can be greatly reduced as compared with the thin film formed on the released substrate surface. By reducing the strain, the conductive thin film 15 spreading from the openings 13 onto the insulating film 12 has good crystallinity with few dislocations and can have low electrical resistance.

  In the configuration of the embodiment, the conductive thin film 15 with good crystallinity in which dislocations are suppressed is formed, and the nanowire 21 formed of the same material and the same composition as the conductive thin film 15 is connected to the conductive thin film 15. The resistance of the entire device can be reduced. In addition, by appropriately limiting the size and shape of the opening region 14 for forming the plurality of openings 13, the conductive thin film 15 can be disposed only in the region for forming the electrode pad or the lower electrode 27, and parasitic capacitance can be reduced. Can be reduced. Therefore, taking advantage of the sensitivity and high-frequency characteristics of the nanowire element 20, the performance of the device using the nanowire element 20 can be improved. Furthermore, since the conductive thin film 15 and the nanowire 21 can be formed by batch growth, an electronic device can be manufactured without using a special substrate on which an epi film has been applied in advance.

  FIG. 3 illustrates a configuration example of the electronic device 10 according to the first embodiment. The electronic device 10 is based on the configuration of FIG. The electronic device 10 includes a nanowire backward diode 120 as an example of a nanowire element. The backward diode has a sharp rise in conduction in a low voltage range, and is suitable for a high frequency device such as a detector or a high frequency rectifier.

  The nanowire backward diode 120 is formed by bonding an n-InAs nanowire 121 and a p-type GaAsSb nanowire 122 (which may be referred to as “p-GaAsSb”). The n-InAs nanowire 121 and the p-GaAsSb nanowire 122 are bonded in a direction perpendicular to the substrate surface, and the bonding interface is a heterojunction.

  The nanowire backward diode 120 is formed on the semi-insulating semiconductor substrate 11. A semi-insulating GaAs (111) B substrate is used as the semiconductor substrate 11. An n-InAs conductive thin film 15 is formed in a partial region of the insulating film 12 formed on the semiconductor substrate 11. The n-InAs nanowire 121 is connected to the conductive thin film 15 and is connected to the surface of the semiconductor substrate 11 through the insulating film 12.

  A lower electrode 27 is disposed on a part of the conductive thin film 15, and a p-GaAsSb thin film 23 is disposed on the conductive thin film 15 excluding a region where the lower electrode 27 is disposed. The p-GaAsSb thin film 23 is formed on the conductive thin film 15 simultaneously with the growth of the p-GaAsSb nanowire 122 as described later.

  The nanowire 122 of p-GaAsSb is connected to the positive electrode 36 on the insulating film 31. The lower electrode 27 is connected to the negative electrode 35 on the insulating film 31 through the via contact 33. By applying a reverse bias voltage to the negative electrode 35 and the positive electrode 36, electrons flow from the valence band of p-type GaAsSb to the conduction band of n-type InAs. Since the resistance of the n-InAs nanowire 121 and the conductive thin film 15 is reduced and the parasitic capacitance is also reduced, the operating characteristics of the nanowire backward diode 120 are good.

4 and 5 show a manufacturing process of the electronic device 10 of FIG. In FIG. 4A, an insulating film 12 serving as a growth mask is formed on a semi-insulating GaAs (111) B substrate as the semiconductor substrate 11. As the insulating film 12, for example, a silicon nitride (SiN) film having a thickness of 50 nm is deposited. Instead of the SiN film, a silicon oxide (SiO ₂ ) film or other insulating film may be used. A plurality of openings 13 for forming a conductive thin film and holes 132 for forming nanowires are formed in a predetermined region of the insulating film 12 by lithography. The region where the plurality of openings 13 are formed becomes the opening region 14. The hole 132 is located at the end of the opening region 14. A metal thin film to be a metal catalyst 19 for nanowire growth is deposited in the hole 132. The diameter of the metal thin film disk is preferably 20 to 100 nm. The material of the metal catalyst 19 is, for example, gold (Au). Thereby, the substrate for crystal growth is completed.

In FIG. 4B, n-InAs is grown at a growth temperature of 400 to 450 ° C. by MOCVD, for example. As source gas, for example, trimethyindium (TMIn) and arsine (AsH ₃ ) are used. For n-type doping, hydrogen sulfide (H ₂ S) is supplied during growth to dope sulfur (S). The S concentration is, for example, 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ . During the crystal growth, inside the plurality of openings 13 without the metal catalyst, n-InAs first grows upward (in a direction perpendicular to the substrate surface) without any lateral distortion and goes out of the openings 13. The conductive thin film 15 is formed in the opening region 14 by growing in the lateral direction (in-plane direction). Inside the hole 132 having a metal catalyst, n-InAs nanowires 121 grow. Crystal growth is performed so that the length of the nanowire 121 becomes 1 μm. The thickness of the conductive thin film 15 formed in the opening region 14 simultaneously with the growth of the nanowire 121 can be adjusted by the area ratio of the opening 13 in the opening region 14 to the mask (insulating film 12). For example, the area ratio is adjusted so that the thickness of the conductive thin film 15 is 100 nm.

In FIG. 4C, p-GaAsSb is grown at a growth temperature of 500 to 550 ° C., for example. For example, triethylgallium (TEGa), arsine (AsH ₃ ), or trimethylantimony (TMSb) is used as the source gas. For p-type doping, diethyl zinc (DEZn) is supplied during growth to dope Zn. The Zn concentration is, for example, 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ . The amount of crystal growth is such that the p-GaAsSb nanowire 122 grows by 1 μm on the n-InAs nanowire 121. At this time, a p-GaAsSb thin film 23 having a thickness of 100 nm is formed on the conductive thin film 15 in the opening region 14. The thin film 23 of p-GaAsSb and the nanowire 122 of p-GaAsSb are not electrically connected because the n-InAs nanowire 121 is interposed therebetween. By appropriately controlling the doping concentration and the band gap, a tunnel junction is formed at the interface between the n-InAs nanowire 121 and the p-GaAsSb nanowire 122, and can function as a backward diode.

  In FIG. 4D, a part of the p-GaAsSb thin film 23 is removed, and a metal pad or a lower electrode 27 is formed on the conductive thin film 15 of n-InAs. For example, AuGe is used as the metal material of the lower electrode 27.

In FIG. 5A, the entire surface is embedded with an insulating film 31 such as a resin. Before embedding with the insulating film 31, a protective film having a film thickness of, for example, 5 to 10 nm may be formed around the nanowires 121 and 122 by ALD (Atomic Layer Deposition) in order to protect the nanowires. As the protective film, for example, an Al ₂ O ₃ film is used.

  In FIG. 5B, an opening is formed at a predetermined position of the insulating film 31 by dry etching, the lower electrode 27 is exposed, and a metal (for example, Au) is buried in the opening to form a via contact 33.

  In FIG. 5C, the insulating film 31 is etched until the top of the nanowire 122 is exposed, so that a positive electrode 36 and a negative electrode 35 are formed on the insulating film 31. The positive electrode 36 is connected to the end face of the exposed p-GaAsSb nanowire 122. The negative electrode 35 is electrically connected to the conductive thin film 15 and the n-InAs nanowire 121 via the via contact 33 and the lower electrode 27. Thereafter, the capacity may be further reduced by removing the unnecessary insulating film 31, for example.

  In the manufacturing process described above, the nanowire backward diode 120 is formed of one nanowire grown from, for example, a hole 132 having a diameter of 100 nm, but is not limited thereto. The nanowire backward diode 120 may be formed by expanding the diameter of the hole 132 and growing a plurality of nanowires 121 using an n-type semiconductor and continuously growing a plurality of nanowires 122 using a p-type semiconductor. In this case, the mechanical strength of the nanowire backward diode 120 can be increased. The constituent material of the nanowire backward diode 120 is not limited to the heterojunction of n-InAs and p-GaAsSb, and a known combination can be used. For example, a heterostructure of p-GaSb / i-GaAs / n-InGaAs may be used.

  FIG. 6 shows an example of the shape of the plurality of openings 13 formed in the opening region 14. In FIG. 6A, a plurality of circular openings 13a are arranged in the opening region 14a. The opening region 14a tapers in the direction of the hole 132 in which the metal catalyst 19 serving as a catalyst is disposed, and a plurality of circular openings 13a are formed at a predetermined pitch without the opening region 14a. The diameter of the opening 13a is a submicron diameter, for example, 200 nm or less, and more preferably 20 nm to 100 nm. By setting the diameter of the opening 13a to 200 nm or less, the conductive thin film 15 with few defects and good crystallinity can be formed.

As described above, the semiconductor crystal can release strain in the lateral direction (in-plane direction) inside the submicron-diameter opening 13a. The smaller the diameter of the opening, the smaller the constrained area between the semi-insulating semiconductor substrate 11 and the in-plane strain is released, and a uniform crystal grows in a direction perpendicular to the substrate. From the experimental data curve of critical diameter as a function of lattice mismatch (%) shown in Non-Patent Document 2, the inventor found that In _0.3 Ga _0.7 As (strain) is a practical compound semiconductor material. 2%) was analyzed to be 200 nm or less in diameter, which can be formed without dislocation in the opening 13a. When the diameter of the opening 13a is 100 nm or less, there is one initial nucleus for crystal growth per opening, and the probability of defect generation due to coalescence of initial nuclei inside the opening 13a can be made almost zero. it can. Therefore, it is more desirable that the diameter of the opening 13a be 100 nm or less. On the other hand, when the diameter of the opening 13a is less than 20 nm, it is difficult to ensure a sufficient area for forming one initial nucleus. Therefore, the diameter of the opening 13a is desirably 20 nm to 200 nm, and more preferably in the range of 20 nm to 100 nm.

  In FIG. 6B, a plurality of hexagonal openings 13b are formed in the opening region 14b. Also in FIG. 6C, a plurality of hexagonal openings 13c are formed in the opening region 14c. 6B and 6C, the direction in which the apex angle of the hexagon is directed to the hole 132 in which the metal catalyst 19 is disposed is different. In either case, the apex angle of the hexagonal opening is different. Are arranged so as to face the [110] direction of the semiconductor substrate 11. Since the orientation of the semiconductor substrate 11 is different between FIG. 6B and FIG. 6C, the directions of the apex angles of the opening 13b and the opening 13c with respect to the hole 132 for nanowire formation are different. When the conductive thin film 15 is formed of a wurtzite crystal by arranging the opening 13b and the opening 13c so that the apex angle of the hexagon faces a direction parallel to the [110] direction, [11-20] Crystals coalesce in the direction. In this case, the conductive thin film 15 having particularly good crystallinity can be obtained due to the effect peculiar to the wurtzite crystal.

  In FIG. 6D, a slit-like opening 13d is formed in the opening region 14d, and in FIG. 6E, a slit-like opening 13e is formed in the opening region 14e. Although the major axis direction of the slit differs between the opening 13d and the opening 13e, the major axis of the slit may be directed in any direction as long as the opening diameter is submicron in at least one direction of the opening. In the example of FIG. 6D and FIG. 6E, the direction in which the size of the opening is limited is limited to one direction. Therefore, in the opening compared to FIGS. 6A to 6C. Although the effect of releasing the strain is slightly reduced, the effect of releasing the strain and improving the crystallinity can be obtained by appropriately selecting the width, pitch, length, etc. of the slit-like opening.

  In FIG. 6F, a lattice groove-like opening 13f is formed in the opening region 14f. When the opening patterns of FIG. 6D and FIG. 6E are added, the opening pattern of FIG. 6F is obtained. In FIG. 6F, since the number of places where the size of the opening is limited increases, the effect of strain release can be improved as compared with FIGS. 6D and 6E.

  6D to 6F, the width of the openings 13d to 13f is 200 nm or less, more preferably 20 to 100 nm, so that a crystal with few defects can be grown in the openings. In addition to the example shown in FIG. 6, the plurality of openings 13 may be elliptical holes. In this case, at least the diameter in the minor axis direction may be submicron, preferably 20 nm to 200 nm, more preferably 20 nm to 100 nm. As the polygon, in addition to the hexagon, any shape such as a quadrangle, a pentagon, and an octagon can be adopted.

  6A to 6F, the interval between the openings can be adjusted as appropriate. By making the distance d1 from the hole 132 for forming the nanowire to the nearest opening 13 larger than the distance d2 between the adjacent openings 13 in the opening region 14, the interference of the growth of the nanowire 121 and the conductive thin film 15 at the initial stage of growth. Is suppressed. In the opening region 14, when the distance between adjacent openings 13 is 200 nm or less, good adhesion to the semiconductor substrate 11 is obtained, and a continuous film is formed on the insulating film 12 at an early stage of growth. There is a merit that

  In FIG. 6, the shape of the opening regions 14 a to 14 f is a pentagonal shape whose apex faces in the direction of the nanowire forming hole 132, but is not limited to this example. Since it is only necessary to reduce the influence of the parasitic capacitance on the nanowire, a region such as a triangle or a diamond having a vertex in the direction of the hole 132 may be used. By making the shape of the opening region 14 a shape whose apex is directed in the direction of the hole 132 for forming the nanowire, the conductive thin film 15 formed in the opening region 14 is n-InAs in a state close to a point contact or a line contact. This is connected to the nanowire 121 and the parasitic capacitance can be reduced.

<Modification>
FIG. 7 shows a modification of FIG. In FIG. 2, the conductive thin film 15 is a thin film that is in contact with the surface of the insulating film 12 and is continuous in the in-plane direction. In FIG. 7, the conductive thin film 15 is continuously extended in the in-plane direction while maintaining a space 16 between the surface of the insulating film 12. The space 16 can be provided by appropriately controlling the growth conditions such as promoting crystal growth in a direction perpendicular to the substrate surface outside the opening 13 and then promoting growth in the lateral direction. For example, in the first half of the growth, the V / III ratio (partial pressure ratio or molecular number ratio of the Group V and Group III raw materials supplied to the reactor) is set low to promote growth in the direction perpendicular to the substrate from the opening 13. . Thereafter, the V / III ratio is increased to promote lateral (in-plane) growth. As an example, the V / III ratio may be increased by using tributylarsenic (TBAs) as the source gas in the first half of growth and using arsine (AsH ₃ ) as the source gas in the second half of the growth. The configuration of FIG. 7 is preferable in terms of reducing the capacity.
The conductive thin film 15 is connected to the nanowire 21 in a state close to a point contact or a line contact by making the shape of the opening region 14 of the insulating film 12 taper toward the hole 132 for forming the nanowire. This is the same as the above-described embodiment.

  FIG. 8 illustrates a configuration example of the electronic device 10A according to the second embodiment. The electronic device 10A uses a Schottky junction instead of the nanowire PN junction. The electronic device 10A includes a Schottky barrier diode 120A as a nanowire element.

  The Schottky barrier diode 120 </ b> A includes an n-InAs nanowire 121 and a Schottky barrier formed in the interface region 41 between the nanowire 121 and the metal electrode 36. A Schottky junction is formed when the work function of the electrode 36 is larger than the work function of the n-InAs nanowire 121.

  The n-InAs nanowire 121 grows from the surface of the semi-insulating semiconductor substrate 11 inside the hole 132 formed in the insulating film 12, as in the first embodiment, and the n-InAs on the insulating film 12. The conductive thin film 15 is connected. The n-InAs conductive thin film 15 is grown from the surface of the semi-insulating semiconductor substrate 11 in the plurality of openings 13 formed in the opening region 14 of the insulating film 12 as in the first embodiment. In the opening region 14 on the insulating film 12, it extends in the in-plane direction.

  A lower electrode 27 is disposed on a part of the conductive thin film 15, and the lower electrode 27 is connected to an electrode 35 on the insulating film 31 through a via contact 33. The entire substrate on which the n-InAs nanowires 121, the conductive thin film 15, and the lower electrode 27 are formed is filled with an insulating film 31, a via hole reaching the lower electrode 27 is formed, a metal is buried in the via hole, and a via plug 33 is formed. Form. Then, the thickness of the insulating film 31 is reduced and planarized until the upper end of the n-InAs nanowire 121 is exposed. An electrode 35 connected to the via plug 33 and an electrode 36 connected to the upper surface of the n-InAs nanowire are formed of metal.

By applying a forward bias voltage to the electrodes 35 and 36, electrons that have passed the Schottky barrier flow from the n-InAs nanowire 121 to the electrode 36. When a reverse bias voltage is applied, the current is less likely to flow in the forward direction due to the presence of the Schottky barrier. As a result, a diode characteristic in which a large amount of current flows in the forward direction (has rectification) can be obtained.
The electronic device 10A includes a conductive thin film 15 having good crystallinity that is grown from a plurality of openings 13 and is continuous in the in-plane direction. The conductive thin film 15 is formed of the same material and the same composition as the nanowire 121 and is connected to the nanowire 121 in a state close to a point contact or a line contact. This provides a high performance nanowire device with reduced resistance and parasitic capacitance.

  FIG. 9 illustrates a configuration example of the electronic device 10B according to the third embodiment. The electronic device 10B includes a transistor using the nanowire element 120B. In the nanowire element 120B, as shown in FIG. 9B, an n-InAs nanowire 121 and a p-GaAsSb nanowire 122 are bonded in a direction perpendicular to the substrate, and an insulating thin film is formed on the outer periphery of the nanowires 121 and 122. 125 is formed.

The insulating thin film 125 is an Al ₂ O ₃ film having a thickness of 5 to 10 nm formed by an ALD method as an example, and functions as a gate insulating film. As shown in FIG. 9A, the electronic device 10B includes a gate electrode 51, a source electrode 52, and a drain electrode 53. The gate electrode 51 is connected to a position corresponding to the pn junction 126 of the nanowire element 120 </ b> B via the via plug 46 and the horizontal wiring 45. A gate voltage is applied from the gate electrode 51 to the pn junction 126 via the insulating thin film 125.

  The rest of the configuration except for the transistor configuration is the same as that of the first embodiment, and a duplicate description is omitted. Also in Example 3, the nanowire 121 is connected to the conductive thin film 15 having good crystallinity that is grown from the plurality of openings 13 and is continuous in the in-plane direction, so that a transistor having a low resistance and a low parasitic capacitance can be obtained. it can.

<Application examples of electronic devices>
FIG. 10 is a schematic diagram of the radio wave receiver 60 of the large-capacity wireless communication system including the nanowire diode of the embodiment. The radio wave receiver 60 includes a reception antenna 61, a low noise amplifier 62 connected to the reception antenna, a nanowire diode 130 connected to the low noise amplifier 62, an inductor 63 connected to the low noise amplifier 62, and an output terminal.

  The radio wave received by the receiving antenna 61 is amplified by the low noise amplifier 62, half-wave rectified by the nanowire diode 130, impedance-matched by the inductor 63, and output from the output terminal. As the nanowire diode 130, for example, the nanowire element 20 of FIG. 2 or the nanowire backward diode 120 of Example 1 can be used.

  The nanowire diode 130 has a smaller junction capacitance than conventional diodes, and can receive radio waves up to the terahertz wave band region. In addition, when a plurality of nanowires are used in a bundle, it has sufficient mechanical strength. The mechanical strength and excellent high frequency characteristics of the nanowire diode 130 realize a highly reliable large-capacity wireless communication network system.

  FIG. 11 is a schematic view of a so-called IoT (Internet of Things) sensor generator 70 including the nanowire diode of the embodiment. The generator 70 includes a receiving antenna 71, nanowire diodes 130-1 and 130-2 connected to the receiving antenna 71, a smoothing capacitor 72 connected to the nanowire diodes 130-1 and 130-2, and nanowire diodes 130-1 and 130. -2 is connected to the voltage stabilization circuit 73 and the output terminal.

  The receiving antenna 71 is an antenna that receives, for example, microwaves as energy. The nanowire diodes 130-1 and 130-2 are alternately conducted, and full-wave rectification of the microwave incident from the receiving antenna 71 is performed. The smoothing capacitor 72 provides a stable DC (direct current) output. The voltage stabilizing circuit 73 sets the DC output to a constant value. The output terminal is connected to the power source of the IoT sensor, and the DC output that has been rectified and has a constant value is supplied to the power source of the IoT sensor.

  Even in the configuration of FIG. 11, the nanowire diodes 130-1 and 130-2 can harvest minute electric power such as microwaves with high energy conversion efficiency by the mechanical strength and excellent high frequency characteristics. Thereby, the IoT sensor which can be operated with low power can be driven without using a battery or the like.

  As mentioned above, although this invention was demonstrated based on specific embodiment, this invention is not limited to these examples, You may combine the structure of each Example arbitrarily. For example, the nanowire backward diode 120 of Example 1 and the nanowire transistor of Example 3 may be formed simultaneously to produce an electronic device having a nanowire diode and a nanowire transistor. Further, in the electronic device 10A of FIG. 8 and the electronic device 10B of FIG. 9, a space 16 may be provided between the insulating film 12 and the conductive thin film 15 as shown in FIG. 7 to reduce the parasitic capacitance.

For the above explanation, the following notes are presented.
(Appendix 1)
A semi-insulating semiconductor substrate;
An insulating film disposed on the semiconductor substrate and having an opening region in which a plurality of submicron-sized openings are formed; and a hole provided at an end of the opening region;
A conductive thin film disposed in the opening region on the insulating film;
A first nanowire extending from the surface of the semiconductor substrate in the hole in a direction perpendicular to the substrate surface;
Have
The first nanowire has the same conductivity type and the same composition as the conductive thin film,
The electronic device is characterized in that the conductive thin film fills the inside of the opening and is connected to the first nanowire on the insulating film.
(Appendix 2)
2. The electronic device according to appendix 1, wherein a space is provided between the insulating film and the conductive thin film.
(Appendix 3)
A second nanowire bonded to the first nanowire in a direction perpendicular to the substrate surface and having a composition different from that of the first nanowire and a different conductivity type;
The electronic device according to appendix 1 or 2, further comprising:
(Appendix 4)
An insulating thin film covering the outer periphery of the first nanowire and the second nanowire;
A gate electrode connected to the junction of the first nanowire and the second nanowire via the insulating thin film;
The electronic device according to appendix 3, further comprising:
(Appendix 5)
A metal layer in contact with an upper end surface of the first nanowire;
The electronic device according to appendix 1 or 2, further comprising: a Schottky barrier formed at an interface between the first nanowire and the metal layer.
(Appendix 6)
The electronic device according to any one of appendices 1 to 5, wherein the opening region has a tapered shape toward the hole.
(Appendix 7)
The electronic device according to appendix 6, wherein the conductive thin film and the nanowire are connected by point contact or line contact.
(Appendix 8)
The electronic device according to any one of appendices 1 to 7, wherein the opening has a circular, elliptical, or polygonal shape.
(Appendix 9)
The electronic device according to appendix 8, wherein the opening has a diameter of 20 nm to 200 nm.
(Appendix 10)
The electronic device according to appendix 8 or 9, wherein the opening is a hexagonal opening, and an apex angle of the opening is in a direction parallel to a [110] direction of the semiconductor substrate.
(Appendix 11)
The electronic device according to any one of appendices 1 to 7, wherein the opening is a slit or a lattice groove.
(Appendix 12)
The electronic device according to appendix 11, wherein a maximum width of the slit or the grating groove is 20 nm to 200 nm.
(Appendix 13)
The electronic device according to any one of appendices 1 to 12, wherein a distance from the hole to the nearest opening in the opening region is larger than a distance between adjacent openings in the opening region.
(Appendix 14)
14. The electronic device according to any one of appendices 1 to 13, wherein an interval between the plurality of openings is 200 nm or less.
(Appendix 15)
On the semi-insulating semiconductor substrate, an insulating film having an opening region in which a plurality of submicron-sized openings are formed and a hole provided at an end of the opening region is formed.
Placing a metal catalyst in the hole,
Growing a semiconductor crystal of a first conductivity type from the surface of the semiconductor substrate inside the opening and the hole;
A conductive thin film grown from the inside of the opening and continuously extending in a direction parallel to the insulating film in the opening region is grown from the inside of the hole in a direction perpendicular to the surface of the semiconductor substrate. Connect to nanowires,
The manufacturing method of the electronic device characterized by the above-mentioned.
(Appendix 16)
The first conductivity type semiconductor crystal is grown in a direction perpendicular to the surface of the semiconductor substrate from the opening beyond the surface of the insulating film and then in a direction parallel to the surface of the semiconductor substrate. And forming the conductive thin film,
Forming a space between the conductive thin film and the surface of the insulating film;
The method for manufacturing an electronic device according to Supplementary Note 15, wherein:
(Appendix 17)
Growing a semiconductor crystal of a second conductivity type different from the first conductivity type on the conductive thin film and the first nanowire;
Item 17. The method for manufacturing an electronic device according to Item 15 or 16, wherein
(Appendix 18)
Growing a second nanowire of the second conductivity type on the first nanowire;
Coating the outer periphery of the first nanowire and the second nanowire with an insulating thin film;
Forming a gate electrode connected to a junction of the first nanowire and the second nanowire through the insulating thin film;
18. The method for manufacturing an electronic device according to appendix 17, wherein:
(Appendix 19)
The method of manufacturing an electronic electric field chair according to appendix 15 or 16, wherein a metal layer that contacts the upper end surface of the first nanowire is formed.

1, 2, 3 Optical transmitter 10, 10A, 10B Electronic device 11 Semiconductor substrate 12, 31 Insulating film 13 Opening 14 Opening region 15 Conductive thin film 16 Space 19 Metal catalyst 20, 120B Nanowire element 21, 121 Nanowire (first wire Nanowire)
22, 122 nanowire (second nanowire)
23 Thin film 27 Lower electrode 33 Via contact 35 Electrode 36 Electrode (metal layer)
45 Horizontal wiring 46 Via plug 51 Gate electrode 52 Source electrode 53 Drain electrode 60 Radio wave receivers 61 and 71 Receiving antenna 62 Low noise amplifier 63 Inductor 70 Generator 72 Smoothing capacitor
73 Voltage stabilization circuit 120 Nanowire backward diode 125 Insulating thin film 126 pn junction 120A Schottky barrier diode 130, 130-1, 130-2 Nanowire diode 132 Hole 151 Leg

Claims (8)

A semi-insulating semiconductor substrate;
An insulating film disposed on the semiconductor substrate and having an opening region in which a plurality of submicron-sized openings are formed; and a hole provided at an end of the opening region;
A conductive thin film disposed in the opening region on the insulating film;
A first nanowire extending from the surface of the semiconductor substrate in the hole in a direction perpendicular to the substrate surface;
Have
The first nanowire has the same conductivity type and the same composition as the conductive thin film,
The electronic device is characterized in that the conductive thin film fills the inside of the opening and is connected to the first nanowire on the insulating film.   The electronic device according to claim 1, wherein a space is provided between the insulating film and the conductive thin film. A second nanowire bonded to the first nanowire in a direction perpendicular to the substrate surface and having a composition different from that of the first nanowire and a different conductivity type;
The electronic device according to claim 1, further comprising: An insulating thin film covering the outer periphery of the first nanowire and the second nanowire;
A gate electrode connected to the junction of the first nanowire and the second nanowire via the insulating thin film;
The electronic device according to claim 3, further comprising: A metal layer in contact with an upper end surface of the first nanowire;
The electronic device according to claim 1, further comprising: a Schottky barrier formed at an interface between the first nanowire and the metal layer.   The distance from the said hole to the nearest opening in the said opening area | region is larger than the distance between the adjacent openings in the said opening area | region, The Claim 1 characterized by the above-mentioned. Electronic devices. On the semi-insulating semiconductor substrate, an insulating film having an opening region in which a plurality of submicron-sized openings are formed and a hole provided at an end of the opening region is formed.
Placing a metal catalyst in the hole,
Growing a semiconductor crystal of a first conductivity type from the surface of the semiconductor substrate inside the opening and the hole;
A conductive thin film grown from the inside of the opening and continuously extending in a direction parallel to the insulating film in the opening region is grown from the inside of the hole in a direction perpendicular to the surface of the semiconductor substrate. Connect to nanowires,
The manufacturing method of the electronic device characterized by the above-mentioned. The first conductivity type semiconductor crystal is grown in a direction perpendicular to the surface of the semiconductor substrate from the opening beyond the surface of the insulating film and then in a direction parallel to the surface of the semiconductor substrate. And forming the conductive thin film,
Forming a space between the conductive thin film and the surface of the insulating film;
The method of manufacturing an electronic device according to claim 7.

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