JP2019004669A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device which can improve a switching loss and a steady loss and inhibit deterioration in improvement effect on a loss, which is caused by decrease in switching speed.SOLUTION: A semiconductor device comprises a switching element including a MOSFET 1 and an IGBT 2, a first conditioning circuit 23 and a second conditioning circuit 24. The first conditioning circuit 23 and the second conditioning circuit 24 drive the MOSFET 1 at the time of turn-on and turn-off of the switching element, and drive the IGBT 2 at the time of stationary current carrying of the switching element; and a source electrode of the MOSFET 1 and en emitter electrode of the IGBT 2 are connected to control emitter wiring 8 extending from an emitter terminal Es and the source electrode of the MOSFET 1 is arranged in a peripheral region of the emitter terminal Es.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power semiconductor device in which power semiconductor elements having different characteristics are connected in parallel.

  Conventionally, high-speed power semiconductor devices have only high-speed switching elements, and low-speed power semiconductor devices have only low-speed switching elements. Conventional power semiconductor devices have been designed for high-speed specifications and low-speed specifications based on the trade-off between switching loss and steady-state loss. For this reason, steady loss was sacrificed for the high-speed specification, and switching loss was sacrificed for the low-speed specification.

  For example, Patent Document 1 discloses a technique for improving both steady loss and switching loss by connecting MOSFETs and IGBTs having different characteristics in parallel.

JP 2002-165439 A

  However, when the emitter terminal is located away from the MOSFET, the negative feedback applied between the gate electrode and the source electrode of the MOSFET in which switching loss mainly occurs among the MOSFET and IGBT connected in parallel may increase. is there. Therefore, there has been a problem that the loss improvement effect of the entire power semiconductor device is reduced due to the reduction in switching speed of the MOSFET.

  Therefore, an object of the present invention is to provide a semiconductor device that can improve switching loss and steady loss, and can suppress a reduction in loss improvement effect due to a reduction in switching speed.

  The semiconductor device according to the present invention drives the MOSFET by adjusting a switching element including a MOSFET, an IGBT connected in parallel with the MOSFET, and a first control signal input to the gate electrode of the MOSFET. A first adjustment circuit; and a second adjustment circuit that drives the IGBT by adjusting a second control signal input to the gate electrode of the IGBT, wherein the first adjustment circuit and the second adjustment circuit include: The MOSFET is driven when the switching element is turned on and off, and the IGBT is driven when a steady current is supplied to the switching element. The source electrode of the MOSFET and the emitter electrode of the IGBT are connected to a control emitter wiring extending from an emitter terminal. Connected, and the source electrode of the MOSFET is the In which are arranged in the peripheral region of the emitter terminal.

  According to the present invention, the first adjustment circuit and the second adjustment circuit drive the MOSFET when the switching element is turned on and off, and drive the IGBT when the switching element is energized with a steady current. Therefore, both the switching loss and the steady loss can be improved by realizing the reduction of the switching loss by the MOSFET having the smaller switching loss than the IGBT and the reduction of the steady loss by the IGBT having the smaller steady loss than the MOSFET.

  The source electrode of the MOSFET and the emitter electrode of the IGBT were connected to a control emitter wiring extending from the emitter terminal, and the source electrode of the MOSFET was disposed in the peripheral region of the emitter terminal. Therefore, since the negative feedback applied between the gate electrode and the source electrode of the MOSFET can be reduced, it is possible to suppress a reduction in loss improvement effect due to a reduction in switching speed.

1 is a circuit diagram of a semiconductor device according to a first embodiment. 3 is a timing chart showing the operation of the semiconductor device. It is a current / voltage waveform schematic diagram of a semiconductor device. It is explanatory drawing for demonstrating the negative feedback concerning between the gate electrode and source electrode of MOSFET. It is a circuit diagram for demonstrating the negative feedback applied between the gate electrode and source electrode of MOSFET. FIG. 6 is a circuit diagram of a semiconductor device according to a second embodiment. 3 is a timing chart showing the operation of the semiconductor device. FIG. 6 is a circuit diagram of a semiconductor device according to a third embodiment. It is a drive current waveform figure at the time of driving only IGBT at the time of turn-on. It is a drive current waveform figure at the time of driving MOSFET at the time of turn-on. FIG. 6 is a circuit diagram of a semiconductor device according to a fourth embodiment. 3 is a timing chart showing the operation of the semiconductor device.

<Embodiment 1>
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of the semiconductor device according to the first embodiment. FIG. 2 is a timing chart showing the operation of the semiconductor device. FIG. 3 is a schematic diagram of current / voltage waveforms of the semiconductor device.

  As shown in FIG. 1, the semiconductor device is a power module, and includes a MOSFET 1, an IGBT 2, a first adjustment circuit 23, and a second adjustment circuit 24. MOSFET 1 and IGBT 2 correspond to switching elements.

  MOSFET 1 and IGBT 2 are connected in parallel. More specifically, the drain electrode of MOSFET 1 and the collector electrode of IGBT 2 are connected, and the source electrode of MOSFET 1 and the emitter electrode of IGBT 2 are connected. The gate electrode of the MOSFET 1 is connected to the output electrode of the first adjustment circuit 23, and the gate electrode of the IGBT 2 is connected to the output electrode of the second adjustment circuit 24.

  The first adjustment circuit 23 includes the XOR circuit 3 and the first delay circuit 3a, and drives the MOSFET 1 by adjusting the first control signal VG1 input to the gate electrode of the MOSFET 1. The first delay circuit 3a is a circuit that uses a delay caused by an RC filter including a resistor R1 and a capacitor C1. The control signal Vcin output from the outside is input to one input of the XOR circuit 3 and the first delay circuit 3a, and the control signal Vcin delayed by the first delay circuit 3a is input to the other input of the XOR circuit 3. Entered. The XOR circuit 3 outputs the first control signal VG1 to the gate electrode of the MOSFET1.

  The second adjustment circuit 24 includes an inverter circuit 4 and a second delay circuit 4a, and drives the IGBT 2 by adjusting a second control signal VG2 input to the gate electrode of the IGBT 2. The second delay circuit 4a is a circuit that uses a delay caused by an RC filter including a resistor R2 and a capacitor C2. The control signal Vcin output from the outside is input to the second delay circuit 4a, and the control signal Vcin delayed by the second delay circuit 4a is input to the inverter circuit 4. The inverter circuit 4 outputs the second control signal VG2 to the gate electrode of the IGBT2. The resistance value of the resistor R1 is set to be larger than the resistance value of the resistor R2, and the delay time by the first delay circuit 3a is longer than the delay time by the second delay circuit 4a.

  Next, the operation of the semiconductor device will be described with reference to FIG. As shown in FIG. 2, when the control signal Vcin output from the outside is turned on from a high potential (“H” level) to a low potential (“L” level), the first adjustment circuit 23 and the second adjustment circuit 24 adjusts the first control signal VG1 and the second control signal VG2 to turn on the MOSFET 1 and the IGBT 2 in this order. After the delay time by the first delay circuit 3a elapses, the first adjustment circuit 23 and the second adjustment circuit 24 output the first control signal VG1 and the second control signal VG2 so as to turn off the MOSFET 1 with the IGBT 2 turned on. adjust.

  That is, when the switching element is turned on, only the MOSFET 1 whose switching loss is smaller than that of the IGBT 2 is first driven, and the IGBT 2 is driven after a predetermined time has elapsed, so that the switching loss can be improved as shown in FIG. Note that the predetermined time from when the MOSFET 1 is driven to when the IGBT 2 is driven is the difference between the delay time by the first delay circuit 3a and the delay time by the second delay circuit 4a.

  After the delay time by the first delay circuit 3a elapses after the MOSFET 1 is driven, the driving of the MOSFET 1 is stopped, so that only the IGBT 2 having a steady loss smaller than that of the MOSFET 1 is driven when the steady current is applied. Thereby, as shown in FIG. 3, steady loss can be improved.

  Next, when the control signal Vcin is turned off from a low potential (“L” level) to a high potential (“H” level), the first adjustment circuit 23 and the second adjustment circuit 24 are in a state where the IGBT 2 is on. The first control signal VG1 and the second control signal VG2 are adjusted so that the MOSFET 1 is turned on and the IGBT 2 and the MOSFET 1 are turned off in this order.

  That is, when the switching element is turned off, the driving of the IGBT 2 having a switching loss larger than that of the MOSFET 1 is stopped first, and the driving of the MOSFET 1 is stopped after a predetermined time has elapsed, so that the switching loss can be improved as shown in FIG. it can. The predetermined time from when the driving of the IGBT 2 is stopped until the driving of the MOSFET 1 is stopped is the difference between the delay time by the first delay circuit 3a and the delay time by the second delay circuit 4a.

  Next, negative feedback between the gate electrode and the source electrode of MOSFET 1 will be described with reference to FIGS. FIG. 4 is an explanatory diagram for explaining the negative feedback applied between the gate electrode and the source electrode of the MOSFET. FIG. 5 is a circuit diagram for explaining the negative feedback applied between the gate electrode and the source electrode of the MOSFET.

  As shown in FIG. 4, the source electrode of MOSFET 1 and the emitter electrode of IGBT 2 are connected to a control emitter wiring 8 extending from the emitter terminal Es. More specifically, since the source electrode of the MOSFET 1 is arranged in the peripheral region of the emitter terminal Es, it is directly connected to the control emitter wiring 8. On the other hand, since the emitter electrode of the IGBT 2 is located away from the emitter terminal Es, it is not directly connected to the control emitter wiring 8 but is connected to the control emitter wiring 8 via the lead frame 9. As described above, the wiring path from the emitter terminal Es to the source electrode of the MOSFET 1 becomes short, but the wiring path from the emitter terminal Es to the emitter electrode of the IGBT 2 becomes long.

  Thereby, since the negative feedback applied between the gate electrode and the source electrode of MOSFET 1 can be reduced, it is possible to suppress a reduction in loss improvement effect due to a reduction in switching speed. Moreover, since the negative feedback applied between the gate electrode of the IGBT 2 and the source electrode of the MOSFET 1 can be increased, the peak current at the time of short circuit can be suppressed by reducing the switching speed of the IGBT 2.

  As described above, in the semiconductor device according to the first embodiment, the first adjustment circuit 23 and the second adjustment circuit 24 drive the MOSFET 1 when the switching element is turned on and off, and the IGBT 2 is supplied when the switching element is energized with a steady current. To drive. Therefore, both the switching loss and the steady loss can be improved by realizing the reduction of the switching loss by the MOSFET 1 having a smaller switching loss than that of the IGBT 2 and the reduction of the steady loss by the IGBT 2 having a smaller steady loss than that of the MOSFET 1.

  Further, since the switching loss and the steady loss are distributed to each of the MOSFET 1 and the IGBT 2, the temperature rise of the MOSFET 1 and the IGBT 2 can be suppressed.

  The source electrode of the MOSFET 1 and the emitter electrode of the IGBT 2 are connected to the control emitter wiring 8 extending from the emitter terminal Es, and the source electrode of the MOSFET 1 is disposed in the peripheral region of the emitter terminal Es. Therefore, since negative feedback applied between the gate electrode and the source electrode of MOSFET 1 can be reduced, it is possible to suppress a loss improvement effect due to a decrease in switching speed.

  Moreover, since the negative feedback applied between the gate electrode of the IGBT 2 and the source electrode of the MOSFET 1 can be increased, the peak current at the time of short circuit can be suppressed by reducing the switching speed of the IGBT 2.

<Embodiment 2>
Next, a semiconductor device according to the second embodiment will be described. FIG. 6 is a circuit diagram of the semiconductor device according to the second embodiment. FIG. 7 is a timing chart showing the operation of the semiconductor device. In the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 6 and FIG. 7, in the second embodiment, the first adjustment circuit 33 monitors the temperature of the IGBT 2 and first increases the ON time of the MOSFET 1 when the temperature becomes higher than a predetermined temperature. The control signal VG1 is adjusted.

  Next, the first adjustment circuit 33 will be described in detail. As shown in FIG. 6, the first adjustment circuit 33 includes a first delay circuit 3 b and a sense circuit 25.

  The first delay circuit 3b includes a resistor R1, a capacitor C1, a transistor 7, and a capacitor C3. That is, the first delay circuit 3b has a configuration in which the transistor 7 and the capacitor C3 are added to the first delay circuit 3a of the first embodiment.

  The sense circuit 25 includes a pull-up resistor R3, a plurality of diodes 5, and a comparator 6. A connection point between the pull-up resistor R3 and the anode of the diode 5 is connected to the positive input (+) of the comparator 6, and the reference voltage Vref1 is input to the negative input (−). The sense circuit 25 is arranged in the peripheral region of the IGBT 2 and determines the element temperature Tj of the IGBT 2 using the temperature dependence characteristic of the forward drop voltage Vf of the diode 5.

  Next, the operation of the semiconductor device will be described with reference to FIGS. As shown in FIGS. 6 and 7, when Tj is lower than a predetermined temperature, a voltage lower than Vref1 is input to the positive input (+) of the comparator 6, and therefore the output signal Vt of the comparator 6 is “L”. "Is the level. When Tj becomes higher than a predetermined temperature, the voltage Vf of the diode 5 decreases and a voltage higher than Vref1 is input to the positive input (+) of the comparator 6, so that the output signal Vt of the comparator 6 becomes “H” level. Become.

  At this time, since the transistor 7 is turned on and the delay time by the first delay circuit 3b is increased, the “H” level time of the first control signal VG1 is increased. Thereby, the ON time of MOSFET1 is adjusted. More specifically, the ON time of MOSFET 1 increases. Note that the predetermined temperature is, for example, 150 ° C. or 175 ° C.

  As described above, in the semiconductor device according to the second embodiment, the first adjustment circuit 33 monitors the temperature of the IGBT 2 and performs the first control so as to extend the ON time of the MOSFET 1 when the temperature becomes higher than a predetermined temperature. Adjust the signal VG1. Therefore, the overheating state of the IGBT 2 can be suppressed by extending the ON time of the MOSFET 1 and distributing the generated loss in the IGBT 2 to the MOSFET 1 in accordance with the element temperature Tj of the IGBT 2.

<Embodiment 3>
Next, a semiconductor device according to the third embodiment will be described. FIG. 8 is a circuit diagram of the semiconductor device according to the third embodiment. FIG. 9 is a drive current waveform diagram when only IGBT 2 is driven at turn-on. FIG. 10 is a drive current waveform diagram when MOSFET 1 is driven at the time of turn-on. In the third embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 8, in the third embodiment, the semiconductor device monitors the current value of the sense current Isense flowing through the IGBT 2 and turns off the IGBT 2 when the current value becomes higher than a predetermined value. Is further provided.

  The overcurrent cutoff circuit 26 includes a resistor R5, a noise filter circuit 10, a comparator 11, a resistor R6, and a transistor 15. The noise filter circuit 10 includes a resistor R4 and a capacitor C4. The current sense electrode of the IGBT 2 is connected to the positive input (+) of the comparator 6 via the noise filter circuit 10, and the reference voltage Vref 2 is input to the negative input (−). The output of the comparator 6 is connected to the gate electrode of the transistor 15.

  Next, the operation of the semiconductor device will be described with reference to FIG. As shown in FIG. 8, when the current value of the sense current Isense is lower than a predetermined value, a voltage lower than Vref2 is input to the positive input (+) of the comparator 11, and therefore the output signal Vt of the comparator 11 is “L” level. When an overcurrent flows through the IGBT 2 and the current value of the sense current Isense becomes higher than a predetermined value, a voltage higher than Vref2 is input to the positive input (+) of the comparator 11, and therefore the output signal Vt of the comparator 11 is It becomes “H” level.

  At this time, since the transistor 15 is turned on and the second control signal VG2 is set to the “L” level, the IGBT 2 is turned off.

  Next, optimization of the noise filter circuit 10 will be described with reference to FIGS. 9 and 10. As shown in FIG. 9, when only the IGBT 2 is driven when the switching element is turned on, since a recovery current flows through the IGBT 2, noise is added to the sense current Isense of the IGBT 2. Therefore, a noise filter circuit for preventing erroneous detection of overcurrent. Is required.

  On the other hand, in the third embodiment, only the MOSFET 1 is first driven first when the switching element is turned on. Next, after the recovery current flows through the MOSFET 1, the IGBT 2 is driven. As a result, as shown in FIG. 10, since no recovery current flows through the IGBT 2, no noise is added to the sense current Isense of the IGBT 2, so that the noise filter circuit 10 can be reduced and optimized.

  As described above, the semiconductor device according to the third embodiment further monitors the current value of the sense current Isense flowing through the IGBT 2 and further includes the overcurrent cutoff circuit 26 that turns off the IGBT 2 when the current value becomes higher than a predetermined value. I have.

  Conventionally, since a recovery current flows through the IGBT 2 and noise is added to the sense current Isense of the IGBT 2, a noise filter circuit for preventing erroneous detection of overcurrent has been required. However, in the semiconductor device according to the third embodiment, since the MOSFET 1 is driven when the switching element is turned on, the recovery current does not flow through the IGBT 2, so that no noise is added to the sense current Isense of the IGBT 2. And can be optimized.

  Therefore, by performing overcurrent protection using the current sense electrode of the IGBT 2 in the ON state of the IGBT 2, it is possible to reduce the noise filter circuit 10 and the number of parts. Further, when the above-described overcurrent protection method is used, the MOSFET 1 is in an OFF state when the switching element is energized with a steady current. Therefore, it is not necessary to provide the current sensing electrode in the MOSFET 1, so that the manufacturing cost of the MOSFET 1 can be reduced and the effective area Can be expanded.

<Embodiment 4>
Next, a semiconductor device according to the fourth embodiment will be described. FIG. 11 is a circuit diagram of a semiconductor device according to the fourth embodiment. FIG. 12 is a timing chart showing the operation of the semiconductor device. Note that in the fourth embodiment, the same components as those described in the first to third embodiments are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIGS. 11 and 12, in the fourth embodiment, the overcurrent cutoff circuit 36 monitors the first control signal VG1, the first control signal VG1 becomes “L” level, and the sense of the IGBT 2 is detected. When the current value of the current Isense becomes higher than a predetermined value, the IGBT 2 is turned off. That is, in the fourth embodiment, overcurrent protection is performed only when the first control signal VG1 is at “L” level. Here, the reason why the overcurrent protection is not performed when the first control signal VG1 is at the “H” level is that if the overcurrent detection is performed when the first control signal VG1 is at the “H” level, erroneous detection is caused by noise. This is because the possibility increases.

  As shown in FIG. 11, the overcurrent cutoff circuit 36 has a configuration in which the noise filter circuit 10 is eliminated from the overcurrent cutoff circuit 26 of the third embodiment, and the inverter circuit 12 and the AND circuit 14 are added. The output of the XOR circuit 3 is connected to one input of the AND circuit 14 via the inverter circuit 12, and the output of the comparator 11 is connected to the other input. The output of the AND circuit 14 is connected to the gate electrode of the transistor 15.

  As shown in FIGS. 11 and 12, when the first control signal VG1 is at “H” level, the output of the AND circuit 14 is always at “L” level, so that the transistor 15 is turned off. Therefore, the IGBT 2 operates based on the control signal Vcin.

  When the second control signal VG2 becomes “H” level and the current value of the sense current Isense of the IGBT 2 becomes higher than a predetermined value, the voltage applied to the current sense electrode becomes “H” level, and the positive input ( Since a voltage higher than Vref2 is input to (+), the output signal of the comparator 11 is at the “H” level. When the first control signal VG1 becomes “L” level in this state, the output voltage Vsc of the AND circuit 14 becomes “H” level, so that the transistor 15 is turned on. As a result, the second control signal VG2 becomes “L” level, and the IGBT 2 is turned off. Note that a latch circuit (not shown) is connected to the output of the AND circuit 14, and after the IGBT 2 is turned off, the output voltage Vsc of the AND circuit 14 is "until a reset signal is separately input by the latch circuit". Maintain the “H” level. Thereby, the IGBT 2 maintains the turn-off state regardless of the state of the control signal Vcin.

  As described above, in the semiconductor device according to the fourth embodiment, the overcurrent cutoff circuit 36 monitors the first control signal VG1, the first control signal VG1 becomes “L” level, and the sense current of the IGBT 2 When the current value of Isense becomes higher than a predetermined value, the IGBT 2 is turned off.

  Therefore, the possibility of erroneous detection due to noise with respect to overcurrent detection can be reduced. Further, since the turn-off operation is performed by the IGBT 2 whose switching speed is slower than that of the MOSFET 1, the turn-off surge voltage can be suppressed.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  DESCRIPTION OF SYMBOLS 1 MOSFET, 2 IGBT, 23 1st adjustment circuit, 24 2nd adjustment circuit, 26 Overcurrent interruption circuit, 33 1st adjustment circuit, 36 Overcurrent interruption circuit

Claims (4)

A switching element including a MOSFET and an IGBT connected in parallel with the MOSFET;
A first adjustment circuit that drives the MOSFET by adjusting a first control signal input to the gate electrode of the MOSFET;
A second adjustment circuit that drives the IGBT by adjusting a second control signal input to the gate electrode of the IGBT;
With
The first adjustment circuit and the second adjustment circuit drive the MOSFET when the switching element is turned on and off, and drive the IGBT when the switching element is supplied with a steady current.
The source electrode of the MOSFET and the emitter electrode of the IGBT are connected to a control emitter wiring extending from an emitter terminal,
The semiconductor device, wherein the source electrode of the MOSFET is disposed in a peripheral region of the emitter terminal.   2. The semiconductor according to claim 1, wherein the first adjustment circuit monitors the temperature of the IGBT and adjusts the first control signal so as to extend an ON time of the MOSFET when the temperature becomes higher than a predetermined temperature. apparatus.   The semiconductor device according to claim 1, further comprising an overcurrent cutoff circuit that monitors a current value of a current flowing through the IGBT and turns off the IGBT when the current value becomes higher than a predetermined value.   The overcurrent interrupt circuit monitors the first control signal, and turns off the IGBT when the first control signal becomes L level and the current value becomes higher than a predetermined value. The semiconductor device described.

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