JP2013115931A - Switching element driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching element driving circuit capable of achieving high efficiency and low noise with no necessity for a communication terminal to a circuit apt to have an adverse effect of noise, such as a tuner circuit.SOLUTION: The switching element driving circuit controls a through rate of a driving signal of a switching section SW in accordance with acquired internal information including internal information (input voltage information of a power supply voltage VB) of a switching power supply circuit 1, load current information (energization current information flowing into the switching section SW) and temperature information of the switching section SW.

Description

  The present invention relates to a drive circuit for a switching element.

  A driving circuit for this type of switching element is configured using, for example, a power MOS transistor. In this case, the switching loss is caused by turning on or off the power MOS transistor. Therefore, the switching loss can be reduced by increasing the slew rate of the output voltage of the drive circuit that drives the power MOS transistor.

  On the other hand, when the power MOS transistor is turned on or off, spike voltages and spike currents are generated, and switching noise caused by these spike voltages and spike currents is generated.

  In order to reduce this switching noise, the slew rate of the output voltage of the drive circuit is preferably lowered. Therefore, the slew rate of the output voltage of the drive circuit should be set at a trade-off in consideration of the occurrence of switching loss and switching noise, and the slew rate should be optimized according to the application and specifications.

  A technique described in Patent Document 1 is provided for the purpose of reducing switching loss to achieve high efficiency and low noise. In Patent Document 1, two drive circuits having different slew rates are provided, and the drive circuit is switched according to the operating state of the tuner circuit that is susceptible to noise, thereby achieving both high efficiency and noise reduction. ing.

JP 2006-129593 A

However, when the technique described in Patent Document 1 is applied, for example, an external terminal for receiving the operating state of the tuner circuit is required, which causes a problem that downsizing becomes difficult.
Further, for example, even when the tuner circuit is not operating, switching noise increases when the input voltage, load current, or temperature of the switching power supply circuit rises, and noise given to other devices may become a problem. Thus, reduction of switching loss and reduction of low switching noise are desired.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a switching element drive circuit that can achieve high efficiency and low noise while eliminating the need for a communication terminal with a circuit that is susceptible to noise, such as a tuner circuit.

  According to the first aspect of the present invention, the slew rate control unit adjusts the slew rate of the drive signal according to at least one of the input voltage, the load current, and the temperature of the switching element. The switching element is driven according to the drive signal. When any one of the input voltage, the load current, and the temperature of the switching element changes, the switching loss or / and the switching noise change. Depending on at least one of these input voltage, load current, and temperature, the drive signal Since the slew rate is adjusted, it can be configured to satisfy desired switching loss and switching noise. In addition, there is no need for a communication terminal with a circuit that is susceptible to noise as in the prior art.

  According to the second aspect of the present invention, since the slew rate control unit independently adjusts the slew rate according to the rise time and fall time of the drive signal, the turn-on loss and the turn-off that vary depending on the switching element characteristics. Loss can be adjusted independently.

  According to the third aspect of the present invention, since the drive unit adjusts the slew rate by controlling the drive capability of a plurality of drive elements connected in parallel, the slew rate can be easily changed by changing the on-resistance of the switching element. Can be adjusted.

Overall electrical configuration diagram for the first embodiment Block diagram Example of driver circuit configuration Timing chart schematically showing relationship between input pulse signal and drive signal Explanatory diagram showing an example of slew rate control according to purpose Modified example of driver circuit (1) Modified example of driver circuit (2) FIG. 1 equivalent view showing a modification (No. 1) FIG. 1 equivalent view showing a modification (No. 2) FIG. 1 equivalent view showing a modification (No. 3) FIG. 1 equivalent view showing a modification (No. 4) FIG. 1 equivalent view showing the second embodiment 2 equivalent diagram FIG. 12 equivalent view showing a modification (No. 1) FIG. 12 equivalent view showing a modification (part 2) FIG. 12 equivalent diagram showing a modification (No. 3)

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 to 11. FIG. 1A shows an electrical configuration of the switching power supply circuit, and FIG. 1B shows an example of a transistor constituting the switching unit.

  As shown in FIG. 1A, a switching unit SW and a diode D1 in the reverse direction are connected in series between a supply terminal of a power supply voltage (input voltage) VB and the ground GND. A common connection node N1 of the cathode of the diode D1 and the switching unit SW is connected to the output terminal OUT through a series connection circuit including an inductor L1 and a capacitor C1.

  The switching unit SW is configured by using an N-channel type power MOSFET, and a drive signal is given to the control terminal of the switching unit SW from the driver circuit DRV. The driver circuit DRV outputs a drive signal to the switching unit SW in response to an externally supplied PWM signal (pulse signal) and an n-bit slew rate control signal from the slew rate control logic SCLG.

  On the other hand, a current detection resistor R1 is connected to an energization path for energizing the switching unit SW from the supply terminal of the power supply voltage VB. The measurement amplifier AMP1 detects the terminal voltage of the current detection resistor R1, and outputs the detection terminal voltage to the peak hold circuit PH.

  The peak hold circuit PH holds a voltage value corresponding to the peak value of the terminal voltage of the current detection resistor R1, and this output voltage is given to the comparators CMP1 and CMP2. The comparator CMP1 compares the peak hold voltage with the reference voltage Vref1, the comparator CMP2 compares the peak hold voltage with the reference voltage Vref2 (<Vref1), and outputs these comparison results to the slew rate control logic SCLG.

  The comparators CMP1 and CMP2 determine whether or not the peak hold voltage V of the peak hold circuit PH is within a predetermined voltage range (Vref2 <V <Vref1), and output this determination result to the slew rate control logic SCLG. Thereby, current information flowing into the switching unit SW is given to the slew rate control logic SCLG.

  The power supply voltage VB is given to a voltage dividing circuit in which resistors R2, R3, and R4 are connected in series. Each voltage dividing voltage V1 (voltage of a common connection node of R2 and R3), voltage dividing of the voltage dividing circuit The voltage V2 (the voltage at the common connection node of R3 and R4) is applied to the comparators CMP3 and CMP4, respectively.

  The comparator CMP3 compares the divided voltage V1 with the reference voltage Vref3, and the comparator CMP4 compares the divided voltage V2 with the reference voltage Vref4 (<Vref3). The comparators CMP3 and CMP4 output the respective comparison results to the slew rate control logic SCLG.

  The comparators CMP3 and CMP4 determine whether or not the power supply voltage VB is within a predetermined voltage range, and output the determination result to the slew rate control logic SCLG. As a result, the power supply voltage (input voltage) VB information is given to the slew rate control logic SCLG.

  The power supply voltage applied to the series circuit of the resistor R5 and the thermistor NTC is a constant power supply voltage independent of the input voltage VB, load current, and temperature. The thermistor NTC is disposed adjacent to the switching unit SW and measures the temperature of the switching unit SW. The thermistor NTC has a negative temperature coefficient characteristic in which the resistance value decreases as the temperature rises.

  The comparator CMP5 compares the divided voltage of the series circuit of the resistor R5 and the thermistor NTC with the reference voltage Vref5, and the comparator CMP6 compares the divided voltage with the reference voltage Vref6 (<Vref5). The comparators CMP5 and CMP6 output the respective comparison results to the slew rate control logic SCLG.

  The terminal voltage of the thermistor NTC varies depending on the temperature of the switching unit SW. The comparators CMP5 and CMP6 determine whether or not the divided voltage that fluctuates according to the temperature change of the switching unit SW is within a predetermined voltage range, and outputs the determination result to the slew rate control logic SCLG. Thereby, the temperature information of the switching unit SW is given to the slew rate control logic SCLG. The switching power supply circuit 1 is configured in such a form.

FIG. 2 is a block diagram showing the configuration of this characteristic portion.
The slew rate control circuit SCLC shown in FIG. 2 mainly includes the slew rate control logic SCLG described above, and includes load current information (corresponding to information corresponding to the energization current flowing from the resistor R1 into the switching unit SW in FIG. 1), input Voltage information (corresponding to information corresponding to the power supply voltage VB in FIG. 1) and temperature information (corresponding to information corresponding to the detected voltage of the thermistor NTC in FIG. 1) are input, and n is supplied to the driver circuit DRV according to these information. Output bit slew rate control signal. The driver circuit DRV generates a drive signal according to the slew rate control signal and the PWM signal (pulse signal), and outputs the drive signal to the switching unit SW.

FIG. 3 shows an example of the electrical configuration of the driver circuit.
As shown in FIG. 3, the driver circuit DRV has a plurality of switching elements M1 to M3 (for example, P-channel type power MOSFETs) connected in parallel between the supply terminals of the power supply voltage VB and the ground GND on the upper arm side. In addition, a plurality of switching elements M4 to M6 (for example, N-channel type power MOSFETs) are connected in parallel on the lower arm side.

  FIG. 3 shows an example in which three switching elements are configured on each of the upper arm side and the lower arm side. However, the number of switching elements is not necessarily three, and one, two, or four or more switching elements are provided. You may connect in parallel. In the following description of the embodiment, an example will be described in which the switching elements M1 to M3 are configured using P-channel power MOSFETs and the switching elements M4 to M6 are configured using N-channel power MOSFETs.

  The driver circuit DRV is configured by connecting a drive circuit DR1 of the switching elements M1 to M3 to control terminals (gates of power MOSFETs) of the plurality of switching elements M1 to M3 on the upper arm side. The drive circuit DR1 is configured by connecting various gates (NOT gate Ga, AND gates G1a to G3a, NOT gates G1b to G3b) in the illustrated form, and includes select signals SEL [0], SEL [1] and a through current. The switching elements M1 to M3 are driven according to a signal given through the prevention circuit PT.

  The driver circuit DRV is configured by connecting the drive circuit DR2 of the switching elements M4 to M6 to the control terminals (the gates of the power MOSFETs) of the plurality of switching elements M4 to M6 on the lower arm side. The drive circuit DR2 is configured by connecting various gates (AND gate G4a, NAND gates G5a to G6a, NOT gates G4b to G6b, G4c) in the illustrated form, and includes select signals SEL [2], SEL [3], and The switching elements M4 to M6 are driven in accordance with a signal given through the through current prevention circuit PT.

  The through-current prevention circuit PT is divided into an upper arm circuit and a lower arm circuit, and the lower arm circuit is configured using a NOR circuit in which OR gates G7a and G7b and a NOT gate G7c are combined. The circuit is configured using an AND circuit combining AND gates G8a and G8b.

  The through-current prevention circuits (G7a, G7b, G7c) for the lower arm have their inputs connected to the control terminals (the gates of the power MOSFETs) of the switching elements M4 to M6, and all the control terminals of the switching elements M4 to M6 are “ The "H" level is output to the AND gate G1a of the drive circuit DR1 on condition that the "L" level is obtained.

  Accordingly, the through current prevention circuits (G7a, G7b, G7c) validate the operation of the drive circuit DR1 while the off drive control signal “L” is applied to the control terminals of the switching elements M4 to M6. In response to the drive circuit DR1 applying the “L” level to the control terminals of the switching elements M1 to M3 during the period, the switching elements M1 to M3 can be turned on.

  Conversely, while the control terminal of any of the switching elements M4 to M6 is at the “H” level, the “L” level is input to the AND gate G1a of the drive circuit DR1, and thus the operation of the drive circuit DR1 is performed. When disabled and any one of the switching elements M4 to M6 is turned on, the drive circuit DR1 holds the output at the “H” level, thereby holding the switching elements M1 to M3 in the off state. Thereby, a through current can be prevented.

  Since the through-current prevention circuits (G8a, G8b) for the upper arm are connected to the control terminals (the gates of the power MOSFETs) of the switching elements M1 to M3, all the control terminals are set to the “H” level. As a condition, an “H” level is output to the AND gate G4a. Therefore, the through current prevention circuits (G8a, G8b) validate the drive circuit DR2 while the off drive control signal “H” is applied to the control terminals of the switching elements M1 to M3, and the drive circuit during this validation period. When the DR2 applies the “H” level to the control terminals of the switching elements M4 to M6, the switching elements M4 to M6 can be turned on.

  On the other hand, when any of the control terminals of the switching elements M1 to M3 is at the “L” level, the “L” level is input to the AND gate G4a, so that the operation of the drive circuit DR2 is invalidated, and the switching element M1. When any of .about.M3 is on, the drive circuit DR2 can hold the switching elements M4 to M6 in the off state by holding the output at the "L" level. Thereby, a through current can be prevented.

  Hereinafter, a method for adjusting the slew rate will be described. In the following example, the select signals SEL [0] and SEL [3] are the same signal, and the select signals SEL [1] and SEL [2] are the same signal.

  The select signal SEL [0] is input to the AND gate G2a, and the select signal SEL [1] is input to the AND gate G3a. The select signal SEL [2] is input to the NAND gate G6a, and the select signal SEL [3] is input to the NAND gate G5a.

  For example, when the select signal SEL [0] is at “H” level, the AND gate G2a and the NOT gate G2b are validated, and the drive circuit DR1 can drive the switching element M2. At the same time, when the select signal SEL [3] is at the “H” level, the NAND gate G5a and the NOT gate G5b are validated, so that the drive circuit DR2 can drive the switching element M5.

  Similarly, when the select signal SEL [1] is at “H” level, the AND gate G3a and the NOT gate G3b are validated, and the drive circuit DR1 can drive the switching element M3. At the same time, when the select signal SEL [2] is at the “H” level, the NAND gate G6a and the NOT gate G6b are validated, so that the drive circuit DR2 can drive the switching element M6.

  On the contrary, when the select signal SEL [0] is at the “L” level, the NOT gate G2b forcibly outputs the “H” level, so that the switching element M2 is held in the off state. At the same time, when the select signal SEL [3] is at the “L” level, the NOT gate G5b forcibly outputs the “L” level, so that the switching element M5 is held in the off state.

  Further, when the select signal SEL [1] is at the “L” level, the NOT gate G3b forcibly outputs the “H” level, so that the switching element M3 is held in the off state. At the same time, when the select signal SEL [2] is at the “L” level, the NOT gate G6b forcibly outputs the “L” level, so that the switching element M6 is held in the off state. In this example, the select signals SEL [0] and SEL [3] are the same signal, and the select signals SEL [1] and SEL [2] are the same signal. However, they are different from each other. Also good.

The operation will be described for a case where the select signals SEL [0] to SEL [3] are all given at the “H” level.
When the PWM signal becomes “H” level, the control terminals of the switching elements M1 to M3 become “H” level. Then, all the switching elements M1 to M3 are turned off. When all the control terminals of the switching elements M1 to M3 are set to the “H” level, the AND gate G4a is given the “H” level from the through current prevention circuit PT. Then, the driving operation by the driving circuit DR2 is validated. Since the “H” level by the PWM signal is given to the AND gate G4a, the control terminals of the switching elements M4 to M6 all become “H” level. Accordingly, the switching elements M1 to M3 are turned off and the switching elements M4 to M6 are turned on.

  Thereafter, when the PWM signal becomes “L” level, the drive circuit DR2 sets the control terminals of the switching elements M4 to M6 to “L” level. Then, the switching elements M4 to M6 are all turned off. When all the control terminals of the switching elements M4 to M6 are set to the “L” level, the through current prevention circuit PT outputs the “H” level to the AND gate G1a. Then, the drive circuit DR1 is validated.

  Note that while the control terminal of any of the switching elements M4 to M6 is at the “H” level, the through-current prevention circuit PT is connected to the AND gate G1a even if the PWM signal is at the “L” level. Since the “L” level is output, the drive circuit DR1 can be invalidated, and the switching elements M1 to M3 are held in the OFF state. Thereby, a through current can be prevented.

  When the driving circuit DR1 is enabled by the through current prevention circuit PT outputting the “H” level to the AND gate G1a, the driving circuit DR1 controls the control terminals of the switching elements M1 to M3 according to the “L” level of the PWM signal. Is given an “L” level. Then, all the switching elements M1 to M3 are turned on. Thereafter, when the PWM signal becomes “H” level, the control terminals of the switching elements M1 to M3 become “H” level. Then, the switching elements M1 to M3 are turned off.

  The through current prevention circuit PT outputs “H” level to the AND gate G4a on condition that all the control terminals of the switching elements M1 to M3 are at “H” level. Then, the drive operation of the drive circuit DR2 is validated. Since the PWM signal shifts to the “H” level, the AND gate G4a outputs the “H” level, and all the control terminals of the switching elements M4 to M6 are set to the “H” level.

  Note that while any of the control terminals of the switching elements M1 to M3 is at the “L” level, even if the PWM signal is at the “H” level, the through-current prevention circuit PT supplies “AND” to the AND gate G4a. Since the “L” level is output, the drive circuit DR2 can be invalidated, and the switching elements M4 to M6 are held in the OFF state. Thereby, a through current can be prevented.

  When the select signals SEL [0] to SEL [3] change, the number of switching elements M1 to M3 and M4 to M6 that are turned on / off changes. For this reason, the driving capability can be changed by changing the effective size of the switching elements on the upper arm side and the lower arm side. Various characteristics such as transistor sizes (gate length and gate width) of the switching elements M1 to M3 and M4 to M6 may be changed from each other, or those having the same characteristics may be used. Further, the upper arm and the lower arm may have the same characteristics or different characteristics.

  FIG. 4 schematically shows the waveform of the PWM signal and the drive signal waveform of the driver circuit. As described above, since the number of switching elements M1 to M3 and M4 to M6 that are simultaneously driven can be controlled by the select signals SEL [0] to SEL [3], for example, the switching elements M1 to M3 on the upper arm side that are simultaneously driven. Since the combined on-resistance becomes relatively high, the driving ability to inject driving charge into the control terminal of the switching unit SW is lowered, and the slew rate when the switching unit SW is turned on can be lowered.

  Conversely, when the number of switching elements M1 to M3 of the upper arm that are driven simultaneously is large, the combined on-resistance is relatively low, so that the driving capability of injecting a driving current into the control terminal of the switching unit SW increases. The slew rate when the switching unit SW is turned on can be increased.

  Further, when the number of lower-arm switching elements M4 to M6 that are driven simultaneously is small, the combined on-resistance becomes relatively high, so that the driving ability to draw the driving current from the control terminal of the switching unit SW becomes low. The slew rate at turn-off can be lowered. On the other hand, when the number of switching elements M4 to M6 of the lower arm that are driven simultaneously is large, the combined on-resistance becomes relatively low, so that the driving ability to draw the driving current from the control terminal of the switching unit SW increases. The slew rate at turn-off can be increased.

<Description of switching loss and switching noise>
As described in the background art section, the switching loss of the switching power supply circuit 1 can be reduced by increasing the slew rate of the output voltage of the drive circuit for driving the switching unit SW. However, when the slew rate is increased indefinitely, the switching unit SW is turned on or turned off at high speed, so that a surge occurs due to a sudden voltage change or current change, and these surges become noise generation sources. These surges are generated due to a change in circuit configuration or circuit mounting environment (for example, a change in the in-vehicle power supply voltage), or in addition, depending on a parasitic inductor or a parasitic capacitor.

In particular, when the switching unit SW is turned on and turned off, a surge current and a surge voltage are likely to be generated according to the parasitic capacitor and the parasitic inductor. If the parasitic capacitance is C and the input voltage is V, the stored energy U of the parasitic capacitor C is
^{U = C × V 2/2} ... (1)
It becomes. Also, if the surge current flowing through the parasitic capacitor C is I,
I = C × dV / dt (2)
It becomes. From this, it can be seen that the surge current I increases in proportion to the minute change dV / dt of the input voltage V. If the parasitic inductance is L and the load current is I, the stored energy U of the parasitic inductance L is
^{U = L × I 2/2} ... (3)
It becomes. At this time, if the surge voltage generated in the parasitic inductor is V,
V = L × dI / dt (4)
It becomes. Therefore, the surge voltage V increases in proportion to the minute change dI / dt of the load current. For example, when the power MOSFET is turned on or turned off, a surge is generated by the parasitic capacitor or the parasitic inductor.

  It is generally known that switching noise increases in proportion to the magnitude of these surge current and surge voltage. It has been derived by the inventors that the state of occurrence of these switching noises varies depending on the environmental change of the switching power supply circuit 1, such as the power supply voltage (input voltage) VB, the load current, and the temperature of the switching unit SW. Therefore, in the present embodiment, as described above, the slew rate can be controlled so that the switching noise can be adjusted while reducing the loss.

  FIG. 5 shows an example of a control method according to the purpose. As shown in FIG. 5, when the power supply voltage (input voltage) VB increases or the load current increases, switching noise and loss (heat loss) increase. Further, the switching loss increases as the temperature of the switching unit SW rises. Heat is generated due to the switching loss, resulting in heat loss.

  In such a case, when it is desired to reduce the switching noise, the slew rate may be controlled to be low when the power supply voltage VB or the load current is increased, and the slew rate may be controlled to be high when the temperature of the switching unit SW is increased. .

  On the other hand, when it is desired to reduce the heat loss (switching loss), the slew rate may be controlled to be high when the power supply voltage VB or the load current increases. Further, the slew rate may be controlled to be high when the temperature of the switching unit SW rises. By controlling the slew rate, various characteristics of switching noise and heat loss (switching loss) can be controlled to a desired state.

  Further, these heat loss (switching loss) and switching noise differ depending on the element characteristics (model, element size, package, electrode configuration, etc.) of the switching unit SW. Therefore, when practically used, the slew rate is adjusted to an initial value in advance when the switching power supply circuit 1 is manufactured, and the slew rate control logic SCLG (slew rate control circuit SCLC) is shown in a state where the slew rate is adjusted to the initial value. The correction control is preferably performed in the direction shown in FIG.

<Modification of Driver Circuit DRV>
6 and 7 show modifications of the driver circuit. As shown in FIG. 6, a plurality of switching elements M1 to M3 may be connected in parallel only on the upper arm side, and only one switching element M4 may be provided on the lower arm side. In this case, the slew rate at turn-on can be adjusted. On the contrary, as shown in FIG. 7, the switching elements M4 to M6 may be connected in parallel only on the lower arm side, and only one switching element M1 may be provided on the upper arm side. In this case, the slew rate at turn-off can be adjusted.

<Modified example of internal information to be referenced>
8 to 11 show modifications in which the internal information to be referred is changed.
As shown in FIG. 8, the driver circuit DRV may drive the switching unit SW based only on the information of the power supply voltage (input voltage) VB, or as shown in FIG. 9, only based on the temperature of the switching unit SW. The driver circuit DRV may drive the switching unit SW. In addition, as shown in FIG. 10, the driver circuit DRV may drive the switching unit SW based only on the energization current of the switching unit SW. Furthermore, as shown in FIG. 11, the driver circuit DRV may drive the switching unit SW based only on the power supply voltage (input voltage) VB and the energization current of the switching unit SW.

<Summary of this embodiment>
In the present embodiment, a part or all of the internal information (input voltage information of the power supply voltage VB, load current information (information of current supplied to the switching unit SW), temperature information of the switching unit SW) of the switching power supply circuit 1 is acquired. In addition, since the slew rate of the drive signal of the switching unit SW is controlled according to the internal information, an external terminal that has been a problem in the prior art becomes unnecessary.

  Further, when the power supply voltage (input voltage) VB of the switching power supply circuit 1, the energization current (load current) of the switching unit SW, or the temperature of the switching unit SW changes, switching loss or switching noise increases according to the change. However, in this embodiment, switching is performed by detecting at least one element or all elements of the input voltage, load current, and temperature of the switching unit SW, and changing the slew rate in accordance with the internal information. Loss or switching noise can be reduced. Thereby, the switching power supply circuit 1 having various characteristics of desired switching loss and switching noise can be configured while eliminating the need for external terminals.

(Second Embodiment)
FIG. 12 and FIG. 13 show the second embodiment. The difference from the previous embodiment is that the switching power supply circuit is applied to a synchronous rectification circuit configuration. Portions having the same functions and similar functions as those of the above-described embodiment are denoted by the same or similar reference numerals, description thereof is omitted, and different portions are described below.

FIG. 12 shows an electrical configuration of a switching power supply step-down circuit that replaces FIG. 1, and FIG. 13 shows a block diagram that replaces FIG.
As shown in FIG. 12, the switching unit SW is configured by connecting switching units SW1 and SW2 in series between the supply terminal of the power supply voltage VB and the ground GND. This employs a synchronous rectification type configuration by configuring the switching unit SW2 instead of the diode D1 of the above-described embodiment.

  N-channel type power MOSFETs are used for the switching units SW1 and SW2, respectively. The driver circuit DRV1 drives the switching unit SW1, and the driver circuit DRV2 drives the switching unit SW2 independently. These driver circuits DRV1, DRV2 have substantially the same circuit configuration as the driver circuit DRV shown in the above-described embodiment. In the present embodiment, the through current prevention circuit PT is configured separately.

  The control unit CP detects the output signal of the output terminal OUT serving as a common connection point of the inductor L1 and the capacitor C1, adjusts the duty ratio of the PWM signal (pulse signal), and outputs the PWM signal to the through current prevention circuit PT. . The through-current prevention circuit PT outputs a drive signal with a predetermined dead time for the switching units SW1 and SW2 of the upper arm and the lower arm in accordance with the input PWM signal.

  In this case, as in the previous embodiment, the slew rate control circuit SCLC sends a slew rate control signal to the driver circuit DRV1 in accordance with the load current information, the power supply voltage (input voltage) VB information, and the temperature information of the switching unit SW. By outputting, the slew rate when the switching unit SW1 is turned on and turned off is controlled.

  At the same time, the slew rate control circuit SCLC outputs a slew rate control signal to the driver circuit DRV2, thereby controlling the slew rate when the switching unit SW2 is turned on and turned off. Then, each of the driver circuits DRV1 and DRV2 can drive the switching unit SW (switching unit SW1 and SW2) using the drive signal whose slew rate is adjusted.

<Main factors of turn-on loss and turn-off loss>
Since the circuit configuration in the present embodiment is configured to perform synchronous rectification, when a power MOSFET or the like is applied to each of the switching units SW1 and SW2, a self turn-on phenomenon occurs. The self-turn-on phenomenon indicates a phenomenon that occurs at the on-switching timing of the high-side switching unit SW1 when the low-side switching unit SW2 is in the off state. When current flows to the load side between the drain and source of the MOSFET constituting the switching unit SW1, the voltage between the drain and source of the power MOSFET constituting the switching unit SW2 rises.

  Then, the control terminal (the gate of the power MOSFET) of the switching unit SW2 is charged through the drain-gate parasitic capacitance Cdg of the switching unit SW2, thereby turning on the switching unit SW2 that should be turned off. Then, when the switching units SW1 and SW2 are turned on at the same time, an excessive loss occurs, and the element generates heat and the temperature rises, so that the efficiency deteriorates.

  When a MOSFET is applied, a turn-on phenomenon tends to occur when the drain-source voltage rises sharply. This is due to the semiconductor structure constituting the MOSFET, and the charge current of the drain-gate parasitic capacitance Cdg generates a base current for turning on the parasitic NPN transistor. In addition, a reverse recovery time is required for the parasitic diode. A large turn-off loss occurs during the reverse recovery time.

  When the IGBT is applied as the switching units SW1 and SW2, a current tail phenomenon is caused when the IGBT is turned off. When the channel conduction of the MOSFET portion stops, the flow of electrons stops and the IGBT current drops rapidly, but a tail current thereafter occurs. This current tail phenomenon increases the turn-off loss.

  According to the present embodiment, since the slew rate can be adjusted, the temporal change dV / dt of the drain-source voltage of the switching units SW1 and SW2 can be appropriately controlled so that the self turn-on phenomenon can be prevented. In addition, since the slew rate can be adjusted, the current change di / dt at the time of turn-off of the switching units SW1 and SW2 can be appropriately reduced, and the turn-off loss can be appropriately reduced. Thus, the present invention can be similarly applied to the switching power supply circuit 2 that performs synchronous rectification.

(Third embodiment)
FIG. 14 and FIG. 15 show a third embodiment. The difference from the previous embodiment is that the circuit configuration is changed. Parts having the same or similar functions are denoted by the same or similar reference numerals and description thereof is omitted. Hereinafter, different parts will be described.

  FIG. 14 shows an electrical configuration of a switching power supply booster circuit 3 in place of FIGS. 1 and 12. The power supply voltage VB is supplied to one terminal of the inductor L1, and the other terminal of the inductor L1 is connected to the common connection node N2 of the switching units SW1 and SW2 constituting the switching unit SW. The node N2 is connected to one terminal of the capacitor C1 and the output terminal OUT through the switching unit SW1, and the other terminal of the capacitor C1 is connected to the ground GND.

  The control unit CP outputs a PWM signal to the through current prevention circuit PT according to the output voltage of the output terminal OUT, and the through current prevention circuit PT sends a control signal for prevention of penetration according to the PWM signal to the driver circuits DRV1 and DRV2. Output to. The driver circuits DRV1 and DRV2 output drive signals to the switching units SW1 and SW2, respectively, according to the given control signal. Thereby, switching part SW (switching part SW1 and SW2) can be driven on-off.

  In the circuit configuration shown in FIG. 14, when the switching unit SW2 is turned off and SW1 is turned on, energy is stored in the inductor L1 by energizing the inductor L1 from the power supply voltage VB, and then the switching unit SW1 is turned off and then the switching is performed. By turning on the part SW2, the energy stored in the inductor L1 is discharged to the capacitor C1. Then, energy is stored in the capacitor C1. The switching power supply step-down circuit 3 operates by performing power conversion in this way.

  FIG. 15 shows an electrical configuration of the switching power supply inverting circuit 4 in place of FIG. 1, FIG. 12, or FIG. In the circuit configuration shown in FIG. 15, the power supply voltage VB is supplied through one terminal of the switching unit SW1, and the other terminal of the switching unit SW1 is connected to the node N3. An inductor L1 is connected between the node N3 and the ground GND, and a switching unit SW2 is connected between the node N3 and the output terminal OUT. A capacitor C1 is connected between the output terminal OUT and the ground GND.

  In the circuit configuration shown in FIG. 15, when the switching unit SW2 is turned off and SW1 is turned on, energy is stored in the inductor L1 by energizing the inductor L1 from the power supply voltage VB. Thereafter, when the switching unit SW2 is turned on after the switching unit SW1 is turned off, the energy can be stored in the capacitor C1 by discharging the stored energy of the inductor L1 to the capacitor C1. The switching power supply inverting circuit 4 operates by performing power conversion in this way.

  Even when the circuit configurations shown in FIGS. 14 and 15 are applied, the slew rate control signals are applied to the driver circuits DRV1 to DRV2, so that these driver circuits DRV1 to DRV2 are turned on and turned off. The switching unit SW (switching units SW1 and SW2) can be driven using the drive signal after adjusting the slew rate.

(Fourth embodiment)
FIG. 16 shows a fourth embodiment. The difference from the previous embodiment is that it is applied to a motor drive circuit. Parts having the same or similar functions are denoted by the same or similar reference numerals and description thereof is omitted. Hereinafter, different parts will be described.

  FIG. 16 shows an H-bridge type motor drive circuit. The motor drive circuit 5 is configured using switching units SW1 to SW4 that are H-bridge connected to the motor winding L. In the present embodiment, each switching unit SW1, SW3 is configured using a P-channel power MOSFET, and each switching unit SW2, SW4 is configured using an N-channel power MOSFET.

  The controller CP outputs a PWM signal to the through current prevention circuit PT1, and the through current prevention circuit PT1 outputs a control signal to the driver circuits DRV1 and DRV2 according to the given PWM signal. The driver circuits DRV1 and DRV2 output drive signals to the control terminals of the switching units SW1 and SW2 constituting the H bridge, respectively, according to the control signal. In response to this, the switching units SW1 and SW2 are turned on and off.

  On the other hand, when the control unit CP outputs a PWM signal to the through current prevention circuit PT2, the through current prevention circuit PT2 outputs a control signal to the driver circuits DRV3 and DRV4 according to the PWM signal. The driver circuits DRV3 and DRV4 output drive signals to the switching units SW3 and SW4 constituting the H bridge according to the control signals. In response to this, the switching units SW1 and SW2 are turned on and off.

  The slew rate control signal is given to the driver circuits DRV1 to DRV4, and these driver circuits DRV1 to DRV4 can drive the switching units SW1 to SW4 with the slew rate adjusted at turn-on and turn-off. Although the example which applied power MOSFET was mainly shown as the switching element which comprises switching part SW, it is not restricted to this, You may use IGBT.

  In the drawing, 1 to 4 are switching power supply circuits (switching element drive circuits), 5 is a motor drive circuit (switching element drive circuit), SW is a switching unit, SCLC is a slew rate control circuit (slew rate control unit), and SCLG. Denotes a slew rate control logic (slew rate control unit), and DRV denotes a driver circuit (drive unit).

Claims (4)

In the drive circuit that drives the switching unit,
A slew rate control unit that adjusts the slew rate of the drive signal in accordance with at least one of the input voltage, the load current, and the temperature of the switching unit;
A switching element drive circuit comprising: a drive unit that drives the switching unit in accordance with a drive signal whose slew rate is adjusted by the slew rate control unit.   2. The switching element drive circuit according to claim 1, wherein the slew rate control unit independently adjusts the slew rate based on a rise time and a fall time of the drive signal. The switching element is configured by connecting a plurality of parallel elements,
3. The drive unit according to claim 1, wherein the drive unit adjusts a slew rate by controlling a number of switching elements connected in parallel to each other to drive the switching unit according to a drive signal. Switching element driving circuit.   4. The switching element drive circuit according to claim 1, wherein the switching element drive circuit is applied to a switching power supply circuit or a motor drive circuit.

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