JP6638628B2 - Gate drive - Google Patents

Description

  The present invention relates to a gate driving device.

  2. Description of the Related Art As a gate drive type semiconductor device, for example, in a gate drive device for driving a gate such as an IGBT (Insulated Gate Bipolar Transistor), a configuration in which a plurality of semiconductor power devices are connected in parallel and power is supplied to a load is adopted. is there. This is because, when a large current flows, the on-resistance of the semiconductor power element can be reduced by connecting in parallel to reduce the on-resistance loss.

  However, when a plurality of semiconductor power elements are connected in parallel and driven, the switching loss increases in proportion to the number, and a large loss particularly occurs when switching is performed in a state where the collector voltage is high. For this reason, there is a disadvantage that increasing the number of semiconductor power elements connected in parallel to allow a large current to flow increases the loss.

JP 2012-249509 A JP-A-2005-6412

  The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce a loss as much as possible by connecting a plurality of semiconductor elements in parallel in order to flow a large current in a state where a high voltage is applied. It is an object of the present invention to provide a gate drive device capable of performing drive control while driving.

  2. The gate drive device according to claim 1, wherein the gate drive device drives a plurality of semiconductor devices of a gate drive type connected in parallel, the plurality of semiconductor devices being a starting semiconductor device and a final driving device. And at least one next-stage driving semiconductor element including the semiconductor element is provided, and the current of each of the remaining semiconductor elements other than the final driving semiconductor element is detected among the plurality of semiconductor elements. A current detection circuit, a constant current circuit for performing gate driving with a constant current for the starting semiconductor element, and a constant current circuit for disabling the constant current circuit to the next-stage driving and final driving semiconductor elements. A switch for performing gate drive at a constant voltage, and a control circuit for controlling the driving of the plurality of semiconductor elements, wherein the control circuit starts when an ON operation drive signal is externally supplied. As a control, a gate signal is given to the starting semiconductor element by a constant current by the constant current circuit to be turned on, and as a next-stage driving control, the gate signal is detected by the current detection circuit provided in the turned on semiconductor element. When the current reaches a set threshold current, the changeover switch is turned on, a gate signal is applied at a constant voltage to the next-stage driving semiconductor element in the off state to turn on the next-stage driving semiconductor element, and thereafter, the next stage in the off state is turned on. When there is a driving semiconductor element, the next-stage driving control is configured to be repeatedly performed, and the threshold current is set to turn on the next-stage driving semiconductor element of the plurality of semiconductor elements. When a current flows, the sum of the on-resistance loss and the switching loss generated by all the semiconductor elements in the on state becomes smaller than before the execution of the next-stage drive control. It is set to be.

  By adopting the above configuration, when a drive signal for an ON operation is externally supplied by the control circuit, as a start control, a gate signal is supplied to the start semiconductor element with a constant current by a constant current circuit by a constant current circuit to turn on the semiconductor element. When the current detected by the current detection circuit provided in the semiconductor element that has been turned on reaches a set threshold current as a subsequent next-stage drive control, the changeover switch is set to the operating state, and the next-stage driving semiconductor in the off state is set. A gate signal is applied to the element at a constant voltage to turn on the element. Thereafter, when there is a semiconductor element for driving the next stage in the OFF state, the next driving control is repeatedly executed by the control circuit.

  In this case, the setting of the threshold current is performed by setting the ON resistance loss and the switching loss generated by all the semiconductor elements in the ON state when the semiconductor element for driving the next stage among the plurality of semiconductor elements is turned on and the current flows. We try to minimize the sum. In general, in a gate drive type semiconductor device, the on-resistance loss and the switching loss have a trade-off relationship. Therefore, by setting the threshold current as described above, by optimizing the number of driven semiconductor elements, The combined loss can be minimized.

Schematic electrical configuration diagram showing a first embodiment Specific electrical configuration diagram Flow chart of drive control operation Time chart (Part 1) Time chart (Part 2) Schematic electrical configuration diagram showing a second embodiment Flow chart of drive control operation Time chart (Part 1) Time chart (Part 2) Time chart (3) Diagram showing the relationship between the number of IGBTs driven and the loss Flow chart of drive control operation showing a third embodiment Time chart (Part 1) Time chart (Part 2) Time chart showing the fourth embodiment Flow chart of drive control operation showing a fifth embodiment Time chart

(1st Embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 shows the basic configuration of the electrical configuration. This embodiment shows an example in which two IGBTs 1 and 2 are used as a plurality of gate control type semiconductor elements. The IGBT 1 has a sense emitter SE1 for monitoring current in addition to the collector C1, the emitter E1, and the gate G1. Similarly, the IGBT 2 has a collector C2, an emitter E2, a gate G2, and a sense emitter SE2 for monitoring current.

  The IGBTs 1 and 2 are provided in a power supply path to a load (not shown), and have a parallel drive system configuration in which the collectors C1 and C2 are commonly connected and the emitters E1 and E2 are commonly connected. Gate drive voltages VG1 and VG2 to the two IGBTs 1 and 2 are configured to be supplied from a DC power supply VD via a parallel circuit of a constant current circuit 3 and a changeover switch 4.

  The gate drive voltage VG1 is applied to the gate G1 of the IGBT1 from the constant current circuit 3 via the gate current cutoff switch 5. Further, the gate G1 of the IGBT1 is connected to the ground via the gate-off switch 6. The gate drive voltage VG2 is applied to the gate G2 of the IGBT2 from the constant current circuit 3 via the gate current cutoff switch 7. The gate G2 of the IGBT 2 is connected to the ground via the gate off switch 8.

  The control circuit 9 is constituted by a logic circuit including a gate drive circuit and the like, and supplies gate drive signals SA1 and SA2 to the IGBTs 1 and 2 according to an external drive signal SA. Current detection circuits 10 and 11 receive signals corresponding to collector-emitter currents Ic1 and Ic2 from sense emitters SE1 and SE2 of IGBTs 1 and 2, respectively, and output current detection signals S1 and S2 to control circuit 9. The control circuit 9 performs on / off control of the changeover switch 4, the current cutoff switches 5, 7 and the gate-off switches 6, 8 in accordance with the current detection signals S1, S2 as described later.

FIG. 2 shows a specific configuration of each part of the above configuration.
The sense emitter SE1 of the IGBT1 is connected to the emitter E1 via the current detection resistor 1a, and is provided so as to output a terminal voltage Vse1 of the current detection resistor 1a as a detection signal of the current Ic1 of the IGBT1. The sense emitter SE2 of the IGBT2 is connected to the emitter E2 via the current detection resistor 2a, and is provided so as to output a terminal voltage Vse2 of the current detection resistor 2a as a detection signal of the current Ic2 of the IGBT2.

  The constant current circuit 3 includes pnp transistors 3a and 3b forming a current mirror circuit, a transistor 3c for drawing a constant current, resistors 3d and 3e, a transistor 3f, and a reference power supply 3g. The constant current circuit 3 supplies a predetermined current to the transistor 3a by the reference voltage Vrefc set by the reference power supply 3g, and supplies a constant current Is from the power supply VD to the gates of the IGBTs 1 and 2 via the transistor 3b.

  The changeover switch 4 connected in parallel to the transistor 3b of the constant current circuit 3 short-circuits the emitter and the collector of the transistor 3b of the constant current circuit 3, and applies the power supply VD directly to the gates of the IGBTs 1 and 2. The changeover switch 4 includes a p-channel MOSFET 4a and a buffer circuit 4b connected to the gate. The switching circuit SX is supplied from the control circuit 9 to the buffer circuit 4b.

  The current cutoff switch 5 has a p-channel MOSFET 5a and an input resistor 5b connected in series. The gate of the MOSFET 5a is connected to a buffer circuit 5c, and a gate drive signal SA1 is supplied from the control circuit 9. Similarly, the power cutoff switch 7 has a p-channel MOSFET 7a and an input resistor 7b connected in series. The gate of the MOSFET 7a is connected to a buffer circuit 7c, and a gate drive signal SA2 is supplied from the control circuit 9.

  The gate-off switch 6 has an n-channel MOSFET 6a and an input resistor 6b connected in series. The gate of the MOSFET 6a is connected to a buffer circuit 6c, and receives a gate drive signal SA1 from a control circuit 9. Similarly, the gate-off switch 8 has an n-channel MOSFET 8a and an input resistor 8b connected in series. The gate of the MOSFET 8a is connected to a buffer circuit 8c, and a gate drive signal SA2 is supplied from a control circuit 9.

  The current detection circuit 10 includes a comparator 10a, a reference power supply 10b, and a filter 10c. The current detection signal Vse1 appearing at the sense emitter SE1 of the IGBT1 is input to the non-inverting input terminal of the comparator 10a, and the reference voltage Vref1 is input to the inverting input terminal by the reference power supply 10b that sets the threshold current value Ith1. The comparator 10a compares the current detection signal Vse1 of the IGBT1 with the reference voltage Vref1, outputs a high-level detection signal S1 when the voltage is equal to or higher than the reference voltage Vref1, and inputs the signal to the control circuit 9 via the filter 10c. The filter 10c outputs the detection signal S1 to the control circuit when the high-level detection signal S1 continues for a predetermined time.

  The current detection circuit 11 includes a comparator 11a, a reference power supply 11b, and a filter 11c. The current detection signal Vse2 appearing on the sense emitter SE2 of the IGBT 2 is input to the non-inverting input terminal of the comparator 11a, and the reference voltage Vref2 is input to the inverting input terminal by the reference power supply 11b that sets the threshold current value Ith1. The comparator 11a compares the current detection signal Vse2 of the IGBT 2 with the reference voltage Vref2, outputs a high-level detection signal S2 when the voltage is equal to or higher than the reference voltage Vref2, and inputs the signal to the control circuit 9 via the filter 11c. The filter 11c outputs the detection signal S2 to the control circuit when the high-level detection signal S2 continues for a predetermined time.

Next, the operation of the above configuration will be described with reference to FIGS.
FIG. 3 shows a flow of the gate drive control operation of the IGBTs 1 and 2 by the logic function of the control circuit 9. In the standby state, the control circuit 9 outputs a high-level signal SX that maintains the OFF state to the changeover switch 4, whereby the power supply VD outputs the constant current Is generated by the constant current circuit 3. This is a state in which the gate drive voltage VG1 or VG2 is supplied by flowing.

  When the IGBTs 1 and 2 are not driven, the control circuit 9 outputs high-level gate drive signals SA1 and SA2 to the IGBTs 1 and 2. Thus, the MOSFETs 5a and 7a of the current cutoff switches 5 and 7 are kept off, and the MOSFETs 6a and 8a of the gate off switches 6 and 8 are kept on. The gate G1 of the IGBT1 is connected to the ground via the MOSFET 6a, and the gate G2 of the IGBT2 is connected to the ground via the MOSFET 8a, and the off state is maintained.

  Then, when the drive signal SA is supplied from the outside, the control circuit 9 outputs a low-level gate drive signal SA1 for driving the IGBT 1 which is a starting semiconductor element with a constant current as step A1. In response to the gate drive signal SA1, the MOSFET 6a of the gate-off switch 6 is turned off, and the MOSFET 5a of the current cutoff switch 5 is driven on. In the IGBT1, a gate current Is flows from the power supply VD to the gate G1 via the constant current circuit 3, and the gate drive voltage VG1 is supplied. Thus, the IGBT 1 is driven with the variation of the switching loss reduced because the gate voltage VG1 is applied with the dV / dt being relatively gentle.

  Thereafter, when the gate voltage of the IGBT 1 is stabilized, the control circuit 9 outputs a low-level switching signal SX to the buffer circuit 4b of the changeover switch 4 in step A2. As a result, the MOSFET 4a is turned on, so that the constant current supply state by the constant current circuit 3 is stopped, and the state is switched to the constant voltage supply state in which the power supply VD is directly supplied.

  At this time, the current Ic1 of the IGBT1 has been detected by the current detection circuit 10. In the current detection circuit 10, the detection voltage Vse1 corresponding to the current value Ic1 of the IGBT1 is input. When the detection voltage Vse1 becomes equal to or higher than the reference voltage Vref1 for setting the threshold current Ith1, the current detection circuit 10 outputs the detection signal S1 to the control circuit 9. . When the level of the detection voltage Vse1 increases and the high-level signal from the comparator 10a continues for a certain period of time or more, the detection signal S1 is output from the filter 10c.

  When the current value Ic1 of the IGBT1 by the current detection circuit 10 is less than the threshold current Ith1, the control circuit 9 continues the on-state of the IGBT1 alone as YES in step A3. When the current value Ic1 becomes equal to or larger than the threshold current Ith1 and the detection signal S1 is output, the control circuit 9 proceeds to step A4 and drives the IGBT 2 at a constant voltage. The control circuit 9 outputs the gate drive signal SA2 to the IGBT2 in addition to the IGBT1.

In response to the gate drive signal SA2, the MOSFET 8a of the gate off switch 8 is turned off, and the MOSFET 7a of the current cutoff switch 7 is driven on. In the IGBT 2, a gate voltage is applied to the gate G2 from the power supply VD via the MOSFET 4a of the changeover switch 4. At this time, since the voltage applied between the drain and the source of the IGBT 2 is low because the IGBT 1 is already on, the loss can be reduced by driving the IGBT 2 at a constant voltage.
In addition, by driving the two IGBTs 1 and 2, the entire current can flow while the on-resistance is lowered as a whole, and the on-resistance loss can be reduced.

  In the above operation, when the collector current Ic1 of the IGBT1 further increases, the threshold current Ith1 of the current detection circuit 10 increases the loss due to the ON resistance of the IGBT1, and the switching loss increases by driving the IGBT2. Even so, the loss is set to a level that can reduce the loss as a whole by reducing the loss due to the on-resistance.

  Thus, at the time of the initial drive, the IGBT 1 is driven by the constant current Is in order to reduce the variation of the switching loss. When the current Ic1 of the IGBT 1 becomes equal to or more than the threshold current Ith1, the IGBT 2 which is a semiconductor element for driving the next stage is fixed. By driving with the voltage VD, an on operation in which the loss is reduced by increasing dV / dt can be performed.

  Next, the above operation will be described with reference to FIGS. FIG. 4 shows a time chart when a large current flows through a load (not shown) and both IGBTs 1 and 2 are turned on. FIG. 5 shows a time chart when only a small amount of current flows through the load and only the IGBT 1 is turned on.

  As shown in FIG. 4A, when the high-level drive signal SA is input at time ta1, the control circuit 9 causes the low-level gate to turn on the IGBT1, as shown in FIG. 4C. The driving signal SA1 is output. As a result, the gate-off switch 6 is turned off, the current cutoff switch 5 is turned on, and the gate drive voltage VG1 is applied to the gate G1 of the IGBT 1 by the constant current Is from the constant current circuit 3.

  The gate voltage Vg1 of the IGBT1 rises with a constant slope by supplying a constant current Is to the gate G1 as shown by a solid line in FIG. 4B, and as shown in FIG. The current Ic1 gradually increases. After the gate voltage Vg1 of the IGBT 1 becomes equal to or higher than the predetermined level, the control circuit 9 switches the changeover switch 4 to the ON state, invalidates the constant current circuit 3, and switches to the constant voltage supply state.

  Thereafter, as shown in FIG. 4E, when the collector current Ic1 of the IGBT1 reaches the threshold current Ith1 at time ta2, the control circuit 9 turns on the IGBT2 as shown in FIG. 4D. A low level gate drive signal SA2 is output. As a result, the gate-off switch 8 is turned off, the current cutoff switch 7 is turned on, and the gate drive voltage VG2 is applied to the gate G2 of the IGBT 2 at a constant voltage from the power supply VD.

  As shown by the broken line in FIG. 4B, the gate voltage Vg2 of the IGBT2 rises at a steeper slope than the gate voltage Vg1 of the IGBT1 by applying a constant voltage to the gate G2. As shown, the collector current Ic2 of the IGBT2 increases. At this time, the collector current Ic1 of the IGBT1 becomes lower than the threshold current Ith1 because the shared current decreases as the collector current Ic2 of the IGBT2 increases, as shown in FIG. 4E. Thus, power is supplied to the load by the two IGBTs 1 and 2.

  Thereafter, as shown in FIG. 4 (f), at time ta3, the rise of the collector current Ic2 of the IGBT2 stops, and when the current becomes a constant current, the collector current Ic1 of the IGBT1 also becomes a constant current, and the current flowing through the load as a whole is constant. It will be in the state of As a result, although the switching loss when the IGBT 2 is turned on increases, the sum of the losses due to the on-resistances of the two IGBTs 1 and 2 further decreases, so that the overall loss can be reduced.

  Further, as shown in FIG. 4A, when a low-level drive signal SA for the OFF operation is input to the control circuit 9 from the outside at time ta4, the control circuit 9 transmits the signals shown in FIGS. As shown in d), high level gate drive signals SA1 and SA2 are output. As a result, the current cutoff switches 5 and 7 are turned off, the gate-off switches 6 and 8 are turned on, the gate voltages Vg1 and Vg2 of the IGBTs 1 and 2 decrease, and the collector currents Ic1 and Ic2 also decrease to shift to the off state. .

  Next, when the current flowing through the load is small and only the IGBT 1 is turned on, the operation as shown in FIG. 5A is performed. That is, when the high-level drive signal SA is input at time tb1, the control circuit 9 outputs a low-level gate drive signal SA1 to turn on the IGBT1, as shown in FIG. 5C. Thus, the gate drive voltage VG1 is supplied from the constant current circuit 3 to the gate G1 of the IGBT 1 by the constant current Is in the same manner as described above.

  The gate voltage Vg1 of the IGBT1 rises with a constant slope by supplying a constant current Is to the gate G1 as shown by a solid line in FIG. 5B, and as shown in FIG. 5E, the collector of the IGBT1 The current Ic1 gradually increases. After the gate voltage Vg1 of the IGBT 1 has become equal to or higher than the predetermined level, the control circuit 9 switches the changeover switch 4 to the ON state to invalidate the constant current circuit 3.

  Thereafter, when the collector current Ic1 of the IGBT1 reaches a constant current level before reaching the threshold current Ith1 at time tb2, the IGBT2 is not turned on, and the control circuit 9 keeps the IGBT1 alone on. Therefore, in this state, the control circuit 9 keeps the gate drive signal SA2 at a high level as shown in FIG. 5D, and the collector current Ic2 of the IGBT 2 becomes zero as shown in FIG. It remains in a state.

  The loss due to the ON operation of the IGBT 1 in this state is the sum of the switching loss and the ON resistance loss. However, the current flowing through the load, that is, the level of the collector current Ic1 of the IGBT 1 is reduced as compared with the case where the IGBT 2 is also turned ON. Can be.

  Thereafter, as shown in FIG. 5A, when a low-level drive signal SA for the OFF operation is input from the outside to the control circuit 9 at time tb3, the control circuit 9 returns to FIG. As shown, a high-level gate drive signal SA1 is output. As a result, the current cutoff switch 5 is turned off, the gate-off switch 6 is turned on, the gate voltage Vg1 of the IGBT 1 decreases, the collector current Ic1 also decreases, and the IGBT 1 shifts to the off state.

  Next, a rotation operation by the control circuit 9 will be described. In the present embodiment, the current detection circuit 11 is provided in the IGBT 2 as well. Although not used in the drive control of the IGBTs 1 and 2, the IGBTs to be driven first are replaced by the IGBTs 1 and 2 each time the drive signal SA is supplied.

  Therefore, when the driving signal SA is input from the outside next time, the control circuit 9 controls the driving of the IGBT 2 so that the gate driving voltage VG2 is applied with the constant current Is first. When the collector current Ic2 of the IGBT2 reaches the threshold current Ith1, the control circuit 9 outputs a gate drive signal SA1 to turn on the IGBT1 in accordance with the current detection signal S2 input from the current detection circuit 11. Drive control.

  The rotation control as described above may be performed by exchanging the IGBTs 1 and 2 each time the drive signal SA is input, or may be switched by a counter or the like every time the drive signal SA is input a plurality of times. Can also be set. Further, the rotation control can be performed by another method instead of the number of times of input of the drive signal SA.

  By controlling the rotation of the IGBTs 1 and 2 by the control circuit 9 in this way, the IGBTs 1 and 2 can be used in an averaged use state, and thereby the life of the IGBTs 1 and 2 can be averaged.

  According to this embodiment, the control circuit 9 drives the IGBT 1 with the constant current Is, and drives the IGBT 2 with the constant voltage VD when the collector current Ic1 of the IGBT 1 reaches the current threshold Ith1. Therefore, the combined value of the switching loss and the on-resistance loss can be reduced as compared with the case where only IGBT 1 is driven or the case where IGBTs 1 and 2 are simultaneously driven.

  Further, by changing the number of driven IGBTs 1 and 2 in accordance with the current flowing through the load, driving can be performed under the condition that the sum of the switching loss and the on-resistance loss is reduced. In other words, by setting the threshold current Ith1 to such a level, it is possible to set and drive the above-described conditions.

  In the above embodiment, the current detection circuit 11 for detecting the collector current Ic2 of the IGBT 2 is provided on the assumption that the IGBTs 1 and 2 are controlled by the control circuit 9 for rotation. However, the IGBT 1 is exclusively used for starting. In this case, the current detection circuit 10 for the IGBT 1 may be provided and the current detection circuit 11 may not be provided.

  The output timing of the drive signal SX to the changeover switch 4 by the control circuit 9 is set at the time when the gate voltage Vg1 of the IGBT1 reaches a predetermined level. However, the collector current Ic1 of the IGBT1 reaches the threshold current Ith1 and the IGBT2 is turned on. When operating, it may be performed prior to this.

(2nd Embodiment)
FIGS. 6 to 11 show a second embodiment. Hereinafter, portions different from the first embodiment will be described. This embodiment shows an example of a gate drive device applied to a configuration in which three IGBTs 21 to 23 are connected in parallel as a plurality of semiconductor elements.

  FIG. 6 shows a schematic electrical configuration. Each of IGBTs 21 to 23 includes collectors C1 to C3, emitters E1 to E3, and gates G1 to G3, and further includes sense emitters SE1 to SE3 for monitoring current. Have.

  The IGBTs 21 to 23 are provided in a power supply path to a load (not shown), and have a parallel drive system configuration in which the collectors C1 to C3 are commonly connected and the emitters E1 to E3 are commonly connected. Gate drive voltages VG1 to VG3 to the three IGBTs 21 to 23 are configured to be supplied from a DC power supply VD via a parallel circuit of a constant current circuit 24 and a changeover switch 25.

  The gate drive voltage VG1 is applied to the gate G1 of the IGBT 21 from the constant current circuit 24 via the gate current cutoff switch 26. The gate G1 of the IGBT 21 is connected to the ground via the gate-off switch 27. The gate drive voltage VG2 is applied to the gate G2 of the IGBT 22 from the constant current circuit 24 via the gate current cutoff switch 28. The gate G2 of the IGBT 22 is connected to the ground via the gate-off switch 29. The gate drive voltage VG3 is applied to the gate G3 of the IGBT 23 from the constant current circuit 24 via the gate current cutoff switch 30. Further, the gate G3 of the IGBT 23 is connected to the ground via the gate-off switch 31.

  The control circuit 32 is composed of a logic circuit including a gate drive circuit and the like, and supplies gate drive signals SA1 to SA3 to the IGBTs 21 to 23 according to an external drive signal SA. Current detection circuits 33 to 35 receive signals corresponding to collector-emitter currents Ic1 to Ic3 from sense emitters SE1 to SE3 of IGBTs 21 to 23, respectively, and output current detection signals S1 to S3 to control circuit 32. The control circuit 32 performs on / off control of the changeover switch 25, the current cutoff switches 26, 28, 30 and the gate-off switches 27, 29, 30 in accordance with the current detection signals S1 to S3 as described later.

  Although the description of a specific circuit configuration of the above configuration is omitted, a circuit configuration substantially equivalent to that of the first embodiment shown in FIG. 2 is provided corresponding to the three IGBTs 21 to 23. In this embodiment, the current detection circuits 33 to 35 determine the levels of the collector currents Ic1 to Ic3 based on two threshold currents, that is, threshold currents Ith1 and Ith2. As the current detection signals S1 to S3, signals corresponding to the respective detection levels are output.

Next, the operation of the above configuration will be described with reference to FIGS.
FIG. 7 shows a flow of the gate drive control operation of the IGBTs 21 to 23 by the logic function of the control circuit 32. In the standby state, the control circuit 32 outputs a low-level signal SX that holds the OFF state to the changeover switch 25, whereby the power supply VD outputs the constant current Is generated by the constant current circuit 24. This is a state in which the gate drive voltages VG1 to VG3 are supplied by flowing.

  When the IGBTs 21 to 23 are not driven, the control circuit 32 outputs high-level gate drive signals SA1 to SA3 to the IGBTs 21 to 23. As a result, the current cutoff switches 26, 28, and 30 are kept in the off state, and the gate off switches 27, 29, and 31 are kept in the on state. The gates G1 to G3 of the IGBTs 21 to 23 are connected to the ground via gate-off switches 27, 29, and 31, respectively, and are kept in the off state.

  Then, when a high-level drive signal SA is supplied from the outside, the control circuit 32 drives the IGBT 21 which is a starting semiconductor element with a constant current as step A1, as in the first embodiment. Thereafter, when the gate voltage of the IGBT 21 is stabilized, the control circuit 32 outputs a low-level switching signal SX to the changeover switch 25 in step A2 to stop the constant current supply state by the constant current circuit 24. The state is switched to a constant voltage supply state for directly supplying the power supply VD.

  When detecting that the current value Ic1 of the IGBT 21 becomes equal to or greater than the threshold current Ith1, the current detection circuit 33 outputs a detection signal S1 to the control circuit 32. When the current value Ic1 of the IGBT 21 is less than the threshold current Ith1, the control circuit 32 continues the ON state of the IGBT 21 alone as YES in step A3. When the current value Ic1 becomes equal to or more than the threshold current Ith1 and the detection signal S1 that has reached the threshold current Ith1 or more is output from the current detection circuit 33, the control circuit 32 proceeds to step A4 and drives the IGBT 22 at a constant voltage. .

  At this time, since the voltage applied between the drain and the source of the IGBT 22 is low because the IGBT 21 is already on, the loss can be reduced by driving the IGBT 22 at a constant voltage. In addition, by driving the two IGBTs 21 and 22, the entire current can flow while the on-resistance is lowered as a whole, and the on-resistance loss can be reduced.

  In this state, when detecting that the current value Ic2 of the IGBT 22 becomes equal to or larger than the threshold current Ith2, the current detection circuit 34 outputs a detection signal S2 to the control circuit 32. When the current value Ic2 of the IGBT 22 has not reached the threshold current Ith2, the control circuit 32 continues the on state of the IGBTs 21 and 22 as YES in step A5. When the current value Ic2 becomes equal to or more than the threshold current Ith2 and the detection signal S2 that has reached the threshold current Ith2 or more is output from the current detection circuit 34, the control circuit 32 proceeds to step A6, and further drives the IGBT 23 with the constant voltage drive. I do.

  At this time, since the voltage applied between the drain and the source of the IGBT 23 is low because the IGBTs 21 and 22 are already turned on, the loss can be reduced by performing the constant voltage driving. In addition, by driving the three IGBTs 21 to 23, the entire current can flow while the on-resistance is lowered as a whole, and the on-resistance loss can be reduced.

  In the above operation, when the collector current Ic1 of the IGBT 21 further increases, the value of the threshold current Ith1 of the current detection circuit 33 increases, so that the loss due to the ON resistance of the IGBT 21 increases, and the IGBT 22 also drives to increase the switching loss. Even so, the loss is set to a level that can reduce the loss as a whole by reducing the loss due to the on-resistance.

  Also, the value of the threshold current Ith2 of the current detection circuit 34 is such that if the collector current Ic2 of the IGBT 22 further increases, the loss due to the on-resistance of the IGBTs 21 and 22 increases, and the switching loss increases by driving the IGBT 23 as well. However, the level is set to a level that can reduce the loss as a whole by reducing the loss due to the on-resistance.

  Thus, in the initial drive, the IGBT 21 is driven with a constant current in order to reduce the variation of the switching loss. When the current Ic1 of the IGBT 21 becomes equal to or more than the threshold current Ith1, the IGBT 22 which is a semiconductor element for driving the next stage is driven at a constant voltage. , It is possible to perform an on operation in which dV / dt is increased and loss is reduced. Further, when the current Ic2 of the IGBT 22 becomes equal to or larger than the threshold current Ith2, the IGBT 23, which is a semiconductor element for the next-stage drive and for final drive, is driven at a constant voltage, thereby increasing the dV / dt to reduce the loss to reduce the loss. It can be carried out.

Next, the above operation will be described with reference to FIGS.
FIG. 8 is a time chart in the case where the current flowing through the load is large and all three IGBTs 21 to 23 are turned on. FIG. 9 shows a time chart when the IGBTs 21 and 22 are turned on when the current flowing through the load is medium. FIG. 10 shows a time chart when the current flowing through the load is small and only the IGBT 21 is turned on.

  As shown in FIG. 8A, when the high-level drive signal SA is input at time ta1, the control circuit 32 causes the low-level gate to turn on the IGBT 21 as shown in FIG. 8C. The driving signal SA1 is output. As a result, the gate-off switch 27 is turned off, the current cutoff switch 26 is turned on, and the gate drive voltage VG1 is supplied from the constant current circuit 24 to the gate G1 of the IGBT 21 by the constant current Is.

  As shown by the solid line in FIG. 8B, the gate voltage Vg1 of the IGBT 21 rises with a constant slope by supplying a constant current Is to the gate G1, and as shown in FIG. 8F, the collector voltage of the IGBT 21 The current Ic1 gradually increases. After the gate voltage Vg1 of the IGBT 21 becomes equal to or higher than the predetermined level, the control circuit 32 switches the changeover switch 25 to the ON state to invalidate the constant current circuit 24.

  Thereafter, when the collector current Ic1 of the IGBT 21 reaches the threshold current Ith1 at time ta2, the control circuit 32 outputs a low-level gate drive signal SA2 to turn on the IGBT 22, as shown in FIG. 8D. . As a result, the gate-off switch 29 is turned off, the current cutoff switch 28 is turned on, and the gate drive voltage VG2 is applied to the gate G2 of the IGBT 22 at a constant voltage from the power supply VD.

  The gate voltage Vg2 of the IGBT 22 rises at a steeper slope than the gate voltage Vg1 of the IGBT 21 by applying a constant voltage to the gate G2, as shown by a broken line in FIG. As shown, the collector current Ic2 of the IGBT 22 increases. At this time, the collector current Ic1 of the IGBT 21 becomes equal to or less than the threshold current Ith1 because the current shared by the collector current Ic2 of the IGBT 22 increases and decreases. Thus, power is supplied to the load by the two IGBTs 21 and 22.

  Thereafter, when the collector current Ic2 of the IGBT 22 reaches the threshold current Ith2 at time ta3, the control circuit 32 outputs a low-level gate drive signal SA3 to turn on the IGBT 23, as shown in FIG. . Accordingly, the gate-off switch 31 is turned off, the current cutoff switch 30 is turned on, and the gate drive voltage VG3 is applied to the gate G3 of the IGBT 23 from the power supply VD at a constant voltage.

  As shown by a dotted line in FIG. 8B, the gate voltage Vg3 of the IGBT 23 rises with a steep slope in the same manner as the gate voltage Vg2 of the IGBT 22 by applying a constant voltage to the gate G3, as shown by a dotted line in FIG. ), The collector current Ic3 of the IGBT 23 increases. At this time, the collector currents Ic1 and Ic2 of the IGBTs 21 and 22 decrease as the collector current Ic3 of the IGBT 23 increases, and the collector current Ic2 becomes equal to or smaller than the threshold current Ith2. As a result, the power supply to the load is performed by the three IGBTs 21 to 23.

  Thereafter, at time ta4, the rise of the collector current Ic3 of the IGBT 23 stops, and when the current becomes constant, the collector currents Ic1 and Ic2 of the IGBTs 21 and 22 also become constant, and the current flowing to the load as a whole becomes constant. . As a result, although the switching loss when the IGBTs 22 and 23 are turned on increases, the sum of the losses due to the on-resistances of the three IGBTs 21 to 23 further decreases, so that the overall loss can be reduced.

  Further, as shown in FIG. 8A, when a low-level drive signal SA for the off operation is input from the outside to the control circuit 32 at time ta5, the control circuit 32 transmits the signals shown in FIGS. As shown in e), high-level gate drive signals SA1 to SA3 are output. As a result, the current cutoff switches 26, 28, and 30 are turned off, the gate-off switches 27, 29, and 31 are turned on, the gate voltages Vg1 to Vg3 of the IGBTs 21 to 23 decrease, and the collector currents Ic1 to Ic3 also decrease and turn off. Transition to the state.

  Next, when the IGBTs 21 and 22 are turned on when the current flowing through the load is medium, the operation shown in FIG. 9 is performed. This operation is the same as the operation in the case of FIG. 4 described in the first embodiment, and a description thereof will be omitted. Similarly, when the current flowing to the load is small and only the IGBT 21 is turned on, the operation shown in FIG. 10 is performed. This operation is also the same as the operation in the case of FIG. 5 described in the first embodiment, and a description thereof will be omitted.

  Next, the relationship between the above operation and the occurrence of loss will be described with reference to FIG. In this embodiment, the three IGBTs 21 to 23 are configured to control the ON operation according to the magnitude of the load current. In this case, the relationship between the number of the IGBTs 21 to 23 to be turned on and the switching loss, the on-resistance loss, and the total loss occurring at that time is shown.

  Regarding the switching loss, the loss per IGBT is slightly smaller in the constant current drive, and the loss generated in the constant voltage drive after the constant current drive is almost the same. Therefore, as shown by a black square and a dotted line in the drawing, the number of the IGBTs to be turned on tends to increase substantially in proportion to the number of IGBTs to be turned on.

  On the other hand, the on-resistance loss varies depending on the current level of the load current, and corresponds to the case where the load current is “large”, “medium”, and “small”. The case where the above-mentioned three IGBTs 21 to 23 are turned on is indicated by a black square and a solid line with the load current being “large”. The case where the two IGBTs 21 and 22 are turned on is indicated by a black square and a broken line as the load current “medium”. The case where only the IGBT 21 is turned on is indicated by a black square and a dashed line as the load current “small”. At any load current level, the on-resistance loss tends to decrease as the number of on-operations of the IGBT increases.

  The total loss when the IGBTs 21 to 23 are turned on is the sum of the switching loss and the on-resistance loss. The total loss is indicated by a thick solid line, a thick broken line, a thick dashed-dotted line, and a black triangle according to the current levels of the load currents “large”, “medium”, and “small”. Therefore, it can be said that the number of IGBTs driven when the total loss is minimized is in an appropriate drive control state.

  As a result, when the load current is “large”, the total loss when the three IGBTs 21 to 23 in which “3” is described in the open triangle is turned on is the smallest. When the load current is “medium”, the combined loss when the two IGBTs 21 and 22 with “2” described in the open triangle are turned on is the smallest. When the load current is “small”, the combined loss when one IGBT 21 in which “1” is described in the open triangle is turned on is the smallest.

  In other words, by setting the threshold currents Ith1 and Ith2 such that the drive number of the IGBTs 21 to 23 is switched according to the load current level as described above, it is possible to minimize the total loss caused by the load current level. You can.

  In the above configuration, since the current detection circuits 33 to 35 are provided corresponding to the respective IGBTs 21 to 23, similarly to the first embodiment, the drive control is performed by the rotation operation of the IGBTs 21 to 23 by the control circuit 32. can do.

  Further, the rotation control by the control circuit 32 may be performed by appropriately switching the IGBTs 21 to 23 every time the drive signal SA is input, or may be switched by a counter or the like every time the drive signal SA is input a plurality of times. Can also be set to Further, the rotation control can be performed by another method instead of the number of times of input of the drive signal SA.

  In this way, by controlling the rotation of the IGBTs 21 to 23 by the control circuit 32, the IGBTs 21 to 23 can be used in an averaged use state, whereby the life of the IGBTs 21 to 23 can be averaged.

Therefore, according to the second embodiment, even when the three IGBTs 21 to 23 are provided, the same operation and effect as those of the first embodiment can be obtained.
In the above embodiment, the current detection circuit 35 for detecting the collector current Ic3 of the IGBT 23 is provided on the premise that the IGBTs 21 to 23 are controlled to be rotated by the control circuit 32. However, the current detection circuit 35 is not provided. As a configuration, the two IGBTs 21 and 22 can be rotated.

(Third embodiment)
FIGS. 12 to 14 show a third embodiment. Hereinafter, portions different from the first embodiment will be described. In this embodiment, a control in the case where the IGBTs 1 and 2 are turned on and both are turned off in the same configuration as the first embodiment is described. In this embodiment, since the control mainly includes the off operation, the on operation indicates the case where the two IGBTs 1 and 2 are simultaneously turned on. However, as a matter of course, the on operation is performed as in the first embodiment. It is possible to control the operation.

  FIG. 12 shows a flow of a control operation performed by the control circuit 9 to turn off the IGBTs 1 and 2 during the ON operation. In this embodiment, when the on-period Ton by the externally applied drive signal SA is set to fall within a certain range, the off-time toff of the IGBT 2 to be turned off first is set in advance.

  When the high-level drive signal SA for the ON operation is input from the outside, the control circuit 9 starts counting the elapsed time from that point. The control circuit 9 performs the operation shown in FIG. 12 when the two IGBTs 1 and 2 are turned on. That is, the control circuit 9 first determines whether or not the drive signal SA has changed to a low level indicating the off operation in step B while waiting for the elapsed time to exceed the off time toff in step B1. .

  Here, in the normal case, since the off-time toff elapses first, the control circuit 9 outputs a high-level gate drive signal SA2 so as to turn off the IGBT 2 first, as step B3. Thereby, IGBT2 is turned off while IGBT1 is kept on. Thereafter, the control circuit 9 waits for the input of the low-level drive signal SA from the outside in step B4, and in step B5, turns off the IGBT 1 and ends the operation.

  On the other hand, if the low-level drive signal SA is input from the outside before the off-time toff elapses, the control circuit 9 turns to YES in step B2, and thereafter in step B6, the two IGBTs 1 and 2 Are turned off together.

  Next, the above-mentioned off operation will be described with reference to FIGS. FIG. 13 shows a time chart in a case where the off period toff elapses before the low-level drive signal SA is input after the two IGBTs 1 and 2 are turned on. FIG. 14 shows a time chart when the low-level drive signal SA is input before the off period toff elapses after the two IGBTs 1 and 2 are turned on.

  First, in the operation of FIG. 13, as shown in FIG. 13A, when the high-level drive signal SA is input at the time tx1, the control circuit 9 causes the control circuit 9 to operate as shown in FIGS. 13C and 13D. To turn on the IGBTs 1 and 2 to output low-level gate drive signals SA1 and SA2. As a result, the gate-off switches 6, 8 are turned off, the current cutoff switches 5, 7 are turned on, and the gate drive voltages VG1, VG2 are supplied from the constant current circuit 3 to the gates G1, G2 of the IGBTs 1, 2 by the constant current Is. .

  The gate voltages Vg1 and Vg2 of the IGBTs 1 and 2 rise with a constant slope by supplying a constant current Is to the gates G1 and G2, as shown by a solid line and a broken line in FIG. As shown in (f), the collector currents Ic1 and Ic2 of the IGBTs 1 and 2 gradually increase and turn on. After that, the control circuit 9 switches the changeover switch 4 to the ON state to invalidate the constant current circuit 3.

  Thereafter, when the off period toff elapses at time tx2 during the ON operation of the IGBTs 1 and 2, the control circuit 9 outputs a high-level gate drive signal SA2 to output the IGBT2 as shown in FIG. Off. The gate voltage Vg2 of the IGBT2 drops to zero as shown in FIG. 13B, and the collector current Ic2 also drops to zero as shown in FIG. At this time, as shown in FIG. 13E, the collector current Ic1 of the IGBT1 increases by adding the collector current Ic2 flowing through the IGBT2.

  Thereafter, at time txn, as shown in FIG. 13A, when a low-level driving signal SA is input from the outside, the control circuit 9 causes the high-level gate to be driven as shown in FIG. The drive signal SA1 is output to turn off the IGBT1. The gate voltage Vg1 of the IGBT1 gradually decreases as shown in FIG. 13B, and the collector current Ic1 also drops to zero as shown in FIG. 13E.

  As a result, for the two IGBTs 1 and 2 that are in the ON operation, the IGBT 2 is turned off and then the IGBT 1 is turned off when the timer time toff elapses, so that the two IGBTs 1 and 2 are simultaneously turned off. As compared with the case, the switching off loss such as heat generation due to the tail current at the time of off driving can be reduced.

  Next, in the above operation, since the off-period toff is set to elapse before the period Toff until the low-level drive signal SA is input from the outside, the IGBT 2 is turned off first. Is what you can do. However, the operation illustrated in FIG. 14 is performed on the assumption that a low-level drive signal SA instructing an OFF operation is input before the period Toff elapses.

  That is, in FIG. 14, when the two IGBTs 1 and 2 are in the on state, and as shown in FIG. 14A, at time txn before the time tx2 when the off period toff elapses, the low-level drive signal SA is output. When input from outside, the control circuit 9 outputs high-level gate drive signals SA1 and SA2 as shown in FIGS. As a result, the gate voltages Vg1 and Vg2 of the two IGBTs 1 and 2 both drop to zero as shown in FIG. 14B, and the collector current Ic1 as shown in FIGS. 14E and 14F. , Ic2 become zero and turn off.

  According to the third embodiment, the control circuit 9 turns off the IGBT 2 first after the elapse of the off-time toff, and then turns off the IGBT 1 at the timing of the drive signal SA. Switching off loss such as heat generation due to the tail current can be reduced.

  In the above embodiment, two IGBTs 1 and 2 are used, but the present invention can also be applied to the second embodiment in which three IGBTs are provided or a configuration in which four or more IGBTs are provided in parallel. In this case, one IGBT to be turned off last can be left, and the remaining IGBTs can be turned off simultaneously.

(Fourth embodiment)
FIG. 15 shows a fourth embodiment, and parts different from the third embodiment will be described. In this embodiment, a gate drive signal to be given to the control circuit 9 is given a drive signal SAb to be turned off before a drive signal SAa to be finally turned off.

  When the two IGBTs 1 and 2 are turned on at time ty1 in the same manner as described above, the control circuit 9 thereafter receives an external low-level drive signal SAb at time ty2 as shown in FIG. Is done. As a result, the control circuit 9 outputs the high-level gate drive signal SA2 to turn off the IGBT 2 as shown in FIG. The gate voltage Vg2 of the IGBT2 drops to zero as shown in FIG. 15C, and the collector current Ic2 also drops to zero as shown in FIG. At this time, the collector current Ic1 of the IGBT1 increases as shown in FIG. 1F (e) by adding the collector current Ic2 flowing through the IGBT2.

  Thereafter, at time ty3, when a low-level drive signal SAa is input from the outside as shown in FIG. 15A, the control circuit 9 switches the high-level gate as shown in FIG. The drive signal SA1 is output to turn off the IGBT1. The gate voltage Vg1 of the IGBT1 gradually decreases as shown in FIG. 15B, and the collector current Ic1 also drops to zero as shown in FIG. 15E.

As a result, with respect to the two IGBTs 1 and 2 in the ON operation, the IGBT 2 is turned off and then the IGBT 1 is turned off by the drive signals SAa and SAb input at different timings. Can be obtained.
Note that this embodiment can also be applied to the second embodiment having three IGBTs or the configuration in which four or more IGBTs are provided in parallel, similarly to the third embodiment.

(Fifth embodiment)
FIGS. 16 and 17 show the fifth embodiment. Hereinafter, portions different from the first embodiment will be described. The electrical configuration is the same as in FIGS. 1 and 2 shown in the first embodiment. This embodiment shows an operation when the collector current Ic1 fluctuates while a plurality of IGBTs 1 and 2 are driven together or one of them is driven. In this embodiment, since the control mainly includes the off operation, the on operation indicates the case where the two IGBTs 1 and 2 are simultaneously turned on. However, as a matter of course, the on operation is performed as in the first embodiment. It is possible to control the operation.

  FIG. 16 is a diagram showing control when the control circuit 9 controls the IGBT 2 and the IGBT 2 during the ON operation while detecting the collector current Ic1 of the IGBT 1 or turning the IGBT 2 on after the IGBT 2 is turned off. The flow of the operation is shown.

  The control circuit 9 starts the operation of the gate drive control shown in FIG. 16 after driving the IGBTs 1 and 2 by receiving a high-level drive signal SA of the ON operation from the outside. The control circuit 9 first determines whether or not the IGBT 2 is currently turned on at Step C1, and since the IGBTs 1 and 2 are on at the first stage, the control circuit 9 proceeds to Step C2 with YES.

  In step C2, the control circuit 9 determines whether or not the level of the collector current Ic1 of the IGBT 1 is a level at which a single ON operation can be performed, based on the off-level threshold current Ith1x. The off-level threshold current Ith1x is set to, for example, about 以下 or less of the above-described threshold current Ith1. Therefore, if the answer is YES here, the control circuit 9 turns off the IGBT 2 in step C3. As a result, the collector current obtained by adding the collector currents Ic1 and Ic2 shared by the two IGBTs 1 and 2 flows to the IGBT1, but the collector current Ic1 at this time has a level not exceeding the threshold current Ith1.

  In addition, if NO in step C2, that is, if the collector current Ic1 of the IGBT1 is not lower than the off-level threshold current Ith1x, the control circuit 9 holds the IGBT2 in the ON state. Hereinafter, while the two IGBTs 1 and 2 are being driven, the control circuit 9 repeatedly executes the above-described steps.

  Next, in a state in which the IGBT 1 is driven alone, the control circuit 9 makes a negative determination in step C1 and proceeds to step C4 to determine whether the collector current Ic1 of the IGBT 1 is lower than the threshold current Ith1. If the collector current Ic1 has not increased from the state described above, the control circuit 9 determines YES in step C4, and enters a state in which nothing is performed.

  On the other hand, when the collector current Ic1 of the IGBT1 increases and becomes equal to or larger than the threshold current Ith1, the control circuit 9 determines NO in step C4 and proceeds to step C5 to drive the IGBT2 in the same manner as described above. I do. Thereafter, the control circuit 9 repeatedly performs the above-described gate drive control until an off signal is supplied as an external signal SA to the IGBTs 1 and 2.

  Next, an example of the gate drive control will be described with reference to FIG. FIG. 17 is a time chart in the case where two IGBTs 1 and 2 are simultaneously turned on, and then gate drive control is performed according to a change in the collector current Ic1 of the IGBT 1.

  As shown in FIG. 17A, when the high-level drive signal SA is input at time ts1, the control circuit 9 turns on the IGBTs 1 and 2 as shown in FIGS. 17C and 17D. For this purpose, it outputs low-level gate drive signals SA1 and SA2. As a result, the gate-off switches 6, 8 are turned off, the current cutoff switches 5, 7 are turned on, and the gate drive voltages VG1, VG2 are supplied to the gates G1, G2 of the IGBTs 1, 2 by the constant current Is from the constant current circuit 3. .

  The gate voltages Vg1 and Vg2 of the IGBTs 1 and 2 rise with a constant slope by supplying a constant current Is to the gates G1 and G2, as shown by the solid and broken lines in FIG. As shown in (f), the collector currents Ic1 and Ic2 of the IGBTs 1 and 2 gradually increase and turn on. After that, the control circuit 9 switches the changeover switch 4 to the ON state to invalidate the constant current circuit 3.

  Thereafter, if the level of the collector current Ic1 of the IGBT1 does not exceed the off-level threshold current Ith1x during the ON operation of the IGBTs 1 and 2, the control circuit 9 turns off the IGBT2 at time tx2. As a result, the collector current obtained by adding the collector currents Ic1 and Ic2 shared by the two IGBTs 1 and 2 flows into the IGBT1.

  Thereafter, when the collector current Ic1 flowing through the IGBT1 gradually increases and becomes equal to or larger than the threshold current Ith1 at time ts3, the control circuit 9 drives the IGBT2 at a constant voltage. As a result, part of the collector current Ic1 flowing through the IGBT1 flows as the collector current Ic2 of the IGBT2, and the collector current Ic1 of the IGBT1 becomes smaller than the threshold current Ith1.

  Such gate drive control is repeatedly executed by the control circuit 9, and in response to the change in the current flowing to the load, the drive control is performed so that the IGBTs 1 and 2 do not exceed the threshold current Ith1.

According to the fifth embodiment, the control circuit 9 turns off the IGBT 2 while the two IGBTs 1 and 2 are on, or turns on the IGBT 2 at a constant voltage while the one IGBT 1 is on. By doing so, the same effects as in the first embodiment can be obtained even during the operation of the IGBTs 1 and 2.
In the above embodiment, two IGBTs 1 and 2 are used, but the present invention can also be applied to the second embodiment in which three IGBTs are provided or a configuration in which four or more IGBTs are provided in parallel.

(Other embodiments)
Note that the present invention is not limited to only the above-described embodiment, and can be applied to various embodiments without departing from the gist thereof. For example, the present invention can be modified or expanded as follows.

As a plurality of semiconductor elements, four or more IGBTs can be provided.
Further, as the gate drive type semiconductor element, a gate drive type semiconductor device such as a MOSFET can be provided in addition to the IGBT.

The current detection circuits 10, 11, and 33 to 35 are configured to determine the current level by a comparator that compares the current values with reference to a threshold current, but the current value is read by an A / D conversion circuit or the like, May be used to determine the current level.
The IGBT on / off control is performed by hardware processing using a logic circuit by the control circuits 9 and 32, but can be controlled by software using a program.

  In the drawings, 1, 2, 21, 22, and 23 are IGBTs (semiconductor elements), 3 and 24 are constant current circuits, 4 and 25 are changeover switches, 5, 7, 26, 28, and 30 are current cutoff switches, 6, and 8, 27, 29 and 31 are off switches, 9 and 32 are control circuits, and 10, 11, 33, 34 and 35 are current detection circuits.

Claims (6)

A gate drive device for driving a plurality of gate drive type semiconductor elements (1, 2, 21, 22, 23) connected in parallel,
The plurality of semiconductor elements include a starting semiconductor element (1, 21) and at least one next-stage driving semiconductor element (2, 22, 23) including a final driving semiconductor element (2, 23). ) Is provided,
A current detection circuit (10, 33, 34) for detecting a current of each of the remaining semiconductor elements excluding the final driving semiconductor element among the plurality of semiconductor elements;
A constant current circuit (3, 24) for performing a gate drive with a constant current to the starting semiconductor element;
Changeover switches (4, 25) for disabling the constant current circuit and performing gate drive at a constant voltage on the next-stage driving and final driving semiconductor elements;
A control circuit (9, 32) for driving and controlling the plurality of semiconductor elements;
The control circuit includes:
When an ON operation drive signal is given from outside,
As a start control, a gate signal is supplied to the start semiconductor element with a constant current by the constant current circuit to turn on the semiconductor element,
As the next-stage drive control, when the current detected by the current detection circuit provided in the semiconductor element that has been turned on reaches a set threshold current, the changeover switch is set to an operating state, and the next-stage drive in the off state is performed. A gate signal at a constant voltage to the semiconductor element for
Thereafter, when there is a semiconductor element for driving the next stage in the off state, the next-stage driving control is configured to be repeatedly executed,
The threshold current is a sum of an on-resistance loss and a switching loss generated by all of the semiconductor elements in an on state when the semiconductor element for driving the next stage of the plurality of semiconductor elements is turned on and a current flows. Is set to be smaller than before the execution of the next-stage drive control. In the configuration in which the plurality of semiconductor elements (22, 23) for driving the next stage are provided,
The control circuit (32) includes a semiconductor element (22) for driving the next stage and the semiconductor element (21) for starting, excluding the semiconductor element (23) for final driving, of the plurality of semiconductor elements. The gate drive device according to claim 1, wherein the order of the on-operation is configured to be changeable. The current detection circuits (33, 34, 35) are provided in all of the plurality of semiconductor elements (21, 22, 23),
The gate drive device according to claim 1, wherein the control circuit (32) is configured to be able to change an order in which the plurality of semiconductor elements are turned on. The control circuit (9, 32)
In a state where a plurality of semiconductor elements (1, 2, 21, 22, 23) are turned on,
4. The gate drive device according to claim 1, wherein the plurality of semiconductor elements that are turned on are turned off at different timings. 5. The control circuit (9, 32)
In a state where a plurality of semiconductor elements (1, 2, 21, 22, 23) are turned on,
5. The semiconductor device according to claim 1, wherein, when the current value detected by the current detection circuit is lower than a predetermined threshold current, the semiconductor device is turned off. The gate drive device according to claim 1. The control circuit (9, 32)
In a state where any one of the plurality of semiconductor elements (1, 2, 21, 22, 23) is turned on,
The gate drive device according to claim 1, wherein the next-stage drive control is performed on an off-state of the plurality of semiconductor elements.

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