WO2015022860A1 - Switching device - Google Patents

Switching device Download PDF

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Publication number
WO2015022860A1
WO2015022860A1 PCT/JP2014/070092 JP2014070092W WO2015022860A1 WO 2015022860 A1 WO2015022860 A1 WO 2015022860A1 JP 2014070092 W JP2014070092 W JP 2014070092W WO 2015022860 A1 WO2015022860 A1 WO 2015022860A1
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WIPO (PCT)
Prior art keywords
semiconductor element
time
timing
semiconductor
switching device
Prior art date
Application number
PCT/JP2014/070092
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French (fr)
Japanese (ja)
Inventor
卓 下村
林　哲也
啓一郎 沼倉
崇 広田
大 津川
Original Assignee
日産自動車株式会社
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Publication of WO2015022860A1 publication Critical patent/WO2015022860A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/12—Modifications for increasing the maximum permissible switched current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H03K17/163—Soft switching
    • H03K17/164—Soft switching using parallel switching arrangements

Definitions

  • the present invention relates to a switching device for switching between conduction and non-conduction of a circuit by connecting a plurality of semiconductor elements in parallel.
  • a switching device in which a plurality of semiconductor elements (for example, FETs, IGBTs) are connected in parallel and each semiconductor element is interlocked to switch between on and off, thereby switching between conduction and non-conduction (shutoff) of the load circuit. Many are used.
  • a cooling device is provided to cool the semiconductor element.
  • the cooling device does not necessarily uniformly cool all semiconductor elements, and the cooling effect varies. For this reason, the problem that the dispersion
  • Patent Document 1 discloses a technique for increasing the switching speed of a semiconductor element by reducing the gate resistance of the semiconductor element provided at a position where cooling efficiency is low, thereby making the temperature of the plurality of semiconductor elements uniform. ing.
  • Patent Document 1 describes a configuration that increases the switching speed for the purpose of reducing the amount of heat generation.
  • the switching speed is increased, when another semiconductor element is in an off state, a current flows only to one semiconductor element that has been turned on first, and there is a problem that the amount of heat generation increases.
  • the present invention has been made to solve such a conventional problem, and an object of the present invention is to control the temperature of a plurality of semiconductor elements connected in parallel to be uniform. It is to provide a switching device.
  • a switching device includes a switch control that outputs a plurality of semiconductor elements connected in parallel and a control signal that switches between conduction and non-conduction of each semiconductor element in conjunction with each other. Part. Then, the switch control unit sets at least one of the off timing and the on timing of the semiconductor element to be different from the other semiconductor elements.
  • FIG. 1 is a circuit diagram showing a connection state of semiconductor elements in switching devices according to first to third embodiments of the present invention.
  • FIG. 2 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the first embodiment of the present invention.
  • FIG. 3 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the second embodiment of the present invention.
  • FIG. 4 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the third embodiment of the present invention.
  • FIG. 5 is a circuit diagram showing the connection state of the semiconductor elements in the switching device according to the fourth embodiment of the present invention.
  • FIG. 6 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the fourth embodiment of the present invention.
  • FIG. 7 is a circuit diagram showing a connection state of the semiconductor elements in the switching device according to the fifth embodiment of the present invention.
  • FIG. 8 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the fifth embodiment of the present invention.
  • FIG. 9 is a block diagram showing a drive circuit of the first control method by the switching device according to the present invention.
  • FIG. 10 is a timing chart showing changes in the control signal in the first control method by the switching device according to the present invention.
  • FIG. 11 is a block diagram showing a drive circuit of the second control method by the switching device according to the present invention.
  • FIG. 12 is a timing chart showing changes in control signals in the second control method by the switching device according to the present invention.
  • FIG. 13 is a block diagram showing a drive circuit of a third control method by the switching device according to the present invention.
  • FIG. 14 is a timing chart showing changes in the control signal in the third control method by the switching device according to the present invention.
  • FIG. 15 is a block diagram showing a drive circuit of a fourth control method by the switching device according to the present invention.
  • FIG. 16 is a timing chart showing changes in the control signal in the fourth control method by the switching device according to the present invention.
  • FIG. 17 is a circuit diagram showing a connection state of the semiconductor elements in the switching device according to the sixth embodiment of the present invention.
  • FIG. 18 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the sixth embodiment of the present invention.
  • FIG. 19 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the seventh embodiment of the present invention.
  • two semiconductor elements that is, a first semiconductor element Q1 and a second semiconductor element Q2 are connected in parallel to two electrodes a1 and a2.
  • the semiconductor elements Q1 and Q2 connected in parallel are connected to, for example, a load circuit (not shown) to switch the load circuit on (conductive) and off (non-conductive).
  • the electrode a1 shown in FIG. 1 is connected to a DC power source
  • the electrode a2 is connected to a load
  • the semiconductor elements Q1 and Q2 are controlled to be turned on and off in conjunction with each other, thereby supplying and stopping current to the load ( That is, the driving and stopping of the load can be controlled.
  • the first semiconductor element Q1 and the second semiconductor element Q2 are, for example, FETs (field effect transistors) or IGBTs (insulated gate bipolar transistors).
  • a cooling device 51 for cooling the semiconductor elements Q1 and Q2 is provided in the vicinity of the semiconductor elements Q1 and Q2.
  • the semiconductor elements Q1 and Q2 may have the same shape and the same electrical characteristics, or may be different.
  • the time when the semiconductor elements Q1 and Q2 are turned on (on (Timing) is adjusted to control the heat generation amount of each of the semiconductor elements Q1 and Q2. That is, the switching loss of each of the semiconductor elements Q1 and Q2 changes by changing the time to turn on, so that the amount of heat generated due to this switching loss can be controlled.
  • the on-time of the first semiconductor element Q1 is delayed with respect to the on-time of the second semiconductor element Q2.
  • the switching loss of each of the semiconductor elements Q1, Q2 is adjusted, and consequently, the amount of heat generated by each of the semiconductor elements Q1, Q2 is adjusted. That is, by setting the ON time of the first semiconductor element Q1 to time T2 and the ON time of the second semiconductor element Q2 to time T1 earlier than the time T2, the amount of heat generated by the second semiconductor element Q2 is set to the first semiconductor element Q1. It can be made relatively higher than the calorific value.
  • the control signals supplied to the control terminals of the semiconductor elements Q1 and Q2 are not limited to electrical signals, and can be signals such as light, electric field, magnetic field, pressure, and sound wave.
  • the heat generation amount of each of the semiconductor elements Q1 and Q2 can be adjusted by individually setting the on times T1 and T2 shown in FIG. Accordingly, even when the on-resistances of the semiconductor elements Q1 and Q2 are different due to differences in the shape and electrical characteristics of the semiconductor elements Q1 and Q2, and the steady loss that is the amount of heat generated at the time of on is different, the semiconductor elements Q1 and Q2 are different. It is possible to adjust the temperature balance of Q2.
  • the second semiconductor element Q2 shown in FIG. 1 when the second semiconductor element Q2 shown in FIG. 1 is arranged at a position where the cooling effect by the cooling device 51 is high, and the first semiconductor element Q1 is arranged at a position where the cooling effect is relatively low,
  • the time at which the second semiconductor element Q2 is turned on is relatively earlier than the time at which the first semiconductor element Q1 is turned on (T1 in FIG. 2).
  • T1 in FIG. 2 the amount of heat generated by the first semiconductor element Q1 can be relatively reduced, and as a result, the temperatures of the semiconductor elements Q1 and Q2 can be kept substantially constant.
  • the switching loss amount can be adjusted by the time difference between the two ON times T1 and T2. That is, the larger the time difference is, the larger the switching loss is, so that the difference in heat generation amount can be increased. Further, it is desirable that the ON time T2 of the first semiconductor element Q1 is within the period from the ON time T1 to the OFF time T3 (T4) of the second semiconductor element Q2 and close to the time T1. Note that specific control methods for the switching device according to the first embodiment will be described in first to fourth control methods described later.
  • the temperature of each semiconductor element can be adjusted even when there is a difference in the shape and electrical characteristics of each semiconductor element. It can be controlled to be uniform.
  • an on time (on timing) for switching from off (non-conduction) to on (conduction) for at least one semiconductor element (for example, Q1) is set to another semiconductor element (for example, Q1). , Q2), the temperature of each semiconductor element can be kept substantially uniform. Therefore, it is possible to suppress temperature variations among the respective semiconductor elements, and to avoid problems such as a large load applied only to a specific semiconductor. Moreover, since the ON time of each semiconductor element is changed according to the cooling effect by the cooling device 51, the temperature variation can be suppressed. In particular, since the on-time is delayed for the semiconductor element (for example, Q1) arranged at a position where the cooling effect by the cooling device 51 is low, even if the cooling effect varies, the temperature of each semiconductor element is kept uniform. can do.
  • FIG. 3 is a timing chart of the switching device according to the second embodiment.
  • the configuration of the switching device according to the second embodiment is the same as that in FIG.
  • the time at which the semiconductor elements Q1 and Q2 are turned off is adjusted, and the heat generation of the semiconductor elements Q1 and Q2 is performed. Control the amount. That is, by changing the off time, the switching loss of each of the semiconductor elements Q1, Q2 changes, so that the amount of heat generated due to this switching loss can be controlled.
  • the off time of the second semiconductor element Q2 is delayed with respect to the off time of the first semiconductor element Q1.
  • the switching loss of each of the semiconductor elements Q1, Q2 is adjusted, and consequently, the amount of heat generated by each of the semiconductor elements Q1, Q2 is adjusted. That is, by delaying the off time T3 of the second semiconductor element Q2 from the off time T4 of the first semiconductor element Q1, the amount of heat generated by the second semiconductor element Q2 is made relatively larger than the amount of heat generated by the first semiconductor element Q1. Can be high.
  • the control signals supplied to the semiconductor elements Q1 and Q2 are not limited to electrical signals, and may be signals such as light, electric field, magnetic field, pressure, and sound wave.
  • the heat generation amount of each semiconductor element Q1, Q2 can be adjusted by individually setting the off times T3, T4 shown in FIG. Accordingly, even when the on-resistances of the semiconductor elements Q1 and Q2 are different due to differences in the shape and electrical characteristics of the semiconductor elements Q1 and Q2, and the steady loss that is the amount of heat generated at the time of on is different, the semiconductor elements Q1 , Q2 temperature balance can be adjusted.
  • the second semiconductor element Q2 shown in FIG. 1 when the second semiconductor element Q2 shown in FIG. 1 is arranged at a position where the cooling effect by the cooling device 51 is high, and the first semiconductor element Q1 is arranged at a position where the cooling effect is relatively low,
  • the time at which the second semiconductor element Q2 is turned off is relatively delayed with respect to the time at which the first semiconductor element Q1 is turned off (T3 in FIG. 3).
  • T3 in FIG. 3 the amount of heat generated by the first semiconductor element Q1 can be relatively reduced, and as a result, the temperatures of the semiconductor elements Q1 and Q2 can be kept substantially constant.
  • the switching loss amount can be adjusted by the time difference between the two off times T3 and T4. That is, the larger the time difference is, the larger the switching loss is, so that the difference in heat generation amount can be increased. Further, it is desirable that the time T4 is within the period from the time T1 (T2) to the time T3 and is close to T3. A specific control method for the switching device according to the second embodiment will be described in first to fourth control methods described later.
  • the temperature of each semiconductor element is It can be controlled to be uniform.
  • an off time (off timing) for switching from on (conducting) to off (non-conducting) is set to another semiconductor element (for example, , Q2), the temperature of each semiconductor element can be kept substantially uniform. Therefore, it is possible to suppress temperature variations among the respective semiconductor elements, and to avoid problems such as a large load applied only to a specific semiconductor. Moreover, since the off time of each semiconductor element is changed according to the cooling effect by the cooling device 51, the temperature variation can be suppressed. In particular, since the off time is advanced for the semiconductor element (for example, Q1) arranged at a position where the cooling effect by the cooling device 51 is low, even if the cooling effect varies, the temperature of each semiconductor element is kept uniform. can do.
  • FIG. 4 is a timing chart of the switching device according to the third embodiment.
  • the configuration of the switching device according to the third embodiment is the same as that in FIG.
  • the control signal supplied to the control terminals of the semiconductor elements Q1 and Q2 by changing the control signal supplied to the control terminals of the semiconductor elements Q1 and Q2, the time when the semiconductor elements Q1 and Q2 are turned on and the time when the semiconductor elements Q1 and Q2 are turned off are adjusted.
  • the amount of heat generated by the elements Q1 and Q2 is controlled. That is, by changing both the on time and the off time, the switching loss of each of the semiconductor elements Q1 and Q2 changes, so that the amount of heat generated due to this switching loss can be controlled.
  • the ON time of the second semiconductor element Q2 is advanced with respect to the ON time and OFF time of the first semiconductor element Q1, and the OFF time is further delayed. .
  • the switching loss of each of the semiconductor elements Q1, Q2 is adjusted, and consequently, the amount of heat generated by each of the semiconductor elements Q1, Q2 is adjusted. That is, the ON time T1 of the second semiconductor element Q2 is set earlier than the ON time T2 of the first semiconductor element Q1, and the OFF time T3 of the second semiconductor element Q2 is set to be higher than the OFF time T4 of the first semiconductor element Q1. Delay.
  • the control signals supplied to the semiconductor elements Q1 and Q2 are not limited to electrical signals, and may be signals such as light, electric field, magnetic field, pressure, and sound wave.
  • the heat generation amounts of the semiconductor elements Q1 and Q2 can be adjusted by individually setting the on times T1 and T2 and the off times T3 and T4 shown in FIG. Accordingly, even when the on-resistances of the semiconductor elements Q1 and Q2 are different due to differences in the shape and electrical characteristics of the semiconductor elements Q1 and Q2, and the steady loss that is the amount of heat generated at the time of on is different, the semiconductor elements Q1 , Q2 temperature balance can be adjusted.
  • the second semiconductor element Q2 shown in FIG. 1 when the second semiconductor element Q2 shown in FIG. 1 is arranged at a position where the cooling effect by the cooling device 51 is high, and the first semiconductor element Q1 is arranged at a position where the cooling effect is relatively low,
  • the on time of the second semiconductor element Q2 is relatively earlier than the on time of the first semiconductor element Q1 (T1 in FIG. 4), and the second semiconductor element is compared with the off time of the first semiconductor element Q1.
  • the off time of Q2 is relatively delayed (T3 in FIG. 4).
  • the switching loss amount can be adjusted by the time difference between the two on times T1 and T2 and the time difference between the two off times T3 and T4. That is, the larger the time difference is, the larger the switching loss is, so that the difference in heat generation amount can be increased.
  • the time T2 is within a period from the time T1 to the off time T4, and is preferably close to the time T1.
  • it is desirable that the time T4 is within the period from the time T2 to the time T3 and is close to T3.
  • the switching device As described above, in the switching device according to the present embodiment, even when there is a difference in the shape and electrical characteristics of each semiconductor element by adjusting the off timing and the on timing of the semiconductor element, It is possible to control so that the temperature is uniform.
  • At least one semiconductor element for example, Q1 is switched from off (non-conduction) to on (conduction) on time (on timing) and from on (conduction). Since the off time (off timing) for switching to off (non-conduction) is set to be different from that of other semiconductor elements (for example, Q2), the temperature of each semiconductor element can be maintained substantially uniformly. Therefore, it is possible to suppress temperature variations among the respective semiconductor elements, and to avoid problems such as a large load applied only to a specific semiconductor.
  • each semiconductor element since the on time and the off time of each semiconductor element are changed according to the cooling effect by the cooling device 51, the temperature variation can be suppressed.
  • the semiconductor element for example, Q1 arranged at a position where the cooling effect by the cooling device 51 is low, the on time is delayed and the off time is advanced, so even if the cooling effect varies, each semiconductor device The temperature of the element can be kept uniform.
  • FIG. 5 and 6 are an explanatory diagram and a timing chart showing the switching device according to the fourth embodiment.
  • the first semiconductor element Q1 and the second semiconductor element Q2 are connected to the two electrodes a1 and a2 in the same manner as in the first embodiment described above. Connected in parallel.
  • the semiconductor elements Q1 and Q2 connected in parallel are connected to, for example, a load circuit (not shown) to control on (conduction) and off (non-conduction) of the load circuit.
  • the semiconductor elements Q1 and Q2 may have the same shape and the same electrical characteristics, or may be different.
  • the heat resistance ⁇ 1 (difficult to dissipate heat) of the heat removal path of the first semiconductor element Q1 is relatively larger than the heat resistance ⁇ 2 of the heat removal path of the second semiconductor element Q2. That is, ⁇ 1> ⁇ 2.
  • the on time and the off time of each semiconductor element Q1, Q2 are adjusted, and each semiconductor element Q1. , Q2 is controlled. That is, by changing the on time and the off time, the switching loss of each of the semiconductor elements Q1, Q2 changes, so that the amount of heat generated due to this switching loss can be controlled.
  • the ON time of the second semiconductor element Q2 is advanced with respect to the ON time and OFF time of the first semiconductor element Q1, and the OFF time is further delayed. .
  • the switching loss of each of the semiconductor elements Q1, Q2 is adjusted, and consequently, the amount of heat generated by each of the semiconductor elements Q1, Q2 is adjusted.
  • the on-time T1 is advanced, and the heat resistance in the heat removal path is relatively large (thermal resistance ⁇ 1).
  • the ON time T2 is relatively delayed.
  • the off time T3 is delayed for the second semiconductor element Q2, and the off time T4 is relatively advanced for the first semiconductor element Q1.
  • the heat generation amount of the second semiconductor element Q2 can be made relatively higher than the heat generation amount of the first semiconductor element Q1.
  • the control signals supplied to the semiconductor elements Q1 and Q2 are not limited to electrical signals, and may be signals such as light, electric field, magnetic field, pressure, and sound wave.
  • the heat generation amount of the first semiconductor element Q1 is made relatively lower than the heat generation amount of the second semiconductor element Q2. It becomes possible. For this reason, the amount of heat generated by the first semiconductor element Q1, which has a large heat extraction resistance and is difficult to dissipate heat, can be reduced, so that the temperature of each of the semiconductor elements Q1, Q2 can be kept substantially constant.
  • the switching loss amount can be adjusted by the time difference between the two on times T1 and T2 and the time difference between the two off times T3 and T4. That is, the larger the time difference is, the larger the switching loss is, so that the difference in heat generation amount can be increased.
  • the time T2 is within a period from the time T1 to the time T4, and is preferably close to the time T1. Furthermore, it is desirable that the time T4 is within the period from the time T2 to the time T3 and is close to T3.
  • the semiconductor element (for example, Q1) installed at a position with a high heat removal resistance is installed at a position with a relatively low heat extraction resistance. Since the on-timing is set to be delayed and the off-timing is set to be earlier with respect to the semiconductor element (for example, Q2), the temperature of each semiconductor element can be kept substantially uniform. Become. Therefore, it is possible to suppress temperature variations among the respective semiconductor elements, and to avoid problems such as a large load applied only to a specific semiconductor.
  • FIG. 7 and 8 are an explanatory diagram and a timing chart showing the switching device according to the fifth embodiment.
  • the first semiconductor element Q1 and the second semiconductor element Q2 are connected to the two electrodes a1 and a2 as in the first embodiment described above. They are connected in parallel to each other.
  • the semiconductor elements Q1 and Q2 connected in parallel are connected to, for example, a load circuit (not shown) to control on (conduction) and off (non-conduction) of the load circuit.
  • the semiconductor elements Q1 and Q2 may have the same shape and the same electrical characteristics, or may be different.
  • the ambient temperature (t1) of the first semiconductor element Q1 is relatively higher than the ambient temperature (t2) of the second semiconductor element Q2.
  • the heat generation temperature of the first semiconductor element Q1 has a characteristic that it is relatively higher than the heat generation temperature of the second semiconductor element Q2.
  • the on time and the off time of each semiconductor element Q1, Q2 are adjusted, and each semiconductor element Q1. , Q2 is controlled. That is, by changing the on time and the off time, the switching loss of each of the semiconductor elements Q1, Q2 changes, so that the amount of heat generated due to this switching loss can be controlled.
  • the ON time of the second semiconductor element Q2 is advanced with respect to the ON time and OFF time of the first semiconductor element Q1, and the OFF time is further delayed. .
  • the switching loss of each of the semiconductor elements Q1, Q2 is adjusted, and consequently, the amount of heat generated by each of the semiconductor elements Q1, Q2 is adjusted.
  • the ON time T1 of the second semiconductor element Q2 is set earlier than the ON time T2 of the first semiconductor element Q1, and the OFF time T3 of the second semiconductor element Q2 is set to be higher than the OFF time T4 of the first semiconductor element Q1. Delay. Thereby, the heat generation amount of the second semiconductor element Q2 can be made relatively higher than the heat generation amount of the first semiconductor element Q1.
  • the control signals supplied to the semiconductor elements Q1 and Q2 are not limited to electrical signals, and may be signals such as light, electric field, magnetic field, pressure, and sound wave.
  • the heat generation amount of the first semiconductor element Q1 is made relatively lower than the heat generation amount of the second semiconductor element Q2. It becomes possible. For this reason, the amount of heat generated by the first semiconductor element Q1 disposed at a high ambient temperature can be reduced, so that the temperature of each of the semiconductor elements Q1 and Q2 can be kept substantially constant.
  • the switching loss amount can be adjusted by the time difference between the two on times T1 and T2 and the time difference between the two off times T3 and T4. That is, the larger the time difference is, the larger the switching loss is, so that the difference in the heat generation amount can be increased.
  • the time T2 is within a period from the time T1 to the time T4, and is preferably close to the time T1. Furthermore, it is desirable that the time T4 is within the period from the time T2 to the time T3 and is close to T3. Note that specific control methods for the switching device according to the fifth embodiment will be described in first to fourth control methods described later.
  • the semiconductor element (for example, Q1) installed at a position where the ambient temperature is high is installed at a position where the ambient temperature is relatively low.
  • the semiconductor element (for example, Q2) is set so that the on-timing is delayed, and further, the off-timing is set so that the temperature of each semiconductor element can be kept substantially uniform. Therefore, it is possible to suppress temperature variations among the respective semiconductor elements, and to avoid problems such as a large load applied only to a specific semiconductor.
  • FIG. 9 is a block diagram showing a drive circuit according to the first control method
  • FIG. 10 is a timing chart of control signals.
  • a drive circuit 11 switch control unit
  • the drive circuit 11 outputs a first control signal Vg1 and a second control signal Vg2 to a control unit 12 that outputs a time difference command value and generates a drive signal to the control terminals of the semiconductor elements Q1 and Q2.
  • a drive signal generator 13a and a second drive signal generator 13b are provided.
  • a drive signal is output at a preset timing from each of the drive signal generating units 13a and 13b. That is, the first drive signal generator 13a outputs the first control signal Vg1, and the second drive signal generator 13b outputs the second control signal Vg2.
  • the first control signal Vg1 is supplied to the control terminal (gate in the case of FET) of the first semiconductor element Q1, and the second control signal Vg2 is supplied to the control terminal of the second semiconductor element Q2.
  • the drive circuit 11 can be configured as an integrated computer including a central processing unit (CPU), storage means such as RAM, ROM, and hard disk.
  • CPU central processing unit
  • storage means such as RAM, ROM, and hard disk.
  • FIG. 10 is a timing chart showing change characteristics of the first control signal Vg1 and the second control signal Vg2.
  • the second control signal Vg2 is switched from OFF to ON at time T5, and is switched from ON to OFF at time T9. Therefore, the second semiconductor element Q2 is turned on at time T7 slightly delayed from time T5, and is turned off at time T11 slightly delayed from time T9.
  • the first control signal Vg1 is set so that the ON time is later than the second control signal Vg2, and the OFF time is earlier. That is, as shown in FIG. 10B, the first control signal Vg1 is switched from OFF to ON at time T6 later than time T5, and is switched from ON to OFF at time T10 earlier than time T9. Accordingly, the first semiconductor element Q1 is turned on at time T8 slightly delayed from time T6, and is turned off at time T12 slightly delayed from time T10.
  • each semiconductor element Q1 is controlled.
  • Q2 can be set arbitrarily.
  • control signals Vg1 and Vg2 are controlled to have different on times, and in the second embodiment, the control signals Vg1 and Vg2 are controlled to have different off times. . In the third to fifth embodiments, the control signals Vg1 and Vg2 are controlled so that both the on time and the off time are different.
  • the on timing and the off timing are controlled by adjusting at least one of the rising timing and falling timing of the control signal output to the control terminal of the semiconductor element. Can do. Therefore, the ON time and the OFF time of each semiconductor element Q1, Q2 can be adjusted with simple control, and the temperature of each semiconductor element Q1, Q2 can be made uniform.
  • FIG. 11 is a block diagram showing a drive circuit according to the second control method
  • FIG. 12 is a timing chart of control signals.
  • a drive circuit 21 (switch control unit) is connected to the control terminals of the first semiconductor element Q1 and the second semiconductor element Q2.
  • the drive circuit 21 includes a drive signal generator 22 that outputs a drive command signal, diodes D1 and D2, and resistors Rg1 to Rg4.
  • the diode D1 and the resistor Rg1 are connected in series, and the resistor Rg2 is connected in parallel to the series connection.
  • the parallel connection circuit is connected to the control terminal of the first semiconductor element Q1.
  • the diode D2 and the resistor Rg3 are connected in series, and the resistor Rg4 is connected in parallel to the series connection.
  • the parallel connection circuit is connected to the control terminal of the second semiconductor element Q2.
  • the drive signal generator 22 can be configured as an integrated computer including a central processing unit (CPU) and storage means such as RAM, ROM, and hard disk.
  • CPU central processing unit
  • storage means such as RAM, ROM, and hard disk.
  • the first control signal Vg1 is output to the control terminal of the first semiconductor element Q1 via the parallel connection circuit of the resistors Rg1 and Rg2. Further, the second control signal Vg2 is output to the control terminal of the second semiconductor element Q2 via the parallel connection circuit of the resistors Rg3 and Rg4. At this time, as described above, since there is a relationship of “Rg1> Rg3”, the ON time of the first semiconductor element Q1 is later than the ON time of the second semiconductor element Q2.
  • the second control signal Vg2 gradually increases in voltage after being turned on at time T5. Then, at time T7, the second semiconductor element Q2 is turned on.
  • the on-timing can be controlled by adjusting the rising slope of the control signal output to the control terminal of each of the semiconductor elements Q1 and Q2. Therefore, the ON time of each semiconductor element Q1, Q2 can be adjusted with simple control, and the temperature of each semiconductor element Q1, Q2 can be made uniform.
  • the slope of the rising edge of the control signal can be adjusted by changing the magnitude of the resistor connected to the control terminal of each of the semiconductor elements Q1 and Q2, the configuration can be further simplified.
  • FIG. 13 is a block diagram showing a drive circuit according to the third control method
  • FIG. 14 is a timing chart of control signals.
  • a drive circuit 31 (switch control unit) is connected to the control terminals of the first semiconductor element Q1 and the second semiconductor element Q2.
  • the drive circuit 31 includes a drive signal generator 32 that outputs a drive command signal, diodes D11 and D12, and resistors Rg1 to Rg4.
  • the diode D11 and the resistor Rg2 are connected in series, and the resistor Rg1 is connected in parallel to the series connection.
  • the parallel connection circuit is connected to the control terminal of the first semiconductor element Q1.
  • the diode D12 and the resistor Rg4 are connected in series, and the resistor Rg3 is connected in parallel to the series connection.
  • the drive signal generation unit 32 can be configured as an integrated computer including a central processing unit (CPU) and storage means such as a RAM, a ROM, and a hard disk.
  • CPU central processing unit
  • storage means such as a RAM, a ROM, and a hard disk.
  • the first control signal Vg1 is output to the control terminal of the first semiconductor element Q1 via the resistor Rg1.
  • the second control signal Vg2 is output to the control terminal of the second semiconductor element Q2 via the resistor Rg3.
  • Rg1 Rg3
  • the presence of the diodes D11 and D12 causes the first control signal Vg1 and the second control signal Vg2 to increase in voltage with the same characteristics. . Therefore, the on time of the first semiconductor element Q1 and the on time of the second semiconductor element Q2 coincide.
  • the off time of the first semiconductor element Q1 can be relatively advanced with respect to the second semiconductor element Q2.
  • the off time of the first semiconductor element Q1 can be advanced with respect to the second semiconductor element Q2.
  • the off timing can be controlled by adjusting the slope of the fall of the control signal output to the control input terminal of each of the semiconductor elements Q1 and Q2. Therefore, the off time of each semiconductor element Q1, Q2 can be adjusted with simple control, and the temperature of each semiconductor element Q1, Q2 can be made uniform.
  • FIG. 15 is a block diagram showing a drive circuit according to the fourth control method
  • FIG. 16 is a timing chart of control signals.
  • a drive circuit 41 (switch control unit) is connected to the control terminals of the first semiconductor element Q1 and the second semiconductor element Q2.
  • the drive circuit 41 includes a drive signal generator 42 that outputs a drive command signal, diodes D21, D22, D23, and D24, and resistors Rg1 to Rg4.
  • the diode D21 and the resistor Rg1 are connected in series, the diode D22 and the resistor Rg2 are connected in series, and the series connection circuits are connected in parallel to each other.
  • the parallel connection circuit is connected to the control terminal of the first semiconductor element Q1.
  • the diode D23 and the resistor Rg3 are connected in series
  • the diode D24 and the resistor Rg4 are connected in series
  • the series connection circuits are connected in parallel to each other.
  • the parallel connection circuit is connected to the control terminal of the second semiconductor element Q2.
  • the resistance values of the resistors Rg1 to Rg4 have a relationship of “Rg1> Rg3” and “Rg2 ⁇ Rg4”.
  • the drive signal generator 42 can be configured as an integrated computer including a central processing unit (CPU) and storage means such as a RAM, a ROM, and a hard disk.
  • CPU central processing unit
  • storage means such as a RAM, a ROM, and a hard disk.
  • the first control signal Vg1 is output to the control terminal of the first semiconductor element Q1 via the resistor Rg1.
  • the second control signal Vg2 is output to the control terminal of the second semiconductor element Q2 via the resistor Rg3.
  • the ON time of the second semiconductor element Q2 is earlier than the ON time of the first semiconductor element Q1.
  • the second control signal Vg2 gradually increases in voltage after being turned on at time T5. Then, at time T7, the second semiconductor element Q2 is turned on.
  • the first control signal Vg1 decreases via the resistor Rg2. Further, the second control signal Vg2 decreases via the resistor Rg4. At this time, as described above, since there is a relationship of “Rg2 ⁇ Rg4”, the off time of the second semiconductor element Q2 is later than the off time of the first semiconductor element Q1.
  • the voltage of the second control signal Vg2 gradually decreases after being turned off at time T9. Then, at time T11, the second semiconductor element Q2 is turned off.
  • the first semiconductor element Q1 is turned off at time T12 slightly earlier than time T11. Therefore, the off time of the first semiconductor element Q1 can be relatively advanced with respect to the second semiconductor element Q2.
  • the on-time of the first semiconductor element Q1 is delayed with respect to the second semiconductor element Q2, and The off time can be advanced.
  • the on-timing and off-timing are controlled by adjusting the rising and falling slopes of the control signals output to the control input terminals of the semiconductor elements Q1 and Q2. can do. Therefore, the ON time and the OFF time of each semiconductor element Q1, Q2 can be adjusted with simple control, and the temperature of each semiconductor element Q1, Q2 can be made uniform.
  • the rising slope and falling slope of the control signal can be adjusted, so that the configuration can be further simplified. It becomes possible.
  • three semiconductor elements that is, a first semiconductor element Q11, a second semiconductor element Q12, and a third semiconductor element Q13 are formed on two electrodes a1 and a2. On the other hand, they are connected in parallel.
  • the semiconductor elements Q11 to Q13 connected in parallel are connected to, for example, a load circuit (not shown) to control on (conduction) and off (non-conduction) of the load circuit.
  • a load circuit not shown
  • each of the semiconductor elements Q11 to Q13 is, for example, an FET (field effect transistor) or an IGBT (insulated gate bipolar transistor).
  • the semiconductor elements Q11 to Q13 may have the same shape and the same electrical characteristics, or may be different.
  • the control signal supplied to the control terminals (gate terminals in the case of FETs) of the semiconductor elements Q11 to Q13 by changing the control signal supplied to the control terminals (gate terminals in the case of FETs) of the semiconductor elements Q11 to Q13, the time when the semiconductor elements Q11 to Q13 are turned on, and The amount of heat generated by each of the semiconductor elements Q11 to Q13 is controlled by adjusting the time to turn off. That is, by changing the on time and the off time, the switching loss of each of the semiconductor elements Q11 to Q13 changes, so that the amount of heat generated due to this switching loss can be controlled.
  • the ON time of the second semiconductor element Q12 is delayed with respect to the ON time and OFF time of the first semiconductor element Q11 (see T13 and T14). ) And advance the off time (see T16 and T17). Thereby, the heat generation amount of the second semiconductor element Q12 can be made lower than the heat generation amount of the first semiconductor element Q11.
  • the ON time of the third semiconductor element Q13 is delayed with respect to the ON time and OFF time of the second semiconductor element Q12 (see T14 and T15), and the OFF time is advanced (see T17 and T18). Thereby, the heat generation amount of the third semiconductor element Q13 can be made lower than the heat generation amount of the second semiconductor element Q12.
  • the control signals supplied to the control terminals of the semiconductor elements Q11 to Q13 are not limited to electrical signals, and may be signals such as light, electric field, magnetic field, pressure, and sound wave.
  • the amount of heat generated by each of the semiconductor elements Q11 to Q13 can be adjusted. Therefore, even if the semiconductor elements Q11 to Q13 have different on-resistances due to differences in the shape and electrical characteristics of the semiconductor elements Q11 to Q13, and the steady loss that is the amount of heat generated when the semiconductor elements are turned on, the semiconductor elements Q11 to Q13 are different. It is possible to adjust the temperature balance of .about.Q13. That is, by setting the on times (T13, T14, T15 shown in FIG. 18) of each of the semiconductor elements Q11 to Q13 individually and individually setting the off times (T16, T17, T18), It is possible to adjust the temperature balance of Q11 to Q13.
  • the first semiconductor element Q11 shown in FIG. 17 is disposed at a position where the cooling effect by the cooling device is high, the second semiconductor element Q12 is disposed at a position where the cooling effect is relatively low, and further, the third semiconductor element Q13.
  • the on time is advanced and the off time is delayed in the order of Q11, Q12, and Q13.
  • the emitted-heat amount can be enlarged in order of Q11, Q12, Q13.
  • the temperatures of the semiconductor elements Q11 to Q13 can be kept substantially constant.
  • the temperature of each semiconductor element is set as in the first to fifth embodiments described above. It becomes possible to make uniform.
  • the ON time and OFF time of the first semiconductor element Q11 and the third semiconductor element Q13 are made the same, and the ON time and OFF time of the second semiconductor element Q12 are set to be different.
  • the ON time of the second semiconductor element Q12 is T14 that is slightly later than T13, and the OFF time is T17 that is slightly earlier than T16.
  • the heat generation amounts of the first semiconductor element Q11 and the third semiconductor element Q13 can be made substantially the same, and the heat generation amount of the second semiconductor element Q12 can be relatively reduced. Therefore, for example, when the second semiconductor element Q12 is arranged at a position where the cooling effect by the cooling device is low, and the first semiconductor element Q11 and the third semiconductor element Q13 are arranged at a position where the cooling effect is relatively high, The amount of heat generated by the second semiconductor element Q2 can be reduced relative to the first semiconductor element Q11 and the third semiconductor element Q13. Therefore, as a result, the temperatures of the semiconductor elements Q11 to Q13 can be kept substantially constant. Note that as a specific control method of the switching device according to the seventh embodiment, the same method as the first to fourth control methods described above can be used.
  • the temperature of each semiconductor element is set as in the first to fifth embodiments. It becomes possible to make uniform.
  • the switching device of the present invention has been described based on the illustrated embodiment, but the present invention is not limited to this, and the configuration of each part may be replaced with any configuration having the same function. it can.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

A switching device according to the present invention comprises: a plurality of semiconductor elements connected mutually in parallel; and a drive circuit for outputting control signals for switching the ON and OFF times for the semiconductor elements in coordination with each other. For at least one semiconductor element, the drive circuit sets an off-timing for switching from on to off and/or an on-timing for switching from off to on so as to be different from that of the other semiconductor element.

Description

スイッチング装置Switching device
　本発明は、複数の半導体素子を並列に接続して回路の導通、非導通を切り替えるスイッチング装置に関する。 The present invention relates to a switching device for switching between conduction and non-conduction of a circuit by connecting a plurality of semiconductor elements in parallel.
　複数の半導体素子（例えば、ＦＥＴ、ＩＧＢＴ）を並列に接続し、各半導体素子を連動させてオン、オフを切り替えることにより、負荷回路の導通、非導通（遮断）を切り替えるようにしたスイッチング装置が多く用いられている。このような、スイッチング装置においては、各半導体素子が発熱するので、半導体素子を冷却するために冷却装置が設けられている。しかし、冷却装置は、全ての半導体素子を均等に冷却するとは限らず、冷却効果にばらつきが生じる。このため、各半導体素子に温度のばらつきが生じるという問題が発生する。 A switching device in which a plurality of semiconductor elements (for example, FETs, IGBTs) are connected in parallel and each semiconductor element is interlocked to switch between on and off, thereby switching between conduction and non-conduction (shutoff) of the load circuit. Many are used. In such a switching device, since each semiconductor element generates heat, a cooling device is provided to cool the semiconductor element. However, the cooling device does not necessarily uniformly cool all semiconductor elements, and the cooling effect varies. For this reason, the problem that the dispersion | variation in temperature arises in each semiconductor element generate | occur | produces.
　特許文献１には、冷却効率の低い位置に設けられた半導体素子のゲート抵抗を小さくすることにより半導体素子のスイッチング速度を速め、これにより複数の半導体素子全体の温度を均一にする技術が開示されている。 Patent Document 1 discloses a technique for increasing the switching speed of a semiconductor element by reducing the gate resistance of the semiconductor element provided at a position where cooling efficiency is low, thereby making the temperature of the plurality of semiconductor elements uniform. ing.
特開２００６－１９１７７４号公報JP 2006-191774 A
　しかしながら、特許文献１のように並列に接続された複数の半導体素子のスイッチング速度にばらつきが生じると、最初に電流が流れ始める半導体素子に電流が集中して流れる。このため、スイッチング速度が速い半導体素子（冷却効率が低い位置に設置された半導体素子）に集中して電流が流れることになり、この半導体素子の発熱量が増えるという問題がある。より詳細に、特許文献１には、発熱量を低減させる目的で、スイッチング速度を速める構成が記載されている。しかし、スイッチング速度を速めると、他の半導体素子がオフ状態であるときに、先にオンとなった一つの半導体素子にのみ電流が流れることになり、却って発熱量が増加するという問題が生じる。 However, when variations occur in the switching speeds of a plurality of semiconductor elements connected in parallel as in Patent Document 1, the current flows in a concentrated manner in the semiconductor element where current starts to flow first. For this reason, a current flows in a concentrated manner in a semiconductor element having a high switching speed (a semiconductor element installed at a position where cooling efficiency is low), and there is a problem that the amount of heat generated by the semiconductor element increases. More specifically, Patent Document 1 describes a configuration that increases the switching speed for the purpose of reducing the amount of heat generation. However, when the switching speed is increased, when another semiconductor element is in an off state, a current flows only to one semiconductor element that has been turned on first, and there is a problem that the amount of heat generation increases.
　本発明は、このような従来の課題を解決するためになされたものであり、その目的とするところは、並列接続された複数の半導体素子の温度が均一となるように制御することが可能なスイッチング装置を提供することにある。 The present invention has been made to solve such a conventional problem, and an object of the present invention is to control the temperature of a plurality of semiconductor elements connected in parallel to be uniform. It is to provide a switching device.
　上記目的を達成するため、本発明の一態様に係るスイッチング装置は、並列に接続された複数の半導体素子と、各半導体素子の導通、非導通を互いに連動して切り替える制御信号を出力するスイッチ制御部とを有する。そして、スイッチ制御部は、半導体素子のオフタイミング及びオンタイミングのうちの少なくとも一方を、他の半導体素子と異なるように設定する。 In order to achieve the above object, a switching device according to one embodiment of the present invention includes a switch control that outputs a plurality of semiconductor elements connected in parallel and a control signal that switches between conduction and non-conduction of each semiconductor element in conjunction with each other. Part. Then, the switch control unit sets at least one of the off timing and the on timing of the semiconductor element to be different from the other semiconductor elements.
図１は、本発明の第１～第３実施形態に係るスイッチング装置における半導体素子の接続状態を示す回路図である。FIG. 1 is a circuit diagram showing a connection state of semiconductor elements in switching devices according to first to third embodiments of the present invention. 図２は、本発明の第１実施形態に係るスイッチング装置における各半導体素子のオン、オフのタイミングを示す図である。FIG. 2 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the first embodiment of the present invention. 図３は、本発明の第２実施形態に係るスイッチング装置における各半導体素子のオン、オフのタイミングを示す図である。FIG. 3 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the second embodiment of the present invention. 図４は、本発明の第３実施形態に係るスイッチング装置における各半導体素子のオン、オフのタイミングを示す図である。FIG. 4 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the third embodiment of the present invention. 図５は、本発明の第４実施形態に係るスイッチング装置における半導体素子の接続状態を示す回路図である。FIG. 5 is a circuit diagram showing the connection state of the semiconductor elements in the switching device according to the fourth embodiment of the present invention. 図６は、本発明の第４実施形態に係るスイッチング装置における各半導体素子のオン、オフのタイミングを示す図である。FIG. 6 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the fourth embodiment of the present invention. 図７は、本発明の第５実施形態に係るスイッチング装置における半導体素子の接続状態を示す回路図である。FIG. 7 is a circuit diagram showing a connection state of the semiconductor elements in the switching device according to the fifth embodiment of the present invention. 図８は、本発明の第５実施形態に係るスイッチング装置における各半導体素子のオン、オフのタイミングを示す図である。FIG. 8 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the fifth embodiment of the present invention. 図９は、本発明に係るスイッチング装置による第１の制御方法の駆動回路を示すブロック図である。FIG. 9 is a block diagram showing a drive circuit of the first control method by the switching device according to the present invention. 図１０は、本発明に係るスイッチング装置による第１の制御方法における制御信号の変化を示すタイミングチャートである。FIG. 10 is a timing chart showing changes in the control signal in the first control method by the switching device according to the present invention. 図１１は、本発明に係るスイッチング装置による第２の制御方法の駆動回路を示すブロック図である。FIG. 11 is a block diagram showing a drive circuit of the second control method by the switching device according to the present invention. 図１２は、本発明に係るスイッチング装置による第２の制御方法における制御信号の変化を示すタイミングチャートである。FIG. 12 is a timing chart showing changes in control signals in the second control method by the switching device according to the present invention. 図１３は、本発明に係るスイッチング装置による第３の制御方法の駆動回路を示すブロック図である。FIG. 13 is a block diagram showing a drive circuit of a third control method by the switching device according to the present invention. 図１４は、本発明に係るスイッチング装置による第３の制御方法における制御信号の変化を示すタイミングチャートである。FIG. 14 is a timing chart showing changes in the control signal in the third control method by the switching device according to the present invention. 図１５は、本発明に係るスイッチング装置による第４の制御方法の駆動回路を示すブロック図である。FIG. 15 is a block diagram showing a drive circuit of a fourth control method by the switching device according to the present invention. 図１６は、本発明に係るスイッチング装置による第４の制御方法における制御信号の変化を示すタイミングチャートである。FIG. 16 is a timing chart showing changes in the control signal in the fourth control method by the switching device according to the present invention. 図１７は、本発明の第６実施形態に係るスイッチング装置における半導体素子の接続状態を示す回路図である。FIG. 17 is a circuit diagram showing a connection state of the semiconductor elements in the switching device according to the sixth embodiment of the present invention. 図１８は、本発明の第６実施形態に係るスイッチング装置における各半導体素子のオン、オフのタイミングを示す図である。FIG. 18 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the sixth embodiment of the present invention. 図１９は、本発明の第７実施形態に係るスイッチング装置における各半導体素子のオン、オフのタイミングを示す図である。FIG. 19 is a diagram showing the on / off timing of each semiconductor element in the switching device according to the seventh embodiment of the present invention.
　以下、本発明の実施形態を図面に基づいて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
［第１実施形態の説明］
　図１、図２は、本発明の第１実施形態に係るスイッチング装置を示す説明図、及びタイミングチャートである。 [Description of First Embodiment]
1 and 2 are an explanatory diagram and a timing chart showing the switching device according to the first embodiment of the present invention.
　図１に示すように、第１実施形態に係るスイッチング装置は、２つの半導体素子、即ち、第１半導体素子Ｑ１、及び第２半導体素子Ｑ２が２つの電極ａ１，ａ２に対して互いに並列接続されている。並列接続された半導体素子Ｑ１，Ｑ２は、例えば負荷回路（図示省略）に接続されて該負荷回路のオン（導通）、オフ（非導通）を切り替える。例えば、図１に示す電極ａ１が直流電源に接続され、電極ａ２が負荷に接続され、各半導体素子Ｑ１，Ｑ２を連動させてオン、オフ制御することにより、負荷への電流の供給、停止（即ち、負荷の駆動、停止）を制御することができる。第１半導体素子Ｑ１、及び第２半導体素子Ｑ２は、例えばＦＥＴ（電界効果トランジスタ）やＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）である。 As shown in FIG. 1, in the switching device according to the first embodiment, two semiconductor elements, that is, a first semiconductor element Q1 and a second semiconductor element Q2 are connected in parallel to two electrodes a1 and a2. ing. The semiconductor elements Q1 and Q2 connected in parallel are connected to, for example, a load circuit (not shown) to switch the load circuit on (conductive) and off (non-conductive). For example, the electrode a1 shown in FIG. 1 is connected to a DC power source, the electrode a2 is connected to a load, and the semiconductor elements Q1 and Q2 are controlled to be turned on and off in conjunction with each other, thereby supplying and stopping current to the load ( That is, the driving and stopping of the load can be controlled. The first semiconductor element Q1 and the second semiconductor element Q2 are, for example, FETs (field effect transistors) or IGBTs (insulated gate bipolar transistors).
　また、各半導体素子Ｑ１，Ｑ２の近傍には、各半導体素子Ｑ１，Ｑ２を冷却するための冷却装置５１（冷却部）が設けられている。なお、各半導体素子Ｑ１，Ｑ２は、同一の形状、同一の電気特性のものを用いても良いし、異なるものであっても良い。 Further, a cooling device 51 (cooling unit) for cooling the semiconductor elements Q1 and Q2 is provided in the vicinity of the semiconductor elements Q1 and Q2. The semiconductor elements Q1 and Q2 may have the same shape and the same electrical characteristics, or may be different.
　そして、第１実施形態では、各半導体素子Ｑ１，Ｑ２の制御端子（ＦＥＴの場合にはゲート端子）に供給する制御信号を変更することにより、各半導体素子Ｑ１，Ｑ２をオンとする時刻（オンタイミング）を調整して、各半導体素子Ｑ１，Ｑ２の発熱量を制御する。即ち、オンとする時刻を変更することにより、各半導体素子Ｑ１，Ｑ２のスイッチング損失が変化するので、このスイッチング損失に起因して生じる発熱量を制御することができる。 In the first embodiment, by changing the control signal supplied to the control terminals (gate terminals in the case of FETs) of the semiconductor elements Q1 and Q2, the time when the semiconductor elements Q1 and Q2 are turned on (on (Timing) is adjusted to control the heat generation amount of each of the semiconductor elements Q1 and Q2. That is, the switching loss of each of the semiconductor elements Q1 and Q2 changes by changing the time to turn on, so that the amount of heat generated due to this switching loss can be controlled.
　具体的には、図２（ａ）、（ｂ）に示すように、第２半導体素子Ｑ２のオン時刻に対して第１半導体素子Ｑ１のオン時刻を遅くする。これにより、各半導体素子Ｑ１，Ｑ２のスイッチング損失を調整し、ひいては各半導体素子Ｑ１，Ｑ２の発熱量を調整する。即ち、第１半導体素子Ｑ１のオン時刻を時刻Ｔ２とし、第２半導体素子Ｑ２のオン時刻を時刻Ｔ２よりも早い時刻Ｔ１とすることにより、第２半導体素子Ｑ２の発熱量を第１半導体素子Ｑ１の発熱量よりも相対的に高くすることができる。なお、各半導体素子Ｑ１，Ｑ２の制御端子に供給する制御信号は電気信号に限定されず、光、電界、磁界、圧力、音波等の各信号とすることも可能である。 Specifically, as shown in FIGS. 2A and 2B, the on-time of the first semiconductor element Q1 is delayed with respect to the on-time of the second semiconductor element Q2. As a result, the switching loss of each of the semiconductor elements Q1, Q2 is adjusted, and consequently, the amount of heat generated by each of the semiconductor elements Q1, Q2 is adjusted. That is, by setting the ON time of the first semiconductor element Q1 to time T2 and the ON time of the second semiconductor element Q2 to time T1 earlier than the time T2, the amount of heat generated by the second semiconductor element Q2 is set to the first semiconductor element Q1. It can be made relatively higher than the calorific value. The control signals supplied to the control terminals of the semiconductor elements Q1 and Q2 are not limited to electrical signals, and can be signals such as light, electric field, magnetic field, pressure, and sound wave.
　こうして、図２に示したオン時刻Ｔ１，Ｔ２を個別に設定することにより、各半導体素子Ｑ１，Ｑ２の発熱量を調整することができる。従って、半導体素子Ｑ１，Ｑ２の形状や電気特性の違いにより、各半導体素子Ｑ１，Ｑ２のオン抵抗が異なり、オン時の発熱量である定常損失が異なる場合であっても、各半導体素子Ｑ１，Ｑ２の温度のバランスを調整することが可能である。 Thus, the heat generation amount of each of the semiconductor elements Q1 and Q2 can be adjusted by individually setting the on times T1 and T2 shown in FIG. Accordingly, even when the on-resistances of the semiconductor elements Q1 and Q2 are different due to differences in the shape and electrical characteristics of the semiconductor elements Q1 and Q2, and the steady loss that is the amount of heat generated at the time of on is different, the semiconductor elements Q1 and Q2 are different. It is possible to adjust the temperature balance of Q2.
　また、例えば、図１に示す第２半導体素子Ｑ２が冷却装置５１による冷却効果の高い位置に配置され、第１半導体素子Ｑ１が相対的に冷却効果の低い位置に配置されている場合には、第１半導体素子Ｑ１のオン時刻に対して、第２半導体素子Ｑ２をオンとする時刻を相対的に早める（図２のＴ１）。これにより、第１半導体素子Ｑ１の発熱量を相対的に低減することができ、結果として、各半導体素子Ｑ１，Ｑ２の温度をほぼ一定に保持することが可能となる。 Further, for example, when the second semiconductor element Q2 shown in FIG. 1 is arranged at a position where the cooling effect by the cooling device 51 is high, and the first semiconductor element Q1 is arranged at a position where the cooling effect is relatively low, The time at which the second semiconductor element Q2 is turned on is relatively earlier than the time at which the first semiconductor element Q1 is turned on (T1 in FIG. 2). As a result, the amount of heat generated by the first semiconductor element Q1 can be relatively reduced, and as a result, the temperatures of the semiconductor elements Q1 and Q2 can be kept substantially constant.
　スイッチング損失量は、２つのオン時刻Ｔ１とＴ２との時間差により調整することができる。つまり、この時間差が大きいほど、スイッチング損失が大きくなるので、発熱量の差分を大きくすることができる。また、第１半導体素子Ｑ１のオン時刻Ｔ２は、第２半導体素子Ｑ２のオン時刻Ｔ１からオフ時刻Ｔ３（Ｔ４）までの期間内であり、且つ、時刻Ｔ１に近いことが望ましい。なお、第１実施形態に係るスイッチング装置の具体的な制御方法については、後述の第１～第４の制御方法にて説明する。 The switching loss amount can be adjusted by the time difference between the two ON times T1 and T2. That is, the larger the time difference is, the larger the switching loss is, so that the difference in heat generation amount can be increased. Further, it is desirable that the ON time T2 of the first semiconductor element Q1 is within the period from the ON time T1 to the OFF time T3 (T4) of the second semiconductor element Q2 and close to the time T1. Note that specific control methods for the switching device according to the first embodiment will be described in first to fourth control methods described later.
　このように、本実施形態に係るスイッチング装置では、半導体素子のオンタイミングを調整することにより、各半導体素子の形状や電気特性に違いが生じている場合であっても、各半導体素子の温度が均一となるように制御することが可能となる。 As described above, in the switching device according to the present embodiment, by adjusting the on-timing of the semiconductor element, the temperature of each semiconductor element can be adjusted even when there is a difference in the shape and electrical characteristics of each semiconductor element. It can be controlled to be uniform.
　すなわち、第１実施形態に係るスイッチング装置では、少なくとも１つの半導体素子（例えば、Ｑ１）について、オフ（非導通）からオン（導通）へ切り替えるオン時刻（オンタイミング）を、他の半導体素子（例えば、Ｑ２）と異なるように設定するので、各半導体素子の温度をほぼ均一に保持することが可能となる。従って、各半導体素子毎の温度のばらつきを抑制でき、特定の半導体のみに多くの負荷がかかる等の問題を回避することができる。また、冷却装置５１による冷却効果に応じて、各半導体素子のオン時刻を変更するので、温度のばらつきを抑制できる。特に、冷却装置５１による冷却効果の低い位置に配置された半導体素子（例えば、Ｑ１）について、オン時刻を遅らせるので、冷却効果にばらつきが生じている場合でも、各半導体素子の温度を均一に保持することができる。 In other words, in the switching device according to the first embodiment, an on time (on timing) for switching from off (non-conduction) to on (conduction) for at least one semiconductor element (for example, Q1) is set to another semiconductor element (for example, Q1). , Q2), the temperature of each semiconductor element can be kept substantially uniform. Therefore, it is possible to suppress temperature variations among the respective semiconductor elements, and to avoid problems such as a large load applied only to a specific semiconductor. Moreover, since the ON time of each semiconductor element is changed according to the cooling effect by the cooling device 51, the temperature variation can be suppressed. In particular, since the on-time is delayed for the semiconductor element (for example, Q1) arranged at a position where the cooling effect by the cooling device 51 is low, even if the cooling effect varies, the temperature of each semiconductor element is kept uniform. can do.
［第２実施形態の説明］
　次に、本発明の第２実施形態について説明する。図３は、第２実施形態に係るスイッチング装置のタイミングチャートである。また、第２実施形態に係るスイッチング装置の構成は、図１と同一である。 [Description of Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 3 is a timing chart of the switching device according to the second embodiment. The configuration of the switching device according to the second embodiment is the same as that in FIG.
　第２実施形態では、各半導体素子Ｑ１，Ｑ２の制御端子に供給する制御信号を変更することにより、各半導体素子Ｑ１，Ｑ２をオフとする時刻を調整して、各半導体素子Ｑ１，Ｑ２の発熱量を制御する。即ち、オフ時刻を変更することにより、各半導体素子Ｑ１，Ｑ２のスイッチング損失が変化するので、このスイッチング損失に起因して生じる発熱量を制御することができる。 In the second embodiment, by changing the control signal supplied to the control terminals of the semiconductor elements Q1 and Q2, the time at which the semiconductor elements Q1 and Q2 are turned off is adjusted, and the heat generation of the semiconductor elements Q1 and Q2 is performed. Control the amount. That is, by changing the off time, the switching loss of each of the semiconductor elements Q1, Q2 changes, so that the amount of heat generated due to this switching loss can be controlled.
　具体的には、図３（ａ）、（ｂ）に示すように、第１半導体素子Ｑ１のオフ時刻に対して第２半導体素子Ｑ２のオフ時刻を遅らせる。これにより、各半導体素子Ｑ１，Ｑ２のスイッチング損失を調整し、ひいては各半導体素子Ｑ１，Ｑ２の発熱量を調整する。即ち、第２半導体素子Ｑ２のオフ時刻Ｔ３を、第１半導体素子Ｑ１のオフ時刻Ｔ４よりも遅らせることにより、第２半導体素子Ｑ２の発熱量を第１半導体素子Ｑ１の発熱量よりも相対的に高くすることができる。なお、各半導体素子Ｑ１，Ｑ２に供給する制御信号は電気信号に限定されず、光、電界、磁界、圧力、音波等の各信号とすることも可能である。 Specifically, as shown in FIGS. 3A and 3B, the off time of the second semiconductor element Q2 is delayed with respect to the off time of the first semiconductor element Q1. As a result, the switching loss of each of the semiconductor elements Q1, Q2 is adjusted, and consequently, the amount of heat generated by each of the semiconductor elements Q1, Q2 is adjusted. That is, by delaying the off time T3 of the second semiconductor element Q2 from the off time T4 of the first semiconductor element Q1, the amount of heat generated by the second semiconductor element Q2 is made relatively larger than the amount of heat generated by the first semiconductor element Q1. Can be high. The control signals supplied to the semiconductor elements Q1 and Q2 are not limited to electrical signals, and may be signals such as light, electric field, magnetic field, pressure, and sound wave.
　こうして、図３に示したオフ時刻Ｔ３，Ｔ４を個別に設定することにより、各半導体素子Ｑ１，Ｑ２の発熱量を調整することができる。従って、各半導体素子Ｑ１，Ｑ２の形状や電気特性の違いにより、各半導体素子Ｑ１，Ｑ２のオン抵抗が異なり、オン時の発熱量である定常損失が異なる場合であっても、各半導体素子Ｑ１，Ｑ２の温度のバランスを調整することが可能である。 Thus, the heat generation amount of each semiconductor element Q1, Q2 can be adjusted by individually setting the off times T3, T4 shown in FIG. Accordingly, even when the on-resistances of the semiconductor elements Q1 and Q2 are different due to differences in the shape and electrical characteristics of the semiconductor elements Q1 and Q2, and the steady loss that is the amount of heat generated at the time of on is different, the semiconductor elements Q1 , Q2 temperature balance can be adjusted.
　また、例えば、図１に示す第２半導体素子Ｑ２が冷却装置５１による冷却効果の高い位置に配置され、第１半導体素子Ｑ１が相対的に冷却効果の低い位置に配置されている場合には、第１半導体素子Ｑ１のオフ時刻に対して、第２半導体素子Ｑ２をオフとする時刻を相対的に遅くする（図３のＴ３）。これにより、第１半導体素子Ｑ１の発熱量を相対的に低減することができ、結果として、各半導体素子Ｑ１，Ｑ２の温度をほぼ一定に保持することが可能となる。 Further, for example, when the second semiconductor element Q2 shown in FIG. 1 is arranged at a position where the cooling effect by the cooling device 51 is high, and the first semiconductor element Q1 is arranged at a position where the cooling effect is relatively low, The time at which the second semiconductor element Q2 is turned off is relatively delayed with respect to the time at which the first semiconductor element Q1 is turned off (T3 in FIG. 3). As a result, the amount of heat generated by the first semiconductor element Q1 can be relatively reduced, and as a result, the temperatures of the semiconductor elements Q1 and Q2 can be kept substantially constant.
　スイッチング損失量は、２つのオフ時刻Ｔ３とＴ４との時間差により調整することができる。つまり、この時間差が大きいほど、スイッチング損失が大きくなるので、発熱量の差分を大きくすることができる。また、時刻Ｔ４は、時刻Ｔ１（Ｔ２）から時刻Ｔ３までの期間内であり、且つ、Ｔ３に近いことが望ましい。なお、第２実施形態に係るスイッチング装置の具体的な制御方法については、後述の第１～第４の制御方法にて説明する。 The switching loss amount can be adjusted by the time difference between the two off times T3 and T4. That is, the larger the time difference is, the larger the switching loss is, so that the difference in heat generation amount can be increased. Further, it is desirable that the time T4 is within the period from the time T1 (T2) to the time T3 and is close to T3. A specific control method for the switching device according to the second embodiment will be described in first to fourth control methods described later.
　このように、本実施形態に係るスイッチング装置では、半導体素子のオフタイミングを調整することにより、各半導体素子の形状や電気特性に違いが生じている場合であっても、各半導体素子の温度が均一となるように制御することが可能となる。 As described above, in the switching device according to the present embodiment, by adjusting the off-timing of the semiconductor element, even if there is a difference in the shape and electrical characteristics of each semiconductor element, the temperature of each semiconductor element is It can be controlled to be uniform.
　すなわち、第２実施形態に係るスイッチング装置では、少なくとも１つの半導体素子（例えば、Ｑ１）について、オン（導通）からオフ（非導通）へ切り替えるオフ時刻（オフタイミング）を、他の半導体素子（例えば、Ｑ２）と異なるように設定するので、各半導体素子の温度をほぼ均一に保持することが可能となる。従って、各半導体素子毎の温度のばらつきを抑制でき、特定の半導体のみに多くの負荷がかかる等の問題を回避することができる。また、冷却装置５１による冷却効果に応じて、各半導体素子のオフ時刻を変更するので、温度のばらつきを抑制できる。特に、冷却装置５１による冷却効果の低い位置に配置された半導体素子（例えば、Ｑ１）について、オフ時刻を早めるので、冷却効果にばらつきが生じている場合でも、各半導体素子の温度を均一に保持することができる。 That is, in the switching device according to the second embodiment, for at least one semiconductor element (for example, Q1), an off time (off timing) for switching from on (conducting) to off (non-conducting) is set to another semiconductor element (for example, , Q2), the temperature of each semiconductor element can be kept substantially uniform. Therefore, it is possible to suppress temperature variations among the respective semiconductor elements, and to avoid problems such as a large load applied only to a specific semiconductor. Moreover, since the off time of each semiconductor element is changed according to the cooling effect by the cooling device 51, the temperature variation can be suppressed. In particular, since the off time is advanced for the semiconductor element (for example, Q1) arranged at a position where the cooling effect by the cooling device 51 is low, even if the cooling effect varies, the temperature of each semiconductor element is kept uniform. can do.
［第３実施形態の説明］
　次に、本発明の第３実施形態について説明する。図４は、第３実施形態に係るスイッチング装置のタイミングチャートである。また、第３実施形態に係るスイッチング装置の構成は、図１と同一である。 [Description of Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 4 is a timing chart of the switching device according to the third embodiment. The configuration of the switching device according to the third embodiment is the same as that in FIG.
　第３実施形態では、各半導体素子Ｑ１，Ｑ２の制御端子に供給する制御信号を変更することにより、各半導体素子Ｑ１，Ｑ２をオンとする時刻、及びオフとする時刻を調整して、各半導体素子Ｑ１，Ｑ２の発熱量を制御する。即ち、オン時刻及びオフ時刻の双方を変更することにより、各半導体素子Ｑ１，Ｑ２のスイッチング損失が変化するので、このスイッチング損失に起因する発熱量を制御することができる。 In the third embodiment, by changing the control signal supplied to the control terminals of the semiconductor elements Q1 and Q2, the time when the semiconductor elements Q1 and Q2 are turned on and the time when the semiconductor elements Q1 and Q2 are turned off are adjusted. The amount of heat generated by the elements Q1 and Q2 is controlled. That is, by changing both the on time and the off time, the switching loss of each of the semiconductor elements Q1 and Q2 changes, so that the amount of heat generated due to this switching loss can be controlled.
　具体的には、図４（ａ）、（ｂ）に示すように、第１半導体素子Ｑ１のオン時刻及びオフ時刻に対して第２半導体素子Ｑ２のオン時刻を早め、更に、オフ時刻を遅らせる。これにより、各半導体素子Ｑ１，Ｑ２のスイッチング損失を調整し、ひいては各半導体素子Ｑ１，Ｑ２の発熱量を調整する。即ち、第２半導体素子Ｑ２のオン時刻Ｔ１を、第１半導体素子Ｑ１のオン時刻Ｔ２よりも早め、且つ、第２半導体素子Ｑ２のオフ時刻Ｔ３を、第１半導体素子Ｑ１のオフ時刻Ｔ４よりも遅らせる。これにより、第２半導体素子Ｑ２の発熱量を第１半導体素子Ｑ１の発熱量よりも相対的に高くすることができる。なお、各半導体素子Ｑ１，Ｑ２に供給する制御信号は電気信号に限定されず、光、電界、磁界、圧力、音波等の各信号とすることも可能である。 Specifically, as shown in FIGS. 4A and 4B, the ON time of the second semiconductor element Q2 is advanced with respect to the ON time and OFF time of the first semiconductor element Q1, and the OFF time is further delayed. . As a result, the switching loss of each of the semiconductor elements Q1, Q2 is adjusted, and consequently, the amount of heat generated by each of the semiconductor elements Q1, Q2 is adjusted. That is, the ON time T1 of the second semiconductor element Q2 is set earlier than the ON time T2 of the first semiconductor element Q1, and the OFF time T3 of the second semiconductor element Q2 is set to be higher than the OFF time T4 of the first semiconductor element Q1. Delay. Thereby, the heat generation amount of the second semiconductor element Q2 can be made relatively higher than the heat generation amount of the first semiconductor element Q1. The control signals supplied to the semiconductor elements Q1 and Q2 are not limited to electrical signals, and may be signals such as light, electric field, magnetic field, pressure, and sound wave.
　こうして、図４に示したオン時刻Ｔ１，Ｔ２、及びオフ時刻Ｔ３，Ｔ４を個別に設定することにより、各半導体素子Ｑ１，Ｑ２の発熱量を調整することができる。従って、各半導体素子Ｑ１，Ｑ２の形状や電気特性の違いにより、各半導体素子Ｑ１，Ｑ２のオン抵抗が異なり、オン時の発熱量である定常損失が異なる場合であっても、各半導体素子Ｑ１，Ｑ２の温度のバランスを調整することが可能である。 Thus, the heat generation amounts of the semiconductor elements Q1 and Q2 can be adjusted by individually setting the on times T1 and T2 and the off times T3 and T4 shown in FIG. Accordingly, even when the on-resistances of the semiconductor elements Q1 and Q2 are different due to differences in the shape and electrical characteristics of the semiconductor elements Q1 and Q2, and the steady loss that is the amount of heat generated at the time of on is different, the semiconductor elements Q1 , Q2 temperature balance can be adjusted.
　また、例えば、図１に示す第２半導体素子Ｑ２が冷却装置５１による冷却効果の高い位置に配置され、第１半導体素子Ｑ１が相対的に冷却効果の低い位置に配置されている場合には、第１半導体素子Ｑ１のオン時刻に対して、第２半導体素子Ｑ２のオン時刻を相対的に早め（図４のＴ１）、且つ、第１半導体素子Ｑ１のオフ時刻に対して、第２半導体素子Ｑ２のオフ時刻を相対的に遅くする（図４のＴ３）。これにより、第１半導体素子Ｑ１の発熱量を相対的に低減することができ、結果として、各半導体素子Ｑ１，Ｑ２の温度をほぼ一定に保持することが可能となる。 Further, for example, when the second semiconductor element Q2 shown in FIG. 1 is arranged at a position where the cooling effect by the cooling device 51 is high, and the first semiconductor element Q1 is arranged at a position where the cooling effect is relatively low, The on time of the second semiconductor element Q2 is relatively earlier than the on time of the first semiconductor element Q1 (T1 in FIG. 4), and the second semiconductor element is compared with the off time of the first semiconductor element Q1. The off time of Q2 is relatively delayed (T3 in FIG. 4). As a result, the amount of heat generated by the first semiconductor element Q1 can be relatively reduced, and as a result, the temperatures of the semiconductor elements Q1 and Q2 can be kept substantially constant.
　スイッチング損失量は、２つのオン時刻Ｔ１とＴ２の時間差、及び２つのオフ時刻Ｔ３とＴ４との時間差により調整することができる。つまり、この時間差が大きいほど、スイッチング損失が大きくなるので、発熱量の差分を大きくすることができる。また、時刻Ｔ２は、時刻Ｔ１からオフ時刻Ｔ４までの期間内であり、時刻Ｔ１に近いことが望ましい。更に、時刻Ｔ４は、時刻Ｔ２から時刻Ｔ３までの期間内であり、且つ、Ｔ３に近いことが望ましい。なお、第３実施形態に係るスイッチング装置の具体的な制御方法については、後述の第１～第４の制御方法にて説明する。 The switching loss amount can be adjusted by the time difference between the two on times T1 and T2 and the time difference between the two off times T3 and T4. That is, the larger the time difference is, the larger the switching loss is, so that the difference in heat generation amount can be increased. Further, the time T2 is within a period from the time T1 to the off time T4, and is preferably close to the time T1. Furthermore, it is desirable that the time T4 is within the period from the time T2 to the time T3 and is close to T3. A specific control method for the switching device according to the third embodiment will be described in first to fourth control methods described later.
 
　このように、本実施形態に係るスイッチング装置では、半導体素子のオフタイミング、オンタイミングを調整することにより、各半導体素子の形状や電気特性に違いが生じている場合であっても、各半導体素子の温度が均一となるように制御することが可能となる。
As described above, in the switching device according to the present embodiment, even when there is a difference in the shape and electrical characteristics of each semiconductor element by adjusting the off timing and the on timing of the semiconductor element, It is possible to control so that the temperature is uniform.
　すなわち、第３実施形態に係るスイッチング装置では、少なくとも１つの半導体素子（例えば、Ｑ１）について、オフ（非導通）からオン（導通）へ切り替えるオン時刻（オンタイミング）、及び、オン（導通）からオフ（非導通）へ切り替えるオフ時刻（オフタイミング）を、他の半導体素子（例えば、Ｑ２）と異なるように設定するので、各半導体素子の温度をほぼ均一に保持することが可能となる。従って、各半導体素子毎の温度のばらつきを抑制でき、特定の半導体のみに多くの負荷がかかる等の問題を回避することができる。 That is, in the switching device according to the third embodiment, at least one semiconductor element (for example, Q1) is switched from off (non-conduction) to on (conduction) on time (on timing) and from on (conduction). Since the off time (off timing) for switching to off (non-conduction) is set to be different from that of other semiconductor elements (for example, Q2), the temperature of each semiconductor element can be maintained substantially uniformly. Therefore, it is possible to suppress temperature variations among the respective semiconductor elements, and to avoid problems such as a large load applied only to a specific semiconductor.
　また、冷却装置５１による冷却効果に応じて、各半導体素子のオン時刻及びオフ時刻を変更するので、温度のばらつきを抑制できる。特に、冷却装置５１による冷却効果の低い位置に配置された半導体素子（例えば、Ｑ１）について、オン時刻を遅らせ、且つ、オフ時刻を早めるので、冷却効果にばらつきが生じている場合でも、各半導体素子の温度を均一に保持することができる。 Further, since the on time and the off time of each semiconductor element are changed according to the cooling effect by the cooling device 51, the temperature variation can be suppressed. In particular, for the semiconductor element (for example, Q1) arranged at a position where the cooling effect by the cooling device 51 is low, the on time is delayed and the off time is advanced, so even if the cooling effect varies, each semiconductor device The temperature of the element can be kept uniform.
［第４実施形態の説明］
　次に、本発明の第４実施形態について説明する。図５、図６は、第４実施形態に係るスイッチング装置を示す説明図、及びタイミングチャートである。 [Description of Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. 5 and 6 are an explanatory diagram and a timing chart showing the switching device according to the fourth embodiment.
　図５に示すように、第４実施形態に係るスイッチング装置は、前述した第１実施形態と同様に、第１半導体素子Ｑ１、及び第２半導体素子Ｑ２が２つの電極ａ１，ａ２に対して互いに並列接続されている。並列接続された半導体素子Ｑ１，Ｑ２は、例えば負荷回路（図示省略）に接続されて該負荷回路のオン（導通）、オフ（非導通）を制御する。なお、各半導体素子Ｑ１，Ｑ２は、同一の形状、同一の電気特性のものを用いても良いし、異なるものであっても良い。 As shown in FIG. 5, in the switching device according to the fourth embodiment, the first semiconductor element Q1 and the second semiconductor element Q2 are connected to the two electrodes a1 and a2 in the same manner as in the first embodiment described above. Connected in parallel. The semiconductor elements Q1 and Q2 connected in parallel are connected to, for example, a load circuit (not shown) to control on (conduction) and off (non-conduction) of the load circuit. The semiconductor elements Q1 and Q2 may have the same shape and the same electrical characteristics, or may be different.
　また、第１半導体素子Ｑ１の抜熱経路の熱抵抗θ１（放熱し難さ）は、第２半導体素子Ｑ２の抜熱経路の熱抵抗θ２よりも、相対的に大きくなっている。即ち、θ１＞θ２である。 Further, the heat resistance θ1 (difficult to dissipate heat) of the heat removal path of the first semiconductor element Q1 is relatively larger than the heat resistance θ2 of the heat removal path of the second semiconductor element Q2. That is, θ1> θ2.
　そして、第４実施形態では、各半導体素子Ｑ１，Ｑ２の制御端子に供給する制御信号を変更することにより、各半導体素子Ｑ１，Ｑ２のオン時刻、及びオフ時刻を調整して、各半導体素子Ｑ１，Ｑ２の発熱量を制御する。即ち、オン時刻及びオフ時刻を変更することにより、各半導体素子Ｑ１，Ｑ２のスイッチング損失が変化するので、このスイッチング損失に起因して発生する発熱量を制御することができる。 In the fourth embodiment, by changing the control signal supplied to the control terminal of each semiconductor element Q1, Q2, the on time and the off time of each semiconductor element Q1, Q2 are adjusted, and each semiconductor element Q1. , Q2 is controlled. That is, by changing the on time and the off time, the switching loss of each of the semiconductor elements Q1, Q2 changes, so that the amount of heat generated due to this switching loss can be controlled.
　具体的には、図６（ａ）、（ｂ）に示すように、第１半導体素子Ｑ１のオン時刻及びオフ時刻に対して第２半導体素子Ｑ２のオン時刻を早め、更に、オフ時刻を遅らせる。これにより、各半導体素子Ｑ１，Ｑ２のスイッチング損失を調整し、ひいては各半導体素子Ｑ１，Ｑ２の発熱量を調整する。 Specifically, as shown in FIGS. 6A and 6B, the ON time of the second semiconductor element Q2 is advanced with respect to the ON time and OFF time of the first semiconductor element Q1, and the OFF time is further delayed. . As a result, the switching loss of each of the semiconductor elements Q1, Q2 is adjusted, and consequently, the amount of heat generated by each of the semiconductor elements Q1, Q2 is adjusted.
　即ち、抜熱経路の熱抵抗が小さい（熱抵抗θ２）第２半導体素子Ｑ２については、オン時刻Ｔ１を早め、抜熱経路の熱抵抗が相対的に大きい（熱抵抗θ１）第１半導体素子Ｑ１については、オン時刻Ｔ２を相対的に遅らせる。更に、第２半導体素子Ｑ２については、オフ時刻Ｔ３を遅らせ、第１半導体素子Ｑ１については、オフ時刻Ｔ４を相対的に早める。これにより、第２半導体素子Ｑ２の発熱量を第１半導体素子Ｑ１の発熱量よりも相対的に高めることが可能となる。なお、各半導体素子Ｑ１，Ｑ２に供給する制御信号は電気信号に限定されず、光、電界、磁界、圧力、音波等の各信号とすることも可能である。 That is, for the second semiconductor element Q2 having a small heat resistance in the heat removal path (thermal resistance θ2), the on-time T1 is advanced, and the heat resistance in the heat removal path is relatively large (thermal resistance θ1). For, the ON time T2 is relatively delayed. Further, the off time T3 is delayed for the second semiconductor element Q2, and the off time T4 is relatively advanced for the first semiconductor element Q1. As a result, the heat generation amount of the second semiconductor element Q2 can be made relatively higher than the heat generation amount of the first semiconductor element Q1. The control signals supplied to the semiconductor elements Q1 and Q2 are not limited to electrical signals, and may be signals such as light, electric field, magnetic field, pressure, and sound wave.
　こうして、図６に示した時刻Ｔ１，Ｔ２、及び時刻Ｔ３，Ｔ４を個別に設定することにより、第１半導体素子Ｑ１の発熱量を第２半導体素子Ｑ２の発熱量に対して相対的に低くすることが可能となる。このため、抜熱抵抗が大きく放熱し難い第１半導体素子Ｑ１の発熱量を低減できるので、各半導体素子Ｑ１，Ｑ２の温度をほぼ一定に保持することが可能となる。 Thus, by setting the times T1 and T2 and the times T3 and T4 shown in FIG. 6 individually, the heat generation amount of the first semiconductor element Q1 is made relatively lower than the heat generation amount of the second semiconductor element Q2. It becomes possible. For this reason, the amount of heat generated by the first semiconductor element Q1, which has a large heat extraction resistance and is difficult to dissipate heat, can be reduced, so that the temperature of each of the semiconductor elements Q1, Q2 can be kept substantially constant.
　スイッチング損失量は、２つのオン時刻Ｔ１とＴ２の時間差、及び２つのオフ時刻Ｔ３とＴ４との時間差により調整することができる。つまり、この時間差が大きいほど、スイッチング損失が大きくなるので、発熱量の差分を大きくすることができる。また、時刻Ｔ２は、時刻Ｔ１から時刻Ｔ４までの期間内であり、時刻Ｔ１に近いことが望ましい。更に、時刻Ｔ４は、時刻Ｔ２から時刻Ｔ３までの期間内であり、且つ、Ｔ３に近いことが望ましい。なお、第４実施形態に係るスイッチング装置の具体的な制御方法については、後述の第１～第４の制御方法にて説明する。 The switching loss amount can be adjusted by the time difference between the two on times T1 and T2 and the time difference between the two off times T3 and T4. That is, the larger the time difference is, the larger the switching loss is, so that the difference in heat generation amount can be increased. Further, the time T2 is within a period from the time T1 to the time T4, and is preferably close to the time T1. Furthermore, it is desirable that the time T4 is within the period from the time T2 to the time T3 and is close to T3. A specific control method for the switching device according to the fourth embodiment will be described in first to fourth control methods described later.
　このように、第４実施形態に係るスイッチング装置では、各半導体素子のうち、抜熱抵抗の高い位置に設置された半導体素子（例えば、Ｑ１）を、相対的に抜熱抵抗の低い位置に設置された半導体素子（例えば、Ｑ２）に対し、オンタイミングが遅くなるように設定し、更に、オフタイミングが早くなるように設定するので、各半導体素子の温度をほぼ均一に保持することが可能となる。従って、各半導体素子毎の温度のばらつきを抑制でき、特定の半導体のみに多くの負荷がかかる等の問題を回避することができる。 Thus, in the switching device according to the fourth embodiment, among the semiconductor elements, the semiconductor element (for example, Q1) installed at a position with a high heat removal resistance is installed at a position with a relatively low heat extraction resistance. Since the on-timing is set to be delayed and the off-timing is set to be earlier with respect to the semiconductor element (for example, Q2), the temperature of each semiconductor element can be kept substantially uniform. Become. Therefore, it is possible to suppress temperature variations among the respective semiconductor elements, and to avoid problems such as a large load applied only to a specific semiconductor.
［第５実施形態の説明］
　次に、本発明の第５実施形態について説明する。図７、図８は、第５実施形態に係るスイッチング装置を示す説明図、及びタイミングチャートである。 [Description of Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. 7 and 8 are an explanatory diagram and a timing chart showing the switching device according to the fifth embodiment.
　図７に示すように、第５実施形態に係るスイッチング装置は、前述した第１実施形態と同様に、第１半導体素子Ｑ１、及び第２半導体素子Ｑ２が、２つの電極ａ１，ａ２に対して互いに並列接続されている。並列接続された半導体素子Ｑ１，Ｑ２は、例えば負荷回路（図示省略）に接続されて該負荷回路のオン（導通）、オフ（非導通）を制御する。なお、各半導体素子Ｑ１，Ｑ２は、同一の形状、同一の電気特性のものを用いても良いし、異なるものであっても良い。 As shown in FIG. 7, in the switching device according to the fifth embodiment, the first semiconductor element Q1 and the second semiconductor element Q2 are connected to the two electrodes a1 and a2 as in the first embodiment described above. They are connected in parallel to each other. The semiconductor elements Q1 and Q2 connected in parallel are connected to, for example, a load circuit (not shown) to control on (conduction) and off (non-conduction) of the load circuit. The semiconductor elements Q1 and Q2 may have the same shape and the same electrical characteristics, or may be different.
　また、第１半導体素子Ｑ１の周囲温度（ｔ１）は、第２半導体素子Ｑ２の周囲温度（ｔ２）よりも、相対的に高くなっている。或いは、同一電流を流したときにおいて、第１半導体素子Ｑ１の発熱温度は、第２半導体素子Ｑ２の発熱温度よりも、相対的に高くなる特性を有している。 Further, the ambient temperature (t1) of the first semiconductor element Q1 is relatively higher than the ambient temperature (t2) of the second semiconductor element Q2. Alternatively, when the same current flows, the heat generation temperature of the first semiconductor element Q1 has a characteristic that it is relatively higher than the heat generation temperature of the second semiconductor element Q2.
　そして、第５実施形態では、各半導体素子Ｑ１，Ｑ２の制御端子に供給する制御信号を変更することにより、各半導体素子Ｑ１，Ｑ２のオン時刻、及びオフ時刻を調整して、各半導体素子Ｑ１，Ｑ２の発熱量を制御する。即ち、オン時刻及びオフ時刻を変更することにより、各半導体素子Ｑ１，Ｑ２のスイッチング損失が変化するので、このスイッチング損失に起因して発生する発熱量を制御することができる。 In the fifth embodiment, by changing the control signal supplied to the control terminal of each semiconductor element Q1, Q2, the on time and the off time of each semiconductor element Q1, Q2 are adjusted, and each semiconductor element Q1. , Q2 is controlled. That is, by changing the on time and the off time, the switching loss of each of the semiconductor elements Q1, Q2 changes, so that the amount of heat generated due to this switching loss can be controlled.
　具体的には、図８（ａ）、（ｂ）に示すように、第１半導体素子Ｑ１のオン時刻及びオフ時刻に対して第２半導体素子Ｑ２のオン時刻を早め、更に、オフ時刻を遅らせる。これにより、各半導体素子Ｑ１，Ｑ２のスイッチング損失を調整し、ひいては各半導体素子Ｑ１，Ｑ２の発熱量を調整する。 Specifically, as shown in FIGS. 8A and 8B, the ON time of the second semiconductor element Q2 is advanced with respect to the ON time and OFF time of the first semiconductor element Q1, and the OFF time is further delayed. . As a result, the switching loss of each of the semiconductor elements Q1, Q2 is adjusted, and consequently, the amount of heat generated by each of the semiconductor elements Q1, Q2 is adjusted.
　即ち、第２半導体素子Ｑ２のオン時刻Ｔ１を、第１半導体素子Ｑ１のオン時刻Ｔ２よりも早め、且つ、第２半導体素子Ｑ２のオフ時刻Ｔ３を、第１半導体素子Ｑ１のオフ時刻Ｔ４よりも遅らせる。これにより、第２半導体素子Ｑ２の発熱量を第１半導体素子Ｑ１の発熱量よりも相対的に高くすることができる。なお、各半導体素子Ｑ１，Ｑ２に供給する制御信号は電気信号に限定されず、光、電界、磁界、圧力、音波等の各信号とすることも可能である。 That is, the ON time T1 of the second semiconductor element Q2 is set earlier than the ON time T2 of the first semiconductor element Q1, and the OFF time T3 of the second semiconductor element Q2 is set to be higher than the OFF time T4 of the first semiconductor element Q1. Delay. Thereby, the heat generation amount of the second semiconductor element Q2 can be made relatively higher than the heat generation amount of the first semiconductor element Q1. The control signals supplied to the semiconductor elements Q1 and Q2 are not limited to electrical signals, and may be signals such as light, electric field, magnetic field, pressure, and sound wave.
　こうして、図８に示した時刻Ｔ１，Ｔ２、及び時刻Ｔ３，Ｔ４を個別に設定することにより、第１半導体素子Ｑ１の発熱量を第２半導体素子Ｑ２の発熱量に対して相対的に低くすることが可能となる。このため、周囲温度の高い場所に配置された第１半導体素子Ｑ１の発熱量を低減できるので、各半導体素子Ｑ１，Ｑ２の温度をほぼ一定に保持することが可能となる。 Thus, by setting the times T1 and T2 and the times T3 and T4 shown in FIG. 8 individually, the heat generation amount of the first semiconductor element Q1 is made relatively lower than the heat generation amount of the second semiconductor element Q2. It becomes possible. For this reason, the amount of heat generated by the first semiconductor element Q1 disposed at a high ambient temperature can be reduced, so that the temperature of each of the semiconductor elements Q1 and Q2 can be kept substantially constant.
　スイッチング損失量は、２つのオン時刻Ｔ１とＴ２の時間差、及び２つのオフ時刻Ｔ３とＴ４との時間差により調整することができる。つまり、これらの時間差が大きいほど、スイッチング損失が大きくなるので、発熱量の差分を大きくすることができる。また、時刻Ｔ２は、時刻Ｔ１から時刻Ｔ４までの期間内であり、時刻Ｔ１に近いことが望ましい。更に、時刻Ｔ４は、時刻Ｔ２から時刻Ｔ３までの期間内であり、且つ、Ｔ３に近いことが望ましい。なお、第５実施形態に係るスイッチング装置の具体的な制御方法については、後述の第１～第４の制御方法にて説明する。 The switching loss amount can be adjusted by the time difference between the two on times T1 and T2 and the time difference between the two off times T3 and T4. That is, the larger the time difference is, the larger the switching loss is, so that the difference in the heat generation amount can be increased. Further, the time T2 is within a period from the time T1 to the time T4, and is preferably close to the time T1. Furthermore, it is desirable that the time T4 is within the period from the time T2 to the time T3 and is close to T3. Note that specific control methods for the switching device according to the fifth embodiment will be described in first to fourth control methods described later.
　このように、第５実施形態に係るスイッチング装置では、各半導体素子のうち、周囲温度の高い位置に設置された半導体素子（例えば、Ｑ１）を、相対的に周囲温度の低い位置に設置された半導体素子（例えば、Ｑ２）に対し、オンタイミングが遅くなるように設定し、更に、オフタイミングが早くなるように設定するので、各半導体素子の温度をほぼ均一に保持することが可能となる。従って、各半導体素子毎の温度のばらつきを抑制でき、特定の半導体のみに多くの負荷がかかる等の問題を回避することができる。 Thus, in the switching device according to the fifth embodiment, among the semiconductor elements, the semiconductor element (for example, Q1) installed at a position where the ambient temperature is high is installed at a position where the ambient temperature is relatively low. The semiconductor element (for example, Q2) is set so that the on-timing is delayed, and further, the off-timing is set so that the temperature of each semiconductor element can be kept substantially uniform. Therefore, it is possible to suppress temperature variations among the respective semiconductor elements, and to avoid problems such as a large load applied only to a specific semiconductor.
［第１の制御方法の説明］
　次に、前述した第１～第５実施形態に示したスイッチング装置の具体的な制御方法（第１～第４の制御方法）について説明する。図９は、第１の制御方法に係る駆動回路を示すブロック図であり、図１０は、制御信号のタイミングチャートである。 [Description of First Control Method]
Next, specific control methods (first to fourth control methods) for the switching devices shown in the first to fifth embodiments will be described. FIG. 9 is a block diagram showing a drive circuit according to the first control method, and FIG. 10 is a timing chart of control signals.
　図９に示すように、第１半導体素子Ｑ１、及び第２半導体素子Ｑ２の制御端子（ＦＥＴの場合はゲート端子）には、駆動回路１１（スイッチ制御部）が接続されている。該駆動回路１１は、時間差指令値を出力する制御部１２、及び駆動信号を発生して各半導体素子Ｑ１，Ｑ２の制御端子に第１制御信号Ｖｇ１、及び第２制御信号Ｖｇ２を出力する第１駆動信号発生部１３ａ、第２駆動信号発生部１３ｂを備えている。 As shown in FIG. 9, a drive circuit 11 (switch control unit) is connected to the control terminals (gate terminals in the case of FETs) of the first semiconductor element Q1 and the second semiconductor element Q2. The drive circuit 11 outputs a first control signal Vg1 and a second control signal Vg2 to a control unit 12 that outputs a time difference command value and generates a drive signal to the control terminals of the semiconductor elements Q1 and Q2. A drive signal generator 13a and a second drive signal generator 13b are provided.
　そして、制御部１２により、駆動指令信号が出力された場合には、各駆動信号発生部１３ａ，１３ｂより、予め設定されたタイミングで駆動信号が出力される。即ち、第１駆動信号発生部１３ａより第１制御信号Ｖｇ１が出力され、第２駆動信号発生部１３ｂより第２制御信号Ｖｇ２が出力される。そして、第１制御信号Ｖｇ１は、第１半導体素子Ｑ１の制御端子（ＦＥＴの場合はゲート）に供給され、第２制御信号Ｖｇ２は、第２半導体素子Ｑ２の制御端子に供給される。 And when a drive command signal is output by the control unit 12, a drive signal is output at a preset timing from each of the drive signal generating units 13a and 13b. That is, the first drive signal generator 13a outputs the first control signal Vg1, and the second drive signal generator 13b outputs the second control signal Vg2. The first control signal Vg1 is supplied to the control terminal (gate in the case of FET) of the first semiconductor element Q1, and the second control signal Vg2 is supplied to the control terminal of the second semiconductor element Q2.
　なお、駆動回路１１は、例えば、中央演算ユニット（ＣＰＵ）や、ＲＡＭ、ＲＯＭ、ハードディスク等の記憶手段からなる一体型のコンピュータとして構成することができる。 The drive circuit 11 can be configured as an integrated computer including a central processing unit (CPU), storage means such as RAM, ROM, and hard disk.
　図１０は、第１制御信号Ｖｇ１、及び第２制御信号Ｖｇ２の変化特性を示すタイミングチャートである。図１０（ａ）に示すように、第２制御信号Ｖｇ２は時刻Ｔ５でオフからオンに切り替えられ、時刻Ｔ９でオンからオフに切り替えられる。従って、第２半導体素子Ｑ２は、時刻Ｔ５から若干遅れた時刻Ｔ７にてオンとなり、時刻Ｔ９から若干遅れた時刻Ｔ１１にてオフとなる。 FIG. 10 is a timing chart showing change characteristics of the first control signal Vg1 and the second control signal Vg2. As shown in FIG. 10A, the second control signal Vg2 is switched from OFF to ON at time T5, and is switched from ON to OFF at time T9. Therefore, the second semiconductor element Q2 is turned on at time T7 slightly delayed from time T5, and is turned off at time T11 slightly delayed from time T9.
　一方、第１制御信号Ｖｇ１は、第２制御信号Ｖｇ２よりもオン時刻が遅く、且つオフ時刻が早くなるように設定されている。即ち、図１０（ｂ）に示すように、第１制御信号Ｖｇ１は時刻Ｔ５よりも遅い時刻Ｔ６でオフからオンに切り替えられ、時刻Ｔ９よりも早い時刻Ｔ１０でオンからオフに切り替えられる。従って、第１半導体素子Ｑ１は、時刻Ｔ６から若干遅れた時刻Ｔ８にてオンとなり、時刻Ｔ１０から若干遅れた時刻Ｔ１２にてオフとなる。 On the other hand, the first control signal Vg1 is set so that the ON time is later than the second control signal Vg2, and the OFF time is earlier. That is, as shown in FIG. 10B, the first control signal Vg1 is switched from OFF to ON at time T6 later than time T5, and is switched from ON to OFF at time T10 earlier than time T9. Accordingly, the first semiconductor element Q1 is turned on at time T8 slightly delayed from time T6, and is turned off at time T12 slightly delayed from time T10.
　こうして、第１駆動信号発生部１３ａ、及び第２駆動信号発生部１３ｂより出力する第１制御信号Ｖｇ１、及び第２制御信号Ｖｇ２のオン時刻、及びオフ時刻を制御することにより、各半導体素子Ｑ１，Ｑ２のオン時刻、オフ時刻を任意に設定することが可能となる。 Thus, by controlling the on time and the off time of the first control signal Vg1 and the second control signal Vg2 output from the first drive signal generator 13a and the second drive signal generator 13b, each semiconductor element Q1 is controlled. , Q2 can be set arbitrarily.
　具体的には、前述した第１実施形態では、各制御信号Ｖｇ１，Ｖｇ２のオン時刻が異なるように制御し、第２実施形態では、各制御信号Ｖｇ１，Ｖｇ２のオフ時刻が異なるように制御する。また、第３～第５実施形態では、各制御信号Ｖｇ１，Ｖｇ２のオン時刻、及びオフ時刻の双方が異なるように制御する。 Specifically, in the first embodiment described above, the control signals Vg1 and Vg2 are controlled to have different on times, and in the second embodiment, the control signals Vg1 and Vg2 are controlled to have different off times. . In the third to fifth embodiments, the control signals Vg1 and Vg2 are controlled so that both the on time and the off time are different.
　このように、第１の制御方法では、半導体素子の制御端子へ出力する制御信号の立ち上がり、及び立ち下がりのタイミングのうち、少なくとも一方を調整することにより、オンタイミング、及びオフタイミングを制御することができる。したがって、簡単な制御で各半導体素子Ｑ１，Ｑ２のオン時刻、及びオフ時刻を調整することができ、各半導体素子Ｑ１，Ｑ２の温度を均一化することができる。 Thus, in the first control method, the on timing and the off timing are controlled by adjusting at least one of the rising timing and falling timing of the control signal output to the control terminal of the semiconductor element. Can do. Therefore, the ON time and the OFF time of each semiconductor element Q1, Q2 can be adjusted with simple control, and the temperature of each semiconductor element Q1, Q2 can be made uniform.
［第２の制御方法の説明］
　次に、第２の制御方法について説明する。図１１は、第２の制御方法に係る駆動回路を示すブロック図であり、図１２は、制御信号のタイミングチャートである。 [Description of Second Control Method]
Next, the second control method will be described. FIG. 11 is a block diagram showing a drive circuit according to the second control method, and FIG. 12 is a timing chart of control signals.
　図１１に示すように、第１半導体素子Ｑ１、及び第２半導体素子Ｑ２の制御端子には、駆動回路２１（スイッチ制御部）が接続されている。該駆動回路２１は、駆動指令信号を出力する駆動信号発生部２２と、ダイオードＤ１，Ｄ２、及び抵抗Ｒｇ１～Ｒｇ４を備えている。ダイオードＤ１と抵抗Ｒｇ１は直列接続され、更にこの直列接続に対して、抵抗Ｒｇ２が並列接続されている。そして、この並列接続回路は第１半導体素子Ｑ１の制御端子に接続されている。 As shown in FIG. 11, a drive circuit 21 (switch control unit) is connected to the control terminals of the first semiconductor element Q1 and the second semiconductor element Q2. The drive circuit 21 includes a drive signal generator 22 that outputs a drive command signal, diodes D1 and D2, and resistors Rg1 to Rg4. The diode D1 and the resistor Rg1 are connected in series, and the resistor Rg2 is connected in parallel to the series connection. The parallel connection circuit is connected to the control terminal of the first semiconductor element Q1.
　一方、ダイオードＤ２と抵抗Ｒｇ３は直列接続され、更にこの直列接続に対して、抵抗Ｒｇ４が並列接続されている。そして、この並列接続回路は第２半導体素子Ｑ２の制御端子に接続されている。この際、各抵抗Ｒｇ１～Ｒｇ４の抵抗値は「Ｒｇ１＞Ｒｇ３」、「Ｒｇ２＝Ｒｇ４」なる関係を有している。 On the other hand, the diode D2 and the resistor Rg3 are connected in series, and the resistor Rg4 is connected in parallel to the series connection. The parallel connection circuit is connected to the control terminal of the second semiconductor element Q2. At this time, the resistance values of the resistors Rg1 to Rg4 have a relationship of “Rg1> Rg3” and “Rg2 = Rg4”.
　なお、駆動信号発生部２２は、例えば、中央演算ユニット（ＣＰＵ）や、ＲＡＭ、ＲＯＭ、ハードディスク等の記憶手段からなる一体型のコンピュータとして構成することができる。 The drive signal generator 22 can be configured as an integrated computer including a central processing unit (CPU) and storage means such as RAM, ROM, and hard disk.
　そして、駆動信号発生部２２より駆動指令信号が出力されると、抵抗Ｒｇ１，Ｒｇ２の並列接続回路を経由して第１制御信号Ｖｇ１が第１半導体素子Ｑ１の制御端子に出力される。また、抵抗Ｒｇ３，Ｒｇ４の並列接続回路を経由して第２制御信号Ｖｇ２が第２半導体素子Ｑ２の制御端子に出力される。この際、上述したように、「Ｒｇ１＞Ｒｇ３」なる関係があるので、第１半導体素子Ｑ１のオン時刻は、第２半導体素子Ｑ２のオン時刻よりも遅くなる。 When a drive command signal is output from the drive signal generator 22, the first control signal Vg1 is output to the control terminal of the first semiconductor element Q1 via the parallel connection circuit of the resistors Rg1 and Rg2. Further, the second control signal Vg2 is output to the control terminal of the second semiconductor element Q2 via the parallel connection circuit of the resistors Rg3 and Rg4. At this time, as described above, since there is a relationship of “Rg1> Rg3”, the ON time of the first semiconductor element Q1 is later than the ON time of the second semiconductor element Q2.
　即ち、第２制御信号Ｖｇ２は、図１２（ａ）に示すように、時刻Ｔ５でオンとなった後、徐々に電圧が上昇する。そして、時刻Ｔ７にて第２半導体素子Ｑ２がオンとなる。これに対して、第１制御信号Ｖｇ１は、図１２（ｂ）に示すように、時刻Ｔ６（＝Ｔ５）でオンとなった後、上記の第２制御信号Ｖｇ２よりも遅い速度で（緩やかな傾斜で）電圧が上昇する。そして、時刻Ｔ７よりも若干遅い時刻Ｔ８にて第１半導体素子Ｑ１がオンとなる。従って、第２半導体素子Ｑ２のオン時刻に対して、第１半導体素子Ｑ１をオンとする時刻を相対的に遅くすることが可能となる。 That is, as shown in FIG. 12A, the second control signal Vg2 gradually increases in voltage after being turned on at time T5. Then, at time T7, the second semiconductor element Q2 is turned on. On the other hand, as shown in FIG. 12B, the first control signal Vg1 is turned on at time T6 (= T5), and then at a slower speed than the second control signal Vg2 (slowly). The voltage rises (with a ramp). Then, the first semiconductor element Q1 is turned on at time T8 slightly later than time T7. Therefore, the time at which the first semiconductor element Q1 is turned on can be relatively delayed with respect to the time at which the second semiconductor element Q2 is turned on.
　また、抵抗Ｒｇ２と抵抗Ｒｇ４は抵抗値が同一であるので、オフ時刻は一致する。即ち、第２制御信号Ｖｇ２を時刻Ｔ９でオフとし、第１制御信号Ｖｇ１を同一の時刻Ｔ１０（＝Ｔ９）でオフとした場合には、第２半導体素子Ｑ２、及び第１半導体素子Ｑ１は同一の時刻Ｔ１１（＝Ｔ１２）でオフとなる。従って、前述した第１実施形態に示したように、第２半導体素子Ｑ２のオン時刻に対して、第１半導体素子Ｑ１のオン時刻を遅らせることが可能となる。 Also, since the resistance values of the resistor Rg2 and the resistor Rg4 are the same, the off times coincide. That is, when the second control signal Vg2 is turned off at time T9 and the first control signal Vg1 is turned off at the same time T10 (= T9), the second semiconductor element Q2 and the first semiconductor element Q1 are the same. At time T11 (= T12). Therefore, as shown in the first embodiment described above, the on-time of the first semiconductor element Q1 can be delayed with respect to the on-time of the second semiconductor element Q2.
　このように、第２の制御方法では、各半導体素子Ｑ１，Ｑ２の制御端子へ出力する制御信号の立ち上がりの傾きを調整することにより、オンタイミングを制御することができる。したがって、簡単な制御で各半導体素子Ｑ１，Ｑ２のオン時刻を調整することができ、各半導体素子Ｑ１，Ｑ２の温度を均一化することができる。 As described above, in the second control method, the on-timing can be controlled by adjusting the rising slope of the control signal output to the control terminal of each of the semiconductor elements Q1 and Q2. Therefore, the ON time of each semiconductor element Q1, Q2 can be adjusted with simple control, and the temperature of each semiconductor element Q1, Q2 can be made uniform.
　また、各半導体素子Ｑ１，Ｑ２の制御端子に接続する抵抗の大きさを変更することにより、制御信号の立ち上がりの傾きを調整できるので、構成をより一層簡素化することが可能となる。 In addition, since the slope of the rising edge of the control signal can be adjusted by changing the magnitude of the resistor connected to the control terminal of each of the semiconductor elements Q1 and Q2, the configuration can be further simplified.
［第３の制御方法の説明］
　次に、第３の制御方法について説明する。図１３は、第３の制御方法に係る駆動回路を示すブロック図であり、図１４は、制御信号のタイミングチャートである。 [Description of Third Control Method]
Next, the third control method will be described. FIG. 13 is a block diagram showing a drive circuit according to the third control method, and FIG. 14 is a timing chart of control signals.
　図１３に示すように、第１半導体素子Ｑ１、及び第２半導体素子Ｑ２の制御端子には、駆動回路３１（スイッチ制御部）が接続されている。該駆動回路３１は、駆動指令信号を出力する駆動信号発生部３２と、ダイオードＤ１１，Ｄ１２、及び抵抗Ｒｇ１～Ｒｇ４を備えている。ダイオードＤ１１と抵抗Ｒｇ２は直列接続され、更にこの直列接続に対して、抵抗Ｒｇ１が並列接続されている。そして、この並列接続回路は第１半導体素子Ｑ１の制御端子に接続されている。 As shown in FIG. 13, a drive circuit 31 (switch control unit) is connected to the control terminals of the first semiconductor element Q1 and the second semiconductor element Q2. The drive circuit 31 includes a drive signal generator 32 that outputs a drive command signal, diodes D11 and D12, and resistors Rg1 to Rg4. The diode D11 and the resistor Rg2 are connected in series, and the resistor Rg1 is connected in parallel to the series connection. The parallel connection circuit is connected to the control terminal of the first semiconductor element Q1.
　一方、ダイオードＤ１２と抵抗Ｒｇ４は直列接続され、更にこの直列接続に対して、抵抗Ｒｇ３が並列接続されている。そして、この並列接続回路は第２半導体素子Ｑ２の制御端子に接続されている。この際、各抵抗Ｒｇ１～Ｒｇ４の抵抗値は「Ｒｇ１＝Ｒｇ３」、「Ｒｇ２＜Ｒｇ４」なる関係を有している。 On the other hand, the diode D12 and the resistor Rg4 are connected in series, and the resistor Rg3 is connected in parallel to the series connection. The parallel connection circuit is connected to the control terminal of the second semiconductor element Q2. At this time, the resistance values of the resistors Rg1 to Rg4 have a relationship of “Rg1 = Rg3” and “Rg2 <Rg4”.
　なお、駆動信号発生部３２は、例えば、中央演算ユニット（ＣＰＵ）や、ＲＡＭ、ＲＯＭ、ハードディスク等の記憶手段からなる一体型のコンピュータとして構成することができる。 The drive signal generation unit 32 can be configured as an integrated computer including a central processing unit (CPU) and storage means such as a RAM, a ROM, and a hard disk.
　そして、駆動信号発生部３２より駆動指令信号が出力されると、抵抗Ｒｇ１を経由して第１制御信号Ｖｇ１が第１半導体素子Ｑ１の制御端子に出力される。また、抵抗Ｒｇ３を経由して第２制御信号Ｖｇ２が第２半導体素子Ｑ２の制御端子に出力される。この際、上述したように、「Ｒｇ１＝Ｒｇ３」なる関係があり、且つ、ダイオードＤ１１，Ｄ１２が存在することにより、第１制御信号Ｖｇ１と第２制御信号Ｖｇ２は、同一特性で電圧が上昇する。従って、第１半導体素子Ｑ１のオン時刻と、第２半導体素子Ｑ２のオン時刻は一致する。 When a drive command signal is output from the drive signal generator 32, the first control signal Vg1 is output to the control terminal of the first semiconductor element Q1 via the resistor Rg1. Further, the second control signal Vg2 is output to the control terminal of the second semiconductor element Q2 via the resistor Rg3. At this time, as described above, there is a relationship of “Rg1 = Rg3”, and the presence of the diodes D11 and D12 causes the first control signal Vg1 and the second control signal Vg2 to increase in voltage with the same characteristics. . Therefore, the on time of the first semiconductor element Q1 and the on time of the second semiconductor element Q2 coincide.
　即ち、図１４（ａ）、（ｂ）に示すように、第２制御信号Ｖｇ２、及び第１制御信号Ｖｇ１は、共に時刻Ｔ５（＝Ｔ６）でオンとなり、同一の速度で（同一の傾きで）電圧が上昇し、同一の時刻Ｔ７（＝Ｔ８）で第２半導体素子Ｑ２及び第１半導体素子Ｑ１がオンとなる。 That is, as shown in FIGS. 14A and 14B, the second control signal Vg2 and the first control signal Vg1 are both turned on at time T5 (= T6) and at the same speed (with the same slope). ) The voltage rises, and the second semiconductor element Q2 and the first semiconductor element Q1 are turned on at the same time T7 (= T8).
　一方、駆動信号発生部３２より出力される駆動指令信号がオフとなると、各制御信号Ｖｇ１，Ｖｇ２は低下する。この際、上述したように、「Ｒｇ２＜Ｒｇ４」なる関係があるので、第１制御信号Ｖｇ１の方が第２制御信号Ｖｇ２よりも相対的に早く電圧が低下する。 On the other hand, when the drive command signal output from the drive signal generator 32 is turned off, the control signals Vg1 and Vg2 are lowered. At this time, as described above, since there is a relationship “Rg2 <Rg4”, the voltage of the first control signal Vg1 decreases relatively earlier than the second control signal Vg2.
　即ち、図１４（ａ）、（ｂ）に示すように、時刻Ｔ９（＝Ｔ１０）で、各制御信号Ｖｇ１，Ｖｇ２を共にオフとすると、第１制御信号Ｖｇ１は、第２制御信号Ｖｇ２よりも相対的に早く電圧が低下する。従って、第１半導体素子Ｑ１は時刻Ｔ１２にてオフとなり、第２半導体素子Ｑ２は、この時刻Ｔ１２よりも若干遅い時刻Ｔ１１にてオフとなる。 That is, as shown in FIGS. 14A and 14B, when both control signals Vg1 and Vg2 are turned off at time T9 (= T10), the first control signal Vg1 is more than the second control signal Vg2. The voltage drops relatively quickly. Accordingly, the first semiconductor element Q1 is turned off at time T12, and the second semiconductor element Q2 is turned off at time T11 slightly later than this time T12.
　よって、第２半導体素子Ｑ２に対して、第１半導体素子Ｑ１のオフ時刻を相対的に早めることが可能となる。その結果、前述した第２実施形態に示したように、第２半導体素子Ｑ２に対して、第１半導体素子Ｑ１のオフ時刻を早めることが可能となる。 Therefore, the off time of the first semiconductor element Q1 can be relatively advanced with respect to the second semiconductor element Q2. As a result, as shown in the second embodiment described above, the off time of the first semiconductor element Q1 can be advanced with respect to the second semiconductor element Q2.
　このように、第３の制御方法では、各半導体素子Ｑ１，Ｑ２の制御入力端子へ出力する制御信号の立ち下がりの傾きを調整することにより、オフタイミングを制御することができる。したがって、簡単な制御で各半導体素子Ｑ１，Ｑ２のオフ時刻を調整することができ、各半導体素子Ｑ１，Ｑ２の温度を均一化することができる。 As described above, in the third control method, the off timing can be controlled by adjusting the slope of the fall of the control signal output to the control input terminal of each of the semiconductor elements Q1 and Q2. Therefore, the off time of each semiconductor element Q1, Q2 can be adjusted with simple control, and the temperature of each semiconductor element Q1, Q2 can be made uniform.
　また、各半導体素子Ｑ１，Ｑ２の制御端子に接続する抵抗の大きさを変更することにより、制御信号の立ち下がりの傾きを調整できるので、構成をより一層簡素化することが可能となる。 Also, by changing the magnitude of the resistor connected to the control terminal of each semiconductor element Q1, Q2, the slope of the falling edge of the control signal can be adjusted, so that the configuration can be further simplified.
［第４の制御方法の説明］
　次に、第４の制御方法について説明する。図１５は、第４の制御方法に係る駆動回路を示すブロック図であり、図１６は、制御信号のタイミングチャートである。 [Description of Fourth Control Method]
Next, the fourth control method will be described. FIG. 15 is a block diagram showing a drive circuit according to the fourth control method, and FIG. 16 is a timing chart of control signals.
　図１５に示すように、第１半導体素子Ｑ１、及び第２半導体素子Ｑ２の制御端子には、駆動回路４１（スイッチ制御部）が接続されている。該駆動回路４１は、駆動指令信号を出力する駆動信号発生部４２と、ダイオードＤ２１，Ｄ２２，Ｄ２３，Ｄ２４、及び抵抗Ｒｇ１～Ｒｇ４を備えている。ダイオードＤ２１と抵抗Ｒｇ１は直列接続され、ダイオードＤ２２と抵抗Ｒｇ２は直列接続され、更に、各直列接続回路が互いに並列接続されている。そして、この並列接続回路は第１半導体素子Ｑ１の制御端子に接続されている。 As shown in FIG. 15, a drive circuit 41 (switch control unit) is connected to the control terminals of the first semiconductor element Q1 and the second semiconductor element Q2. The drive circuit 41 includes a drive signal generator 42 that outputs a drive command signal, diodes D21, D22, D23, and D24, and resistors Rg1 to Rg4. The diode D21 and the resistor Rg1 are connected in series, the diode D22 and the resistor Rg2 are connected in series, and the series connection circuits are connected in parallel to each other. The parallel connection circuit is connected to the control terminal of the first semiconductor element Q1.
　一方、ダイオードＤ２３と抵抗Ｒｇ３は直列接続され、ダイオードＤ２４と抵抗Ｒｇ４は直列接続され、更に、各直列接続回路が互いに並列接続されている。そして、この並列接続回路は第２半導体素子Ｑ２の制御端子に接続されている。この際、各抵抗Ｒｇ１～Ｒｇ４の抵抗値は「Ｒｇ１＞Ｒｇ３」、「Ｒｇ２＜Ｒｇ４」なる関係を有している。 On the other hand, the diode D23 and the resistor Rg3 are connected in series, the diode D24 and the resistor Rg4 are connected in series, and the series connection circuits are connected in parallel to each other. The parallel connection circuit is connected to the control terminal of the second semiconductor element Q2. At this time, the resistance values of the resistors Rg1 to Rg4 have a relationship of “Rg1> Rg3” and “Rg2 <Rg4”.
　なお、駆動信号発生部４２は、例えば、中央演算ユニット（ＣＰＵ）や、ＲＡＭ、ＲＯＭ、ハードディスク等の記憶手段からなる一体型のコンピュータとして構成することができる。 The drive signal generator 42 can be configured as an integrated computer including a central processing unit (CPU) and storage means such as a RAM, a ROM, and a hard disk.
　そして、駆動信号発生部４２より駆動指令信号が出力されると、抵抗Ｒｇ１を経由して第１制御信号Ｖｇ１が第１半導体素子Ｑ１の制御端子に出力される。また、抵抗Ｒｇ３を経由して第２制御信号Ｖｇ２が第２半導体素子Ｑ２の制御端子に出力される。この際、上述したように、「Ｒｇ１＞Ｒｇ３」なる関係があるので、第２半導体素子Ｑ２のオン時刻は、第１半導体素子Ｑ１のオン時刻よりも早くなる。 Then, when a drive command signal is output from the drive signal generator 42, the first control signal Vg1 is output to the control terminal of the first semiconductor element Q1 via the resistor Rg1. Further, the second control signal Vg2 is output to the control terminal of the second semiconductor element Q2 via the resistor Rg3. At this time, as described above, since there is a relationship of “Rg1> Rg3”, the ON time of the second semiconductor element Q2 is earlier than the ON time of the first semiconductor element Q1.
　即ち、第２制御信号Ｖｇ２は、図１６（ａ）に示すように、時刻Ｔ５でオンとなった後、徐々に電圧が上昇する。そして、時刻Ｔ７にて第２半導体素子Ｑ２がオンとなる。これに対して、第１制御信号Ｖｇ１は、図１６（ｂ）に示すように、時刻Ｔ６（＝Ｔ５）でオンとなった後、上記の第２制御信号Ｖｇ２よりも遅い速度で電圧が上昇する。そして、時刻Ｔ７よりも若干遅い時刻Ｔ８にて第１半導体素子Ｑ１がオンとなる。従って、第２半導体素子Ｑ２に対して、第１半導体素子Ｑ１のオン時刻を相対的に遅くすることが可能となる。 That is, as shown in FIG. 16A, the second control signal Vg2 gradually increases in voltage after being turned on at time T5. Then, at time T7, the second semiconductor element Q2 is turned on. On the other hand, as shown in FIG. 16B, the first control signal Vg1 increases at a slower speed than the second control signal Vg2 after being turned on at time T6 (= T5). To do. Then, the first semiconductor element Q1 is turned on at time T8 slightly later than time T7. Therefore, the on-time of the first semiconductor element Q1 can be relatively delayed with respect to the second semiconductor element Q2.
　一方、駆動信号発生部４２より出力されている駆動指令信号をオフとした場合には、抵抗Ｒｇ２を経由して第１制御信号Ｖｇ１が低下する。また、抵抗Ｒｇ４を経由して第２制御信号Ｖｇ２が低下する。この際、上述したように、「Ｒｇ２＜Ｒｇ４」なる関係があるので、第２半導体素子Ｑ２のオフ時刻は、第１半導体素子Ｑ１のオフ時刻よりも遅くなる。 On the other hand, when the drive command signal output from the drive signal generator 42 is turned off, the first control signal Vg1 decreases via the resistor Rg2. Further, the second control signal Vg2 decreases via the resistor Rg4. At this time, as described above, since there is a relationship of “Rg2 <Rg4”, the off time of the second semiconductor element Q2 is later than the off time of the first semiconductor element Q1.
　即ち、第２制御信号Ｖｇ２は、図１６（ａ）に示すように、時刻Ｔ９でオフとなった後、徐々に電圧が低下する。そして、時刻Ｔ１１にて第２半導体素子Ｑ２がオフとなる。これに対して、第１制御信号Ｖｇ１は、図１６（ｂ）に示すように、時刻Ｔ１０（＝Ｔ９）でオフとなった後、上記の第２制御信号Ｖｇ２よりも速い速度で電圧が低下する。そして、時刻Ｔ１１よりも若干早い時刻Ｔ１２にて第１半導体素子Ｑ１がオフとなる。従って、第２半導体素子Ｑ２に対して、第１半導体素子Ｑ１のオフ時刻を相対的に早めることが可能となる。 That is, as shown in FIG. 16A, the voltage of the second control signal Vg2 gradually decreases after being turned off at time T9. Then, at time T11, the second semiconductor element Q2 is turned off. On the other hand, as shown in FIG. 16 (b), the first control signal Vg1 decreases at a faster speed than the second control signal Vg2 after being turned off at time T10 (= T9). To do. The first semiconductor element Q1 is turned off at time T12 slightly earlier than time T11. Therefore, the off time of the first semiconductor element Q1 can be relatively advanced with respect to the second semiconductor element Q2.
　このため、第４の制御方法を採用することにより、前述した第３～第５実施形態に示したように、第２半導体素子Ｑ２に対して、第１半導体素子Ｑ１のオン時刻を遅らせ、且つ、オフ時刻を早めることが可能となる。 Therefore, by adopting the fourth control method, as shown in the third to fifth embodiments, the on-time of the first semiconductor element Q1 is delayed with respect to the second semiconductor element Q2, and The off time can be advanced.
　このように、第４の制御方法では、各半導体素子Ｑ１，Ｑ２の制御入力端子へ出力する制御信号の立ち上がりの傾き、及び立ち下がりの傾きを調整することにより、オンタイミング、及びオフタイミングを制御することができる。したがって、簡単な制御で各半導体素子Ｑ１，Ｑ２のオン時刻、及びオフ時刻を調整することができ、各半導体素子Ｑ１，Ｑ２の温度を均一化することができる。 Thus, in the fourth control method, the on-timing and off-timing are controlled by adjusting the rising and falling slopes of the control signals output to the control input terminals of the semiconductor elements Q1 and Q2. can do. Therefore, the ON time and the OFF time of each semiconductor element Q1, Q2 can be adjusted with simple control, and the temperature of each semiconductor element Q1, Q2 can be made uniform.
　また、各半導体素子Ｑ１，Ｑ２の制御端子に接続する抵抗の大きさを変更することにより、制御信号の立ち上がりの傾き、及び立ち下がりの傾きを調整できるので、構成をより一層簡素化することが可能となる。 Further, by changing the magnitude of the resistance connected to the control terminal of each semiconductor element Q1, Q2, the rising slope and falling slope of the control signal can be adjusted, so that the configuration can be further simplified. It becomes possible.
［第６実施形態の説明］
　図１７、図１８は、本発明の第６実施形態に係るスイッチング装置を示す説明図、及びタイミングチャートである。 [Explanation of Sixth Embodiment]
17 and 18 are an explanatory diagram and a timing chart showing the switching device according to the sixth embodiment of the present invention.
　図１７に示すように、第６実施形態に係るスイッチング装置は、３つの半導体素子、即ち、第１半導体素子Ｑ１１、第２半導体素子Ｑ１２、及び第３半導体素子Ｑ１３が２つの電極ａ１，ａ２に対して互いに並列接続されている。並列接続された半導体素子Ｑ１１～Ｑ１３は、例えば負荷回路（図示省略）に接続されて該負荷回路のオン（導通）、オフ（非導通）を制御する。例えば、図１７に示す電極ａ１が直流電源に接続され、電極ａ２が負荷に接続され、各半導体素子Ｑ１１～Ｑ１３を連動させてオン、オフを切り替えることにより、負荷への電流の供給、停止（即ち、負荷の駆動、停止）を制御することができる。各半導体素子Ｑ１１～Ｑ１３は、例えばＦＥＴ（電界効果トランジスタ）やＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）である。なお、各半導体素子Ｑ１１～Ｑ１３は、同一の形状、同一の電気特性のものを用いても良いし、異なるものであっても良い。 As shown in FIG. 17, in the switching device according to the sixth embodiment, three semiconductor elements, that is, a first semiconductor element Q11, a second semiconductor element Q12, and a third semiconductor element Q13 are formed on two electrodes a1 and a2. On the other hand, they are connected in parallel. The semiconductor elements Q11 to Q13 connected in parallel are connected to, for example, a load circuit (not shown) to control on (conduction) and off (non-conduction) of the load circuit. For example, the electrode a1 shown in FIG. 17 is connected to a DC power source, the electrode a2 is connected to a load, and the semiconductor elements Q11 to Q13 are switched on and off in conjunction with each other, thereby supplying and stopping current to the load ( That is, the driving and stopping of the load can be controlled. Each of the semiconductor elements Q11 to Q13 is, for example, an FET (field effect transistor) or an IGBT (insulated gate bipolar transistor). The semiconductor elements Q11 to Q13 may have the same shape and the same electrical characteristics, or may be different.
　そして、第６実施形態では、各半導体素子Ｑ１１～Ｑ１３の制御端子（ＦＥＴの場合にはゲート端子）に供給する制御信号を変更することにより、各半導体素子Ｑ１１～Ｑ１３をオンとする時刻、及びオフとする時刻を調整して、各半導体素子Ｑ１１～Ｑ１３の発熱量を制御する。即ち、オン時刻、及びオフ時刻を変更することにより、各半導体素子Ｑ１１～Ｑ１３のスイッチング損失が変化するので、このスイッチング損失に起因して生じる発熱量を制御することができる。 In the sixth embodiment, by changing the control signal supplied to the control terminals (gate terminals in the case of FETs) of the semiconductor elements Q11 to Q13, the time when the semiconductor elements Q11 to Q13 are turned on, and The amount of heat generated by each of the semiconductor elements Q11 to Q13 is controlled by adjusting the time to turn off. That is, by changing the on time and the off time, the switching loss of each of the semiconductor elements Q11 to Q13 changes, so that the amount of heat generated due to this switching loss can be controlled.
　具体的には、図１８（ａ）、（ｂ）に示すように、第１半導体素子Ｑ１１のオン時刻及びオフ時刻に対して、第２半導体素子Ｑ１２のオン時刻を遅くし（Ｔ１３，Ｔ１４参照）、且つオフ時刻を早める（Ｔ１６，Ｔ１７参照）。これにより、第２半導体素子Ｑ１２の発熱量を第１半導体素子Ｑ１１の発熱量よりも低くすることができる。更に、第２半導体素子Ｑ１２のオン時刻及びオフ時刻に対して、第３半導体素子Ｑ１３のオン時刻を遅くし（Ｔ１４，Ｔ１５参照）、且つオフ時刻を早める（Ｔ１７，Ｔ１８参照）。これにより、第３半導体素子Ｑ１３の発熱量を第２半導体素子Ｑ１２の発熱量よりも低くすることができる。なお、各半導体素子Ｑ１１～Ｑ１３の制御端子に供給する制御信号は電気信号に限定されず、光、電界、磁界、圧力、音波等の各信号とすることも可能である。 Specifically, as shown in FIGS. 18A and 18B, the ON time of the second semiconductor element Q12 is delayed with respect to the ON time and OFF time of the first semiconductor element Q11 (see T13 and T14). ) And advance the off time (see T16 and T17). Thereby, the heat generation amount of the second semiconductor element Q12 can be made lower than the heat generation amount of the first semiconductor element Q11. Further, the ON time of the third semiconductor element Q13 is delayed with respect to the ON time and OFF time of the second semiconductor element Q12 (see T14 and T15), and the OFF time is advanced (see T17 and T18). Thereby, the heat generation amount of the third semiconductor element Q13 can be made lower than the heat generation amount of the second semiconductor element Q12. The control signals supplied to the control terminals of the semiconductor elements Q11 to Q13 are not limited to electrical signals, and may be signals such as light, electric field, magnetic field, pressure, and sound wave.
　こうして、図１８に示した時刻Ｔ１３～Ｔ１８を個別に設定することにより、各半導体素子Ｑ１１～Ｑ１３の発熱量を調整することができる。従って、各半導体素子Ｑ１１～Ｑ１３の形状や電気特性の違いにより、各半導体素子Ｑ１１～Ｑ１３のオン抵抗が異なり、オン時の発熱量である定常損失が異なる場合であっても、各半導体素子Ｑ１１～Ｑ１３の温度のバランスを調整することが可能である。即ち、各半導体素子Ｑ１１～Ｑ１３のオン時刻（図１８に示すＴ１３，Ｔ１４，Ｔ１５）を個別に設定し、且つ、オフ時刻（Ｔ１６，Ｔ１７，Ｔ１８）を個別に設定することにより、各半導体素子Ｑ１１～Ｑ１３の温度のバランスを調整することが可能である。 Thus, by individually setting the times T13 to T18 shown in FIG. 18, the amount of heat generated by each of the semiconductor elements Q11 to Q13 can be adjusted. Therefore, even if the semiconductor elements Q11 to Q13 have different on-resistances due to differences in the shape and electrical characteristics of the semiconductor elements Q11 to Q13, and the steady loss that is the amount of heat generated when the semiconductor elements are turned on, the semiconductor elements Q11 to Q13 are different. It is possible to adjust the temperature balance of .about.Q13. That is, by setting the on times (T13, T14, T15 shown in FIG. 18) of each of the semiconductor elements Q11 to Q13 individually and individually setting the off times (T16, T17, T18), It is possible to adjust the temperature balance of Q11 to Q13.
　また、例えば図１７に示す第１半導体素子Ｑ１１が冷却装置による冷却効果の高い位置に配置され、第２半導体素子Ｑ１２が相対的に冷却効果の低い位置に配置され、更に、第３半導体素子Ｑ１３がより冷却効果の低い位置に配置されている場合には、Ｑ１１，Ｑ１２，Ｑ１３の順にオン時刻を早め、且つ、オフ時刻を遅らせる。これにより、Ｑ１１，Ｑ１２，Ｑ１３の順に発熱量を大きくすることができる。その結果、各半導体素子Ｑ１１～Ｑ１３の温度をほぼ一定に保持することが可能となる。なお、第６実施形態に係るスイッチング装置の具体的な制御方法については、前述した第１～第４の制御方法と同様の方法を用いることが可能である。 Further, for example, the first semiconductor element Q11 shown in FIG. 17 is disposed at a position where the cooling effect by the cooling device is high, the second semiconductor element Q12 is disposed at a position where the cooling effect is relatively low, and further, the third semiconductor element Q13. Is placed at a position with a lower cooling effect, the on time is advanced and the off time is delayed in the order of Q11, Q12, and Q13. Thereby, the emitted-heat amount can be enlarged in order of Q11, Q12, Q13. As a result, the temperatures of the semiconductor elements Q11 to Q13 can be kept substantially constant. Note that, as a specific control method of the switching device according to the sixth embodiment, the same methods as the first to fourth control methods described above can be used.
　このようにして、第６実施形態に係るスイッチング装置では、並列接続される半導体素子が３個以上となった場合でも、前述した第１～第５実施形態と同様に、各半導体素子の温度を均一化することが可能となる。 As described above, in the switching device according to the sixth embodiment, even when there are three or more semiconductor elements connected in parallel, the temperature of each semiconductor element is set as in the first to fifth embodiments described above. It becomes possible to make uniform.
［第７実施形態の説明］
　次に、本発明の第７実施形態に係るスイッチング装置について説明する。回路構成は、前述した図１７と同様である。以下、図１９（ａ）、（ｂ）を参照して、各半導体素子Ｑ１１～Ｑ１３の制御について説明する。 [Description of Seventh Embodiment]
Next, a switching device according to a seventh embodiment of the present invention will be described. The circuit configuration is the same as that shown in FIG. Hereinafter, with reference to FIGS. 19A and 19B, control of each of the semiconductor elements Q11 to Q13 will be described.
　第７実施形態では、第１半導体素子Ｑ１１及び第３半導体素子Ｑ１３のオン時刻、及びオフ時刻を同一とし、第２半導体素子Ｑ１２のオン時刻及びオフ時刻が異なるように設定する。具体的には、第１半導体素子Ｑ１１及び第３半導体素子Ｑ１３のオン時刻をＴ１３（＝Ｔ１５）とし、オフ時刻をＴ１６（＝Ｔ１８）とする。これに対して、第２半導体素子Ｑ１２のオン時刻をＴ１３よりも若干遅いＴ１４とし、オフ時刻をＴ１６よりも若干早いＴ１７としている。 In the seventh embodiment, the ON time and OFF time of the first semiconductor element Q11 and the third semiconductor element Q13 are made the same, and the ON time and OFF time of the second semiconductor element Q12 are set to be different. Specifically, the on time of the first semiconductor element Q11 and the third semiconductor element Q13 is T13 (= T15), and the off time is T16 (= T18). On the other hand, the ON time of the second semiconductor element Q12 is T14 that is slightly later than T13, and the OFF time is T17 that is slightly earlier than T16.
　こうすることにより、第１半導体素子Ｑ１１、及び第３半導体素子Ｑ１３の発熱量をほぼ同一とし、第２半導体素子Ｑ１２の発熱量を相対的に低下させることが可能となる。従って、例えば第２半導体素子Ｑ１２が冷却装置による冷却効果の低い位置に配置され、第１半導体素子Ｑ１１及び第３半導体素子Ｑ１３が相対的に冷却効果の高い位置に配置されている場合には、第２半導体素子Ｑ２の発熱量を、第１半導体素子Ｑ１１及び第３半導体素子Ｑ１３に対して相対的に低減させることができる。したがって、結果として、各半導体素子Ｑ１１～Ｑ１３の温度をほぼ一定に保持することが可能となる。なお、第７実施形態に係るスイッチング装置の具体的な制御方法については、前述した第１～第４の制御方法と同様の方法を用いることが可能である。 By so doing, the heat generation amounts of the first semiconductor element Q11 and the third semiconductor element Q13 can be made substantially the same, and the heat generation amount of the second semiconductor element Q12 can be relatively reduced. Therefore, for example, when the second semiconductor element Q12 is arranged at a position where the cooling effect by the cooling device is low, and the first semiconductor element Q11 and the third semiconductor element Q13 are arranged at a position where the cooling effect is relatively high, The amount of heat generated by the second semiconductor element Q2 can be reduced relative to the first semiconductor element Q11 and the third semiconductor element Q13. Therefore, as a result, the temperatures of the semiconductor elements Q11 to Q13 can be kept substantially constant. Note that as a specific control method of the switching device according to the seventh embodiment, the same method as the first to fourth control methods described above can be used.
　このようにして、第７実施形態に係るスイッチング装置では、並列接続される半導体素子が３個以上となった場合でも、前述した第１～第５実施形態と同様に、各半導体素子の温度を均一化することが可能となる。 As described above, in the switching device according to the seventh embodiment, even when there are three or more semiconductor elements connected in parallel, the temperature of each semiconductor element is set as in the first to fifth embodiments. It becomes possible to make uniform.
　以上、本発明のスイッチング装置を図示の実施形態に基づいて説明したが、本発明はこれに限定されるものではなく、各部の構成は、同様の機能を有する任意の構成のものに置き換えることができる。 As described above, the switching device of the present invention has been described based on the illustrated embodiment, but the present invention is not limited to this, and the configuration of each part may be replaced with any configuration having the same function. it can.
　本出願は、２０１３年８月１２日に出願された日本国特許願第２０１３－１６７４６２号に基づく優先権を主張しており、この出願の内容が参照により本発明の明細書に組み込まれる。 This application claims priority based on Japanese Patent Application No. 2013-167462 filed on August 12, 2013, and the contents of this application are incorporated into the specification of the present invention by reference.
　Ｑ１　　第１半導体素子
　Ｑ２　　第２半導体素子
　Ｑ１１　第１半導体素子
　Ｑ１２　第２半導体素子
　Ｑ１３　第３半導体素子
　ａ１　　電極
　ａ２　　電極
　１１　　駆動回路
　１２　　制御部
　１３ａ　第１駆動信号発生部
　１３ｂ　第２駆動信号発生部
　２１　　駆動回路
　２２　　駆動信号発生部
　３１　　駆動回路
　３２　　駆動信号発生部
　４１　　駆動回路
　４２　　駆動信号発生部
　５１　　冷却装置 Q1 first semiconductor element Q2 second semiconductor element Q11 first semiconductor element Q12 second semiconductor element Q13 third semiconductor element a1 electrode a2 electrode 11 drive circuit 12 control unit 13a first drive signal generation unit 13b second drive signal generation unit 21 Drive circuit 22 Drive signal generator 31 Drive circuit 32 Drive signal generator 41 Drive circuit 42 Drive signal generator 51 Cooling device

Claims (8)

  1. 　互いに並列に接続された複数の半導体素子と、
    　前記各半導体素子の導通、非導通を互いに連動して切り替える制御信号を出力するスイッチ制御部と、を有し、
    　前記スイッチ制御部は、少なくとも１つの前記半導体素子について、導通から非導通へ切り替えるオフタイミング、及び非導通から導通へ切り替えるオンタイミングのうちの少なくとも一方を、他の半導体素子と異なるように設定すること
    　を特徴とするスイッチング装置。     A plurality of semiconductor elements connected in parallel to each other;
    A switch control unit that outputs a control signal for switching between conduction and non-conduction of each semiconductor element in conjunction with each other;
    The switch control unit sets at least one of an off timing for switching from conduction to non-conduction and an on timing for switching from non-conduction to conduction for at least one of the semiconductor elements to be different from other semiconductor elements. A switching device characterized by the above.
  2. 　前記各半導体素子の近傍に設けられ、各半導体素子を冷却する冷却部を更に備え、
    　前記スイッチ制御部は、それぞれの半導体素子に対する前記冷却部による冷却効果に応じて、前記オンタイミング、及びオフタイミングの少なくとも一方を設定することを特徴とする請求項１に記載のスイッチング装置。     Provided in the vicinity of each semiconductor element, further comprising a cooling unit for cooling each semiconductor element;
    The switching device according to claim 1, wherein the switch control unit sets at least one of the on-timing and the off-timing according to a cooling effect of the cooling unit on each semiconductor element.
  3. 　前記スイッチ制御部は、
    　前記冷却部による冷却効果の低い半導体素子を、相対的に冷却効果の高い半導体素子に対して、前記オンタイミングが遅くなるように設定すること、及び、オフタイミングが早くなるように設定すること、の少なくとも一方の設定を行うことを特徴とする請求項２に記載のスイッチング装置。     The switch control unit
    Setting a semiconductor element having a low cooling effect by the cooling unit so that the on-timing is delayed with respect to a semiconductor element having a relatively high cooling effect, and setting the off-timing to be earlier; The switching device according to claim 2, wherein at least one of the settings is performed.
  4. 　前記スイッチ制御部は、
    　前記各半導体素子のうち、抜熱抵抗の高い位置に設置された半導体素子を、相対的に抜熱抵抗の低い位置に設置された半導体素子に対して、前記オンタイミングが遅くなるように設定すること、及び、オフタイミングが早くなるように設定すること、の少なくとも一方の設定を行うことを特徴とする請求項１に記載のスイッチング装置。     The switch control unit
    Among the semiconductor elements, a semiconductor element installed at a position with a high heat extraction resistance is set so that the on-timing is delayed with respect to a semiconductor element installed at a position with a relatively low heat extraction resistance. The switching device according to claim 1, wherein at least one of the setting and the setting so that the off timing is advanced is performed.
  5. 　前記スイッチ制御部は、
    　前記各半導体素子のうち、周囲温度の高い位置に設置された半導体素子を、相対的に周囲温度の低い位置に設置された半導体素子に対して、前記オンタイミングが遅くなるように設定すること、及び、オフタイミングが早くなるように設定すること、の少なくとも一方の設定を行うことを特徴とする請求項１に記載のスイッチング装置。     The switch control unit
    Among the semiconductor elements, setting a semiconductor element installed at a high ambient temperature position so that the on-timing is delayed with respect to a semiconductor element installed at a relatively low ambient temperature position, 2. The switching device according to claim 1, wherein at least one of the setting is performed so that the off timing is advanced.
  6. 　前記スイッチ制御部は、
    　前記半導体素子の制御端子へ出力する制御信号の立ち上がり、及び立ち下がりのタイミングのうち、少なくとも一方を調整することにより、前記オンタイミング、及びオフタイミングを制御することを特徴とする請求項１～請求項５のいずれか１項に記載のスイッチング装置。     The switch control unit
    The on-timing and off-timing are controlled by adjusting at least one of rising timing and falling timing of a control signal output to the control terminal of the semiconductor element. 6. The switching device according to any one of items 5.
  7. 　前記スイッチ制御部は、
    　前記半導体素子の制御端子へ出力する制御信号の立ち上がりの傾き、及び立ち下がりの傾きのうち、少なくとも一方を調整することにより、前記オンタイミング、及びオフタイミングを制御することを特徴とする請求項１～請求項５のいずれか１項に記載のスイッチング装置。     The switch control unit
    2. The on-timing and off-timing are controlled by adjusting at least one of a rising slope and a falling slope of a control signal output to a control terminal of the semiconductor element. The switching device according to any one of claims 5 to 6.
  8. 　前記スイッチ制御部は、各半導体素子の前記制御端子に接続される抵抗の大きさを変更することにより、前記制御信号の立ち上がりの傾き、及び立ち下がりの傾きを調整することを特徴とする請求項７に記載のスイッチング装置。 The switch control unit adjusts a rising slope and a falling slope of the control signal by changing a magnitude of a resistor connected to the control terminal of each semiconductor element. 8. The switching device according to 7.
PCT/JP2014/070092 2013-08-12 2014-07-30 Switching device WO2015022860A1 (en)

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WO2020134134A1 (en) * 2018-12-29 2020-07-02 中兴通讯股份有限公司 Switch circuit and switch power supply
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