JP2018534847A5 - - Google Patents

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Publication number
JP2018534847A5
JP2018534847A5 JP2018517310A JP2018517310A JP2018534847A5 JP 2018534847 A5 JP2018534847 A5 JP 2018534847A5 JP 2018517310 A JP2018517310 A JP 2018517310A JP 2018517310 A JP2018517310 A JP 2018517310A JP 2018534847 A5 JP2018534847 A5 JP 2018534847A5
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JP
Japan
Prior art keywords
symbols
sequence
clock signal
line
wire link
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2018517310A
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English (en)
Japanese (ja)
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JP2018534847A (ja
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Publication date
Priority claimed from US14/875,592 external-priority patent/US9735948B2/en
Application filed filed Critical
Priority claimed from PCT/US2016/051131 external-priority patent/WO2017062132A1/en
Publication of JP2018534847A publication Critical patent/JP2018534847A/ja
Publication of JP2018534847A5 publication Critical patent/JP2018534847A5/ja
Pending legal-status Critical Current

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JP2018517310A 2015-10-05 2016-09-09 マルチレーンｎ階乗符号化通信システムおよび他のマルチワイヤ通信システム Pending JP2018534847A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/875,592 US9735948B2 (en) 2013-10-03 2015-10-05 Multi-lane N-factorial (N!) and other multi-wire communication systems
US14/875,592 2015-10-05
PCT/US2016/051131 WO2017062132A1 (en) 2015-10-05 2016-09-09 Multi-lane n-factorial encoded and other multi-wire communication systems

Publications (2)

Publication Number Publication Date
JP2018534847A JP2018534847A (ja) 2018-11-22
JP2018534847A5 true JP2018534847A5 (https=) 2019-09-26

Family

ID=56997556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018517310A Pending JP2018534847A (ja) 2015-10-05 2016-09-09 マルチレーンｎ階乗符号化通信システムおよび他のマルチワイヤ通信システム

Country Status (8)

Country Link
EP (1) EP3360278A1 (https=)
JP (1) JP2018534847A (https=)
KR (1) KR102520096B1 (https=)
CN (1) CN108141346A (https=)
AU (1) AU2016335548A1 (https=)
BR (1) BR112018006874A2 (https=)
TW (1) TW201714443A (https=)
WO (1) WO2017062132A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11437998B2 (en) 2020-04-30 2022-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including back side conductive lines for clock signals
CN113192950B (zh) 2020-04-30 2025-04-18 台湾积体电路制造股份有限公司 集成电路及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05227173A (ja) * 1992-02-10 1993-09-03 Oki Electric Ind Co Ltd 多重処理方式
US9711041B2 (en) * 2012-03-16 2017-07-18 Qualcomm Incorporated N-phase polarity data transfer
US9030976B2 (en) * 2008-03-27 2015-05-12 Silicon Image, Inc. Bi-directional digital interface for video and audio (DIVA)
JP2013110554A (ja) * 2011-11-21 2013-06-06 Panasonic Corp 送信装置、受信装置及びシリアル伝送システム
US8996740B2 (en) * 2012-06-29 2015-03-31 Qualcomm Incorporated N-phase polarity output pin mode multiplexer
EP2914033B1 (en) * 2012-10-26 2020-01-15 Hitachi Kokusai Electric Inc. Multichannel wireless communication system, base station, and method for using channel
US9363071B2 (en) * 2013-03-07 2016-06-07 Qualcomm Incorporated Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches
US9552325B2 (en) 2013-06-12 2017-01-24 Qualcomm Incorporated Camera control interface extension bus
US9755818B2 (en) * 2013-10-03 2017-09-05 Qualcomm Incorporated Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes
US20150220472A1 (en) * 2014-02-05 2015-08-06 Qualcomm Incorporated Increasing throughput on multi-wire and multi-lane interfaces
JP6219538B2 (ja) 2014-03-06 2017-10-25 クアルコム，インコーポレイテッド 複数のワイヤデータ信号のためのクロック復元回路

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