JP2018534760A - 縦型電界効果トランジスタ - Google Patents
縦型電界効果トランジスタ Download PDFInfo
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- JP2018534760A JP2018534760A JP2018511421A JP2018511421A JP2018534760A JP 2018534760 A JP2018534760 A JP 2018534760A JP 2018511421 A JP2018511421 A JP 2018511421A JP 2018511421 A JP2018511421 A JP 2018511421A JP 2018534760 A JP2018534760 A JP 2018534760A
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- field effect
- effect transistor
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- electrode
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H10K19/20—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising components having an active region that includes an inorganic semiconductor
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Abstract
Description
幾つかの実施形態によれば、図6a、図6bおよび図7a、図7bは、例示的なVFETの特性を示している。この例示的なVFETの特性の説明を含むこれら図面の以下の説明は、一例として提供するものであり、上述したVFETの特性に関して限定するものではない。
以下に、上述したVFETデバイスの例示的な製造技術を述べる。これらの技術は単なる例として提供するものであり、VFETデバイスおよびVFETの製造方法の両方に関して限定するものではないことを理解されたい。上述したように、VFETは任意選択的に光活性層を含むことができ、VFETが光活性層を含むか否かに応じて、以下に説明する例示的な製造技術の一部のみをVFETデバイスの特定の実施形態に適用することができる。
ZnOナノ結晶合成およびスピンコーティング手順:0.6585gの酢酸亜鉛二水和物(ZnAc、98+%、ACROS有機物)および30mlのジメチルスルホキシド(Fisher Scientific社)を室温下で475rpmの速度でフラスコ内で一緒に撹拌した。別のフラスコにおいて、0.6gのテトラメチルアンモニウムヒドロキシド(>97%、Sigma Aldrich社)および30mlのエチルアルコールを2分間振とうすることによって混合した。その後、両フラスコの溶媒を合わせて、625rpmの速度で50分間攪拌した。次に、溶媒を10mlの量ずつ6本の遠心管に分けた。各管に20mlの酢酸エチルと20mlのヘプタンを加えた後、20℃で6分間7000rpmの速度で遠心分離した。遠心分離プロセスの後、上清み溶媒を除去し、各管に6mlのエタノールを添加してZnO前駆体溶液を作製した。その後、溶液とエタノールが2:3の体積比となるようにエタノールを添加することによってZnO溶液を希釈した。希釈したZnO溶液をITO基板上で、2000rpmの速度で1秒間(第1段階)、4000rpmで1秒間(第2段階)、5000rpmで40秒間(第3段階)スピンコーティングした。スピンコーティングの直後、基板を加熱板上に置き、80℃で10分間の熱処理を行った。最後に、酸素および水分濃度が1ppm未満のグローブボックス内で、30秒間のUV硬化(λ=365nm)を行った。
ポリスチレン単層形成:ポリスチレン粒子懸濁液(平均粒径1.1μm、LB11、Sigma Aldrich社)1mlを10mlの脱イオン水と混合し、その溶液を20℃、8,000rpmの速度で20分間遠心分離した。上清み液を注いだ後、エタノール10mlを加え、溶液を上記条件で遠心分離した。上清みエタノールを注いだ後、エチレングリコール4mlを加え、ロッド超音波処理機で攪拌した。
VFETの作製:パターニングされたITOガラスを、超音波浴中でアセトンおよびイソプロパノールを用いてそれぞれ15分間洗浄し、続いて30分間UV−オゾン処理を行った。溶液処理したZnOナノ結晶膜を空気中でITOガラス基板上にスピンコーティングし、続いて80℃で15分間熱処理を行った。PbS量子ドットナノ結晶は、前のセクションで説明したように、スピンコーティングプロセス中の表面配位子として1,3−ベンゼンジチオール(BDT)を処理することによって、1,046nmにあるピーク吸収波長で合成された。最適な厚さとするために、PbS膜のスピンコーティングを4回行い、240nmのPbS膜厚を得た。次に、原子層堆積(Cambridge Nano Fiji 200、チャンバ温度=80℃、堆積速度=サイクル当たり1Å、サイクル数=500)により、厚さ50nmのHfO2ゲート誘電体をPbS層上に堆積させた。前のセクションで説明したように多孔質ITOソース電極を作製した後、多孔質ITO/HfO2/PbS/ZnO/ITOサンプルを30分間UV−オゾン処理して多孔質ITO電極の仕事関数を増加させた。UV処理の後、サンプルを熱蒸発チャンバ(Kurt J.Lesker社)に移し、C60チャンネルの電流短絡パス(current short path)を避けるために、厚さ1μmのC60チャンネル層(99.5%、M.E.R社)を堆積させた。上部ドレイン電極には、厚さ100nmのAl膜を堆積させた。
図9は、VFETの出力依存性を示している。0.88μW/cm2から81.2μW/cm2までの異なるIR出力密度を持つ伝達曲線が図9(左)にプロットされている。EQEを最大にするために、高いVDS(=13V)を印加した。図9において、例示的な曲線A、B、CおよびDは、光電流無し(暗)、0.88μW/cm2、1.05μW/cm2および81.2μW/cm2にそれぞれ対応するものである。
図10は、デバイス動作ウィンドウに対するPbSの厚さの影響を示している。PbSの厚さは、PbSスピンコーティングプロセスの数によって制御した。図示のように、より厚いPbS膜は、暗伝達曲線(dark transfer curve)をオンにするために、より高いゲート電圧を必要とする。さらに、厚いPbS膜におけるIR吸収は、薄いPbS膜における吸収よりも大きく、IR照明下でより大きな閾値電圧シフトを引き起こす。その結果、厚さ240nmのPbS層を有するデバイスにおいて、より広いデバイス動作ウィンドウが観察された。
図11は、VDSがEQEに与える影響を示している。EQEに対するVDS(3V、6V、10V、13V)の影響を調べた。VDSの関数としてのEQEの大きな変化を示すために、相対的に強いIR出力密度(157μW/cm2)を適用した。
図12は、感光性VFETの再現性を示している。20個のIR感光性VFETデバイスをまったく同じ条件で製造し、各デバイスについてVGS=8VおよびVDS=3VでEQEを測定した。測定には強力なIR出力密度(157μW/cm2)を適用し、20個のデバイスのうち18個が利得EQEを示した。
検出率D*は、以下の式(1)で表される。
ここで、Aはデバイス面積、Δfは帯域幅(Hz)、RはA/Wの応答度、inはノイズ電流(アンペア)である。Rは、以下の式で表される。
ここで、qは電子電荷、hはプランク定数、νは入射光子の周波数である。ノイズ電流は、Stanford Research社のSR830ロックインアンプとSR570低ノイズプリアンプ(2)を使用して、電気的および光学的シールド環境下で測定した。ノイズ電流のロックイン周波数は、測定中に30Hzに設定した。電圧源として、アルカリ電池を使用してノイズを最小限に抑えた。厚さ240nmのPbS膜を用いたVFETでは、VGS=3.5V、VDS=13Vで1.23×1013jonesの高い検出感度が得られ、これは市販のInGaAsフォトダイオード(3)の検出感度に匹敵する。
図13は、ソース−ドレインバイアスの関数としてのVFETのソース−ドレイン電流の一例を示している。VFETにおけるC60層の抵抗は、低電圧でVDSを掃引しながらVGS=11Vで測定した。VGSが高くVDSが低いため、ソース−ドレイン電流はオームの法則に従い、C60層の抵抗を6,024Ωとして計算することができる。抵抗をC60(1,014Ω/m)の一般的な抵抗率から計算する場合、抵抗は250Ωとなるはずであり、これは本出願人のVFETのC60層の測定抵抗率のほぼ24分の1である。抵抗の大きな違いは、上部Alドレイン電極の接触抵抗に起因する。VFETの合計静電容量はVDS=7VおよびVGS=6Vで1.6nFと測定されたため、RC測定から計算されたRC定数は17kHzのカットオフ周波数に対応する9.6μsであった。
以下の文献は、引用によりその全体が本明細書に援用されるものである。
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Claims (20)
- 縦型電界効果トランジスタであって、
第1の電極と、
導電性材料の層から形成された多孔質導電層であって、その中に配置された導電性材料を貫通して延びる複数の孔を有する多孔質導電層と、
前記第1の電極と前記多孔質導電層との間の誘電体層と、
前記多孔質導電層と接触する電荷輸送層と、
前記電荷輸送層に電気的に接続された第2の電極とを備えることを特徴とする縦型電界効果トランジスタ。 - 請求項1に記載の縦型電界効果トランジスタにおいて、
前記複数の孔の各々が0.1μm〜10μmの直径を有することを特徴とする縦型電界効果トランジスタ。 - 請求項1に記載の縦型電界効果トランジスタにおいて、
前記導電性材料が透明であることを特徴とする縦型電界効果トランジスタ。 - 請求項1に記載の縦型電界効果トランジスタにおいて、
前記導電性材料が透明導電体または透明ドープ半導体であることを特徴とする縦型電界効果トランジスタ。 - 請求項4に記載の縦型電界効果トランジスタにおいて、
前記導電性材料がインジウムスズ酸化物(ITO)であることを特徴とする縦型電界効果トランジスタ。 - 請求項1に記載の縦型電界効果トランジスタにおいて、
前記第1の電極、多孔質導電層および第2の電極の各々に結合された電気接続部をさらに備えることを特徴とする縦型電界効果トランジスタ。 - 請求項1に記載の縦型電界効果トランジスタにおいて、
前記電荷輸送層がフラーレンを含むことを特徴とする縦型電界効果トランジスタ。 - 請求項1に記載の縦型電界効果トランジスタにおいて、
前記誘電体層と前記第1の電極との間に光活性層をさらに備えることを特徴とする縦型電界効果トランジスタ。 - 請求項8に記載の縦型電界効果トランジスタにおいて、
前記光活性層が、硫化鉛、硫化銀およびセレン化銀のうちの1またはそれ以上を含むことを特徴とする縦型電界効果トランジスタ。 - 請求項8に記載の縦型電界効果トランジスタにおいて、
前記光活性層がナノ結晶を含むことを特徴とする縦型電界効果トランジスタ。 - 請求項8に記載の縦型電界効果トランジスタにおいて、
前記光活性層と電極との間に正孔ブロック層をさらに備え、前記電極が前記多孔質導電層に電気的に接続されていることを特徴とする縦型電界効果トランジスタ。 - 請求項11に記載の縦型電界効果トランジスタにおいて、
前記正孔ブロック層が、二酸化チタン、酸化亜鉛および硫化亜鉛のうちの1またはそれ以上を含むことを特徴とする縦型電界効果トランジスタ。 - 請求項11に記載の縦型電界効果トランジスタにおいて、
前記正孔ブロック層がナノ結晶を含むことを特徴とする縦型電界効果トランジスタ。 - 請求項1に記載の縦型電界効果トランジスタにおいて、
前記誘電体層がhigh−κ誘電体を含むことを特徴とする縦型電界効果トランジスタ。 - 請求項14に記載の縦型電界効果トランジスタにおいて、
前記誘電体層が酸化ハフニウムを含むことを特徴とする縦型電界効果トランジスタ。 - 請求項1に記載の縦型電界効果トランジスタにおいて、
前記電荷輸送層が、前記多孔質導電層の仕事関数よりも高い仕事関数を有することを特徴とする縦型電界効果トランジスタ。 - 縦型電界効果トランジスタの製造方法であって、
誘電体層を形成するステップと、
前記誘電体層上に導電層を堆積させるステップとを備え、
前記導電層が当該導電層を貫通して延びる複数の孔を含むように、前記誘電体層の1またはそれ以上の領域が堆積中にマスクされることを特徴とする方法。 - 請求項17に記載の方法において、
前記孔の各々が0.1μm〜10μmの直径を有することを特徴とする方法。 - 請求項17に記載の方法において、
前記導電層がスパッタリングにより形成されることを特徴とする方法。 - 縦型電界効果トランジスタを動作させる方法において、
前記縦型電界効果トランジスタが、第1の電極と、誘電体層と、多孔質導電層と、前記多孔質導電層と接触する電荷輸送層と、第2の電極とを備え、前記誘電体層が前記第1の電極と前記多孔質導電層との間に配置され、前記電荷輸送層が前記多孔質導電層と前記第2の電極との間に配置されており、
当該方法が、
前記多孔質導電層から前記第1の電極に第1のバイアス電圧を印加するステップと、
前記多孔質導電層から前記第2の電極に第2のバイアス電圧を印加するステップとを備え、前記第2のバイアス電圧の符号が、前記第1のバイアス電圧の符号と反対であり、
前記第1の電極に注入された正孔が、前記電荷輸送層に自由電子を1000%を超える変換効率で生成することを特徴とすることを特徴とする方法。
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EP3347915A4 (en) | 2019-05-08 |
WO2017044800A1 (en) | 2017-03-16 |
EP3347915A1 (en) | 2018-07-18 |
CA2996892A1 (en) | 2017-03-16 |
US10651407B2 (en) | 2020-05-12 |
KR20180050732A (ko) | 2018-05-15 |
US20180254419A1 (en) | 2018-09-06 |
CN108496240A (zh) | 2018-09-04 |
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