JP2018523876A5 - - Google Patents

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Publication number
JP2018523876A5
JP2018523876A5 JP2018505701A JP2018505701A JP2018523876A5 JP 2018523876 A5 JP2018523876 A5 JP 2018523876A5 JP 2018505701 A JP2018505701 A JP 2018505701A JP 2018505701 A JP2018505701 A JP 2018505701A JP 2018523876 A5 JP2018523876 A5 JP 2018523876A5
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JP
Japan
Prior art keywords
secure
memory
gpu
resource descriptor
resources
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Ceased
Application number
JP2018505701A
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English (en)
Japanese (ja)
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JP2018523876A (ja
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Publication date
Priority claimed from US14/821,174 external-priority patent/US10102391B2/en
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Publication of JP2018523876A publication Critical patent/JP2018523876A/ja
Publication of JP2018523876A5 publication Critical patent/JP2018523876A5/ja
Ceased legal-status Critical Current

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JP2018505701A 2015-08-07 2016-07-25 グラフィックス処理ユニットのためのハードウェア強制コンテンツ保護 Ceased JP2018523876A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/821,174 2015-08-07
US14/821,174 US10102391B2 (en) 2015-08-07 2015-08-07 Hardware enforced content protection for graphics processing units
PCT/US2016/043903 WO2017027196A1 (en) 2015-08-07 2016-07-25 Hardware enforced content protection for graphics processing units

Publications (2)

Publication Number Publication Date
JP2018523876A JP2018523876A (ja) 2018-08-23
JP2018523876A5 true JP2018523876A5 (cg-RX-API-DMAC7.html) 2019-01-24

Family

ID=56609956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018505701A Ceased JP2018523876A (ja) 2015-08-07 2016-07-25 グラフィックス処理ユニットのためのハードウェア強制コンテンツ保護

Country Status (7)

Country Link
US (1) US10102391B2 (cg-RX-API-DMAC7.html)
EP (1) EP3332346B1 (cg-RX-API-DMAC7.html)
JP (1) JP2018523876A (cg-RX-API-DMAC7.html)
KR (1) KR20180036970A (cg-RX-API-DMAC7.html)
CN (1) CN107851138A (cg-RX-API-DMAC7.html)
BR (1) BR112018002466A2 (cg-RX-API-DMAC7.html)
WO (1) WO2017027196A1 (cg-RX-API-DMAC7.html)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3050847B1 (fr) * 2016-05-02 2019-04-05 Morpho Procede d'optimisation d'ecritures en memoire dans un dispositif
US10380039B2 (en) * 2017-04-07 2019-08-13 Intel Corporation Apparatus and method for memory management in a graphics processing environment
KR102569086B1 (ko) * 2017-11-20 2023-08-22 상하이 캠브리콘 인포메이션 테크놀로지 컴퍼니 리미티드 태스크 병렬 처리 방법, 장치, 시스템, 기억 매체 및 컴퓨터 기기
CN113168380B (zh) * 2019-01-29 2022-09-09 华为技术有限公司 电子设备和地址访问方法
WO2020252791A1 (zh) 2019-06-21 2020-12-24 华为技术有限公司 一种集成芯片及数据处理方法
CN110706147B (zh) * 2019-09-29 2023-08-11 阿波罗智联(北京)科技有限公司 图像处理的环境确定方法、装置、电子设备和存储介质
US11379135B2 (en) * 2020-08-04 2022-07-05 Honeywell International Inc. Memory protection unit
CN113344764B (zh) * 2021-05-11 2024-04-19 中天恒星(上海)科技有限公司 安全图形处理器、处理器芯片、显示卡、装置、方法及存储介质
US20230153146A1 (en) * 2021-11-12 2023-05-18 Nvidia Corporation Direct user mode work submission in secure computing enabled processors
CN114995912A (zh) * 2022-06-09 2022-09-02 江苏安超云软件有限公司 支持gpu多模式运行的方法和装置、电子设备和存储介质

Family Cites Families (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4184201A (en) 1978-04-26 1980-01-15 Sperry Rand Corporation Integrating processor element
US6986052B1 (en) 2000-06-30 2006-01-10 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US7055038B2 (en) 2001-05-07 2006-05-30 Ati International Srl Method and apparatus for maintaining secure and nonsecure data in a shared memory system
US7065651B2 (en) 2002-01-16 2006-06-20 Microsoft Corporation Secure video card methods and systems
JP4762494B2 (ja) 2002-04-18 2011-08-31 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド セキュア実行モードを実行可能なcpuおよび高信頼(セキュア)通信路を介して接続されたセキュリティサービスプロセッサを含むコンピュータシステム
AU2003221972A1 (en) 2002-04-18 2003-11-03 Advanced Micro Devices, Inc. Initialization of a computer system including a secure execution mode-capable processor
KR20040000348A (ko) 2002-06-24 2004-01-03 마이크로소프트 코포레이션 비디오 카드 출력을 보호하기 위한 시스템 및 방법
GB0226906D0 (en) * 2002-11-18 2002-12-24 Advanced Risc Mach Ltd Virtual to physical memory address mapping within a system having a secure domain and a non-secure domain
RU2005115083A (ru) 2002-11-18 2006-01-20 Арм Лимитед (Gb) Переключение процессора между защищенным и незащищенным режимами
US7474312B1 (en) 2002-11-25 2009-01-06 Nvidia Corporation Memory redirect primitive for a secure graphics processing unit
US7444523B2 (en) 2004-08-27 2008-10-28 Microsoft Corporation System and method for using address bits to signal security attributes of data in the address space
US7502928B2 (en) * 2004-11-12 2009-03-10 Sony Computer Entertainment Inc. Methods and apparatus for secure data processing and transmission
US7782329B2 (en) 2004-12-10 2010-08-24 Rockwell Collins, Inc. Method and apparatus for protected graphics generation
US8473750B2 (en) 2004-12-15 2013-06-25 Nvidia Corporation Chipset security offload engine
GB0427973D0 (en) 2004-12-21 2005-01-26 Falanx Microsystems As Microprocessor systems
KR100893980B1 (ko) 2005-12-14 2009-04-20 엔비디아 코포레이션 칩세트 보안 오프로드 엔진
US7610464B2 (en) 2006-02-22 2009-10-27 Sony Computer Entertainment Inc. Methods and apparatus for providing independent logical address space and access management
WO2007135672A2 (en) 2006-05-24 2007-11-29 Safend Ltd. Method and system for defending security application in a user's computer
US20080077793A1 (en) 2006-09-21 2008-03-27 Sensory Networks, Inc. Apparatus and method for high throughput network security systems
US7809934B2 (en) 2006-10-13 2010-10-05 Texas Instruments Incorporated Security measures for preventing attacks that use test mechanisms
US7681077B1 (en) * 2006-11-03 2010-03-16 Nvidia Corporation Graphics system with reduced shadowed state memory requirements
US20090079746A1 (en) 2007-09-20 2009-03-26 Apple Inc. Switching between graphics sources to facilitate power management and/or security
US8478959B1 (en) 2007-11-13 2013-07-02 Nvidia Corporation Method and system for protecting content in graphics memory
US20090150631A1 (en) 2007-12-06 2009-06-11 Clifton Labs, Inc. Self-protecting storage device
US8156565B2 (en) 2008-04-28 2012-04-10 Microsoft Corporation Hardware-based protection of secure data
US8393008B2 (en) 2008-05-21 2013-03-05 Microsoft Corporation Hardware-based output protection of multiple video streams
US8578483B2 (en) 2008-07-31 2013-11-05 Carnegie Mellon University Systems and methods for preventing unauthorized modification of an operating system
US8243088B2 (en) 2009-02-26 2012-08-14 Presagis Two dimensional memory access controller
EP2515239B1 (en) 2009-12-14 2017-03-29 Panasonic Intellectual Property Management Co., Ltd. Information processing apparatus
US8869144B2 (en) 2009-12-14 2014-10-21 Citrix Systems, Inc. Managing forwarding of input events in a virtualization environment to prevent keylogging attacks
US8296538B2 (en) 2010-02-17 2012-10-23 Arm Limited Storing secure mode page table data in secure and non-secure regions of memory
US20110202740A1 (en) * 2010-02-17 2011-08-18 Arm Limited Storing secure page table data in secure and non-secure regions of memory
JP5485055B2 (ja) 2010-07-16 2014-05-07 パナソニック株式会社 共有メモリシステム及びその制御方法
US20120036308A1 (en) * 2010-08-06 2012-02-09 Swanson Robert C Supporting a secure readable memory region for pre-boot and secure mode operations
GB2482700A (en) 2010-08-11 2012-02-15 Advanced Risc Mach Ltd Memory access control
US20120079270A1 (en) 2010-09-29 2012-03-29 Navin Patel Hardware-Assisted Content Protection for Graphics Processor
CN101950262B (zh) * 2010-10-20 2011-09-28 深圳市开立科技有限公司 在嵌入式系统中实现安全模式的方法及装置
GB2484717B (en) 2010-10-21 2018-06-13 Advanced Risc Mach Ltd Security provision for a subject image displayed in a non-secure domain
EP2689368A4 (en) * 2011-03-22 2014-08-20 Ericsson Telefon Ab L M METHOD FOR EXECUTING SWITCHING BETWEEN OPERATION IN VIRTUALIZED SYSTEM AND OPERATION IN NON-VIRTUALIZED SYSTEM
US8943330B2 (en) * 2011-05-10 2015-01-27 Qualcomm Incorporated Apparatus and method for hardware-based secure data processing using buffer memory address range rules
US9086989B2 (en) 2011-07-01 2015-07-21 Synopsys, Inc. Extending processor MMU for shared address spaces
US8631212B2 (en) * 2011-09-25 2014-01-14 Advanced Micro Devices, Inc. Input/output memory management unit with protection mode for preventing memory access by I/O devices
JP5664530B2 (ja) 2011-11-17 2015-02-04 トヨタ自動車株式会社 制御装置およびメモリ保護装置の動作確認方法
US20130166922A1 (en) * 2011-12-23 2013-06-27 Ati Technologies Ulc Method and system for frame buffer protection
GB2501274B (en) 2012-04-17 2020-05-13 Advanced Risc Mach Ltd Management of data processing security in a secondary processor
US20130305388A1 (en) 2012-05-10 2013-11-14 Qualcomm Incorporated Link status based content protection buffers
WO2014028663A2 (en) * 2012-08-15 2014-02-20 Synopsys, Inc. Protection scheme for embedded code
US9633230B2 (en) 2012-10-11 2017-04-25 Intel Corporation Hardware assist for privilege access violation checks
US8931108B2 (en) 2013-02-18 2015-01-06 Qualcomm Incorporated Hardware enforced content protection for graphics processing units
US9245129B2 (en) * 2013-03-15 2016-01-26 Nvidia Corporation System and method for protecting data by returning a protect signal with the data
JP6067449B2 (ja) 2013-03-26 2017-01-25 株式会社東芝 情報処理装置、情報処理プログラム
US9507961B2 (en) 2013-07-01 2016-11-29 Qualcomm Incorporated System and method for providing secure access control to a graphics processing unit
US9672162B2 (en) * 2013-08-16 2017-06-06 Arm Limited Data processing systems
US9483653B2 (en) 2014-10-29 2016-11-01 Square, Inc. Secure display element
US9767320B2 (en) 2015-08-07 2017-09-19 Qualcomm Incorporated Hardware enforced content protection for graphics processing units

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