JP2018517987A - ５０ナノ秒スパイクフィルタ用のテスト - Google Patents

５０ナノ秒スパイクフィルタ用のテスト Download PDF

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Publication number
JP2018517987A
JP2018517987A JP2017564614A JP2017564614A JP2018517987A JP 2018517987 A JP2018517987 A JP 2018517987A JP 2017564614 A JP2017564614 A JP 2017564614A JP 2017564614 A JP2017564614 A JP 2017564614A JP 2018517987 A JP2018517987 A JP 2018517987A
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Japan
Prior art keywords
pulses
command
slave device
serial bus
sequence
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Ceased
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JP2017564614A
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English (en)
Japanese (ja)
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JP2018517987A5 (enExample
Inventor
ラドゥ・ピティゴイ−アロン
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クアルコム，インコーポレイテッド
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Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2018517987A publication Critical patent/JP2018517987A/ja
Publication of JP2018517987A5 publication Critical patent/JP2018517987A5/ja
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Dc Digital Transmission (AREA)
JP2017564614A 2015-06-15 2016-06-13 ５０ナノ秒スパイクフィルタ用のテスト Ceased JP2018517987A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562175723P 2015-06-15 2015-06-15
US62/175,723 2015-06-15
US15/179,470 US10108511B2 (en) 2015-06-15 2016-06-10 Test for 50 nanosecond spike filter
US15/179,470 2016-06-10
PCT/US2016/037282 WO2016205142A1 (en) 2015-06-15 2016-06-13 Test for 50 nanosecond spike filter

Publications (2)

Publication Number Publication Date
JP2018517987A true JP2018517987A (ja) 2018-07-05
JP2018517987A5 JP2018517987A5 (enExample) 2019-06-20

Family

ID=57517150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017564614A Ceased JP2018517987A (ja) 2015-06-15 2016-06-13 ５０ナノ秒スパイクフィルタ用のテスト

Country Status (6)

Country Link
US (1) US10108511B2 (enExample)
EP (1) EP3308284A1 (enExample)
JP (1) JP2018517987A (enExample)
KR (1) KR20180017035A (enExample)
CN (1) CN107710183A (enExample)
WO (1) WO2016205142A1 (enExample)

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US9710423B2 (en) * 2014-04-02 2017-07-18 Qualcomm Incorporated Methods to send extra information in-band on inter-integrated circuit (I2C) bus
US10938782B1 (en) * 2016-12-27 2021-03-02 Amazon Technologies, Inc. Secure hardware signal filtering
US10423551B2 (en) 2017-09-07 2019-09-24 Qualcomm Incorporated Ultra-short RFFE datagrams for latency sensitive radio frequency front-end
US10693674B2 (en) * 2018-01-29 2020-06-23 Qualcomm Incorporated In-datagram critical-signaling using pulse-count-modulation for I3C bus
CN110362524B (zh) * 2018-04-11 2021-04-09 杭州海康威视数字技术股份有限公司 时序信号生成方法、装置、逻辑电路板及存储介质
CN109101380B (zh) * 2018-07-27 2022-05-13 广东浪潮大数据研究有限公司 一种i2c信号质量的检测方法及设备
US11119966B2 (en) * 2018-09-07 2021-09-14 Qualcomm Incorporated Mixed-mode radio frequency front-end interface
US11338586B2 (en) 2018-12-03 2022-05-24 Hewlett-Packard Development Company, L.P. Logic circuitry
EP3682359B1 (en) 2018-12-03 2021-01-06 Hewlett-Packard Development Company, L.P. Logic circuitry
US10894423B2 (en) 2018-12-03 2021-01-19 Hewlett-Packard Development Company, L.P. Logic circuitry
CN111527483A (zh) 2018-12-03 2020-08-11 惠普发展公司，有限责任合伙企业 逻辑电路
CA3121146C (en) * 2018-12-03 2024-05-28 Hewlett-Packard Development Company, L.P. Logic circuitry package for controlling ic2 traffic
WO2020117303A1 (en) 2018-12-03 2020-06-11 Hewlett-Packard Development Company, L.P. Logic circuitry
CN113165389A (zh) 2018-12-03 2021-07-23 惠普发展公司，有限责任合伙企业 逻辑电路系统封装
EP3687820B1 (en) 2018-12-03 2022-03-23 Hewlett-Packard Development Company, L.P. Logic circuitry
EP3695334A1 (en) 2018-12-03 2020-08-19 Hewlett Packard Enterprise Development Company LP Logic circuitry
MX2021005988A (es) 2018-12-03 2021-07-06 Hewlett Packard Development Co Conjunto de circuitos logicos.
EP3681723B1 (en) 2018-12-03 2021-07-28 Hewlett-Packard Development Company, L.P. Logic circuitry
US10606794B1 (en) * 2019-05-14 2020-03-31 Infineon Technologies Ag Clock signal monitor for slave device on a master-slave bus
US11327912B2 (en) * 2019-09-12 2022-05-10 Qualcomm Incorporated Controlling the application time of radio frequency front end triggers based on execution of sequences
EP3844000B1 (en) 2019-10-25 2023-04-12 Hewlett-Packard Development Company, L.P. Logic circuitry package
CN113312217A (zh) * 2020-02-26 2021-08-27 瑞昱半导体股份有限公司 内部集成电路总线的从属装置的测试方法
EP4031997A1 (en) 2020-04-30 2022-07-27 Hewlett-Packard Development Company, L.P. Logic circuitry package for print apparatus
JP2024537639A (ja) * 2021-09-08 2024-10-16 パッシブロジック，インコーポレイテッド 静止デバイス（ｑｕｉｅｓｃｅｎｔ ｄｅｖｉｃｅ）の外部始動

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JPS6037059A (ja) * 1983-08-10 1985-02-26 Canon Inc コンピユ−タ端末結合方式
US20080034134A1 (en) * 2006-04-28 2008-02-07 Stmicroelectronics Pvt. Ltd. Configurable i2c interface
JP2014216738A (ja) * 2013-04-24 2014-11-17 セイコーエプソン株式会社 通信回路、物理量測定装置、電子機器、移動体、通信方法

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US5956372A (en) * 1994-03-17 1999-09-21 Digital Compression Technology, L.P. Coding system for digital transmission compression
US5469476A (en) * 1994-03-21 1995-11-21 Motorola, Inc. Circuit and method for filtering voltage spikes
US7313740B2 (en) * 2002-07-25 2007-12-25 Inapac Technology, Inc. Internally generating patterns for testing in an integrated circuit device
US7606955B1 (en) 2003-09-15 2009-10-20 National Semiconductor Corporation Single wire bus for connecting devices and methods of operating the same
US7394260B2 (en) * 2006-05-24 2008-07-01 Sun Microsystems, Inc. Tuning a test trace configured for capacitive coupling to signal traces
US8010724B2 (en) * 2009-10-06 2011-08-30 Maxim Integrated Products, Inc. 12C/SMBus ladders and ladder enabled ICs
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WO2015017452A1 (en) * 2013-07-29 2015-02-05 Wispry,Inc. Adaptive filter response systems and methods

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
JPS6037059A (ja) * 1983-08-10 1985-02-26 Canon Inc コンピユ−タ端末結合方式
US20080034134A1 (en) * 2006-04-28 2008-02-07 Stmicroelectronics Pvt. Ltd. Configurable i2c interface
JP2014216738A (ja) * 2013-04-24 2014-11-17 セイコーエプソン株式会社 通信回路、物理量測定装置、電子機器、移動体、通信方法

Also Published As

Publication number Publication date
CN107710183A (zh) 2018-02-16
EP3308284A1 (en) 2018-04-18
US20160364305A1 (en) 2016-12-15
KR20180017035A (ko) 2018-02-20
WO2016205142A1 (en) 2016-12-22
US10108511B2 (en) 2018-10-23

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