CN107710183A - 针对50纳秒尖峰滤波器的测试 - Google Patents

针对50纳秒尖峰滤波器的测试 Download PDF

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Publication number
CN107710183A
CN107710183A CN201680034080.XA CN201680034080A CN107710183A CN 107710183 A CN107710183 A CN 107710183A CN 201680034080 A CN201680034080 A CN 201680034080A CN 107710183 A CN107710183 A CN 107710183A
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CN
China
Prior art keywords
slave unit
order
universal serial
serial bus
pulse train
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201680034080.XA
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English (en)
Chinese (zh)
Inventor
R·皮提果-艾伦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
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Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN107710183A publication Critical patent/CN107710183A/zh
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Dc Digital Transmission (AREA)
CN201680034080.XA 2015-06-15 2016-06-13 针对50纳秒尖峰滤波器的测试 Pending CN107710183A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562175723P 2015-06-15 2015-06-15
US62/175,723 2015-06-15
US15/179,470 US10108511B2 (en) 2015-06-15 2016-06-10 Test for 50 nanosecond spike filter
US15/179,470 2016-06-10
PCT/US2016/037282 WO2016205142A1 (en) 2015-06-15 2016-06-13 Test for 50 nanosecond spike filter

Publications (1)

Publication Number Publication Date
CN107710183A true CN107710183A (zh) 2018-02-16

Family

ID=57517150

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201680034080.XA Pending CN107710183A (zh) 2015-06-15 2016-06-13 针对50纳秒尖峰滤波器的测试

Country Status (6)

Country Link
US (1) US10108511B2 (enExample)
EP (1) EP3308284A1 (enExample)
JP (1) JP2018517987A (enExample)
KR (1) KR20180017035A (enExample)
CN (1) CN107710183A (enExample)
WO (1) WO2016205142A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110362524A (zh) * 2018-04-11 2019-10-22 杭州海康威视数字技术股份有限公司 时序信号生成方法、装置、逻辑电路板及存储介质
CN111949593A (zh) * 2019-05-14 2020-11-17 英飞凌科技股份有限公司 用于主从总线上的从设备的时钟信号监测器
CN112639756A (zh) * 2018-09-07 2021-04-09 高通股份有限公司 混合模式射频前端接口
CN114375446A (zh) * 2019-09-12 2022-04-19 高通股份有限公司 基于序列的执行来控制射频前端触发的应用时间

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9710423B2 (en) * 2014-04-02 2017-07-18 Qualcomm Incorporated Methods to send extra information in-band on inter-integrated circuit (I2C) bus
US10938782B1 (en) * 2016-12-27 2021-03-02 Amazon Technologies, Inc. Secure hardware signal filtering
US10423551B2 (en) 2017-09-07 2019-09-24 Qualcomm Incorporated Ultra-short RFFE datagrams for latency sensitive radio frequency front-end
US10693674B2 (en) * 2018-01-29 2020-06-23 Qualcomm Incorporated In-datagram critical-signaling using pulse-count-modulation for I3C bus
CN109101380B (zh) * 2018-07-27 2022-05-13 广东浪潮大数据研究有限公司 一种i2c信号质量的检测方法及设备
KR20210087982A (ko) 2018-12-03 2021-07-13 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 로직 회로
AU2018452006B2 (en) 2018-12-03 2022-12-01 Hewlett-Packard Development Company, L.P. Logic circuitry
US11338586B2 (en) 2018-12-03 2022-05-24 Hewlett-Packard Development Company, L.P. Logic circuitry
AU2018451721B2 (en) 2018-12-03 2023-05-18 Hewlett-Packard Development Company, L.P. Logic circuitry
CA3121418A1 (en) 2018-12-03 2020-06-11 Hewlett-Packard Development Company, L.P. Logic circuitry
US10894423B2 (en) 2018-12-03 2021-01-19 Hewlett-Packard Development Company, L.P. Logic circuitry
US20210216491A1 (en) 2018-12-03 2021-07-15 Hewlett-Packard Development Company, L.P. Logic Circuitry
MX2021005993A (es) 2018-12-03 2021-07-06 Hewlett Packard Development Co Conjunto de circuitos logicos.
HUE063370T2 (hu) * 2018-12-03 2024-01-28 Hewlett Packard Development Co Logikai áramkör
ES2902154T3 (es) 2018-12-03 2022-03-25 Hewlett Packard Development Co Circuitos lógicos
EP3688639B1 (en) 2018-12-03 2021-10-13 Hewlett-Packard Development Company, L.P. Logic circuitry package
US11407229B2 (en) 2019-10-25 2022-08-09 Hewlett-Packard Development Company, L.P. Logic circuitry package
CN113312217A (zh) * 2020-02-26 2021-08-27 瑞昱半导体股份有限公司 内部集成电路总线的从属装置的测试方法
WO2021221678A1 (en) 2020-04-30 2021-11-04 Hewlett-Packard Development Company, L.P. Logic circuitry package for print apparatus
JP2024537639A (ja) * 2021-09-08 2024-10-16 パッシブロジック，インコーポレイテッド 静止デバイス（ｑｕｉｅｓｃｅｎｔ ｄｅｖｉｃｅ）の外部始動

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5469476A (en) * 1994-03-21 1995-11-21 Motorola, Inc. Circuit and method for filtering voltage spikes
CN101163977A (zh) * 2005-03-18 2008-04-16 英沛科技公司 集成电路测试模块
US7606955B1 (en) * 2003-09-15 2009-10-20 National Semiconductor Corporation Single wire bus for connecting devices and methods of operating the same
CN102033837A (zh) * 2009-10-06 2011-04-27 马克西姆综合产品公司 I2c/smbus阶梯以及阶梯使能的ic
US20140149616A1 (en) * 2012-11-27 2014-05-29 Hon Hai Precision Industry Co., Ltd. I2c bus structure and address management method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6037059A (ja) * 1983-08-10 1985-02-26 Canon Inc コンピユ−タ端末結合方式
US5956372A (en) * 1994-03-17 1999-09-21 Digital Compression Technology, L.P. Coding system for digital transmission compression
US7514962B2 (en) * 2006-04-28 2009-04-07 Stmicroelectronics Pvt. Ltd. Configurable I2C interface
US7394260B2 (en) * 2006-05-24 2008-07-01 Sun Microsystems, Inc. Tuning a test trace configured for capacitive coupling to signal traces
JP6232733B2 (ja) * 2013-04-24 2017-11-22 セイコーエプソン株式会社 通信回路、物理量測定装置、電子機器、移動体、通信方法
WO2015017452A1 (en) * 2013-07-29 2015-02-05 Wispry,Inc. Adaptive filter response systems and methods

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5469476A (en) * 1994-03-21 1995-11-21 Motorola, Inc. Circuit and method for filtering voltage spikes
US7606955B1 (en) * 2003-09-15 2009-10-20 National Semiconductor Corporation Single wire bus for connecting devices and methods of operating the same
CN101163977A (zh) * 2005-03-18 2008-04-16 英沛科技公司 集成电路测试模块
CN102033837A (zh) * 2009-10-06 2011-04-27 马克西姆综合产品公司 I2c/smbus阶梯以及阶梯使能的ic
US20140149616A1 (en) * 2012-11-27 2014-05-29 Hon Hai Precision Industry Co., Ltd. I2c bus structure and address management method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110362524A (zh) * 2018-04-11 2019-10-22 杭州海康威视数字技术股份有限公司 时序信号生成方法、装置、逻辑电路板及存储介质
CN110362524B (zh) * 2018-04-11 2021-04-09 杭州海康威视数字技术股份有限公司 时序信号生成方法、装置、逻辑电路板及存储介质
CN112639756A (zh) * 2018-09-07 2021-04-09 高通股份有限公司 混合模式射频前端接口
CN112639756B (zh) * 2018-09-07 2024-02-09 高通股份有限公司 混合模式射频前端接口
CN111949593A (zh) * 2019-05-14 2020-11-17 英飞凌科技股份有限公司 用于主从总线上的从设备的时钟信号监测器
CN114375446A (zh) * 2019-09-12 2022-04-19 高通股份有限公司 基于序列的执行来控制射频前端触发的应用时间

Also Published As

Publication number Publication date
JP2018517987A (ja) 2018-07-05
US10108511B2 (en) 2018-10-23
US20160364305A1 (en) 2016-12-15
KR20180017035A (ko) 2018-02-20
EP3308284A1 (en) 2018-04-18
WO2016205142A1 (en) 2016-12-22

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