JP2018511180A - コバルト相互接続層及びその上のはんだを備えた金属ボンドパッド - Google Patents

コバルト相互接続層及びその上のはんだを備えた金属ボンドパッド Download PDF

Info

Publication number
JP2018511180A
JP2018511180A JP2017550148A JP2017550148A JP2018511180A JP 2018511180 A JP2018511180 A JP 2018511180A JP 2017550148 A JP2017550148 A JP 2017550148A JP 2017550148 A JP2017550148 A JP 2017550148A JP 2018511180 A JP2018511180 A JP 2018511180A
Authority
JP
Japan
Prior art keywords
cobalt
bond pad
layer
metal
connection layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017550148A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018511180A5 (https=
Inventor
リンク ヘルムート
リンク ヘルムート
バウアー ゲーノット
バウアー ゲーノット
ツリレ ロベルト
ツリレ ロベルト
シャハトシュナイダー カイアレクサンダー
シャハトシュナイダー カイアレクサンダー
オーテ ミカエル
オーテ ミカエル
ウィーズナー ハールド
ウィーズナー ハールド
Original Assignee
日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本テキサス・インスツルメンツ株式会社, テキサス インスツルメンツ インコーポレイテッド, テキサス インスツルメンツ インコーポレイテッド filed Critical 日本テキサス・インスツルメンツ株式会社
Publication of JP2018511180A publication Critical patent/JP2018511180A/ja
Publication of JP2018511180A5 publication Critical patent/JP2018511180A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42Vias, e.g. via plugs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44Conductive materials thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01204Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251Changing the shapes of bumps
    • H10W72/01257Changing the shapes of bumps by reflowing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01931Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01938Manufacture or treatment of bond pads using blanket deposition in gaseous form, e.g. by CVD or PVD
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01951Changing the shapes of bond pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01951Changing the shapes of bond pads
    • H10W72/01953Changing the shapes of bond pads by etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/0198Manufacture or treatment batch processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231Shapes
    • H10W72/232Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231Shapes
    • H10W72/234Cross-sectional shape, i.e. in side view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241Dispositions, e.g. layouts
    • H10W72/242Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • H10W72/252Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/923Bond pads having multiple stacked layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/934Cross-sectional shape, i.e. in side view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2017550148A 2015-03-23 2016-03-23 コバルト相互接続層及びその上のはんだを備えた金属ボンドパッド Pending JP2018511180A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/665,799 US9960135B2 (en) 2015-03-23 2015-03-23 Metal bond pad with cobalt interconnect layer and solder thereon
US14/665,799 2015-03-23
PCT/US2016/023785 WO2016154315A1 (en) 2015-03-23 2016-03-23 Metal bond pad with cobalt interconnect layer and solder thereon

Publications (2)

Publication Number Publication Date
JP2018511180A true JP2018511180A (ja) 2018-04-19
JP2018511180A5 JP2018511180A5 (https=) 2019-04-04

Family

ID=56975786

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017550148A Pending JP2018511180A (ja) 2015-03-23 2016-03-23 コバルト相互接続層及びその上のはんだを備えた金属ボンドパッド

Country Status (5)

Country Link
US (2) US9960135B2 (https=)
EP (1) EP3275009A4 (https=)
JP (1) JP2018511180A (https=)
CN (1) CN107431000A (https=)
WO (1) WO2016154315A1 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9971970B1 (en) * 2015-04-27 2018-05-15 Rigetti & Co, Inc. Microwave integrated quantum circuits with VIAS and methods for making the same
US10160639B2 (en) 2016-06-27 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure for MEMS Device
US10131541B2 (en) 2016-07-21 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. MEMS devices having tethering structures
US11121301B1 (en) 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture
US11183472B2 (en) * 2017-11-28 2021-11-23 Sony Semiconductor Solutions Corporation Semiconductor device and manufacturing method of semiconductor device for improving solder connection strength
US10546852B2 (en) * 2018-05-03 2020-01-28 Qualcomm Incorporated Integrated semiconductor devices and method of fabricating the same
US10840185B2 (en) 2019-03-05 2020-11-17 Texas Instruments Incorporated Semiconductor device with vias having a zinc-second metal-copper composite layer
US12607594B2 (en) 2020-09-03 2026-04-21 Texas Instruments Incorporated ISFET biosensor
CN114765125B (zh) * 2021-01-12 2025-11-25 联华电子股份有限公司 集成电路结构及其制作方法
US11676920B2 (en) 2021-01-26 2023-06-13 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US20230187390A1 (en) * 2021-12-15 2023-06-15 Texas Instruments Incorporated Semiconductor die with dissolvable metal layer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040096592A1 (en) * 2002-11-19 2004-05-20 Chebiam Ramanan V. Electroless cobalt plating solution and plating techniques
US20070023919A1 (en) * 2005-07-29 2007-02-01 Mou-Shiung Lin Bonding pad on ic substrate and method for making the same
US20090174069A1 (en) * 2008-01-04 2009-07-09 National Semiconductor Corporation I/o pad structure for enhancing solder joint reliability in integrated circuit devices
US20090283903A1 (en) * 2005-12-02 2009-11-19 Nepes Corporation Bump with multiple vias for semiconductor package and fabrication method thereof, and semiconductor package utilizing the same

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5260234A (en) 1990-12-20 1993-11-09 Vlsi Technology, Inc. Method for bonding a lead to a die pad using an electroless plating solution
US5344793A (en) 1993-03-05 1994-09-06 Siemens Aktiengesellschaft Formation of silicided junctions in deep sub-micron MOSFETs by defect enhanced CoSi2 formation
US5976344A (en) * 1996-05-10 1999-11-02 Lucent Technologies Inc. Composition for electroplating palladium alloys and electroplating process using that composition
JPH11340265A (ja) * 1998-05-22 1999-12-10 Sony Corp 半導体装置及びその製造方法
US6452271B2 (en) 1998-07-31 2002-09-17 Micron Technology, Inc. Interconnect component for a semiconductor die including a ruthenium layer and a method for its fabrication
US6534192B1 (en) * 1999-09-24 2003-03-18 Lucent Technologies Inc. Multi-purpose finish for printed wiring boards and method of manufacture of such boards
DE10231385B4 (de) * 2001-07-10 2007-02-22 Samsung Electronics Co., Ltd., Suwon Halbleiterchip mit Bondkontaktstellen und zugehörige Mehrchippackung
US7064446B2 (en) * 2004-03-29 2006-06-20 Intel Corporation Under bump metallization layer to enable use of high tin content solder bumps
US7410833B2 (en) * 2004-03-31 2008-08-12 International Business Machines Corporation Interconnections for flip-chip using lead-free solders and having reaction barrier layers
US8399989B2 (en) * 2005-07-29 2013-03-19 Megica Corporation Metal pad or metal bump over pad exposed by passivation layer
US8771804B2 (en) * 2005-08-31 2014-07-08 Lam Research Corporation Processes and systems for engineering a copper surface for selective metal deposition
US20070158199A1 (en) * 2005-12-30 2007-07-12 Haight Scott M Method to modulate the surface roughness of a plated deposit and create fine-grained flat bumps
US8367543B2 (en) * 2006-03-21 2013-02-05 International Business Machines Corporation Structure and method to improve current-carrying capabilities of C4 joints
US7752996B2 (en) * 2006-05-11 2010-07-13 Lam Research Corporation Apparatus for applying a plating solution for electroless deposition
US20080003803A1 (en) 2006-06-30 2008-01-03 Pei-Haw Tsao Semiconductor package substrate for flip chip packaging
US7498646B2 (en) * 2006-07-19 2009-03-03 Advanced Chip Engineering Technology Inc. Structure of image sensor module and a method for manufacturing of wafer level package
TWI370515B (en) * 2006-09-29 2012-08-11 Megica Corp Circuit component
US8158519B2 (en) 2008-10-20 2012-04-17 Eon Silicon Solution Inc. Method of manufacturing non-volatile memory cell using self-aligned metal silicide
US20100099250A1 (en) * 2008-10-21 2010-04-22 Samsung Electronics Co., Ltd. Methods of Forming Integrated Circuit Contact Pads Using Electroless Plating of Diffusion Barrier Layers
JP5457374B2 (ja) * 2009-01-29 2014-04-02 Jx日鉱日石金属株式会社 電子回路用の圧延銅箔又は電解銅箔及びこれらを用いた電子回路の形成方法
US8563396B2 (en) * 2011-01-29 2013-10-22 International Business Machines Corporation 3D integration method using SOI substrates and structures produced thereby
US9012265B2 (en) * 2012-03-26 2015-04-21 Ge Yi Magnet assisted alignment method for wafer bonding and wafer level chip scale packaging
KR101890711B1 (ko) * 2012-05-03 2018-08-22 에스케이하이닉스 주식회사 범프 버퍼 스프링패드부를 포함하는 전자 소자의 패키지 및 제조 방법
US9716035B2 (en) * 2014-06-20 2017-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Combination interconnect structure and methods of forming same
TWI550803B (zh) * 2015-02-17 2016-09-21 南茂科技股份有限公司 封裝半導體裝置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040096592A1 (en) * 2002-11-19 2004-05-20 Chebiam Ramanan V. Electroless cobalt plating solution and plating techniques
US20070023919A1 (en) * 2005-07-29 2007-02-01 Mou-Shiung Lin Bonding pad on ic substrate and method for making the same
US20090283903A1 (en) * 2005-12-02 2009-11-19 Nepes Corporation Bump with multiple vias for semiconductor package and fabrication method thereof, and semiconductor package utilizing the same
US20090174069A1 (en) * 2008-01-04 2009-07-09 National Semiconductor Corporation I/o pad structure for enhancing solder joint reliability in integrated circuit devices

Also Published As

Publication number Publication date
US20180218993A1 (en) 2018-08-02
WO2016154315A1 (en) 2016-09-29
US9960135B2 (en) 2018-05-01
CN107431000A (zh) 2017-12-01
EP3275009A4 (en) 2018-10-17
EP3275009A1 (en) 2018-01-31
US20160284656A1 (en) 2016-09-29

Similar Documents

Publication Publication Date Title
JP2018511180A (ja) コバルト相互接続層及びその上のはんだを備えた金属ボンドパッド
US8039385B1 (en) IC devices having TSVS including protruding tips having IMC blocking tip ends
US9142533B2 (en) Substrate interconnections having different sizes
TWI520243B (zh) 半導體裝置及其製造方法
US9373596B2 (en) Passivated copper chip pads
US20110227216A1 (en) Under-Bump Metallization Structure for Semiconductor Devices
CN110010594A (zh) 三维芯片堆叠件及其形成方法
US10115688B2 (en) Solder metallization stack and methods of formation thereof
TW201222752A (en) Packaging assembly, integrated circuit device and method of forming the same
CN107017170A (zh) 连接件结构及其形成方法
US9281275B2 (en) Bond pad having ruthenium directly on passivation sidewall
CN105097717A (zh) 具有位于重分布层下方的复合阻挡层的半导体结构及其制造方法
US12237219B2 (en) Contact with bronze material to mitigate undercut
US8697565B2 (en) Shallow via formation by oxidation
KR101313690B1 (ko) 반도체 소자의 본딩 구조물 형성 방법
CN113508459B (zh) 带有具有锌-第二金属-铜复合层的通孔的半导体器件

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20170925

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190221

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190221

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200205

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20200909