JP2018510505A - 薄型FLIアプリケーションのためのCu表面仕上げ上のZnドープ半田 - Google Patents
薄型FLIアプリケーションのためのCu表面仕上げ上のZnドープ半田 Download PDFInfo
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Abstract
Description
本出願は、「薄型FLIアプリケーションのためのCu表面仕上げ上のZnドープ半田」と題する、2015年4月3日に出願された米国仮特許出願第62/142,997号の利益を主張し、その全内容が参照としてあらゆる目的のために本明細書に組み込まれる。
Claims (25)
- 1つ又は複数のダイコンタクトを有する半導体ダイと、
前記1つ又は複数のダイコンタクトのうちの1つ又は複数上のリフロー済み半田バンプと
を備え、
金属間化合物(IMC)バリア層が、前記半田バンプと前記ダイコンタクトとの間の界面に形成される、
半導体デバイス。 - 前記リフロー済み半田バンプは、およそ0.6重量パーセント以上の重量百分率のZnを含む、請求項1に記載の半導体デバイス。
- Znの前記重量百分率は、およそ0.6重量パーセントから5.0重量パーセントの間である、請求項2に記載の半導体デバイス。
- Znの前記重量百分率は、およそ2.0重量パーセント以上である、請求項2または3に記載の半導体デバイス。
- 前記IMCバリア層はCuZnを含む、請求項1から4のいずれか一項に記載の半導体デバイス。
- 前記IMCバリア層はCu5Zn8を含む、請求項1から5のいずれか一項に記載の半導体デバイス。
- 前記IMCバリア層は、厚さがおよそ10μm未満である、請求項1から6のいずれか一項に記載の半導体デバイス。
- 前記IMCバリア層は、厚さがおよそ6μm未満である、請求項7に記載の半導体デバイス。
- 前記1つ又は複数のダイコンタクトは銅である、請求項1から8のいずれか一項に記載の半導体デバイス。
- 有機表面保護材(OSP)が前記1つ又は複数のダイコンタクトを覆って形成される、請求項9に記載の半導体デバイス。
- 前記1つ又は複数のダイコンタクトは、厚さが5μm未満である、請求項10に記載の半導体デバイス。
- 前記1つ又は複数のダイコンタクトは、厚さが2μm未満である、請求項11に記載の半導体デバイス。
- 前記半田バンプは、第1階層インターコネクトである、請求項1から12のいずれか一項に記載の半導体デバイス。
- 半田インターコネクトを形成する方法であって、
半導体ダイ上にダイコンタクトを形成する段階と、
前記ダイコンタクト上に半田バンプを形成する段階であって、前記半田バンプは、バリア形成元素を含むSn系の半田である、段階と、
前記半田をリフローする段階と
を備え、
前記バリア形成元素は、前記ダイコンタクトと反応して金属間化合物(IMC)バリア層を形成する、
方法。 - 前記バリア形成元素はZnであり、前記ダイコンタクトはCuを含む、請求項14に記載の方法。
- 前記IMCバリア層は、CuZn及びCu5Zn8のうちの少なくとも1つを含む、請求項15に記載の方法。
- 前記半田バンプは、Znがおよそ2重量パーセントから10重量パーセントの間である組成を含む、請求項16に記載の方法。
- 前記半田バンプはさらに、Al、Au、Ag及びCuのうちの1つ又は複数を含む、請求項17に記載の方法。
- 前記半田バンプをリフローする段階は、複数回のリフローを含む、請求項14から18のいずれか一項に記載の方法。
- 前記半田バンプをリフローする段階は、5回以上のリフローを含む、請求項19に記載の方法。
- 前記IMCバリア層は、厚さがおよそ10μm未満である、請求項14から20のいずれか一項に記載の方法。
- 前記ダイコンタクトを形成する段階は、前記ダイコンタクトをおよそ5.0μm未満の厚さに形成する段階を含む、請求項14から21のいずれか一項に記載の方法。
- 1つ又は複数のダイコンタクトを有する半導体ダイと、
前記1つ又は複数のダイコンタクトのうちの1つ又は複数上のリフロー済み半田バンプと
を備え、
前記1つ又は複数のダイコンタクトは、厚さがおよそ5μm未満であり、銅を含み、
前記リフロー済み半田バンプは、およそ2重量パーセントから10重量パーセントの間のZnを含むSn系半田であり、前記Znの一部分は、前記ダイコンタクトからの前記銅と反応して、CuZn及びCu5Zn8のうちの少なくとも1つを含む金属間化合物(IMC)バリア層を前記リフロー済み半田バンプと前記ダイコンタクトとの間の界面に形成する、
半導体デバイス。 - 前記IMCバリア層は、厚さが10μm未満であり、前記リフロー済み半田バンプは、厚さが25μm未満である、請求項23に記載の半導体デバイス。
- 前記リフロー済み半田バンプはさらに、Al、Au、Ag及びCuのうちの1つ又は複数を含む、請求項23または24に記載の半導体デバイス。
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US62/142,997 | 2015-04-03 | ||
PCT/US2016/025652 WO2016161339A1 (en) | 2015-04-03 | 2016-04-01 | Zn doped solders on cu surface finish for thin fli application |
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JP (1) | JP2018510505A (ja) |
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US20050275096A1 (en) * | 2004-06-11 | 2005-12-15 | Kejun Zeng | Pre-doped reflow interconnections for copper pads |
JP2007103462A (ja) * | 2005-09-30 | 2007-04-19 | Oki Electric Ind Co Ltd | 端子パッドと半田の接合構造、当該接合構造を有する半導体装置、およびその半導体装置の製造方法 |
US8143722B2 (en) * | 2006-10-05 | 2012-03-27 | Flipchip International, Llc | Wafer-level interconnect for high mechanical reliability applications |
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TWI359714B (en) * | 2008-11-25 | 2012-03-11 | Univ Yuan Ze | Method for inhibiting the formation of palladium-n |
US8395051B2 (en) * | 2008-12-23 | 2013-03-12 | Intel Corporation | Doping of lead-free solder alloys and structures formed thereby |
US20110303448A1 (en) * | 2010-04-23 | 2011-12-15 | Iowa State University Research Foundation, Inc. | Pb-Free Sn-Ag-Cu-Al or Sn-Cu-Al Solder |
US20120001336A1 (en) * | 2010-07-02 | 2012-01-05 | Texas Instruments Incorporated | Corrosion-resistant copper-to-aluminum bonds |
US9950393B2 (en) * | 2011-12-23 | 2018-04-24 | Intel Corporation | Hybrid low metal loading flux |
US8957323B2 (en) * | 2012-05-10 | 2015-02-17 | National Chiao Tung University | Electrical connecting element having nano-twinned copper, method of fabricating the same, and electrical connecting structure comprising the same |
US20140361070A1 (en) * | 2013-06-05 | 2014-12-11 | The Research Foundation For The State University Of New York | Solder alloys |
US20150151387A1 (en) * | 2013-12-04 | 2015-06-04 | Honeywell International Inc. | Zinc-based lead-free solder compositions |
US9646918B2 (en) * | 2014-08-14 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
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WO2016161339A1 (en) | 2016-10-06 |
CN107408517A (zh) | 2017-11-28 |
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