JP2018508871A5 - - Google Patents

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Publication number
JP2018508871A5
JP2018508871A5 JP2017537486A JP2017537486A JP2018508871A5 JP 2018508871 A5 JP2018508871 A5 JP 2018508871A5 JP 2017537486 A JP2017537486 A JP 2017537486A JP 2017537486 A JP2017537486 A JP 2017537486A JP 2018508871 A5 JP2018508871 A5 JP 2018508871A5
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JP
Japan
Prior art keywords
phy
signal
general purpose
memory
phys
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JP2017537486A
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English (en)
Japanese (ja)
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JP6710689B2 (ja
JP2018508871A (ja
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Priority claimed from US14/598,528 external-priority patent/US9324397B1/en
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Publication of JP6710689B2 publication Critical patent/JP6710689B2/ja
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JP2017537486A 2015-01-16 2016-01-07 最小限のパッケージングの複雑性で異なる外部メモリタイプをサポートするための共通のダイ Expired - Fee Related JP6710689B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/598,528 US9324397B1 (en) 2015-01-16 2015-01-16 Common die for supporting different external memory types with minimal packaging complexity
US14/598,528 2015-01-16
PCT/US2016/012511 WO2016114975A1 (en) 2015-01-16 2016-01-07 A common die for supporting different external memory types with minimal packaging complexity

Publications (3)

Publication Number Publication Date
JP2018508871A JP2018508871A (ja) 2018-03-29
JP2018508871A5 true JP2018508871A5 (https=) 2019-01-24
JP6710689B2 JP6710689B2 (ja) 2020-06-17

Family

ID=55272647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017537486A Expired - Fee Related JP6710689B2 (ja) 2015-01-16 2016-01-07 最小限のパッケージングの複雑性で異なる外部メモリタイプをサポートするための共通のダイ

Country Status (5)

Country Link
US (1) US9324397B1 (https=)
EP (1) EP3245594A1 (https=)
JP (1) JP6710689B2 (https=)
CN (1) CN107209735B (https=)
WO (1) WO2016114975A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6543129B2 (ja) 2015-07-29 2019-07-10 ルネサスエレクトロニクス株式会社 電子装置
US11468925B2 (en) 2018-12-03 2022-10-11 Rambus Inc. DRAM interface mode with improved channel integrity and efficiency at high signaling rates
US10671551B1 (en) * 2019-02-20 2020-06-02 Intel Corporation Selective data lane interface mapping
US11288222B1 (en) * 2020-09-28 2022-03-29 Xilinx, Inc. Multi-die integrated circuit with data processing engine array
KR20240157385A (ko) 2023-04-25 2024-11-01 삼성전자주식회사 메모리 장치 및 이를 포함하는 전자 장치

Family Cites Families (15)

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Publication number Priority date Publication date Assignee Title
US6460120B1 (en) * 1999-08-27 2002-10-01 International Business Machines Corporation Network processor, memory organization and methods
EP3200189B1 (en) * 2007-04-12 2021-06-02 Rambus Inc. Memory system with point-to-point request interconnect
US8356138B1 (en) * 2007-08-20 2013-01-15 Xilinx, Inc. Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP)
EP2529312A4 (en) * 2010-01-28 2013-07-03 Hewlett Packard Development Co INTERFACE METHOD AND DEVICE FOR MEMORY DEVICES
WO2012064670A1 (en) * 2010-11-09 2012-05-18 Rambus Inc. Area-efficient multi-modal signaling interface
US20120185663A1 (en) 2011-01-14 2012-07-19 Satoshi Yokoya Memory Interface Converter
US8446903B1 (en) 2012-05-22 2013-05-21 Intel Corporation Providing a load/store communication protocol with a low power physical unit
US8972640B2 (en) 2012-06-27 2015-03-03 Intel Corporation Controlling a physical link of a first protocol using an extended capability structure of a second protocol
US9697111B2 (en) 2012-08-02 2017-07-04 Samsung Electronics Co., Ltd. Method of managing dynamic memory reallocation and device performing the method
US8680900B2 (en) * 2012-08-10 2014-03-25 Arm Limited Self-initializing on-chip data processing apparatus and method of self-initializing an on-chip data processing apparatus
CN102929828B (zh) * 2012-10-18 2016-01-06 广东欧珀移动通信有限公司 同时支持标准和非标准i2c接口的数据传输方法及装置
CN104956347B (zh) 2013-02-28 2018-05-22 英特尔公司 将一种互连协议的枚举和/或配置机制用于不同的互连协议
KR102029682B1 (ko) * 2013-03-15 2019-10-08 삼성전자주식회사 반도체 장치 및 반도체 패키지
US9123408B2 (en) * 2013-05-24 2015-09-01 Qualcomm Incorporated Low latency synchronization scheme for mesochronous DDR system
US9430434B2 (en) * 2013-09-20 2016-08-30 Qualcomm Incorporated System and method for conserving memory power using dynamic memory I/O resizing

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