CN107209735B - 可配置管芯、层叠封装装置以及方法 - Google Patents

可配置管芯、层叠封装装置以及方法 Download PDF

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Publication number
CN107209735B
CN107209735B CN201680005707.9A CN201680005707A CN107209735B CN 107209735 B CN107209735 B CN 107209735B CN 201680005707 A CN201680005707 A CN 201680005707A CN 107209735 B CN107209735 B CN 107209735B
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China
Prior art keywords
phy
memory
generic
signal
signals
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Expired - Fee Related
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CN201680005707.9A
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English (en)
Chinese (zh)
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CN107209735A (zh
Inventor
K·M·德赛
P·库普塔
B·J·杨
U·M·劳
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
CN201680005707.9A 2015-01-16 2016-01-07 可配置管芯、层叠封装装置以及方法 Expired - Fee Related CN107209735B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/598,528 US9324397B1 (en) 2015-01-16 2015-01-16 Common die for supporting different external memory types with minimal packaging complexity
US14/598,528 2015-01-16
PCT/US2016/012511 WO2016114975A1 (en) 2015-01-16 2016-01-07 A common die for supporting different external memory types with minimal packaging complexity

Publications (2)

Publication Number Publication Date
CN107209735A CN107209735A (zh) 2017-09-26
CN107209735B true CN107209735B (zh) 2020-07-03

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Country Link
US (1) US9324397B1 (https=)
EP (1) EP3245594A1 (https=)
JP (1) JP6710689B2 (https=)
CN (1) CN107209735B (https=)
WO (1) WO2016114975A1 (https=)

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JP6543129B2 (ja) 2015-07-29 2019-07-10 ルネサスエレクトロニクス株式会社 電子装置
US11468925B2 (en) 2018-12-03 2022-10-11 Rambus Inc. DRAM interface mode with improved channel integrity and efficiency at high signaling rates
US10671551B1 (en) * 2019-02-20 2020-06-02 Intel Corporation Selective data lane interface mapping
US11288222B1 (en) * 2020-09-28 2022-03-29 Xilinx, Inc. Multi-die integrated circuit with data processing engine array
KR20240157385A (ko) 2023-04-25 2024-11-01 삼성전자주식회사 메모리 장치 및 이를 포함하는 전자 장치

Citations (3)

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CN101702947A (zh) * 2007-04-12 2010-05-05 拉姆伯斯公司 具有点对点请求互连的存储器系统
CN102576338A (zh) * 2010-01-28 2012-07-11 惠普发展公司，有限责任合伙企业 用于存储器设备的接口方法和装置
CN102929828A (zh) * 2012-10-18 2013-02-13 广东欧珀移动通信有限公司 同时支持标准和非标准i2c接口的数据传输方法及装置

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US6460120B1 (en) * 1999-08-27 2002-10-01 International Business Machines Corporation Network processor, memory organization and methods
US8356138B1 (en) * 2007-08-20 2013-01-15 Xilinx, Inc. Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP)
WO2012064670A1 (en) * 2010-11-09 2012-05-18 Rambus Inc. Area-efficient multi-modal signaling interface
US20120185663A1 (en) 2011-01-14 2012-07-19 Satoshi Yokoya Memory Interface Converter
US8446903B1 (en) 2012-05-22 2013-05-21 Intel Corporation Providing a load/store communication protocol with a low power physical unit
US8972640B2 (en) 2012-06-27 2015-03-03 Intel Corporation Controlling a physical link of a first protocol using an extended capability structure of a second protocol
US9697111B2 (en) 2012-08-02 2017-07-04 Samsung Electronics Co., Ltd. Method of managing dynamic memory reallocation and device performing the method
US8680900B2 (en) * 2012-08-10 2014-03-25 Arm Limited Self-initializing on-chip data processing apparatus and method of self-initializing an on-chip data processing apparatus
CN104956347B (zh) 2013-02-28 2018-05-22 英特尔公司 将一种互连协议的枚举和/或配置机制用于不同的互连协议
KR102029682B1 (ko) * 2013-03-15 2019-10-08 삼성전자주식회사 반도체 장치 및 반도체 패키지
US9123408B2 (en) * 2013-05-24 2015-09-01 Qualcomm Incorporated Low latency synchronization scheme for mesochronous DDR system
US9430434B2 (en) * 2013-09-20 2016-08-30 Qualcomm Incorporated System and method for conserving memory power using dynamic memory I/O resizing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101702947A (zh) * 2007-04-12 2010-05-05 拉姆伯斯公司 具有点对点请求互连的存储器系统
CN102576338A (zh) * 2010-01-28 2012-07-11 惠普发展公司，有限责任合伙企业 用于存储器设备的接口方法和装置
CN102929828A (zh) * 2012-10-18 2013-02-13 广东欧珀移动通信有限公司 同时支持标准和非标准i2c接口的数据传输方法及装置

Also Published As

Publication number Publication date
US9324397B1 (en) 2016-04-26
JP6710689B2 (ja) 2020-06-17
JP2018508871A (ja) 2018-03-29
WO2016114975A1 (en) 2016-07-21
CN107209735A (zh) 2017-09-26
EP3245594A1 (en) 2017-11-22

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