JP2018201050A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of improving voltage-withstanding .SOLUTION: A semiconductor device according to an embodiment has: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a second electrode; a third semiconductor region of the second conductivity type; and a third electrode. The first semiconductor region has a first region, and a second region provided around the first region. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first region. The second electrode is provided on the second semiconductor region, and electrically connected with the second semiconductor region. The third semiconductor region is provided on the second region so as to be separated from the second semiconductor region, and surrounds the second semiconductor region. The third electrode is provided on the third semiconductor region so as to be separated from the second electrode. The third electrode surrounds the second electrode, and has a first projection protruding in a first direction from the first region toward the second region. A lower surface of the first projection is inclined to a second direction vertical to the first direction.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device.

  In order to achieve high-efficiency power conversion, power electronics and power semiconductor development are becoming increasingly popular. Various devices have been developed to support a wide range of rated voltages and currents. Depending on the switching frequency and power capacity, the intended use and the elements used are determined. Typical elements include semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) suitable for high-frequency operation, IGBTs (Insulated Gate Bipolar Transistors) and pin diodes, which are bipolar elements capable of driving high voltages and high currents. is there. For these semiconductor devices, there are demands for operability, breakdown resistance, high breakdown voltage, etc., as well as low loss driving, and high breakdown voltage design is an important design item.

Japanese Patent Laying-Open No. 2015-23061

  The problem to be solved by the present invention is to provide a semiconductor device capable of improving the breakdown voltage.

The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a second electrode, and a third semiconductor region of a second conductivity type. And a third electrode.
The first semiconductor region includes a first region and a second region provided around the first region. The first semiconductor region is provided on the first electrode.
The second semiconductor region is provided on the first region.
The second electrode is provided on the second semiconductor region and is electrically connected to the second semiconductor region.
The third semiconductor region is provided on the second region so as to be separated from the second semiconductor region, and surrounds the second semiconductor region.
The third electrode is provided on the third semiconductor region so as to be separated from the second electrode. The third electrode includes a first protrusion that surrounds the second electrode and protrudes in a first direction from the first region toward the second region. The lower surface of the first protrusion is inclined with respect to a second direction perpendicular to the first direction.

1 is a cross-sectional view illustrating a part of a semiconductor device according to a first embodiment. It is process sectional drawing showing the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing showing the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing showing the manufacturing process of the semiconductor device which concerns on 1st Embodiment. 3 is an enlarged cross-sectional view of the vicinity of the gate electrode of the semiconductor device according to the first embodiment and a graph showing the electric field strength in the vicinity of the gate electrode. It is the graph showing sectional drawing which expanded the gate electrode vicinity of the semiconductor device which concerns on the 1st modification of 1st Embodiment, and the electric field strength of the gate electrode vicinity. It is the graph showing the partial expanded sectional view of the gate electrode vicinity in the semiconductor device which concerns on the 2nd modification of 1st Embodiment, and the electric field strength of the gate electrode vicinity. It is a partial expanded sectional view showing the gate electrode vicinity which the semiconductor device concerning the other modification of 1st Embodiment has. It is a partial expanded sectional view showing the gate electrode vicinity which the semiconductor device concerning the other modification of 1st Embodiment has. It is sectional drawing showing the semiconductor device which concerns on the other modification of 1st Embodiment. It is a top view showing the semiconductor device concerning a 2nd embodiment. It is A-A 'sectional drawing of FIG. It is sectional drawing showing the semiconductor device which concerns on the reference example of 2nd Embodiment. It is sectional drawing showing the semiconductor device which concerns on the modification of 2nd Embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
In the present specification and each drawing, the same elements as those already described are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1 is a cross-sectional view illustrating a part of the semiconductor device 100 according to the first embodiment.
The semiconductor device 100 is, for example, a horizontal HEMT (High Electron Mobility Transistor).
As shown in FIG. 1, the semiconductor device 100 includes a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4 (first semiconductor layer), a gate electrode 10, a gate insulating layer 18, and a source electrode 20 (first electrode). , A drain electrode 30 (second electrode), and an insulating layer 40.

  In the following description of the first embodiment, the direction from the source electrode 20 toward the drain electrode 30 is the X direction (first direction). A direction intersecting the upper surface 4a of the barrier layer 4 is defined as a Z direction (second direction), and a direction perpendicular to the X direction and the Z direction is defined as a Y direction.

The buffer layer 2 is provided on the substrate 1. The buffer layer 2 is provided to alleviate the lattice mismatch between the substrate 1 and the channel layer 3.
The channel layer 3 is provided on the buffer layer 2.

  The barrier layer 4 is provided on the channel layer 3. The band gap of the barrier layer 4 is larger than the band gap of the channel layer 3. The channel layer 3 and the barrier layer 4 form a heterojunction interface, and a two-dimensional electron gas is generated at the heterojunction interface.

  The source electrode 20 and the drain electrode 30 are provided on the upper surface 4 a of the barrier layer 4 so as to be separated from each other. The source electrode 20 and the drain electrode 30 are in ohmic contact with the barrier layer 4.

  The gate electrode 10 is provided on the upper surface 4a via a gate insulating layer 18. The gate electrode 10 is located between the source electrode 20 and the drain electrode 30 and is separated from these electrodes.

  The insulating layer 40 is provided around the gate electrode 10 and covers the source electrode 20 and the drain electrode 30.

Here, the structure of the gate electrode 10 will be described more specifically.
As shown in FIG. 1, the gate electrode 10 has a first portion 11 and a second portion 12.
The first portion 11 is provided on the upper surface 4a via the gate insulating layer 18.
The second portion 12 is provided between the first portion 11 and the drain electrode 30 in the X direction. The distance in the Z direction between the second portion 12 and the barrier layer 4 is longer than the distance in the Z direction between the first portion 11 and the barrier layer 4. Further, the distance in the Z direction between the lower surface BS1 of the second portion 12 and the barrier layer 4 becomes longer in the X direction.

The lower surface BS1 of the second portion 12 has a curvature.
Specifically, the lower surface BS1 is convexly curved downward, and the inclination angle of the lower surface BS1 with respect to the Z direction becomes smaller toward the Z direction. In other words, the distance in the Z direction between the lower surface BS1 and the barrier layer 4 becomes longer as it goes in the X direction, and the amount of change increases as it goes in the X direction.

Next, an example of the material of each component included in the semiconductor device 100 will be described.
The substrate 1 is made of silicon, silicon carbide, or sapphire.
The buffer layer 2 has a structure in which a plurality of aluminum gallium nitride layers are stacked.
The channel layer 3 includes undoped gallium nitride.
The barrier layer 4 includes undoped aluminum gallium nitride.
The gate electrode 10, the source electrode 20, and the drain electrode 30 include a metal such as aluminum, nickel, copper, or titanium.
The gate insulating layer 18 includes an insulating material such as aluminum nitride or aluminum oxide.
The insulating layer 40 includes an insulating material such as silicon oxide.

Next, an example of a method for manufacturing the semiconductor device 100 according to the first embodiment will be described.
2 to 4 are process cross-sectional views illustrating the manufacturing process of the semiconductor device 100 according to the first embodiment.

  First, the buffer layer 2, the channel layer 3, and the barrier layer 4 are sequentially epitaxially grown on the substrate 1. Next, the gate insulating layer 18 is formed on the upper surface 4 a of the barrier layer 4. Subsequently, a part of the gate insulating layer 18 is removed, and a part of the upper surface 4a is exposed. Subsequently, a metal layer covering the gate insulating layer 18 is formed. By patterning this metal layer, as shown in FIG. 2A, a gate electrode 10a, a source electrode 20, and a drain electrode 30 that are part of the gate electrode 10 are formed.

  Next, an insulating layer 40 that covers the gate electrode 10a, the source electrode 20, and the drain electrode 30 is formed. Subsequently, a photoresist layer 45 is formed on the insulating layer 40, and a first recess R1 is formed in the photoresist layer 45 using a nanoimprint method. At this time, the first recess R1 is formed on the gate electrode 10a. A part of the bottom surface 45a of the first recess R1 has a curvature and is convexly curved downward as in the lower surface BS1 of the second portion 12 shown in FIG.

  Next, a part of the insulating layer 40 is removed by anisotropic etching such as RIE (Reactive Ion Etching) using the photoresist layer 45 as a mask. By this step, the shape of the first recess R1 formed in the photoresist layer 45 is transferred to the insulating layer 40, and the second recess R2 is formed in the insulating layer 40 as shown in FIG. At this time, the upper surface of the gate electrode 10a is exposed through the second recess R2. Further, a part of the bottom surface 40a of the second recess R2 has a curvature, like the bottom surface 45a of the first recess R1.

Next, as shown in FIG. 3B, a metal layer 46 is formed on the insulating layer 40, and the second recess R2 is embedded.
Subsequently, by performing CMP (Chemical Mechanical Polishing), as shown in FIG. 4A, the excess metal layer 46 deposited on the insulating layer 40 is removed and the upper surface of the gate electrode 10 is flattened. Is formed. Thereby, the semiconductor device 100 shown in FIG. 1 is obtained.
Alternatively, a photoresist layer may be formed on the metal layer 46 and the metal layer 46 may be etched back to remove the excess metal layer 46 deposited on the insulating layer 40. In this case, as shown in FIG. 4B, a depression is formed on the upper surface of the gate electrode 10.

Here, the operation and effect of the present embodiment will be described with reference to FIG.
FIG. 5 is an enlarged sectional view of the vicinity of the gate electrode 10 of the semiconductor device 100 according to the first embodiment and a graph showing the electric field strength in the vicinity of the gate electrode 10.
In the graph of FIG. 5, the horizontal axis represents the position in the X direction, and the vertical axis represents the maximum electric field strength E [V / m] between the barrier layer 4 and the gate electrode 10 at each position. The broken line represents the maximum electric field strength when the lower surface BS1 of the second portion 12 is inclined at a constant angle with respect to the Z direction. The solid line represents the maximum electric field strength when the lower surface BS1 is convexly curved downward as in the present embodiment.

When the semiconductor device 100 is in an OFF state, an electric field is generated between these electrodes due to a potential difference between the gate electrode 10 and the drain electrode 30 and a potential difference between the source electrode 20 and the drain electrode 30. Since the distance between the gate electrode 10 and the drain electrode 30 is shorter than the distance between the source electrode 20 and the drain electrode 30, a stronger electric field is present in the vicinity of the gate electrode 10 than in the vicinity of the source electrode 20. Arise.
As shown in the graph of FIG. 5, there are two peaks in the electric field intensity near the gate electrode 10. Specifically, there is an end peak in the X direction (first peak) on the lower surface of the first portion 11 and an end peak in the X direction (second peak) on the lower surface BS1 of the second portion 12. To do. From the graph of FIG. 5, it can be seen that when the lower surface BS1 is curved, the maximum electric field strength at each peak is lower than when the lower surface BS1 is inclined at a constant angle.
That is, according to the present embodiment, the maximum electric field strength in the vicinity of the gate electrode 10 can be reduced and the breakdown voltage of the semiconductor device can be improved.

1 to 5, the case where the lower surface BS1 of the second portion 12 is convexly curved downward has been described, but the semiconductor device according to the present embodiment is not limited to this.
A semiconductor device according to a modification of the present embodiment will be described below with reference to FIGS. 6 and 7.

FIG. 6 is an enlarged cross-sectional view of the vicinity of the gate electrode 10 of the semiconductor device 110 according to the first modification of the first embodiment, and a graph showing the electric field strength in the vicinity of the gate electrode 10.
FIG. 7 is an enlarged cross-sectional view of the vicinity of the gate electrode 10 of the semiconductor device 120 according to the second modification of the first embodiment, and a graph showing the electric field strength in the vicinity of the gate electrode 10.

  In the graphs shown in FIGS. 6 and 7, the broken line represents the electric field strength when the lower surface BS1 of the second portion 12 is inclined at a certain angle, and the solid line represents the gate electrode 10 in the semiconductor device according to each modification. It represents the electric field strength in the vicinity.

  In the semiconductor device 110 illustrated in FIG. 6, the lower surface BS1 of the second portion 12 is curved to protrude upward. That is, the inclination angle of the lower surface BS1 with respect to the Z direction increases as it goes in the Z direction.

In this case, as shown in the graph of FIG. 6, the position of the first peak moves in the X direction and the maximum electric field at the first peak as compared with the case where the lower surface BS1 is inclined at a certain angle. Strength decreases. Similarly, the position of the second peak also moves in the X direction, and the maximum electric field strength at the second peak decreases.
That is, according to this modification as well as the semiconductor device 100, the maximum electric field strength at each peak can be reduced and the breakdown voltage of the semiconductor device can be improved as compared with the case where the lower surface BS1 is inclined at a constant angle. Is possible.

  In the semiconductor device 120 shown in FIG. 7, the lower surface BS1 of the second portion 12 includes a first surface 12a and a second surface 12b. The first surface 12a is convexly curved downward. The second surface 12b is located above the first surface 12a and is curved convexly upward.

In this case, as shown in the graph of FIG. 7, the position of the first peak moves in the X direction and the maximum electric field at the first peak as compared with the case where the lower surface BS1 is inclined at a constant angle. The strength and the maximum electric field strength at the second peak are reduced.
That is, according to this modification as well, the breakdown voltage of the semiconductor device can be improved as in the semiconductor device 100.

5 to 7, the maximum electric field strength at the first peak is lower than that of the semiconductor device 100 in the semiconductor device 120, and the maximum electric field strength at the second peak is lower than that of the semiconductor device 110. It can be seen that it has decreased.
That is, according to this modification, it is possible to further reduce the maximum electric field strength of at least one of the first peak and the second peak and further improve the breakdown voltage of the semiconductor device as compared with the semiconductor devices 100 and 110. It is.

Hereinafter, still another modification of the semiconductor device according to the present embodiment will be described.
8 and 9 are partially enlarged cross-sectional views showing the vicinity of the gate electrode 10 included in the semiconductor device according to another modification of the first embodiment.
FIG. 10 is a cross-sectional view illustrating a semiconductor device according to another modification of the first embodiment.
In each of the following modifications shown in FIGS. 8 to 10, similarly to the semiconductor devices 100 to 120, the maximum electric field strength and the second peak at the first peak are compared with the case where the lower surface BS <b> 1 is inclined at a certain angle. It is possible to reduce the maximum electric field strength at the peak and improve the breakdown voltage of the semiconductor device.

  In the semiconductor device shown in FIG. 8A, the lower surface BS1 of the second portion 12 includes a first surface 12a and a second surface 12b. The first surface 12a is curved convexly upward. The second surface 12b is located above the first surface 12a and is curved convexly downward.

  In the semiconductor device shown in FIG. 8B, the upper surface US of the second portion 12 is curved convexly downward along the lower surface BS1. That is, in the semiconductor device shown in FIGS. 5A to 8A, the length of the second portion 12 in the Z direction becomes shorter toward the X direction. On the other hand, in the semiconductor device shown in FIG. 8B, the length of the second portion 12 in the Z direction is substantially constant in the X direction.

  In addition, in FIG.8 (b), the case where the lower surface BS1 was curving so that it might become convex toward the downward direction was illustrated. However, for the gate electrode 10 in each semiconductor device shown in FIGS. 5 to 8A, the upper surface US is similarly set so that the length of the second portion 12 in the Z direction is substantially constant in the X direction. It may be curved along the lower surface BS1.

The semiconductor device shown in FIG. 9A differs from the semiconductor device 100 in that the lower surface BS1 of the second portion 12 is provided smoothly and continuously with the lower surface of the first portion 11.
Similarly, the semiconductor device shown in FIG. 9B is different from the semiconductor device 120 in that the lower surface BS1 is provided smoothly and continuously with the lower surface of the first portion 11.
That is, in each semiconductor device shown in FIGS. 5 to 8, a step is formed between the lower surface of the first portion 11 of the gate electrode 10 and the lower surface BS <b> 1 of the second portion 12. In FIG. 9, each lower surface may be provided continuously as in the example shown in FIG.

In the semiconductor device shown in FIG. 10, the gate electrode 10, a part of the source electrode 20, and the drain electrode 30 are covered with an insulating layer 40. In addition, the source electrode 20 has a third portion 23 provided on the insulating layer 40. The third portion 23 is located above the gate electrode 10, and the end portion of the third portion 23 in the X direction protrudes in the X direction from the end portion of the gate electrode 10 in the X direction.
Further, the lower surface BS2 of the third portion 23 is convexly curved upward.

Since the source electrode 20 has such a third portion 23, the maximum electric field strength in the vicinity of the gate electrode 10 can be further reduced, and the breakdown voltage of the semiconductor device can be further increased.
10 illustrates the case where the lower surface BS1 of the second portion 12 is convexly curved downward, but the lower surface BS1 has any one of the shapes illustrated in FIGS. May be.

  In the description of the first embodiment described above, the case where the gate electrode 10, the source electrode 20, and the drain electrode 30 are provided on a semiconductor layer including a nitride semiconductor has been described. However, the invention according to this embodiment is not limited to this, and can also be applied to the case where the gate electrode 10, the source electrode 20, and the drain electrode 30 are provided on a semiconductor layer containing silicon. is there. By applying the invention according to this embodiment to a gate electrode provided on a semiconductor layer containing silicon, similarly, the maximum electric field strength in the vicinity of the gate electrode is reduced and the breakdown voltage of the semiconductor device is improved. It becomes possible.

(Second Embodiment)
Next, an example of the semiconductor device according to the second embodiment will be described with reference to FIGS. 11 and 12.
In the following description, the notations of n ⁺ , n ⁻ and p ⁺ , p represent the relative level of impurity concentration in each conductivity type. That is, the notation with “+” has a relatively higher impurity concentration than the notation without both “+” and “−”, and the notation with “−” It shows that the impurity concentration is relatively lower than the notation.
About each embodiment described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

An example of the semiconductor device according to the second embodiment will be described with reference to FIGS. 11 and 12.
FIG. 11 is a plan view illustrating a semiconductor device 200 according to the second embodiment.
12 is a cross-sectional view taken along the line AA ′ of FIG.
In FIG. 11, the first region 52a and the second region 52b included in the n ⁻ -type semiconductor region 52 are indicated by a two-dot chain line.

The semiconductor device 200 is a diode.
As shown in FIGS. 11 and 12, the semiconductor device 200 includes an n ^{+ type} (first conductivity type) semiconductor region 51, an n ^{− type} semiconductor region 52 (first semiconductor region), and a p type (second conductivity type) semiconductor. Region 53 (second semiconductor region), p ^{+ -type} semiconductor region 54, p-type guard ring region 55 (third semiconductor region), n ^{+ -type} stopper region 56 (fourth semiconductor region), cathode electrode 61 (first electrode) , An anode electrode 62 (second electrode), a field plate electrode (hereinafter referred to as FP electrode) 63, and a stopper electrode 64 (fourth electrode).

  In the following description of the second embodiment, the direction from the first region 52a toward the second region 52b (the direction from the center of the semiconductor device toward the outer periphery) is the first direction, and the directions are included in the first direction and are mutually Two directions orthogonal to the X direction are defined as an X direction and a Y direction. The direction perpendicular to the first direction is the Z direction (second direction), and the direction from the second region 52b to the first region 52a (the direction from the outer periphery to the center of the semiconductor device) is the third direction. To do.

As shown in FIG. 11, an anode electrode 62, a plurality of FP electrodes 63, and a stopper electrode 64 are provided on the upper surface of the semiconductor device 200 so as to be separated from each other.
Each FP electrode 63 is provided in an annular shape and surrounds the anode electrode 62.
The stopper electrode 64 is provided in an annular shape and surrounds the plurality of FP electrodes 63.

As shown in FIG. 12, a cathode electrode 61 is provided on the lower surface of the semiconductor device 200.
The n ^{+ -type} semiconductor region 51 is provided on the cathode electrode 61 and is electrically connected to the cathode electrode 61.
The n ^{− type} semiconductor region 52 is provided on the n ^{+ type} semiconductor region 51.
As shown in FIGS. 11 and 12, the n ⁻ -type semiconductor region 52 includes a first region 52a and a second region 52b provided around the first region 52a.

As shown in FIG. 11, the p-type semiconductor region 53 is provided on the first region 52a.
The p ^{+ -type} semiconductor region 54 is selectively provided on the p-type semiconductor region 53.
The anode electrode 62 is provided over the p-type semiconductor regions 53 and p ⁺ -type semiconductor regions 54 are electrically connected to the p-type semiconductor regions 53 and p ⁺ -type semiconductor region 54.

The p-type guard ring region 55 is selectively provided on the second region 52b. A plurality of p-type guard ring regions 55 are provided apart from each other. Each p-type guard ring region 55 is provided in an annular shape and surrounds the p-type semiconductor region 53.
The n ^{+ -type} stopper region 56 is annularly provided on the second region 52 b and surrounds the plurality of p-type guard ring regions 55.

Part of the plurality of FP electrodes 63 (fifth electrode) is provided on the p-type semiconductor region 53 so as to be separated from the anode electrode 62 and is electrically connected to the p-type semiconductor region 53.
Another part (third electrode) of the plurality of FP electrodes 63 is provided on the p-type guard ring region 55 and is electrically connected to the p-type guard ring region 55.
Stopper electrode 64 is provided on the n ⁺ -type stopper region 56, n ⁺ -type stopper region 56 is electrically connected to the.
An insulating layer 68 is provided between each of the anode electrode 62, the FP electrode 63, and the stopper electrode 64.

Note that the number of the p-type guard ring region 55 and the FP electrode 63 is arbitrary, and can be appropriately changed according to the breakdown voltage required for the semiconductor device.
Further, the structure on the first portion 52a of the n ⁻ -type semiconductor region 52 is not limited to the example shown in FIGS. 11 and 12 and can be changed as appropriate.

Here, a specific structure of the FP electrode 63 and the stopper electrode 64 will be described.
The FP electrode 63 has a protrusion P1 that protrudes in the first direction. The protrusion P1 is separated from the n ⁻ -type semiconductor region 52, the p-type semiconductor region 53, and the p-type guard ring region 55 in the Z direction, and the lower surface BS3 is inclined with respect to the Z direction. In addition, the distance in the Z direction between the lower surface BS3 and the n ⁻ -type semiconductor region 52 becomes longer toward the first direction.

The stopper electrode 64 has a protrusion P2 that protrudes in the third direction. The protrusion P2 is separated from the n ^{− -type} semiconductor region 52 and the n ^{+ -type} stopper region 56 in the Z direction, and the lower surface BS4 is inclined with respect to the Z direction. In addition, the distance in the Z direction between the lower surface BS4 and the n ⁻ -type semiconductor region 52 becomes longer toward the second direction.

When the semiconductor device 200 is in an off state, a depletion layer spreads from the pn junction surface between the n ⁻ -type semiconductor region 52 and the p-type semiconductor region 53 toward the outer periphery and downward of the semiconductor device. At this time, since the p-type guard ring region 55 and the FP electrode 63 are provided, the depletion layer easily spreads toward the outer periphery of the semiconductor device, and electric field concentration at the end portion in the first direction of the pn junction surface is reduced. Alleviated.
Further, by providing the n ^{+ -type} stopper region 56 and the stopper electrode 64, it is possible to suppress the depletion layer spreading toward the outer periphery of the semiconductor device from reaching the outermost periphery of the semiconductor device.

Here, the operation and effect of the present embodiment will be described with reference to FIG.
FIG. 13 is a cross-sectional view illustrating a semiconductor device 250 according to a reference example of the second embodiment.
In the semiconductor device 250, corners projecting downward are formed on the lower surfaces of the projecting portions of the FP electrode 63 and the stopper electrode 64.
In this case, when the semiconductor device is in the off state, the depletion layer can be expanded toward the outer periphery of the semiconductor device, but electric field concentration occurs in the vicinity of the corners of the FP electrode 63 and the stopper electrode 64 described above.

  In contrast, in the semiconductor device 200 according to the present embodiment, the lower surfaces of the protruding portions of the FP electrode 63 and the stopper electrode 64 are inclined with respect to the Z direction, and no corners are formed on the lower surface. It is flat. By adopting such a structure, it is possible to suppress electric field concentration on the lower surfaces of the FP electrode 63 and the stopper electrode 64 and to improve the breakdown voltage of the semiconductor device.

Although the case where the semiconductor device according to the second embodiment is a diode has been described here, the invention according to this embodiment can also be applied to other semiconductor devices.
FIG. 14 is a cross-sectional view illustrating a semiconductor device 210 according to a modification of the second embodiment.

The semiconductor device 210 is a MOSFET.
In the semiconductor device 210, the electrode 61 functions as a drain electrode, and the electrode 62 functions as a source electrode.
As illustrated in FIG. 14, the semiconductor device 210 includes an n ^{+ -type} semiconductor region 51, an n ^{− -type} semiconductor region 52, a p-type semiconductor region 53, a p-type guard ring region 55, an n ^{+ -type} stopper region 56, and an n ^{+ -type} semiconductor. A region 57 (fifth semiconductor region), a drain electrode 61, a source electrode 62, an FP electrode 63, a stopper electrode 64, a gate electrode 70, and a gate insulating layer 71 are provided.

The p-type semiconductor region 53 is provided on the first region 52a.
The n ^{+ -type} semiconductor region 57 is selectively provided on the p-type semiconductor region 53 and is electrically connected to the source electrode 62.
A plurality of p-type semiconductor regions 53 and n ^{+ -type} semiconductor regions 57 are provided in the X direction, and each extend in the Y direction.

The gate electrode 70 is aligned with a part of the n ^{− type} semiconductor region 52, a p type semiconductor region 53, and a part of the n ^{+ type} semiconductor region 57 in the X direction.
The gate insulating layer 71 is provided between the n ^{− type} semiconductor region 52, the p type semiconductor region 53, the n ^{+ type} semiconductor region 57, and the gate electrode 70.
A gate insulating layer 71 is provided between the source electrode 62 and the gate electrode 70, and these electrodes are electrically separated.

Further, similarly to the semiconductor device 200, the p-type guard ring region 55, the n ^{+ -type} stopper region 56, the FP electrode 63, and the stopper electrode 64 are provided on the second region 52b. Further, the lower surfaces of the protruding portions of the FP electrode 63 and the stopper electrode 64 are inclined at a certain angle with respect to the Z direction.
By adopting such a structure for the semiconductor device 210, as with the semiconductor device 200, the electric field concentration in the FP electrode 63 and the stopper electrode 64 is reduced while expanding the depletion layer toward the outer periphery of the semiconductor device, The breakdown voltage of the semiconductor device can be improved.

  Here, the semiconductor device having the trench gate structure in which the gate electrode 70 is provided in the semiconductor region with the gate insulating layer 71 interposed therebetween has been described. However, the invention according to this embodiment can also be applied to a semiconductor device having a planar gate structure in which the gate electrode 70 is provided on the semiconductor region with the gate insulating layer 71 interposed therebetween.

The invention according to the present embodiment can also be applied to an IGBT (Insulated Gate Bipolar Transistor). In this case, a p ^{+ type} semiconductor region (sixth semiconductor region) is provided between the n ^{− type} semiconductor region 52 and the electrode 61 instead of the n ^{+ type} semiconductor region 51.

Here, the case where the lower surface BS3 of the FP electrode 63 and the lower surface BS4 of the stopper electrode 64 are inclined at a certain angle with respect to the Z direction has been described. However, the invention according to the present embodiment is not limited to this. The lower surfaces BS3 and BS4 may be curved in the same manner as the lower surface BS1 of the gate electrode 10 shown in FIGS.
As an example, the lower surface BS3 may be convexly curved downward or upward like the lower surface BS1 shown in FIG. 5 or FIG. Alternatively, like the lower surface BS1 shown in FIG. 7 and FIG. 8A, a part of the lower surface BS3 is convexly curved upward, and another part of the lower surface BS3 is curved convexly downward. May be.

As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. For example, the substrate 1, the buffer layer 2, the channel layer 3, the barrier layer 4, the gate electrode 10, the gate insulating layer 18, the source electrode 20, the drain electrode 30, the insulating layer 40, and the n ^{+ -type} semiconductor region 51 included in the embodiment. , N ^{− type} semiconductor region 52, p type semiconductor region 53, p ^{+ type} semiconductor region 54, p type guard ring region 55, n ^{+ type} stopper region 56, n ^{+ type} semiconductor region 57, electrode 61, electrode 62, FP electrode The specific configuration of each element such as 63, stopper electrode 64, gate electrode 70, and gate insulating layer 71 can be appropriately selected by those skilled in the art from known techniques. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.

DESCRIPTION OF SYMBOLS 100-120, 200, 210, 250 ... Semiconductor device, 2 ... Buffer layer, 3 ... Channel layer, 4 ... Barrier layer, 10 ... Gate electrode, 20 ... Source electrode, 30 ... Drain electrode, 40 ... Insulating layer, 51 ... n ^{+ -type} semiconductor region, 52 ... n ^{− -type} semiconductor region, 53 ... p-type semiconductor region, 54 ... p ^{+ -type} semiconductor region, 55 ... p-type guard ring region, 56 ... n ^{+ -type} stopper region, 61, 62 ... electrode 63 ... Field plate electrode, 64 ... Stopper electrode, 70 ... Gate electrode

Claims (6)

A first electrode;
A first region having a first region and a second region provided around the first region; and a first semiconductor region of a first conductivity type provided on the first electrode;
A second semiconductor region of a second conductivity type provided on the first region;
A second electrode provided on the second semiconductor region and electrically connected to the second semiconductor region;
A third semiconductor region of a second conductivity type provided on the second region and spaced apart from the second semiconductor region and surrounding the second semiconductor region;
A first protruding portion provided on the third semiconductor region and spaced apart from the second electrode, surrounding the second electrode and protruding in a first direction from the first region toward the second region; A third electrode having a lower surface of the first protrusion inclined with respect to a second direction perpendicular to the first direction;
A semiconductor device comprising: A first conductivity type first electrode disposed on the second region and spaced apart from the third semiconductor region, surrounds the third semiconductor region, and has a higher impurity concentration of the first conductivity type than the first semiconductor region. 4 semiconductor regions;
A second projecting portion provided on the fourth semiconductor region and spaced apart from the third electrode, surrounding the third electrode, and projecting in a third direction from the second region toward the first region; A fourth electrode having a lower surface of the second projecting portion inclined with respect to the second direction;
The semiconductor device according to claim 1, further comprising:   Provided around the second electrode, surrounded by the third electrode, spaced apart from the second electrode and the third electrode, positioned on the second semiconductor region, and projecting in the first direction 3. The semiconductor device according to claim 2, further comprising a fifth electrode having a third protruding portion that has a lower surface inclined with respect to the second direction. A first electrode;
A first region having a first region and a second region provided around the first region; and a first semiconductor region of a first conductivity type provided on the first electrode;
A second semiconductor region of a second conductivity type provided on the first region;
A second electrode provided on the second semiconductor region and electrically connected to the second semiconductor region;
A third semiconductor region of a second conductivity type provided on the second region and spaced apart from the second semiconductor region and surrounding the second semiconductor region;
A first conductivity type first electrode disposed on the second region and spaced apart from the third semiconductor region, surrounds the third semiconductor region, and has a higher impurity concentration of the first conductivity type than the first semiconductor region. 4 semiconductor regions;
A second protrusion that is provided on the fourth semiconductor region and protrudes in a third direction from the second region toward the first region, and a lower surface of the second protrusion is in the second direction; A fourth electrode inclined relative to
Provided around the second electrode, surrounded by the fourth electrode, spaced apart from the second electrode and the fourth electrode, positioned on the second semiconductor region, and projecting in the first direction A third electrode having a third protrusion, and a lower surface of the third protrusion is inclined with respect to the second direction;
A semiconductor device comprising: A fifth semiconductor region of a first conductivity type selectively provided on the second semiconductor region;
A gate electrode;
A gate insulating layer provided between the second semiconductor region and the gate electrode;
The semiconductor device according to claim 1, further comprising:   2. The sixth semiconductor region of a second conductivity type provided between the first electrode and the first semiconductor region and having an impurity concentration of a second conductivity type higher than that of the second semiconductor region. The semiconductor device according to any one of?

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