JP2018198467A - Error correction encoding circuit, error correction decoding circuit and method - Google Patents

Abstract

To improve the processing capacity of error correction encoding and decoding by enabling the application to an arbitrary block code and coping with an increase in the capacity of transmission capacity.SOLUTION: A plurality of encoding circuits for generating a block code undergoing error correction encoding are provided in parallel. A distribution row number determined such that the total is a radio row number of radio frame data to be outputted is allocated to each encoding circuit. Data distribution means distributes information data to encoding circuits in accordance with the distribution row number. Code length frame generation means reads a block code as a first code word from each encoding circuit with a clock operation rate of a ratio of the distribution row number to a symbol size to be processed by the encoding circuit. Radio row number conversion means processes the first code word with the clock operation rate of 100%, and outputs a second code word of a radio row number corresponding to the distribution row number allocated to the encoding circuit. Bit connection means connects the radio row numbers of the second code word corresponding to the encoding circuit and outputs the connected radio row numbers as radio frame data.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a digital wireless communication circuit, and more particularly to an error correction encoding circuit, an error correction decoding circuit and a method of a transmission / reception apparatus.

  In digital communication, error correction coding is performed on the transmission side and error correction decoding is performed on the reception side for the purpose of reducing errors in communication data generated on the communication path. That is, on the transmission side, error correction coding is performed on the information source data. In error correction encoding, redundant information is added by adding extra information to information source data by a method according to a certain rule, and error correction encoded data is generated. On the receiving side, error correction decoding for detecting and correcting an error occurring in the communication path is performed by a method according to a rule based on the error correction encoded data. As a result, it is possible to obtain information source data from which errors in communication data that have occurred on the communication path are eliminated.

  In particular, in the case of digital wireless communication, random errors and burst errors occur in communication data that is propagated due to thermal noise, fading, and interference waves in a radio wave propagation path that is a communication path. Therefore, in digital wireless communication, where the need for high-speed, wideband, and large-capacity data is increasing, the importance of error control technology is increasing in order to provide high-quality and highly reliable services.

  Patent Document 1 discloses a technique for introducing a plurality of encoding processes in parallel to an LDPC (Low Density Parity Check) code. Patent Document 1 is a technique for reducing a processing delay caused by an increase in coding time accompanying a decrease in coding rate, which is caused by improving the parallelism of coding. According to Patent Document 1, an LDPC code having a dual diagonal structure is modified to improve the LDPC code itself by changing the structure of an extended matrix, and a plurality of groups of parity bits can be calculated simultaneously. Yes.

In Patent Document 2, commercially available BPSK (Binary Phase Shift Keying:
There is shown a method of realizing soft decision decoding by a multi-level modulation method of four or more values using a soft decision decoding LSI (Large Scale Integration) compatible with a two-phase phase shift keying) method.

  Patent Document 3 does not mention the modulation multi-level number, but discloses a technique for realizing high-throughput decoding so as not to degrade the decoding performance of soft decision decoding with high error correction capability but large calculation amount as much as possible. Has been. According to Patent Document 3, a hard decision decoding algorithm is applied to perform hard decision decoding, and a soft decision algorithm is applied to only received words that cannot be subjected to hard decision decoding. Yes.

International Publication No. 2009/060627 JP 2002-064579 A JP 2009-152654 A

  In digital wireless communication, transmission capacity is increased in the direction of increasing the number of multi-levels in the multi-level modulation method and in the direction of increasing the speed of FSCLK (Frequency of Symbol Clock). For example, 2048QAM (Quadrature Amplitude Modulation) with a multi-value number of 2048 (symbol size = 11 bits) and 4096QAM with a multi-value number of 4096 (symbol size = 12 bits) are also in the stage of practical use. Also in the error correction coding circuit / error correction decoding circuit of the digital communication transmitting / receiving device, in order to cope with such an increase in transmission capacity, it is required to improve the processing amount per unit time, that is, the processing capacity. It has been.

  The technique disclosed in Patent Document 1 can improve the processing capability by introducing a plurality of encoding processes in parallel. However, this technique attempts to improve the LDPC code itself by changing the structure of the extended matrix. Therefore, this technique is effective only for a specific block code called an LDPC code, and there is a problem that it lacks versatility.

  Patent Document 2 and Patent Document 3 do not refer to the processing capability of the encoding / decoding circuit itself, but are techniques for dealing with the required wireless transmission capacity by devising a method of using the decoding circuit.

  Although the technique disclosed in Patent Document 2 realizes soft-decision decoding by a multi-level modulation system of four or more levels, it is necessary to increase the serial operation clock frequency by the multi-level number. For example, when applying to 256QAM, an operation speed of 8 times the symbol rate is required. Therefore, there is a problem that the high-speed clock operation becomes a bottleneck and cannot withstand the increase in transmission capacity.

  The technique disclosed in Patent Document 3 has a problem that the hard-decision decoding circuit as the main decoding means has an upper limit of processing capability and cannot withstand the increase of the modulation multi-level number.

  An object of the present invention is to solve the above-mentioned problems, and can be applied to an arbitrary block code. Error correction that can improve the processing capacity of error correction encoding / decoding in response to an increase in transmission capacity It is an object to provide an encoding circuit, an error correction decoding circuit, and a method.

  In order to achieve the above object, an error correction coding circuit according to an aspect of the present invention performs error correction coding processing on input information data to obtain a predetermined symbol size (n) and a code symbol. Encoding means comprising a plurality of parallel encoding circuits that generate codewords of block codes having a number (p) as basic codes, and a symbol size corresponding to the modulation multi-level number of the output radio frame data ( m1), and the information data is transferred to each encoding circuit of the encoding means, each of which is assigned an arbitrary positive integer (m2, m3... mk) as the number of fractional arrays. From the data distribution means for distributing to the corresponding encoding circuit according to the number of fractional arrangements, the number of fractional arrangements corresponding to the symbol size (n) of the basic code (m2, m3,. mk), the basic code is read out as the first code word at a clock operating rate that operates at the number of clocks of the ratio (m2 / n, m3 / n... mk / n), and the number of code bits constituting the basic code Code length frame generating means for outputting a code length pulse for each number of clocks corresponding to (n × p), and provided corresponding to each encoding circuit of the encoding means, and the code length from the corresponding encoding circuit The first code word read by the frame generation means is input and processed at a clock operating rate of 100%, and the code number assigned to the corresponding encoding circuit in units of the number of clocks of the cycle of the code length pulse. Radio sequence number conversion means for outputting a second codeword having the number of radio sequences of the fractional arrangement number, and a radio sequence of the second codeword corresponding to each encoding circuit output by the radio sequence number conversion means A third codeword combining numbers And having a bit coupling means for outputting as the radio frame data.

  In addition, the error correction coding method according to another aspect of the present invention outputs a total to each of a plurality of parallel coding circuits that perform error correction coding processing on input information data. Arbitrary positive integers (m2, m3... Mk) determined to have a symbol size (m1) corresponding to the modulation level of radio frame data are assigned as the number of fractional arrays, and according to the number of fractional arrays The information data is distributed to the corresponding encoding circuit, and the encoding circuit performs error correction encoding processing on the information data to obtain a predetermined symbol size (n) and the number of code symbols (p ) Is generated as a basic code, and the ratio (m 2 / m 2) of the corresponding number of array elements (m 2, m 3... Mk) to the symbol size (n) of the basic code is generated from each encoding circuit. n, m3 / n ... The basic code is read out as a first code word at a clock operation rate that operates at a clock number of mk / n), and a code length pulse is generated for each clock number corresponding to the number of code bits (n × p) constituting the basic code. The first code word read from the corresponding encoding circuit is processed at a clock operation rate of 100% and assigned to the corresponding encoding circuit in units of the number of clocks of the cycle of the code length pulse. A second codeword having the number of radio sequences of the divided array number is output, and a third codeword in which the number of radio sequences of the output second codeword is combined is output as the radio frame data It is characterized by doing.

  Furthermore, an error correction decoding circuit according to another aspect of the present invention is configured to perform error correction on a basic code that is a code word of a block code having a predetermined symbol size (n) and the number of code symbols (p). Decoding means having a plurality of decoding circuits that perform decoding processing and generate decoded information data in parallel, and a radio having the number of radio columns of a symbol size (m1) corresponding to a predetermined modulation multi-level number A radio string corresponding to the number of arrays, which is an arbitrary positive integer (m2, m3... Mk), determined so that the frame data is inputted and the sum is the symbol size (m1) of the radio frame data. A bit separation means for outputting a first code word having a number; and input of the radio frame data, and a code length pulse for each number of clocks corresponding to the number of code bits (n × p) constituting the basic code Fre Synchronization detection means, and corresponding to each decoding circuit of the decoding means, having the code length pulse output by the frame synchronization detection means and the corresponding number of radio sequences output by the bit separation means The first code word is inputted, and the ratio (m 2, m 3,..., Mk) of the corresponding number of array elements (m 2, m 3,. / n, m3 / n... mk / n) at a clock operation rate that operates at a clock number, the first codeword is converted to a second codeword having the symbol size of the basic code The reverse of the number of radio columns to be output to the decoding circuit and the inverse of the data that is decoded and read out from the decoding circuits of the decoding means in the order corresponding to the number of divided arrays Having distribution means, Features.

  In addition, an error correction decoding method according to another aspect of the present invention provides a basic code which is a code word of a block code having a predetermined symbol size (n) and the number of code symbols (p) to be input, provided in parallel. The decoding circuit that performs error correction decoding processing to generate decoded information data so that the total becomes a symbol size (m1) corresponding to the modulation multi-level number of the input radio frame data. A first code having a predetermined number of arrangements of arbitrary positive integers (m 2, m 3,... Mk), assigned the radio frame data, and having a number of radio columns corresponding to the number of arrangements A word is output, and a code length pulse is output for each number of clocks corresponding to the number of code bits (n × p) constituting the basic code based on the radio frame data, and the code length pulse and the fractional array are output Before according to the number A first codeword is input, and the ratio (m2 / m2) of the corresponding number of fractional arrays (m2, m3... Mk) to the symbol size (n) of the basic code in units of the number of clocks of the period of the code length pulse. n, m3 / n... mk / n) at a clock operation rate that operates at the number of clocks, the first codeword is converted to a second codeword having the symbol size of the basic code, and corresponding Output to the decoding circuit to which the number of partial arrays is assigned, and read out the decoded information data from each of the decoding circuits provided in parallel in the order according to the number of partial arrays, and output the combined data It is characterized by that.

  The present invention can be applied to arbitrary block codes, and can cope with an increase in transmission capacity and improve the processing capacity of error correction coding / decoding.

It is a block diagram which shows the structure of 1st Embodiment of the error correction encoding circuit of this invention. It is a flowchart which shows operation | movement of 1st Embodiment of the error correction encoding method of this invention. It is a block diagram which shows the structure of 1st Embodiment of the error correction decoding circuit of this invention. It is a flowchart which shows operation | movement of 1st Embodiment of the error correction decoding method of this invention. It is a block diagram which shows the structure of 2nd Embodiment of the error correction encoding circuit of this invention. It is a block diagram which shows the structure of embodiment of the communication apparatus containing the error correction encoding circuit of this invention. It is a conceptual diagram which shows the format example of the basic code which is a codeword of the block code which each encoding circuit of the error correction encoding circuit of 2nd Embodiment produces | generates. It is a conceptual diagram which shows the relationship of FSCLK in the information data input into the error correction encoding circuit of 2nd Embodiment, the valid data flag, and the validity / invalidity of a data stream. It is a conceptual diagram explaining the example of distribution of the information data to each encoding circuit in a data distribution circuit. It is a conceptual diagram which shows the timing which a codeword pulse is output regarding each encoding circuit. It is a timing chart which shows a FIFO read signal corresponding to a clock operation rate. It is a conceptual diagram which shows the codeword symbol read from each FIFO with the applied clock operation rate. It is a conceptual diagram which shows the relationship between the 1st codeword read from each FIFO queue, and the number of clocks of the period of a code length pulse. It is a conceptual diagram which shows the example of a format of the 2nd codeword which a radio sequence number conversion circuit outputs. It is a conceptual diagram which shows the example of a format of the codeword which a specific encoding circuit produces | generates in the modification of 2nd Embodiment of the error correction encoding circuit of this invention. It is a block diagram which shows the structure of another modification of 2nd Embodiment of the error correction encoding circuit of this invention. It is a flowchart which shows operation | movement of 2nd Embodiment of the error correction encoding method of this invention. It is a block diagram which shows the structure of 2nd Embodiment of the error correction decoding circuit of this invention. It is a block diagram which shows the structure of embodiment of the communication apparatus containing the error correction decoding circuit of this invention. It is a flowchart which shows operation | movement of 2nd Embodiment of the error correction decoding method of this invention.

  An embodiment for carrying out the present invention will be described with reference to the drawings.

  The embodiment is an exemplification, and the disclosed circuit, apparatus, and system are not limited to the configurations of the following embodiment.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a first embodiment of an error correction coding circuit of the present invention.

  The error correction encoding circuit 1 according to the first embodiment includes a data distribution unit 11, an encoding unit 12, a radio sequence number conversion unit 13, a code length frame generation unit 14, and a bit combination unit 15.

  Information data obtained by digitally encoding a signal of an information source such as sound, data, and video is input to the error correction encoding circuit 1. The error correction coding circuit 1 performs error correction coding processing on the input information data and outputs it as radio frame data having a symbol size corresponding to a predetermined modulation multilevel number. The radio frame data output from the error correction coding circuit 1 is subjected to predetermined modulation as a transmission signal by a modulation circuit (not shown).

  In the error correction coding circuit 1 of the first embodiment, the coding means 12 performs a plurality of parallel coding circuits 121 that perform error correction coding processing on input information data to generate a predetermined basic code. Prepare for. Each encoding circuit 121 generates a block code codeword having a predetermined symbol size (n) and the number of code symbols (p) as a basic code. That is, in the basic code, a continuous group of n bits (n columns) is used as one symbol, and a sequence of n × p bits composed of p symbols is used as one code word.

  Each encoding circuit 121 has an arbitrary positive integer (m2, m3... Mk) determined so that the sum becomes a symbol size (m1) corresponding to the modulation multi-level number of the output radio frame data. ) Is assigned as the number of minute sequences.

  The data distribution means 11 distributes the input information data to the respective encoding circuits 121 according to the number of arrays. In FIG. 1, it is assumed that the number of arrays m2, m3, and mk is assigned in order from the top of the three encoding circuits 121 shown in the figure.

  The code length frame generation means 14 reads the basic code from each encoding circuit 121 as the first code word, and generates a code length pulse for each clock number corresponding to the number of code bits (n × p) constituting the basic code. Output.

  Here, the code length frame generation means 14 performs reading at a clock operation rate corresponding to the allocated number of arrays. The clock operation rate according to the number of allocated arrangements is the ratio (m2 / n, m3 / n,...) Of the corresponding number of arrangements (m2, m3... Mk) to the symbol size (n) of the basic code. It means that it operates with the number of clocks of mk / n).

  The radio sequence number conversion means 13 is provided corresponding to each encoding circuit of the encoding means 12 and inputs the first code word read by the code length frame generation means 14 from the corresponding encoding circuit 121. And processing at a clock operating rate of 100%. Then, the radio sequence number conversion means 13 outputs a second codeword having the number of radio sequences of the number of arrangements allocated to the corresponding encoding circuit in units of the number of clocks of the cycle of the code length pulse. Note that processing at a clock operation rate of 100% means that the processing operation is performed corresponding to each clock of the cycle of the code length pulse.

  That is, the first code word is the number of clocks of the ratio (m2 / n, m3 / n... Mk / n) of the number of divided arrays (m2, m3... Mk) to the symbol size (n) of the basic code. Therefore, the density of code symbols existing within the number of clocks of the code length pulse period is low. However, the first code word has the same symbol size (n) as the basic code.

  On the other hand, since the second code word is processed at a clock operation rate of 100%, there is valid bit data corresponding to each clock of the cycle of the code length pulse as an encoded bit string. However, the number of columns of the second code word is the number of arrays allocated.

  The bit combination means 15 outputs the third code word output from the wireless sequence number conversion means 13 and combined with the number of wireless sequences of the second code word corresponding to each encoding circuit 121 as radio frame data.

  That is, since each radio column number converting means 13 outputs radio frame data having the allocated column number, the number of radio columns (symbol size) corresponding to the modulation multi-level number required by combining them is output. ) Radio frame data is obtained.

  The error correction coding circuit 1 of the first embodiment can improve the processing capability by using in parallel the coding circuit 121 that performs error correction coding processing in the coding means 12 to generate a block code. it can. That is, it is possible to determine the parallel number according to the symbol size corresponding to the modulation multi-level number required for the radio frame data to be output, and to distribute the processing in each encoding circuit 121. And as each encoding circuit 121, arbitrary encoding circuits can be used.

  As described above, the error correction coding circuit of the present embodiment can be applied to any block code, and can cope with the increase in transmission capacity and improve the error correction coding processing capability.

  FIG. 2 is a flowchart showing the operation of the first embodiment of the error correction coding method of the present invention.

  In the error correction encoding method of the first embodiment, first, the number of arrays to be processed is set in each of the encoding circuits that perform the error correction encoding process on the input information data provided in parallel. Assign (S101). Here, the number of fractional arrays is an arbitrary positive integer (m2, m3,...) Determined so that the sum is the symbol size (m1) corresponding to the modulation multi-level number of the output radio frame data. mk).

  The input information data is distributed to the corresponding encoding circuits according to the number of arrangements (S102).

  The encoding circuit performs error correction encoding processing on the information data to generate a code word of a block code having a predetermined symbol size (n) and the number of code symbols (p) as a basic code (S103).

  From each encoding circuit, the basic code is read as the first code word, and a code length pulse is output for each clock number corresponding to the number of code bits (n × p) constituting the basic code (S104).

  Here, the basic code is read at a clock operation rate corresponding to the allocated number of arrays. The clock operation rate according to the number of allocated arrays is the ratio (m2 / n) of the number of corresponding arrays (m2, m3... Mk) to the symbol size (n) of the basic code processed by the encoding circuit. , M3 / n... Mk / n).

  The first code word read from the corresponding encoding circuit is processed at a clock operation rate of 100%, and the number of arrays allocated to the corresponding encoding circuit in units of the number of clocks of the cycle of the code length pulse. A second codeword having the number of radio trains is output (S105). Note that processing at a clock operation rate of 100% means that the processing operation is performed corresponding to each clock of the cycle of the code length pulse.

  That is, the first code word has the same symbol size (n) as the basic code, although the density of code symbols existing within the number of clocks of the code length pulse period is low.

  By processing this with a clock operation rate of 100%, the encoded bit string has the number of radio columns corresponding to the number of divided arrays in which valid bit data exists corresponding to each clock of the cycle of the code length pulse. Converted to a second codeword.

  A third code word obtained by combining the number of radio strings of the second code word is output as radio frame data (S106). That is, since radio frame data having the allocated number of columns is output, radio frame data having the number of radio columns (symbol size) corresponding to the required modulation multi-level number is obtained by combining them.

  The error correction coding method of the first embodiment can improve the processing capability by using in parallel an encoding circuit that performs error correction coding processing to generate a block code. That is, it is possible to determine the parallel number according to the symbol size corresponding to the modulation multi-level number required for the radio frame data to be output, and to distribute the processing in each encoding circuit. An arbitrary encoding circuit can be used as each encoding circuit.

  As described above, the error correction coding method of the present embodiment can be applied to arbitrary block codes, and can cope with an increase in transmission capacity and improve the error correction coding processing capability.

  FIG. 3 is a block diagram showing the configuration of the first embodiment of the error correction decoding circuit of the present invention.

  The error correction decoding circuit 2 according to the first embodiment includes a bit separation unit 21, a frame synchronization detection unit 22, a radio column number inverse conversion unit 23, a decoding unit 24, and a data reverse distribution unit 25. .

  Radio frame data having a symbol size corresponding to a predetermined modulation multi-level number of a received signal demodulated by a demodulation circuit (not shown) is input to the error correction decoding circuit 2. The error correction decoding circuit 2 performs error correction decoding processing on the block code based on the input radio frame data, and outputs information data in which a data error generated in the transmission process is corrected.

  In the error correction decoding circuit 2 of the first embodiment, the decoding unit 24 includes a plurality of decoding circuits 241 that perform error correction decoding processing on input block codes and generate decoded information data. Prepare in parallel. Each decoding circuit 241 processes a code word of a block code having a predetermined symbol size (n) and the number of code symbols (p) as a basic code.

  That is, in the basic code, a continuous group of n bits (n columns) is used as one symbol, and a sequence of n × p bits composed of p symbols is used as one code word.

  Each decoding circuit 241 has an arbitrary positive integer (m2, m3... Mk) determined so that the sum is the symbol size (m1) corresponding to the modulation multi-level number of the input radio frame data. ) Is assigned.

  When bit frame means 21 receives radio frame data of symbol size m1, it outputs a first codeword having the number of radio columns (m2, m3... Mk) corresponding to the number of divided arrays.

  The frame synchronization detection means 22 inputs radio frame data and outputs a code length pulse for each clock number corresponding to the number of code bits (n × p) constituting the basic code.

  The radio column number inverse conversion means 23 is provided corresponding to each decoding circuit of the decoding means 24.

  The radio sequence number inverse conversion means 23 receives the code length pulse output from the frame synchronization detection means and the first code word having the corresponding radio sequence number output from the bit separation means 21, and performs the sequence number conversion. The second code word is output.

  The radio sequence number inverse conversion means 23 processes the first codeword at a clock operation rate corresponding to the allocated number of arrangements in units of the number of clocks of the code length pulse period, and has the symbol size of the basic code The second code word is output. The clock operation rate according to the number of allocated arrays is the ratio of the corresponding number of array elements (m2, m3... Mk) to the symbol size (n) of the basic code processed by the decoding circuit 241 (m2 / n, m3 / n... mk / n).

  That is, the first code word has valid bit data corresponding to each clock of the cycle of the code length pulse as the encoded bit string, and has the number of columns corresponding to the number of divided arrays. The radio sequence number inverse conversion means 23 processes it at a clock operation rate corresponding to the number of divided sequences, so that the density of code symbols existing within the number of clocks in the cycle of the code length pulse is low, but the same as the basic code Convert to a second codeword having symbol size (n).

  The second codeword output from the radio sequence number inverse conversion means 23 is subjected to error correction decoding processing by the corresponding decoding circuit 241 to generate decoded information data.

  The data reverse distribution unit 25 reads the decoded information data from the respective decoding circuits of the decoding unit 24 in the order corresponding to the number of divided arrays, and outputs the combined data.

  The error correction decoding circuit 2 according to the first embodiment uses the decoding circuit 241 that performs error correction decoding processing in the decoding unit 24 to decode the block code into information data, and improves the processing capability. be able to.

  That is, the number of parallels can be determined according to the symbol size corresponding to the modulation multi-level number required for the input radio frame data, and the processing can be distributed by each decoding circuit 241. An arbitrary decoding circuit can be used as each decoding circuit 241.

  As described above, the error correction decoding circuit of the present embodiment can be applied to any block code, and can cope with an increase in transmission capacity and improve the error correction decoding processing capability.

  FIG. 4 is a flowchart showing the operation of the first embodiment of the error correction decoding method of the present invention.

  In the error correction decoding method of the first embodiment, first, a decoding circuit that performs error correction decoding processing on input basic codes provided in parallel and generates decoded information data, The number of arrays to be processed is assigned (S201). Here, the number of fractional arrays is an arbitrary positive integer (m2, m3,...) Determined so that the sum is the symbol size (m1) corresponding to the modulation multilevel number of the input radio frame data. mk). The basic code is a code word of a block code having a predetermined symbol size (n) and the number of code symbols (p).

  Radio frame data is input, and a first codeword having the number of radio columns corresponding to the number of divided arrays is output (S202).

  Based on the radio frame data, a code length pulse is output for each number of clocks corresponding to the number of code bits (n × p) constituting the basic code (S203).

  The code length pulse and the first code word corresponding to the number of divided sequences are input, and the first code word is converted to the basic code in units of the number of clocks in the cycle of the code length pulse with the clock operation rate corresponding to the number of divided sequences. Convert to a second codeword having a symbol size. The clock operation rate according to the number of fractional arrays is the ratio (m2 / n, m3 / m) of the number of fractional arrays (m2, m3... Mk) to the symbol size (n) of the basic code processed by the decoding circuit. n ... mk / n). The converted second codeword is output to the decoding circuit to which the corresponding number of arrays is assigned (S204).

  That is, the first code word has valid bit data corresponding to each clock of the cycle of the code length pulse as the encoded bit string, and has the number of columns corresponding to the number of divided arrays. It is processed at a clock operation rate according to the number of minute arrangements, and the density of code symbols existing within the number of clocks in the period of the code length pulse is thin, but has the same symbol size (n) as the basic code Are converted into two codewords.

  Each decoding circuit performs error correction decoding processing on the second codeword to generate decoded information data (S205).

  The decoded information data is read from each decoding circuit in the order corresponding to the number of divided arrays, combined and output (S206).

  The error correction decoding method of the first embodiment can improve the processing capability by using in parallel a decoding circuit that performs error correction decoding processing on a block code and outputs information data. That is, it is possible to determine the parallel number according to the symbol size corresponding to the modulation multi-level number required for the input radio frame data, and to distribute the processing in each decoding circuit. An arbitrary decoding circuit can be used as each decoding circuit.

  As described above, the error correction decoding method of the present embodiment can be applied to arbitrary block codes, and can cope with an increase in transmission capacity and improve the error correction decoding processing capability.

  Next, a second embodiment will be described.

(Error correction encoding circuit of the second embodiment)
FIG. 5 is a block diagram showing the configuration of the second embodiment of the error correction coding circuit of the present invention.

  The error correction encoding circuit 10 of the second embodiment includes a data distribution circuit 110, an encoding unit 120, a radio string number conversion circuit 130, a FIFO (First In First Out) delay circuit 135, a code length frame generation circuit 140, and bits. The coupling circuit 150 is included.

  In order to show the positioning of the error correction coding circuit of the present invention, a block diagram showing the configuration of an embodiment of a communication apparatus including the error correction coding circuit of the present invention is shown in FIG.

  The communication apparatus 3 according to this embodiment includes a signal transmission unit 30 including an information source coding circuit 301, an error correction coding circuit 302, a modulation circuit 303, and a transmission circuit 304. Here, the error correction coding circuit 302 in the figure corresponds to the error correction coding circuit 1 of the first embodiment described above or the error correction coding circuit 10 of the second embodiment described later.

  In the signal transmission unit 30 of the communication device 3, information source signals such as voice, data, and video are converted into information data digitally encoded by the information source encoding circuit 301. This information data is processed as a baseband signal. The error correction encoding circuit 302 performs error correction encoding processing on the input information data, and outputs it as radio frame data (encoded bit string) having a symbol size corresponding to a predetermined modulation multilevel number. The radio frame data output from the error correction coding circuit 302 is converted into an Ich / Qch data stream including data symbols of signal points having a predetermined modulation multilevel number before the modulation circuit 303. Further, in the subsequent stage of the modulation circuit 303, the carrier wave is modulated based on the data symbols of the analog-converted Ich / Qch data stream. The modulated carrier wave is output to the transmission circuit 304. The transmission circuit 304 performs processing such as frequency up-conversion and amplification, and is transmitted as a radio wave from the antenna. Note that Ich / Qch is an abbreviation for (in-phase: in-phase component) / (quadrature-phase: quadrature component).

  The preceding stage of the modulation circuit 303 that converts the radio frame data output from the error correction coding circuit 302 into an Ich / Qch data stream including signal point data symbols is shown as a signal point conversion circuit 210 in FIG.

  In the error correction encoding circuit 10 of the second embodiment shown in FIG. 5, the encoding unit 120 corresponds to the encoding means 12 of the error correction encoding circuit 1 of the first embodiment.

  The encoding unit 120 includes a plurality of parallel encoding circuits that perform error correction encoding processing on input information data and generate a basic code that is a code word of a predetermined block code. That is, the parallel number of the encoding circuit to be provided in the encoding unit 120 is determined according to the symbol size corresponding to the modulation multi-level number required for the radio frame data to be output, and each code arranged in parallel as such The error correction encoding process is distributed in the conversion circuit.

  The encoding circuit is handled as an IP (Intellectual Property) macro that is a commonly used circuit block, and any encoding circuit can be used as long as it is an encoding circuit that handles block codes. For example, an encoding circuit that handles block codes such as BCH (Bose-Chaudhuri-Hocqenghem) code, Reed-Solomon (RS) code, and low density parity check (LDPC) code can be used.

  Also, in the encoding unit 120, a FIFO (First In First Out) queue is provided corresponding to the encoding circuit, and the basic code generated by each encoding circuit is output to the corresponding FIFO queue.

  Here, in the second embodiment, 2048QAM modulation scheme in which the number of radio columns (symbol size of radio frame) is 11 is applied to the radio frame data to be output. The encoding circuit to be used is assumed to generate a code word of a block code having a symbol size (n) = 8 bits and the number of code symbols (p) = 255 as a basic code. Note that the number of code bits (8 × 255 = 2040 bits) of the basic code corresponds to the number of bits (frame length) of the transmitted radio frame.

  FIG. 7 shows a conceptual diagram of a format example of a basic code that is a code word of a block code generated by the encoding circuit. In other words, the basic code is a sequence of n × p = 8 × 255 = 2040 bits composed of p = 255 symbols, with a continuous cluster of n = 8 bits (8 columns) as one symbol. It is a word. Of course, the symbol includes both information bits and check bits, and is considered as a code word having redundancy subjected to encoding processing.

  The number of parallel coding circuits to be provided in the coding unit 120 is determined according to the number of arrays to be borne by each coding circuit.

  The number of divided arrays is the number of radio columns (symbol size of radio frame) corresponding to the number of modulation multi-values of the output radio frame data determined to be distributed and processed by a plurality of encoding circuits. It is the number of columns. That is, each encoding circuit has an arbitrary positive integer (m2, m3,...) Determined so that the sum is a symbol size (m1) corresponding to the modulation multi-level number of the output radio frame data. mk) is assigned the number of arrays. The number of arrangements is assumed to be not more than the symbol size (n) of the basic code.

  Therefore, in the second embodiment, m1 = 11 may be arbitrarily determined under the condition of n = 8 or less. Here, it is assumed that processing is performed by three parallel encoding circuits with distribution of m2 = 2, m3 = 3, and m4 = 6.

  Since the distribution may be arbitrarily determined, the present invention is not limited to the above distribution, and three parallel encoding circuits may be used in the distribution of m2 = 3, m3 = 4, and m4 = 4.

  Further, although the symbol size (n) of the basic code processed by the encoding circuit is set to 8, when an encoding circuit that processes a block code having a symbol size (n) of 4 is used, m2 = 2, You may make 4 parallel by the distribution of m3 = 3, m4 = 3, m5 = 3. Needless to say, even in this case, three parallel arrangements may be made by distributing m2 = 3, m3 = 4, and m4 = 4.

  In this way, among the modulation schemes supported by the system, the number of parallel arrangements is determined in advance according to the symbol size of the radio frame corresponding to the modulation scheme having the maximum multi-level number, and the necessary number of parallel encodings is performed. A circuit should be deployed. Information relating to the number of partial arrangements is stored as parameter information in a control unit (not shown) of the communication apparatus, and is notified as information on the number of partial arrangements from the control unit.

  As described above, the encoding unit 120 is provided with “code 1” encoding circuit, “code 2” encoding circuit, and “code 3” encoding circuit in parallel as the encoding circuit 1201. Each encoding circuit 1201 is provided with a corresponding FIFO queue 1202. Note that the “code 1” coding circuit, the “code 2” coding circuit, and the “code 3” coding circuit are not particularly referred to, and the coding circuit 1201 is a generic term.

  In the error correction encoding circuit 10 of the second embodiment shown in FIG. 5, the data distribution circuit 110 corresponds to the data distribution means 11 of the error correction encoding circuit 1 of the first embodiment.

  A plurality of signal lines are input to the data distribution circuit 110. The input signal line Data Stream is a data stream of information data and is input in the form of 16-bit (2-byte) parallel data. The input signal line Frame Pulse is a frame pulse indicating a frame break. The input signal line Data Valid is a valid data flag indicating that the data stream is valid data with respect to the rising edge of FSCLK (Frequency of Symbol Clock).

  The data distribution circuit 110 is provided with information on the number of arrangements allocated to each of the arranged encoding circuits 1201 as a parameter. Here, it is assumed that the number of arrays of m2 = 2 is allocated to the “code 1” encoding circuit, m3 = 3 is allocated to the “code 2” encoding circuit, and m4 = 6 is allocated to the “code 3” encoding circuit. To do.

  FIG. 8 is a conceptual diagram showing the relationship between FSCLK, valid data flag, and valid / invalid of data stream in input information data.

  Here, it is assumed that the transmission capacity data uniquely determined by the coding rate processed by the coding circuit and the modulation method on the output side are controlled to be input.

  The data distribution circuit 110 converts the input information data (valid data of the data stream) into each coding circuit 1201 (“code 1” coding circuit, “code 2” coding circuit, and "Code 3" encoding circuit).

  FIG. 9 is a conceptual diagram illustrating an example of information data distribution to each encoding circuit 1201 in the data distribution circuit 110.

  In FIG. 9, the relationship between the frame pulse (Frame Pulse), the valid data flag (Data Valid), and the data stream (Data Stream) is shown at the top. That is, the head of a frame that is a cluster of data is identified by a frame pulse, and valid data of a data stream is recognized as information data by a valid data flag. As described above, since the data stream is input in the form of 16-bit (2 bytes) parallel data, the information data in the places with numbers in the figure means 8-bit (1 byte) parallel data. In the second embodiment, since each encoding circuit 1201 handles a code word having a symbol size of 8 bits, it is assumed that information data is processed in units of bytes.

  A state in which pieces of information data 1 to 22 recognized as valid data are distributed to the “code 1” coding circuit, the “code 2” coding circuit, and the “code 3” coding circuit is shown in the middle stage of FIG. It is shown.

  Since the code number 1 is assigned to the “code 1” encoding circuit, the first two bytes of information data 1 and 2 are distributed. Since the code number 2 is assigned to the “code 2” encoding circuit, the next 3 bytes of information data 3 to 5 are distributed. Since the number of arrangement m4 = 6 is assigned to the “code 3” encoding circuit, the next 6 bytes of information data 6 to 11 are distributed.

  When the distribution up to the “code 3” encoding circuit is completed, the process returns to the “code 1” encoding circuit, and information data is distributed at the same rate. It should be noted that at the timing when the information data 17 to 22 are distributed to the “code 3” encoding circuit, the next cluster of effective data is recognized and distributed to the “code 1” encoding circuit. .

  The data distribution circuit 110 repeats the distribution of the information data described above to each encoding circuit 1201.

  Further, the data distribution circuit 110 outputs an enable signal indicating the valid data position and a codeword pulse indicating a delimiter of the codeword processed by the encoding circuit 1201 to each encoding circuit 1201 in accordance with the distribution of the information data. . In FIG. 5, an enable signal line, a code word pulse signal line, and an 8-bit signal are supplied from the data distribution circuit 110 to the “code 1” coding circuit, the “code 2” coding circuit, and the “code 3” coding circuit, respectively. It is shown that parallel data signal lines are connected.

  The data distribution circuit 110 receives information data (byte data) corresponding to one codeword having a symbol size (n) = 8 bits and the number of code symbols (p) = 255 according to the coding rate processed by the coding circuit 1201. A code word pulse is output at the time of distribution to each encoding circuit.

  As described above, two pieces of information data are distributed to the “code 1” encoding circuit while counting 11 pieces of information data. For the “code 2” encoding circuit, 3 pieces of information data are distributed while 11 pieces of information data are counted. For the “code 3” encoding circuit, 6 pieces of information data are distributed while 11 pieces of information data are counted.

  That is, a code word pulse is output when the number of pieces of information data (byte data) distributed to each encoding circuit reaches an amount of information data corresponding to 255 code symbols of the basic code.

  Assuming that each encoding circuit performs the encoding process at the same encoding rate, the “code 1” encoding circuit is performed twice, the “code 2” encoding circuit is performed three times, and the “code 3” encoding circuit. If six codeword pulses are output at the same time, the next codeword pulse is output to each encoding circuit at the same timing.

  FIG. 10 is a conceptual diagram showing the timing at which a code word pulse is output for each encoding circuit 1201.

  Some codeword pulses are output from the data distribution circuit 110 and others are output from each encoding circuit 1201 as described later.

  The code word pulse (first code word pulse) output from the data distribution circuit 110 is generated according to the coding rate processed by the coding circuit 1201, and the information data corresponding to one code word is generated in the coding circuit 1201. Means distributed. On the other hand, the code word pulse (second code word pulse) output from the encoding circuit 1201 is a symbol size (n) = 8 bits, which is a basic code generated by the encoding circuit 1201, and the number of code symbols (p) = This means that one code word of 255 has been output.

  In other words, in the case of the first codeword pulse output from the data distribution circuit 110, it corresponds to 255 codeword symbols corresponding to the coding rate within the time delimited by the first codeword pulse. Means that valid information data is included.

  In the case of the second codeword pulse output from the encoding circuit 1201, 255 valid codeword symbols (8 bits) are included in the time delimited by the second codeword pulse. Means that. Of course, effective information data / codeword symbols included between codeword pulses corresponding to each encoding circuit 1201 have a temporal density difference. In the following description, it is assumed that the codeword pulse is the second codeword pulse output from the encoding circuit 1201 unless otherwise specified.

  In addition, there is a code length pulse as information indicating the timing at which the output of the code word pulse output from each encoding circuit 1201 becomes the same. Within the time delimited by the code length pulse, there are two “code 1” coding circuits, three “code 2” coding circuits, and six “code 3” coding circuits. Code). The code length pulse will be described later.

  Each encoding circuit 1201 performs error correction encoding processing on the input information data, and outputs a basic code, which is a code word of the generated block code, to the corresponding FIFO queue 1202. At this time, the code word pulse described above is output.

  Each encoding circuit 1201 performs error correction encoding processing on information data at the input data rate. Further, the phase shift of the codeword pulse is absorbed by the FIFO queue 1202 and output from the FIFO queue 1202.

  In the error correction encoding circuit 10 of the second embodiment shown in FIG. 5, the code length frame generation circuit 140 corresponds to the code length frame generation means 14 of the error correction encoding circuit 1 of the first embodiment.

  The code length frame generation circuit 140 is provided with information on the number of arrangements allocated to each of the arranged encoding circuits as a parameter.

  The code length frame generation circuit 140 reads out the error correction encoded basic code as the first codeword from the FIFO queue 1202 corresponding to each encoding circuit 1201 provided in the encoding unit 120. The first code word read from each FIFO queue 1202 is sent to the corresponding radio string conversion circuit 130.

  The code length frame generation circuit 140 receives a code word pulse from one of the FIFO queues 1202, initializes the phase of each FIFO read signal (read), and reads the first code word to be read from each FIFO queue 1202. Match the beginning. In FIG. 5, the code word pulse output from the FIFO queue corresponding to the “code 1” encoding circuit is input.

  The code length frame generation circuit 140 generates a FIFO read signal at a clock operation rate corresponding to the allocated number of arrays, and performs reading from each FIFO queue 1202. The clock operation rate in accordance with the number of allocated arrays is the ratio (m2 / n, m) of the corresponding number of arrays (m2, m3, m4) to the symbol size (n) of the basic code generated by the encoding circuit 1201. m3 / n, m4 / n).

  In the case of the second embodiment, the symbol size (n) of the basic code is 8. The distribution array numbers (m2, m3, m4) are 2, 3, and 6, respectively. Therefore, a clock operating rate of 2/8 is applied to the “code 1” coding circuit. Similarly, a clock operating rate of 3/8 is applied to the “code 2” encoding circuit, and a clock operating rate of 6/8 is applied to the “code 3” encoding circuit.

  FIG. 11 is a timing chart showing a FIFO read signal corresponding to the clock operation rate.

  As shown in FIG. 11, two readings are performed during 8 clocks from the FIFO queue corresponding to the “code 1” encoding circuit to which the clock operating rate of 2/8 is applied. From the FIFO queue corresponding to the “code 2” encoding circuit to which the clock operating rate of 3/8 is applied, reading is performed three times during 8 clocks. Then, 6 readings are performed during 8 clocks from the FIFO queue corresponding to the “code 3” encoding circuit to which the clock operating rate of 6/8 is applied.

  FIG. 12 is a conceptual diagram showing codeword symbols read from each FIFO queue 1202 at an applied clock operation rate.

  As shown in FIG. 12, in the period of 8 clocks, two from the FIFO queue corresponding to the “code 1” encoding circuit, three from the FIFO queue corresponding to the “code 2” encoding circuit, and “code 3” code Six codeword symbols are read from the FIFO queue corresponding to the conversion circuit.

  The code length frame generation circuit 140 generates and outputs a code length pulse simultaneously with the reading of the first code word. The code length pulse is output for each number of clocks corresponding to the number of code bits (n × p) constituting the basic code. Therefore, in the second embodiment, a code length pulse is output every 8 × 255 = 2040 clocks. Further, the bit string (8 × 255 = 2040 bits) corresponding to the cycle of the code length pulse corresponds to the number of bits (frame length) of the transmitted radio frame.

  FIG. 13 is a conceptual diagram showing the relationship between the first code word read from each FIFO queue and the number of clocks in the cycle of the code length pulse. Since the first code word is read at a clock operation rate based on 8 clocks, it means that there are 255 cycles of 8 clocks between 2040 clocks, which is the number of clocks of the cycle of the code length pulse.

  The upper row shows the first code word read in the code length pulse cycle from the FIFO queue corresponding to the “code 1” coding circuit (m2 path data). The middle row shows the first code word read out from the FIFO queue corresponding to the “code 2” coding circuit at the code length pulse period (m3 path data). The lower row shows the first code word read out from the FIFO queue corresponding to the “code 3” coding circuit at the code length pulse period (m4 path data).

  From the FIFO queue corresponding to the “code 1” coding circuit, two code word symbols are read out at a cycle of 8 clocks. Therefore, 2 × 255 = 512 codeword symbols are read out during 8 clocks of 255 periods, which means that two first codewords are read out in the code length pulse period.

  Three codeword symbols are read out from the FIFO queue corresponding to the “code 2” encoding circuit at a cycle of 8 clocks. Accordingly, 3 × 255 = 765 codeword symbols are read out during 8 clocks of 255 periods, which means that three first codewords are read out in the code length pulse period.

  Six codeword symbols are read out from the FIFO queue corresponding to the “code 3” encoding circuit at a cycle of 8 clocks. Therefore, 6 × 255 = 1530 codeword symbols are read out in 8 clocks of 255 periods, which means that 6 first codewords are read out in the code length pulse period.

  As described above, the first codeword output from each encoding circuit 1201 includes 255 effective codeword symbols (8 bits) although there is a temporal density difference.

  The first code word and the code length pulse shown in FIG. 13 are input to the radio string number conversion circuit 130 provided corresponding to each encoding circuit 1201.

  In the error correction encoding circuit 10 of the second embodiment shown in FIG. 5, the radio column number conversion circuit 130 corresponds to the radio column number conversion means 13 of the error correction encoding circuit 1 of the first embodiment.

  The radio string number conversion circuit 130 is provided corresponding to each of the arranged encoding circuits 1201. The number-of-sequences information assigned to the corresponding encoding circuit 1201 is given to the radio column number conversion circuit 130 as a parameter.

  Note that the FIFO delay circuit 135 shown in FIG. 5 receives the FIFO read signal used for reading the first code word described above and inserts an enable signal with a delay equal to the delay until the corresponding read data is output. Is output to the corresponding radio column number conversion circuit 130.

  The radio sequence number conversion circuit 130 processes the input first codeword at a clock operation rate of 100%, performs sequence conversion processing in units of code length pulse periods, and outputs a second codeword. .

  That is, the radio sequence number conversion circuit 130 regards a unit in which a plurality of first codewords shown in FIG. 13 are collected for each code length pulse period as a new codeword, and processes it at a clock operation rate of 100%. Column conversion is performed, and the result is output as a second codeword. Note that processing at a clock operation rate of 100% means that the processing operation is performed corresponding to each clock of the cycle of the code length pulse.

  In other words, the column conversion is a bit data effective for each clock of the code length pulse cycle, with the symbol size (n) = 8 columns of a plurality of code words existing at different densities for each cycle of the code length pulse. Is a process of converting the format to the corresponding encoded bit string at a rate of 100%. Here, the encoded bit string is the number of bits (frame length) of the radio frame, and the number of converted columns is the number of arrays allocated to the corresponding encoding circuit 1201.

  FIG. 14 is a conceptual diagram illustrating a format example of the second codeword output from the radio column number conversion circuit 130.

  In the two first code words read from the FIFO queue corresponding to the “code 1” encoding circuit, there are 8 × 255 × 2 = 4080 bit data. When each bit data is made to correspond to each clock (2040 clock) of the cycle of the code length pulse, the second code word in two columns is generated in units of the number of clocks (frame length unit) of the cycle of the code length pulse.

  In the three first code words read from the FIFO queue corresponding to the “code 2” encoding circuit, there are 8 × 255 × 3 = 6120 bit data. When each bit data is made to correspond to each clock (2040 clock) of the cycle of the code length pulse, the second code word of 3 columns is generated in the number of clocks (frame length unit) of the cycle of the code length pulse.

  In the first six codewords read from the FIFO queue corresponding to the “code 3” encoding circuit, there are 8 × 255 × 6 = 1240 bit data. When each bit data is made to correspond to each clock (2040 clock) of the cycle of the code length pulse, the second code word of 6 columns is generated in units of the number of clocks (frame length unit) of the cycle of the code length pulse.

  As the data of the m2 path corresponding to the “code 1” encoding circuit, the second code word in two columns in the clock number unit (frame length unit) of the cycle of the code length pulse is shown in the upper part of FIG. As the data of the m3 path corresponding to the “code 2” coding circuit, the second code word of three columns in the clock number unit (frame length unit) of the cycle of the code length pulse is shown in the middle stage of FIG. Then, the second code word of 6 columns in the clock number unit (frame length unit) of the cycle of the code length pulse is shown in the lower part of FIG. 14 as m4 path data corresponding to the “code 3” encoding circuit. Yes.

  In this way, the radio column number conversion circuit 130 processes the first codeword read from the FIFO queue at a clock operation rate of 100%, and performs the corresponding encoding in units of the number of clocks in the cycle of the code length pulse. A second code word having the number of radio columns allocated to the circuit is output.

  Further, the radio sequence number conversion circuit 130 configures the basic code by using the first code word in which the number of basic codes having a symbol size (n) = 8 corresponding to the number of fractional arrays exists in units of the code length pulse period. It can be said that this is converted into a second code word having the number of columns corresponding to the number of fractional arrays. Here, the cycle of the code length pulse corresponds to the number of bits constituting the radio frame (frame length of the radio frame).

  In the error correction encoding circuit 10 of the second embodiment shown in FIG. 5, the bit combination circuit 150 corresponds to the bit combination means 15 of the error correction encoding circuit 1 of the first embodiment.

  The bit combination circuit 150 outputs, as radio frame data, a third code word output from the radio column number conversion circuit 130 and combined with the number of radio columns of the second code word corresponding to each encoding circuit.

  In other words, each radio column number conversion circuit 130 outputs radio frame data having the number of radio columns corresponding to the allocated number of columns, so that by combining them, it corresponds to the required modulation multilevel number. Radio frame data having the number of radio columns (symbol size) is obtained.

  As shown in FIG. 5, the radio frame data output from the bit combination circuit 150 is converted into a symbol stream by the signal point conversion circuit 210 and output as Ich data and Qch data. The signal point conversion circuit 210 is provided with data of a symbol size m1 (= 11) corresponding to the modulation multi-level number of the transmission signal to which the 2048QAM modulation method is applied from a control means (not shown).

  As described above, the error correction coding circuit 10 of the second embodiment uses the coding circuit 1201 that performs error correction coding processing in the coding unit 120 to generate a block code in parallel, and has a processing capability. Can be improved. That is, the number of parallels can be determined according to the symbol size corresponding to the modulation multi-level number required for the radio frame data to be output, and the processing can be distributed by each encoding circuit 1201.

  Since the number of arrays allocated to each encoding circuit 1201 is equal to or smaller than the symbol size of the block code handled by each encoding circuit 1201, any encoding circuit can be used as each encoding circuit 1201. For example, in the second embodiment, an encoding circuit corresponding to 256QAM with a symbol size (n) = 8 is used as a basic code, but an encoding circuit corresponding to 64QAM with n = 6 or 16QAM with n = 4 is used. May be used. As the symbol size of the encoding circuit is reduced, the number of arrays handled by each encoding circuit is reduced, and the parallel number is increased accordingly.

(Modification of Error Correction Encoding Circuit of Second Embodiment)
The second embodiment has been described on the assumption that the encoding circuits arranged in parallel handle code words having the same number of code symbols (p = 255). However, any of the encoding circuits arranged in parallel may generate a code word having a number of code symbols that is an integral multiple of a code word generated by another encoding circuit.

  For example, the “code 3” encoding circuit is an encoding circuit that generates a code word having twice the number of code symbols (p = 510) as a code word generated by another encoding circuit as shown in FIG. It doesn't matter.

  In this case, the code length pulse cycle may be 4080 clocks which is twice the 2040 clocks.

  When the cycle of the code length pulse is 4080 clocks, the first code word is read as follows.

  From the FIFO queue corresponding to the “code 1” coding circuit, four first code words are read in the code length pulse period. From the FIFO queue corresponding to the “code 2” coding circuit, six first code words are read out in the code length pulse period. Then, from the FIFO queue corresponding to the “code 3” coding circuit, six first code words are read in the code length pulse period.

  On the other hand, the second code word output from the radio column number conversion circuit 130 is as follows.

  There are 8 × 255 × 4 = 8160 bit data in the four first codewords read from the FIFO queue corresponding to the “code 1” encoding circuit. If each bit data is made to correspond to each clock (4080 clock) of the cycle of the code length pulse, the second code word in two columns is generated in frame length units corresponding to the number of clocks of the cycle of the code length pulse.

  In the first six code words read from the FIFO queue corresponding to the “code 2” encoding circuit, there are 8 × 255 × 6 = 1240 bit data. When each bit data is made to correspond to each clock (4080 clock) of the code length pulse period, three columns of second code words are generated in frame length units corresponding to the number of clocks of the code length pulse period.

  In the first six code words read from the FIFO queue corresponding to the “code 3” encoding circuit, there are 8 × 510 × 6 = 24480 bit data. If each bit data is made to correspond to each clock (4080 clock) of the cycle of the code length pulse, 6 columns of second code words are generated in frame length units corresponding to the number of clocks of the cycle of the code length pulse.

  In general, when the number of code bits is large, the error correction capability becomes high. Therefore, any of the coding circuits arranged in parallel can handle a code word having a number of code symbols that is an integral multiple of the code word handled by the other coding circuit, thereby correcting error correction as an error correction coding circuit. Ability improves.

(Another modification of the error correction coding circuit of the second embodiment)
FIG. 16 is a block diagram showing the configuration of another modification of the second embodiment of the error correction coding circuit of the present invention.

  This modification is an example when the symbol size (m1) of the output radio frame data is changed to the 32QAM modulation method of 5.

  In this case, since m1 = 5, it is possible to operate in parallel with the number of partial arrangements m2 = 2 and m3 = 3. Here, it is assumed that the “code 3” coding circuit in the configuration of FIG. 5 in which three coding circuits are arranged in parallel is not used. Other configurations are the same as those described with reference to FIG.

  In the data distribution circuit 110, the code length frame generation circuit 140, and the radio column number conversion circuit 130, m2 = 2 is assigned to the “code 1” encoding circuit and m 2 = 2 is assigned to the “code 2” encoding circuit. Information indicating that m3 = 3 is assigned is notified.

  Further, since the clock operation rate of the FIFO read signal is 4/8 or less, the frequency of the operation clock until writing to the FIFO queue can be ½ of FSCLK.

  Also in this configuration, the first code word is read as follows, as in the description of the second embodiment.

  From the FIFO queue corresponding to the “code 1” coding circuit, two first code words are read in the code length pulse period. Then, three first code words are read out in the code length pulse period from the FIFO queue corresponding to the “code 2” coding circuit.

  The second code word output from the radio column number conversion circuit 130 is as follows.

  In the two first code words read from the FIFO queue corresponding to the “code 1” encoding circuit, there are 8 × 255 × 2 = 4080 bit data. When each bit data is made to correspond to each clock (2040 clock) of the cycle of the code length pulse, two columns of second code words are generated in frame length units corresponding to the number of clocks of the cycle of the code length pulse.

  In the three first code words read from the FIFO queue corresponding to the “code 2” encoding circuit, there are 8 × 255 × 3 = 6120 bit data. When each bit data is made to correspond to each clock (2040 clock) of the code length pulse period, three columns of second code words are generated in units of frame length corresponding to the number of clocks of the code length pulse period.

  In this way, if the coding circuit configuration to be deployed is determined in correspondence with the modulation scheme that maximizes the number of modulation multilevels to be applied, the configuration and operation can be dynamically changed according to changes in the modulation multilevel number. Is possible.

  For example, it can also be used for adaptive modulation in which the modulation scheme is changed according to the state of communication quality of the radio wave propagation path. When used for adaptive modulation, the correspondence between the number of arrangements corresponding to the symbol size of the radio frame corresponding to the modulation multi-level number of each modulation method and the encoding circuits arranged in parallel is determined in advance, and is not shown. It is stored as a parameter in the control means. Then, when the control means knows the change of the modulation method, the corresponding array number information may be notified to each circuit described above. Further, as described above, control for changing the operation clock may be performed as necessary.

(Operation Flow of Error Correction Encoding Method of Second Embodiment)
FIG. 17 is a flowchart showing the operation of the second embodiment of the error correction coding method of the present invention.

  First, the number of arrangements of m2 = 2, m3 = 3, and m4 = 6 is allocated to the coding circuits arranged in parallel so that the total becomes the symbol size m1 = 11 of the radio frame (S301). That is, a 2048QAM modulation scheme with a symbol size m1 = 11 is applied to the radio frame data to be output, and the encoding circuit uses a block code with a symbol size (n) = 8 bits and the number of code symbols (p) = 255. Is assumed to be generated as a basic code.

  The input information data (valid data of the data stream) is distributed to each encoding circuit according to the allocated number of arrays (S302).

  In accordance with the distribution of the information data, an enable signal indicating a valid data position and a code word pulse (first code word pulse) indicating a delimiter of code words generated by the encoding circuit are output to each encoding circuit (S303). ). As described above, the first codeword pulse means that information data corresponding to one codeword to be generated is distributed to the encoding circuit according to the encoding rate processed by the encoding circuit. It is.

  The encoding circuit performs error correction encoding processing on the input information data to generate a basic code, and outputs it to the corresponding FIFO queue. At this time, a codeword pulse (second codeword pulse) indicating a delimiter of one codeword of a basic code having a symbol size (n) = 8 bits and the number of code symbols (p) = 255 is output (S304).

  The basic code subjected to error correction coding is read out as the first code word from the FIFO queue corresponding to each coding circuit (S305). At this time, the phase of the FIFO read signal is initialized, and the head of the first code word read from each FIFO queue is aligned. Also, reading of the first code word from the FIFO queue is performed at a clock operation rate corresponding to the allocated number of arrays. The clock operation rate is a ratio (2/8, 3/8, 6) of the number of arrays (2, 3, 6) allocated to the encoding circuit to the symbol size (8) of the basic code processed by the encoding circuit. / 8).

  Simultaneously with the reading of the first codeword, a code length pulse is output for each number of clocks corresponding to the number of code bits (n × p) constituting the basic code (S306). Therefore, a code length pulse is output every 8 × 255 = 2040 clocks. Further, the bit string (8 × 255 = 2040 bits) corresponding to the cycle of the code length pulse corresponds to the number of bits (frame length) of the transmitted radio frame.

  The first code word is processed at a clock operation rate of 100%, and the number of radio columns corresponding to the number of array units allocated to each encoding circuit is expressed in clock number units (frame length units) in the cycle of the code length pulse. The second code word is output (S307). Note that processing at a clock operation rate of 100% means that the processing operation is performed corresponding to each clock of the cycle of the code length pulse.

  In other words, column conversion is performed in which a unit in which a plurality of first code words having different numbers of code symbols are collected for each code length pulse period is regarded as a new code word and processed at a clock operation rate of 100%. And the result is output as a second codeword. The second code word is the number of arrays in which the encoded bit string corresponding to 100% of the effective bit data for each clock of the code length pulse period corresponding to the number of code bits of the basic code is allocated. The only existing format.

  A third code word obtained by combining the number of radio strings of the second code word corresponding to each encoding circuit is output as radio frame data (S308).

  Through the above operation, radio frame data having the number of radio columns (symbol size) corresponding to the required modulation multi-level number is obtained.

(Error correction decoding circuit of the second embodiment)
Next, an error correction decoding circuit according to the second embodiment will be described.

  FIG. 18 is a block diagram showing the configuration of the second embodiment of the error correction decoding circuit of the present invention. FIG. 19 is a block diagram showing a configuration of an embodiment of a communication apparatus including the error correction decoding circuit of the present invention.

  First, the positioning of the error correction decoding circuit of the present invention will be described with reference to FIG.

  The communication device 4 of this embodiment includes a signal receiving unit 40 including a receiving circuit 401, a demodulating circuit 402, an error correction decoding circuit 403, and an information source decoding circuit 404. Here, the error correction decoding circuit 403 in the figure corresponds to the error correction decoding circuit 2 of the first embodiment described above or the error correction decoding circuit 20 of the second embodiment described below.

  In the signal receiving unit 40 of the communication device 4, the radio wave received from the antenna is frequency-converted in the receiving circuit 401 and then digitally converted. Then, it is input to the demodulation circuit 402 as a received signal. The demodulation circuit 402 performs a predetermined demodulation process on the received signal to generate an Ich / Qch data stream. The Ich / Qch data stream is input to a signal point inverse conversion circuit 255 in the demodulation circuit 402 shown in FIG. An Ich / Qch data stream including data symbols of signal points is converted into radio frame data (encoded bit string) by the signal point inverse conversion circuit 255 and input to the error correction decoding circuit 403. The error correction decoding circuit 403 performs error correction decoding processing on the radio frame data and outputs information data. The information data is output as information source data such as voice, data and video by the information source decoding circuit 404.

  Next, the error correction decoding circuit 20 of the second embodiment will be described with reference to FIG.

  The error correction decoding circuit 20 of the second embodiment includes a frame synchronization detection circuit 210, a bit separation circuit 220, a radio column number inverse conversion circuit 230, a delay circuit 235, a decoding unit 240, and a data reverse distribution circuit 250. It has become.

  In the error correction decoding circuit 20 of the second embodiment shown in FIG. 18, the decoding unit 240 corresponds to the decoding means 24 of the error correction decoding circuit 2 of the first embodiment.

  The decoding unit 240 includes a plurality of decoding circuits that perform error correction decoding processing in parallel. The decoding circuit performs error correction decoding processing on the basic code, which is a codeword of a block code having a predetermined symbol size (n) and the number of code symbols (p), and outputs the decoded information data. Generate and output to the corresponding FIFO queue. That is, the parallel number of decoding circuits to be arranged in the decoding unit 240 is determined according to the symbol size corresponding to the modulation multi-level number required for the input radio frame data, and each decoding arranged in parallel as such The error correction decoding process is distributed in the conversion circuit.

  As the decoding circuit, any decoding circuit can be used as long as it is a decoding circuit that handles block codes, similarly to the above-described encoding circuit. For example, a decoding circuit that handles block codes such as BCH codes, RS codes, and LDPC codes can be used.

  Here, the symbol size of the radio frame data and the basic code to be handled are the same as those described above for the encoding circuit. That is, a 2048QAM modulation scheme with a symbol size m1 = 11 is applied to radio frame data, and the basic code is a codeword of a block code with a symbol size (n) = 8 bits and the number of code symbols (p) = 255. .

  In addition, the number of divided arrays for the decoding circuits arranged in parallel is also the same as the description of the encoding circuit described above. In other words, the number of arrangements is an arbitrary positive integer (m2, m3... Mk) determined so that the sum is the symbol size (m1) corresponding to the modulation multilevel number of the input radio frame data. Is assigned. Each number of arrays is equal to or smaller than the symbol size (n) of the basic code. Here, m1 = 11 is processed by three parallel decoding circuits with distribution of m2 = 2, m3 = 3, and m4 = 6. Information relating to the number of partial arrangements is held as parameter information in a control unit (not shown) of the communication apparatus, and is notified as information on the number of partial arrangements from the control unit.

  As described above, the decoding unit 240 is provided with the “code 1” decoding circuit, the “code 2” decoding circuit, and the “code 3” decoding circuit in parallel as the decoding circuit 2401. Note that the “code 1” decoding circuit, the “code 2” decoding circuit, and the “code 3” decoding circuit are not particularly referred to, and the decoding circuit 2401 is a generic term. Each decryption circuit 2401 is provided with a corresponding FIFO queue 2402.

  As described with reference to FIG. 19, the Ich / Qch data stream obtained by performing predetermined demodulation processing on the received signal is input to the signal point inverse conversion circuit 255 as described with reference to FIG. The Ich / Qch data stream including the signal symbol data symbol is converted into radio frame data (encoded bit string) by the signal point inverse conversion circuit 255 and input to the error correction decoding circuit 20.

  The radio frame data input to the error correction decoding circuit 20 is input to the frame synchronization detection circuit 210 and the bit separation circuit 220, respectively.

  In the error correction decoding circuit 20 of the second embodiment shown in FIG. 18, the frame synchronization detection circuit 210 corresponds to the frame synchronization detection means 22 of the error correction encoding circuit 2 of the first embodiment. The bit separation circuit 220 corresponds to the bit separation means 21 of the error correction coding circuit 2 of the first embodiment.

  The frame synchronization detection circuit 210 outputs code length pulses at intervals of the number of bits (frame length) constituting the radio frame based on the input radio frame data. The interval between the code length pulses (code length pulse period) corresponds to the symbol size (8) × the number of code symbols (255), which is the number of code bits of the basic code handled by the decoding circuit.

  The bit separation circuit 220 uses the input wireless frame data as a first codeword having the number of wireless columns corresponding to the number of divided arrays to the wireless column number inverse conversion circuit 230 provided corresponding to each decoding circuit. Output. That is, the first code word has the number of encoded bit strings in units of the number of clocks of the period of the code length pulse as many as the number of columns (the number of radio columns) corresponding to the number of divided arrays.

  Here, m2 = 2 is assigned to the "code 1" decoding circuit, m3 = 3 is assigned to the "code 2" decoding circuit, and m4 = 6 is assigned to the "code 3" decoding circuit. The radio frame data corresponding to the number of columns is also input to the radio column number inverse conversion circuit 230 corresponding to the conversion circuit. The number-of-sequences information assigned to the corresponding decoding circuit 2401 is given to the radio column number inverse conversion circuit 230 as a parameter.

  In the error correction decoding circuit 20 of the second embodiment shown in FIG. 18, the radio sequence number inverse conversion circuit 230 corresponds to the radio sequence number inverse conversion means 23 of the error correction encoding circuit 2 of the first embodiment. .

  A code length pulse is input from the frame synchronization detection circuit 210 to each radio string number inverse conversion circuit 230.

  The radio sequence number inverse conversion circuit 230 converts the first codeword having the number of radio sequences of the number of arrangements assigned to the corresponding decoding circuit 2401 to the symbol size (n = 8) into a second codeword. At this time, the radio sequence number inverse conversion circuit 230 generates a clock having a ratio (2/8, 3/8, 6/8) of the number of corresponding arrangement numbers (2, 3, 6) to the symbol size (8) of the basic code. The first code word is processed at the operation rate to output the second code word.

  In other words, the first code word corresponds to 100% of the bit data corresponding to each clock of the code length pulse period corresponding to the number of code bits constituting the basic code, and the number of columns corresponding to the number of fractional arrangements. Have. This corresponds to the format shown in FIG. 14 described in the above error correction coding circuit.

  The second codeword is a codeword in which 255 codeword symbols (number of code symbols) having a different symbol density (n) = 8 exist, and is divided in units of the number of clocks of the cycle of the code length pulse. There are as many as the number of arrays. This corresponds to the format of FIG. 13 described in the error correction coding circuit described above. This second code word corresponds to a basic code that is a code word of a block code processed by the decoding circuit 2401.

  For example, the second codeword output from the radio sequence number inverse conversion circuit 230 corresponding to the “code 1” decoding circuit includes symbol size = 8 and code symbol number = 255 in units of clock number of code length pulse period. There are two codewords. The second codeword output from the radio sequence number inverse conversion circuit 230 corresponding to the “code 2” decoding circuit has a symbol size = 8 and a code symbol number = 255 in units of the number of clocks of the code length pulse period. There are three codewords. The second codeword output from the radio sequence number inverse conversion circuit 230 corresponding to the “code 3” decoding circuit includes symbol size = 8 and code symbol number = 255 in units of clock number of code length pulse period. There are 6 codewords.

  The radio sequence number inverse conversion circuit 230 outputs a codeword pulse (first codeword pulse) indicating a delimiter of each codeword (basic code) simultaneously with the second codeword.

  Each decoding circuit 2401 performs error correction decoding processing on the input second codeword at the input data rate, generates decoded information data, and outputs it to the corresponding FIFO queue 2402. . At this time, a code word pulse (second code word pulse) indicating a delimiter of information data generated by decoding the basic code is output. This codeword pulse phase shift is absorbed by the FIFO queue 2402 and output from the FIFO queue 2402.

The data reverse distribution circuit 250 reads the decoded information data from each FIFO queue corresponding to the decoding circuit 2401 in the order corresponding to the number of divided arrays, and outputs the combined information data.
In the error correction decoding circuit 20 of the second embodiment shown in FIG. 18, the data reverse distribution circuit 250 corresponds to the data reverse distribution means 25 of the error correction encoding circuit 2 of the first embodiment.

  The data reverse distribution circuit 250 is provided with information on the number of arrangements allocated to each deployed decoding circuit 2401 as a parameter. Then, in synchronization with the code word pulse (second code word pulse), information data is read from each FIFO queue in byte units according to the allocated number of arrays. Then, contrary to the distribution operation described in the error correction coding circuit, the read information data is output on the data stream.

  That is, the information data of the number of bytes corresponding to the number of arrays allocated from each corresponding FIFO queue 2402 in the order of “code 1” decoding circuit, “code 2” decoding circuit, and “code 3” decoding circuit. Are output in units of codeword pulse periods and output as a data stream. A frame pulse indicating a frame delimiter is output by the signal line Frame Pulse, and a valid data flag indicating valid data corresponding to the clock of the data stream is also output by the signal line Data Valid.

  Note that the delay circuit 235 shown in FIG. 18 is a circuit that delays the code length pulse for notifying the data reverse distribution circuit 250 of the frame delimiter by the time required for decoding.

  As described above, the error correction decoding circuit 20 according to the second embodiment uses the decoding circuit 2401 that performs error correction decoding processing in the decoding unit 240 to generate information data, and uses the processing capability in parallel. Can be improved. That is, the number of parallels can be determined according to the symbol size corresponding to the modulation multi-level number required for the input radio frame data, and the processing can be distributed by each decoding circuit 2401.

  Since the number of arrays allocated to each decoding circuit 2401 is equal to or smaller than the symbol size of the block code handled by each decoding circuit 2401, any decoding circuit can be used as each decoding circuit 2401. For example, in the second embodiment, a decoding circuit corresponding to 256QAM with a symbol size (n) = 8 is used, but a decoding circuit corresponding to 64QAM with n = 6 and 16QAM with n = 4 is used. Also good. As the symbol size of the decoding circuit is reduced, the number of arrays handled by each decoding circuit is reduced, and the number of parallels is increased accordingly.

  In addition, as described in the modification of the error correction encoding circuit 10, the error correction decoding circuit 20 according to the second embodiment is an integer multiple of codewords handled by other decoding circuits in any one of the decoding circuits. May handle a code word having the number of code symbols. In this case, similarly to the modification of the error correction coding circuit 10, the code length pulse period may be set to 4080 clocks, which is twice the 2040 clocks.

  Furthermore, the error correction decoding circuit 20 of the second embodiment maximizes the number of modulation multilevels applied to the input radio frame data, as described in another modification of the error correction encoding circuit 10. It is advisable to determine the number of arrays corresponding to the symbol size of the modulation method.

  In other words, if the decoding circuit configuration to be deployed is determined according to the modulation method that maximizes the number of modulation multilevels to be applied, the configuration and operation can be dynamically changed according to changes in the number of modulation multilevels. It becomes. For example, when used for adaptive modulation, the correspondence between the number of arrangements corresponding to the symbol size of the radio frame corresponding to the modulation multi-level number of each modulation method and the decoding circuits arranged in parallel is determined in advance. It is stored as a parameter in a control means (not shown). Then, when the control means knows the change of the modulation method, the corresponding array number information may be notified to each circuit described above.

(Operation Flow of Error Correction Decoding Method of Second Embodiment)
FIG. 20 is a flowchart showing the operation of the second embodiment of the error correction decoding method of the present invention.

  First, the number of arrangements of m2 = 2, m3 = 3, and m4 = 6 is allocated to the decoding circuits arranged in parallel so that the total becomes the symbol size m1 = 11 of the radio frame (S401). That is, a 2048QAM modulation scheme with a symbol size m1 = 11 is applied to input radio frame data, and a decoding circuit to be used has a symbol size (n) = 8 bits and the number of code symbols (p) = 255. It is assumed that a code word of a block code is processed as a basic code.

  Radio frame data is input, and a first codeword having the number of radio columns corresponding to the number of partial arrays is output (S402).

  Based on the radio frame data, a code length pulse is output for each number of code bits (8 × 255 = 2040) constituting a basic code having a symbol size (8) as a decoding unit and the number of code symbols (255). (S403). The interval between the code length pulses (code length pulse period) corresponds to the number of bits (frame length) constituting the radio frame.

  The clock operation rate is the ratio (2/8, 3/8, 6/8) of the corresponding number of arrays (2, 3, 6) to the symbol size (8) of the basic code, with the period of the code length pulse as a unit. The first codeword is converted into a second codeword having a symbol size (8) (S404).

  That is, in the first code word, the valid bit data corresponds to each clock of the cycle of the code length pulse at a rate of 100%, and has the number of columns corresponding to the number of divided arrays. The second codeword is a codeword in which 255 codeword symbols (number of code symbols) having different symbol sizes (n) = 8 are present, and the number of codeword symbols corresponds to the number of divided arrays for each code length pulse period. There are as many.

  The second codeword and a codeword pulse (first codeword pulse) indicating a delimiter between each codeword (basic code) are output to each decoding circuit (S405).

  Each decoding circuit performs error correction decoding processing on the second codeword while maintaining the input data rate, generates decoded information data, and outputs it to the corresponding FIFO queue (S406). At this time, a code word pulse (second code word pulse) indicating a delimiter of information data generated by decoding the basic code is also output to the FIFO queue.

  In synchronization with the codeword pulse (second codeword pulse), information data is read out from each FIFO queue in byte units according to the allocated number of divided arrays in the order according to the number of divided arrays, combined and output. (S407).

  With the above operation, the number of radio columns (symbol size) corresponding to the modulation multi-level number of the input radio frame data is distributed and processed by a plurality of decoding circuits, and decoded information data is obtained.

  As described above, the present invention can be applied to an arbitrary block code, and can cope with an increase in transmission capacity and improve error correction coding / decoding processing capability.

In addition, although a part or all of said embodiment can be described also as the following additional remarks, it is not restricted to the following.
(Supplementary Note 1) Encoding that performs error correction encoding processing on input information data and generates a code word of a block code having a predetermined symbol size (n) and the number of code symbols (p) as a basic code Coding means having a plurality of circuits in parallel, and an arbitrary positive integer (m2, m3) determined so that the sum is a symbol size (m1) corresponding to the modulation multi-level number of the output radio frame data .., Mk) are allocated as the number of divided arrays, respectively, and the data distribution means for distributing the information data to the corresponding encoding circuits according to the number of divided arrays, to the respective encoding circuits of the encoding means, From the respective encoding circuits of the encoding means, the ratio (m2 / n, m3 / n... Mk / n) of the corresponding number of array elements (m2, m3... Mk) to the symbol size (n) of the basic code. ) Code length frame generating means for reading out the basic code as a first code word at a clock operating rate and outputting a code length pulse for each number of clocks corresponding to the number of code bits (n × p) constituting the basic code; A 100% clock operating rate provided for each encoding circuit of the encoding means by inputting the first code word read by the code length frame generating means from the corresponding encoding circuit And a radio sequence number conversion means for outputting a second codeword having the number of radio sequences of the fractional array number assigned to the corresponding encoding circuit in units of clock number of the cycle of the code length pulse, Bit combination means for outputting, as the radio frame data, a third codeword obtained by combining the number of radio strings of the second codeword corresponding to each encoding circuit, which is output from the radio string number conversion means. Preparation Error correction encoding circuit according to claim Rukoto.
(Supplementary note 2) The error correction coding circuit according to Supplementary note 1, wherein the number of divided arrays is set to a symbol size (n) or less of the basic code generated by each coding circuit of the coding means. .
(Additional remark 3) The said data distribution means sends the said information data amount required in order to produce | generate the said basic code to the said encoding circuit according to the coding rate at which the said encoding circuit produces | generates the said basic code. 3. The error correction encoding circuit according to appendix 1 or appendix 2, wherein the first codeword pulse indicating the delimiter of the codeword is output to a corresponding encoding circuit every time the codeword is distributed.
(Supplementary Note 4) The encoding means includes a FIFO (First In First Out) queue corresponding to each of the encoding circuits provided in parallel, and the encoding circuit converts the generated basic code into the basic code 4. The error correction encoding circuit according to appendix 3, wherein the error correction encoding circuit outputs to a corresponding FIFO queue together with a second codeword pulse indicating a delimiter.
(Supplementary Note 5) The code length frame generation means initializes the phase of the FIFO read signal with the second code word pulse input via the FIFO queue, and reads out the first read out from each encoding circuit. The error correction coding circuit according to appendix 4, wherein the heads of the code words are aligned.
(Supplementary Note 6) The first code word input to the radio string number conversion means corresponds to the number of divided arrays allocated to the corresponding encoding circuit in units of clock number of the cycle of the code length pulse. The second codeword including the number of basic codes and output from the radio string number conversion means is bit data corresponding to each clock of the code length pulse period, and is assigned to the corresponding encoding circuit 6. The error correction coding circuit according to any one of supplementary notes 1 to 5, wherein the number of radio columns is equal to the number of the arranged arrays.
(Supplementary Note 7) Any one of a plurality of encoding circuits included in the encoding unit generates a code word having a number of code symbols that is an integral multiple of the basic code generated by another encoding circuit, and the code length pulse The error correction code according to any one of supplementary notes 1 to 6, wherein the period is a number of clocks corresponding to the number of code bits of the code word having a number of code symbols that is an integral multiple of the basic code Circuit.
(Supplementary Note 8) The number of arrangements is determined in advance in correspondence with the number of modulation levels of each of a plurality of modulation schemes applied to output radio frame data, and the number of encoding circuits provided in parallel by the encoding means is: The number of modulation multi-values to be applied to the radio frame data is determined based on the number of arrangements determined corresponding to the symbol size of the modulation scheme that maximizes the number of modulation multi-values applied to the output radio frame data. When changed, the number of divided arrays corresponding to the changed modulation multi-value number is notified to the data distribution means, the code length frame generation means, and the radio string number conversion means. 8. The error correction encoding circuit according to any one of additions 1 to 7.
(Supplementary note 9) A communication apparatus comprising the signal transmission unit including the error correction coding circuit according to any one of supplementary notes 1 to 8.
(Supplementary Note 10) The symbol size corresponding to the modulation multi-level number of the output radio frame data for each of the encoding circuits that perform error correction encoding processing on input information data provided in parallel Arbitrary positive integers (m2, m3... Mk) determined to be (m1) are assigned as the number of fractional arrays, and the information data is distributed to the corresponding encoding circuits according to the number of fractional arrays. Then, the encoding circuit performs error correction encoding processing on the information data, and generates a code word of a block code having a predetermined symbol size (n) and the number of code symbols (p) as a basic code From each encoding circuit, the ratio (m2 / n, m3 / n... Mk / n) of the corresponding number of arrays (m2, m3... Mk) to the symbol size (n) of the basic code. A clock that operates at the number of clocks The basic code is read as a first code word at a clock operation rate, a code length pulse is output for each number of clocks corresponding to the number of code bits (n × p) constituting the basic code, and the corresponding encoding circuit The read first code word is processed at a clock operation rate of 100%, and the number of radio trains of the number of arrangements allocated to the corresponding encoding circuit in units of the number of clocks of the cycle of the code length pulse And a third code word obtained by combining the number of radio strings of the output second code word is output as the radio frame data. Method.
(Supplementary note 11) The error correction coding method according to supplementary note 10, wherein the number of partial arrays is set to be equal to or less than a symbol size (n) of the basic code.
(Supplementary Note 12) When distributing the information data to the corresponding encoding circuit, the encoding circuit is necessary to generate the basic code according to the coding rate when the basic code is generated. The error according to appendix 10 or appendix 11, wherein each time the amount of information data is distributed to the encoding circuit, a first codeword pulse indicating a codeword break is output to the corresponding encoding circuit. Correction encoding method.
(Additional remark 13) The said encoding circuit outputs the produced | generated said basic code to a corresponding FIFO (First In First Out) cue with the 2nd codeword pulse which shows the division | segmentation of this basic code. 12. The error correction coding method according to 12.
(Supplementary Note 14) Initializing the phase of the FIFO read signal with the second codeword pulse input via the FIFO queue and aligning the head of the first codeword read from each encoding circuit. 14. The error correction coding method according to supplementary note 13, which is a feature.
(Supplementary note 15) The first code word includes the number of basic codes corresponding to the number of divided arrays allocated to the corresponding encoding circuit in units of clock number of the cycle of the code length pulse, The second code word is bit data corresponding to each clock of the code length pulse period, and has the number of radio columns corresponding to the number of divided arrays allocated to the corresponding encoding circuit. 15. The error correction encoding method according to any one of supplementary notes 10 to 14, which is a feature.
(Supplementary Note 16) Any one of the plurality of encoding circuits generates a code word having a number of code symbols that is an integral multiple of the basic code generated by another encoding circuit, and the cycle of the code length pulse is 16. The error correction coding method according to any one of supplementary notes 10 to 15, wherein the number of clocks corresponds to the number of code bits of the code word having a number of code symbols that is an integral multiple of the basic code.
(Supplementary Note 17) The number of arrangements is determined in advance in correspondence with the number of modulation levels of each of a plurality of modulation schemes applied to output radio frame data. When the number of modulation multi-values applied to radio frame data is changed based on the number of arrangements determined corresponding to the symbol size of the modulation scheme that maximizes the number of modulation multi-values applied to data, 17. The error correction coding method according to any one of supplementary notes 10 to 16, wherein the number of partial arrays corresponding to the changed modulation multi-level number is notified.
(Supplementary Note 18) Generates decoded information data by performing error correction decoding processing on a basic code which is a code word of a block code having a predetermined symbol size (n) and the number of code symbols (p). And decoding means having a plurality of decoding circuits for performing parallel input, and radio frame data having the number of radio columns having a symbol size (m1) corresponding to a predetermined modulation multilevel number, and the sum of the symbols of the radio frame data Bit separation means for outputting a first codeword having the number of radio columns corresponding to the number of array elements, which is an arbitrary positive integer (m2, m3... Mk), determined to be size (m1) Frame synchronization detecting means for inputting the radio frame data and outputting a code length pulse for each number of clocks corresponding to the number of code bits (n × p) constituting the basic code, and each decoding of the decoding means And the code length pulse output from the frame synchronization detection means and the first code word having the corresponding number of radio strings output from the bit separation means, and the code length The ratio (m2 / n, m3 / n... Mk / n) of the corresponding number of arrangements (m2, m3... Mk) to the symbol size (n) of the basic code in units of the number of clocks of the pulse period. The first codeword is converted to a second codeword having the symbol size of the basic code at a clock operation rate that operates at the number of clocks, and the number of radio columns is inversely converted and output to the corresponding decoding circuit. And data reverse distribution means for reading out the decoded information data from the respective decoding circuits of the decoding means in the order corresponding to the number of partial arrays, and combining and outputting the data. Decoding circuit.
(Supplementary note 19) The error correction decoding circuit according to supplementary note 18, wherein the number of partial arrays is set to a symbol size (n) or less of the basic code handled by each decoding circuit of the decoding means.
(Supplementary note 20) The radio sequence number inverse conversion means divides the number of the second codewords in accordance with the number of divided arrays in units of the number of clocks of the cycle of the code length pulse. The error correction decoding circuit according to appendix 18 or appendix 19, wherein the error correction decoding circuit is output together with a first codeword pulse indicating
(Additional remark 21) The said decoding means is provided with the FIFO (First In First Out) queue corresponding to each decoding circuit provided in parallel, The said decoding circuit is the basis which decoded the said generated information data The error correction decoding circuit according to appendix 20, wherein the error correction decoding circuit outputs to a corresponding FIFO queue together with a second codeword pulse indicating a code delimiter.
(Supplementary note 22) The first code word input to the radio sequence number inverse conversion means is bit data corresponding to each clock of the code length pulse period, and is assigned to the corresponding decoding circuit. The number of radio sequences corresponding to the number of fractional arrays, and the second codeword output from the radio sequence number inverse conversion means corresponds to the decoding unit corresponding to the number of clocks of the cycle of the code length pulse. The error correction decoding circuit according to any one of supplementary notes 18 to 21, wherein the number of the basic codes corresponding to the number of partial arrays allocated to the circuit is included.
(Supplementary note 23) Any one of a plurality of decoding circuits provided in the decoding unit processes a code word having a number of code symbols that is an integral multiple of the basic code handled by another decoding circuit, and The error correction decoding according to any one of supplementary notes 18 to 22, wherein the period is the number of clocks corresponding to the number of code bits of the code word having a number of code symbols that is an integral multiple of the basic code. circuit.
(Supplementary Note 24) The number of array elements is determined in advance in correspondence with the number of modulation multi-values of a plurality of modulation schemes applied to radio frame data, and the number of decoding circuits provided in parallel by the decoding means is determined by radio When the number of modulation multi-levels applied to radio frame data is changed based on the number of arrangements determined corresponding to the symbol size of the modulation scheme that maximizes the number of modulation multi-levels applied to the frame data In any one of appendices 18 to 23, the number of divided arrays corresponding to the changed modulation multi-level number is notified to the radio column number inverse transforming means and the data reverse distribution circuit. The error correction decoding circuit described.
(Supplementary note 25) A communication apparatus comprising the signal receiving unit including the error correction decoding circuit according to any one of supplementary notes 18 to 24.
(Supplementary note 26) A process of error correction decoding is performed on a basic code which is a code word of a block code having a predetermined symbol size (n) and the number of code symbols (p) input in parallel. Arbitrary positive integers (m 2, m 3) determined to be a symbol size (m 1) corresponding to the modulation multilevel number of the input radio frame data to the decoding circuit that generates the decoded information data ... Mk) are allocated the number of arrangements, input the radio frame data, output a first codeword having the number of radio columns according to the number of arrangements, and based on the radio frame data, A code length pulse is output for each number of clocks corresponding to the number of code bits (n × p) constituting the basic code, and the code length pulse and the first code word corresponding to the fractional array number are input. , The code length pal The ratio (m2 / n, m3 / n... Mk / n) of the corresponding number of array elements (m2, m3... Mk) to the symbol size (n) of the basic code in units of the number of clocks The first codeword is converted into a second codeword having a symbol size of the basic code at a clock operation rate that operates at the number of clocks, and the corresponding number of array elements is assigned to the decoding circuit. An error correction decoding method comprising: outputting and decoding the decoded information data from each of the decoding circuits provided in parallel, outputting them in an order corresponding to the number of the partial arrays, and outputting the combined data.
(Supplementary note 27) The error correction decoding method according to supplementary note 26, wherein the number of partial arrays is set to be equal to or less than a symbol size (n) of the basic code.
(Supplementary note 28) When outputting the second codeword, the second codeword is converted into the number of the second codeword corresponding to the number of divided arrays in units of the number of clocks of the cycle of the code length pulse. 28. The error correction decoding method according to appendix 26 or appendix 27, wherein the error-correction decoding method is output together with a first codeword pulse indicating a word break.
(Supplementary note 29) The decoding circuit outputs the generated information data to a corresponding FIFO (First In First Out) queue together with a second codeword pulse indicating a delimiter of a decoded basic code. The error correction decoding method according to appendix 28.
(Supplementary Note 30) The first code word is bit data corresponding to each clock of the code length pulse period, and the number of radio strings corresponding to the number of divided arrays allocated to the corresponding decoding circuit And the second codeword includes the number of basic codes corresponding to the number of divided arrays allocated to the corresponding decoding circuit in units of clock number of the cycle of the code length pulse. 30. The error correction decoding method according to any one of supplementary notes 26 to 29, characterized by:
(Supplementary Note 31) Any one of the plurality of decoding circuits processes a code word having a number of code symbols that is an integral multiple of the basic code handled by the other decoding circuit, and the period of the code length pulse is the basic code 31. The error correction decoding method according to any one of supplementary notes 26 to 30, wherein the number of clocks corresponds to the number of code bits of the code word having a number of code symbols that is an integral multiple of the code.
(Supplementary Note 32) The number of arrangements is determined in advance in association with the number of modulation levels of each of a plurality of modulation schemes applied to radio frame data, and the number of decoding circuits provided in parallel applies to the radio frame data. When the number of modulation multi-levels determined based on the number of arrangements determined corresponding to the symbol size of the modulation scheme that maximizes the modulation multi-level number and applied to the radio frame data is changed. 32. The error correction decoding method according to any one of supplementary notes 26 to 31, wherein the number of partial arrays corresponding to a modulation multi-level number is notified.

DESCRIPTION OF SYMBOLS 1, 10 Error correction encoding circuit 2, 20 Error correction decoding circuit 3, 4 Communication apparatus 30 Signal transmission part 40 Signal receiving part 11 Data distribution means 12 Encoding means 13 Radio sequence number conversion means 14 Code length frame generation means 15 Bit combination means 121, 1201 Encoding circuit 21 Bit separation means 22 Frame synchronization detection means 23 Radio sequence number inverse conversion means 24 Decoding means 25 Data reverse distribution means 241, 401 Decoding circuit 110 Data distribution circuit 120 Encoding unit 130 Wireless Column number conversion circuit 135 FIFO delay circuit 140 Code length frame generation circuit 150 Bit combination circuit 210 Signal point conversion circuit 1202 FIFO queue 210 Frame synchronization detection circuit 220 Bit separation circuit 230 Radio column number inverse conversion circuit 235 Delay circuit 240 Decoding unit 250 Data reverse distribution times Path 255 Signal point inverse transformation circuit 301 Information source coding circuit 302 Error correction coding circuit 303 Modulation circuit 304 Transmission circuit 401 Reception circuit 402 Demodulation circuit 403 Error correction decoding circuit 404 Information source decoding circuit

Claims (10)

Multiple parallel encoding circuits that perform error correction coding processing on input information data and generate code words of block codes having a predetermined symbol size (n) and the number of code symbols (p) as basic codes Encoding means provided for
Arbitrary positive integers (m2, m3... Mk) determined to be the symbol size (m1) corresponding to the modulation multi-level number of the output radio frame data are assigned as the number of fractional arrays. Data distribution means for distributing the information data to the corresponding encoding circuits according to the number of arrangements to each encoding circuit of the encoding means,
From each encoding circuit of the encoding means, the ratio (m2 / n, m3 / n... Mk /) of the corresponding number of array elements (m2, m3... Mk) to the symbol size (n) of the basic code. The basic code is read as the first code word at a clock operation rate that operates at the clock number n), and a code length pulse is output for each clock number corresponding to the number of code bits (n × p) constituting the basic code Code length frame generating means for
Provided corresponding to each encoding circuit of the encoding means, and input the first code word read by the code length frame generating means from the corresponding encoding circuit, and at a clock operation rate of 100% A radio sequence number conversion means for processing and outputting a second codeword having the radio sequence number of the fractional array number assigned to the corresponding encoding circuit in units of the number of clocks of the cycle of the code length pulse;
Bit combination means for outputting, as the radio frame data, a third codeword obtained by combining the number of radio strings of the second codeword corresponding to each encoding circuit, which is output from the radio string number conversion means. An error correction coding circuit characterized by the above. 2. The error correction coding circuit according to claim 1, wherein the number of divided arrays is set to be equal to or smaller than a symbol size (n) of the basic code generated by each coding circuit of the coding means. The data distribution unit distributes the amount of information data necessary to generate the basic code to the encoding circuit according to an encoding rate when the encoding circuit generates the basic code. 3. The error correction encoding circuit according to claim 1, wherein a first codeword pulse indicating a codeword break is output to a corresponding encoding circuit. The encoding means includes a FIFO (First In First Out) queue corresponding to each of the encoding circuits provided in parallel, and the encoding circuit indicates the generated basic code as a first delimiter of the basic code. 4. The error correction coding circuit according to claim 3, wherein the error correction coding circuit outputs to a corresponding FIFO queue together with two codeword pulses. The first codeword input to the radio string number conversion means is the number of the bases corresponding to the number of divided arrays allocated to the corresponding encoding circuit in units of the number of clocks of the cycle of the code length pulse. The second code word that includes a code and is output from the radio string number conversion means is bit data corresponding to each clock of the code length pulse period, and the division code assigned to the corresponding encoding circuit. 5. The error correction coding circuit according to claim 1, wherein the number of radio columns is equal to the number of arrays. One of the plurality of encoding circuits provided in the encoding unit generates a code word having a number of code symbols that is an integral multiple of the basic code generated by another encoding circuit, and the cycle of the code length pulse is: 6. The error correction coding circuit according to claim 1, wherein the number of clocks corresponds to the number of code bits of the code word having a number of code symbols that is an integral multiple of the basic code. . The number of arrangements is determined in advance in correspondence with the number of modulation levels of each of a plurality of modulation schemes applied to radio frame data to be output, and the number of encoding circuits provided in parallel by the encoding means is the number of radio circuits to output. When the number of modulation multi-levels applied to radio frame data is changed based on the number of arrangements determined corresponding to the symbol size of the modulation scheme that maximizes the number of modulation multi-levels applied to the frame data 7. The number of divided arrays corresponding to the changed modulation multi-value number is notified to the data distribution means, the code length frame generation means, and the radio string number conversion means. An error correction coding circuit according to any one of the claims. In each of the encoding circuits that perform error correction encoding processing on input information data provided in parallel, the sum total is a symbol size (m1) corresponding to the modulation multilevel number of output radio frame data, and Any positive integer (m2, m3... Mk) determined to be assigned as the number of fractional arrays,
Distributing the information data to the corresponding encoding circuit in accordance with the number of partial arrays;
The encoding circuit performs error correction encoding processing on the information data to generate a code word of a block code having a predetermined symbol size (n) and the number of code symbols (p) as a basic code,
From each encoding circuit, the number of clocks corresponding to the ratio (m2 / n, m3 / n... Mk / n) of the number of corresponding arrangements (m2, m3... Mk) to the symbol size (n) of the basic code. The basic code is read out as a first code word at a clock operation rate that operates at, and a code length pulse is output for each number of clocks corresponding to the number of code bits (n × p) constituting the basic code,
The first code word read from the corresponding encoding circuit is processed at a clock operation rate of 100%, and the amount allocated to the corresponding encoding circuit in units of the number of clocks of the cycle of the code length pulse. Outputting a second codeword having the number of radio columns of the number of arrangements;
3. An error correction coding method comprising: outputting a third code word obtained by combining the number of radio strings of the output second code word as the radio frame data. A decoding circuit that performs error correction decoding processing on a basic code that is a code word of a block code having a predetermined symbol size (n) and the number of code symbols (p) to generate decoded information data Decoding means comprising a plurality of
Radio frame data having the number of radio columns having a symbol size (m1) corresponding to a predetermined modulation multi-level number is input, and an arbitrary positive value determined so that the total becomes the symbol size (m1) of the radio frame data. Bit separation means for outputting a first codeword having a number of radio columns corresponding to the number of arrays that is an integer (m2, m3... Mk) of
Frame synchronization detecting means for inputting the radio frame data and outputting a code length pulse for each clock number corresponding to the number of code bits (n × p) constituting the basic code;
The first codeword provided corresponding to each decoding circuit of the decoding means and having the code length pulse output from the frame synchronization detection means and the corresponding number of radio strings output from the bit separation means And the ratio (m2 / n, m3 / n) of the corresponding number of divided arrays (m2, m3... Mk) to the symbol size (n) of the basic code in units of the number of clocks of the period of the code length pulse. ... the first codeword is converted to a second codeword having the symbol size of the basic code at a clock operation rate that operates at the number of clocks of mk / n), and the corresponding decoding circuit Radio column number reverse conversion means for outputting;
Data reverse distribution means for reading out the decoded information data from the respective decoding circuits of the decoding means in the order corresponding to the number of divided arrays, combining and outputting the data,
An error correction decoding circuit comprising: Information data decoded by performing error correction decoding processing on a basic code that is a code word of a block code having a predetermined symbol size (n) and the number of code symbols (p) to be provided in parallel Any positive integer (m2, m3... Mk) determined so that the sum is a symbol size (m1) corresponding to the modulation multi-level number of the input radio frame data. ) Is assigned the number of arrays,
The radio frame data is input, and a first codeword having a radio sequence number corresponding to the fractional array number is output,
Based on the radio frame data, a code length pulse is output for each number of clocks corresponding to the number of code bits (n × p) constituting the basic code,
The code length pulse and the first code word corresponding to the number of fractional arrangements are input, and the number of fractional arrangements corresponding to the symbol size (n) of the basic code in clock number units of the period of the code length pulse The symbol size of the basic code is the first code word at a clock operation rate that operates at a clock rate of (m 2, m 3... Mk) (m 2 / n, m 3 / n... Mk / n). And output to the decoding circuit assigned the corresponding number of fractional arrays,
An error correction decoding method, comprising: reading decoded information data from each of a plurality of decoding circuits provided in parallel, in an order corresponding to the number of arrangements, and outputting the combined data.

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