JP2018152489A - Avalanche photodiode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate the avalanche photodiode at higher speed and higher sensitivity while suppressing element degradation of an avalanche photodiode.SOLUTION: An electron transit layer 105 made of a semiconductor is formed on an electric field control layer 104, a light absorption layer 106 made of a semiconductor is formed on the electron transit layer 105, and a p-type contact layer 107 made of a p-type semiconductor is formed on the light absorption layer 106. The p-type contact layer 107 has an area smaller than a layer below the electron transit layer 105. In addition, the electron transit layer 105 has a larger band gap energy than that of the light absorption layer 106.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an avalanche photodiode.

  A general optical receiver in optical communication is usually composed of a light receiving element and a transimpedance amplifier that amplifies a photocurrent generated by the light receiving element. As the light receiving element, there is a photodiode (PD) or an avalanche photodiode (APD). The light receiving element has a role of converting incident light into an electric current, but the PD has a maximum photoelectric conversion efficiency of 100% as a quantum efficiency. On the other hand, the APD is a light receiving element having a function of amplifying carriers by colliding with electrons by accelerating photoelectrons generated in the element under a high electric field and ionizing them. As described above, since a plurality of carriers are output for one photon, the APD can obtain a sensitivity exceeding 100% as a quantum conversion efficiency, and is applied to a high-sensitivity optical receiver (Non-Patent Document). 1).

  An APD used for optical communication is required to have high reliability for ensuring long-term operation, but it is not easy to achieve high reliability in an APD. This is because APD generates a high electric field in the element, but when such a high electric field is generated on the side surface or the surface of the element, deterioration of the element from the surface or the side surface becomes remarkable. For this reason, in order to ensure high reliability in the APD, a structure in which an operation region of the element is defined by doping a desired region by ion implantation or selective diffusion and no electric field is generated on the side surface of the element has been adopted. (See Non-Patent Document 2 and Non-Patent Document 3).

  These structures are called planar structures, and unlike general PIN-PDs in which the operating area of an element is determined by mesa processing, intentional mesa processing is not used, and the effective area is effectively increased by the selective doping. It stipulates. The planar structure achieves high reliability, but precise control of the doping region is difficult with techniques such as ion implantation and selective diffusion. For this reason, when high-speed operation of 25 Gbit / s or more is required, a mesa structure that can realize a small operation area (that is, a small element capacity) with good reproducibility is preferable.

  For these reasons, an inversion / triple mesa structure having a multi-stage mesa structure has been proposed for 25 Gbit / s operation (see Non-Patent Document 4). According to the inverted and triple mesa structure, the uppermost contact layer is processed into the smallest mesa shape, and the lower semiconductor layer is formed into a mesa shape with a larger area, so that the side surface electric field in the semiconductor layer other than the uppermost contact layer is increased. It is relaxed.

  In the inversion type / triple mesa APD described in Non-Patent Document 4, an “edge electric field relaxation layer” is provided for the purpose of suppressing edge breakdown during the high multiplication factor operation of the APD. This is because when the electric field is confined inside the element by the structure of the uppermost layer of the element like the triple mesa structure, the electric field is concentrated at the end of the structure, thereby causing local breakdown. This is because the risk of " By using the edge electric field relaxation layer, the uppermost mesa and the multiplication layer are spatially separated, so that the edge electric field in the multiplication layer is relaxed and the edge breakdown in the multiplication layer is suppressed.

J. C. Campbell, "Recent Advances in Telecommunications Avalanche Photodiodes", Journal of Lightwave Technology, vol. 25, no. 1, pp. 109-121, 207. E. Ishimura et al., "Degradation Mode Analysis on Highly Reliable Guardring-Free Planar InAlAs Avalanche Photodiodes", Journal of Lightwave Technology, vol. 25, no. 12, pp. 3683-3693, 2007. Y. Hirota et al., "Reliable non-Zn-diffused InP / InGaAs avalanche photodiode with buried n-InP layer operated by electron injection mode", Electronics Letters, vol. 40, no. 21, pp. 1378-1379, 2004 . M. Nada et al., "Triple-mesa Avalanche Photodiode With Inverted P-Down Structure for Reliability and Stability", Journal of Lightwave Technology, vol. 32, no. 8, pp. 1543-1548, 2014. Y. Kang et al., "Monolithic germanium / silicon avalanche photodiodes with 340 GHz gain-bandwidth product", Nature Photonics, vol. 3, pp. 59-63, 2009. M. Huang et al., "25Gb / s Normal Incident Ge / Si Avalanche Photodiode", The European Conference on Optical Communication, We. 2. 4. 4, 2004. N. Li et al., "High-Saturation-Current Charge-Compensated InGaAs-InP Uni-Traveling-Carrier Photodiode", IEEE Photonics Technology Letters, vol. 16, no. 3, pp. 864-866, 2004.

  By the way, in recent high-speed APD, in addition to the III-V group semiconductor APD produced on the InP substrate, Si-based APD produced by stacking Si and Ge on the Si substrate has been reported (non-patent). Reference 5 and non-patent reference 6). As for the high-speed performance of APD, there are many reports by III-V group semiconductors, but because Si has a high gain bandwidth product, it is potentially capable of high-speed and high-sensitivity operation, and is excellent in mass productivity by a large-diameter process. There are advantages. The APD shown in Non-Patent Document 5 has a mesa structure. However, when such a mesa structure is used and an electric field is concentrated at the center of the element, there is a concern about malfunction due to an edge electric field. The

  This malfunction will be described with reference to FIG. As shown in FIG. 12, this type of APD has an n-type contact layer 702, a multiplication layer 703, a p-type electric field control layer 704, a light absorption layer 705, a p-type contact layer 706 on a substrate 701. Is formed. The multiplication layer 703 and the electric field control layer 704 are mesas smaller than the contact layer 702. The light absorption layer 705 and the contact layer 706 are smaller mesa than the electric field control layer 704. When a voltage is applied to the APD formed in this way, the electric field strength inside the element increases, but the electric field is concentrated at the edge portion 711 of the multistage mesa in FIG. When such an edge electric field is generated, the APD cannot operate normally due to local breakdown.

  It is not always easy to apply an edge electric field relaxation layer as shown in Non-Patent Document 4 to a Si-based APD. This is different from conventional APDs based on III-V semiconductors using InP substrates and InGaAs light absorption layers. In the case of Si, the Ge light absorption layer is generally the last step of crystal growth. In addition, it is derived from a small degree of freedom in structural design, such as Si, Ge, and SiGe being the only material system that can be used. This problem is not limited to Si-based APDs, but also applies to APDs using InAs, which are said to be capable of realizing extremely high gains.

  As described above, when an APD is formed with a material system different from that of an APD having an InGaAs light absorption layer formed on a conventional InP substrate, and an attempt is made to suppress edge breakdown, the degree of design freedom is small. Therefore, application of the prior art has been difficult. As described above, the conventional technique has a problem that it is not easy to operate at a higher speed and with higher sensitivity while suppressing element deterioration of the APD.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to operate at higher speed and higher sensitivity while suppressing element degradation of an avalanche photodiode.

  An avalanche photodiode according to the present invention includes an n-type contact layer made of an n-type semiconductor formed on a substrate, a multiplication layer made of an undoped semiconductor formed on the n-type contact layer, and a multiplication An electric field control layer made of an n-type or p-type semiconductor formed on the layer, an electron transit layer made of a semiconductor formed on the electric field control layer, and a semiconductor made on the electron transit layer At least a light absorption layer and a p-type contact layer made of a p-type semiconductor formed on the light absorption layer, wherein the p-type contact layer has a smaller area than the layer below the electron transit layer, The layer has a larger band gap energy than the light absorption layer.

  In the avalanche photodiode, the electron transit layer may be made of a semiconductor having a higher hole saturation rate than the light absorption layer.

In the avalanche photodiode, the electron transit layer may be p-type by adding an acceptor impurity, and the acceptor impurity concentration of the electron transit layer may be 5 × 10 ¹⁷ cm ⁻³ or less.

In the avalanche photodiode, the light absorption layer may be p-type by adding an acceptor impurity, and the acceptor impurity concentration of the light absorption layer may be 5 × 10 ¹⁵ cm ⁻³ or more.

  In the avalanche photodiode, the n-type contact layer, multiplication layer, electric field control layer, and electron transit layer may be made of the same semiconductor.

  In the avalanche photodiode, the light absorption layer can be made of germanium, and the multiplication layer can be made of silicon.

  In the avalanche photodiode, the light absorption layer may have the same area as the p-type contact layer. In this case, the electron transit layer is composed of a lower portion and an upper portion having a smaller area than the lower portion, the upper portion has the same area as the p-type contact layer and the light absorption layer, and the lower portion is formed from the electron transit layer. The area may be the same as that of the lower layer.

  As described above, according to the present invention, the electron transit layer has a band gap energy larger than that of the light absorption layer. Therefore, the element degradation of the avalanche photodiode is suppressed, and at a higher speed. An excellent effect of being able to operate with higher sensitivity is obtained.

FIG. 1 is a cross-sectional view schematically showing a configuration of an avalanche photodiode according to Embodiment 1 of the present invention. FIG. 2 is a characteristic diagram showing an electric field strength profile in the vertical direction of the avalanche photodiode in the first embodiment. FIG. 3 is an explanatory diagram for explaining drift movement of electrons and holes in the light absorption layer 106 of the avalanche photodiode. FIG. 4 is a cross-sectional view schematically showing the configuration of the avalanche photodiode in the second embodiment of the present invention. FIG. 5 is a characteristic diagram showing an electric field intensity profile in the vertical direction of the avalanche photodiode in the second embodiment. FIG. 6A is a cross-sectional view schematically showing the configuration of the avalanche photodiode in the third embodiment of the present invention. FIG. 6B is a cross-sectional view schematically showing the configuration of the avalanche photodiode in the third embodiment of the present invention. FIG. 7 is a characteristic diagram showing the electric field strength profile in the vertical direction of the avalanche photodiode in the third embodiment. FIG. 8 is a cross-sectional view schematically showing the configuration of the avalanche photodiode in the fourth embodiment of the present invention. FIG. 9 is a characteristic diagram showing an electric field strength profile in the vertical direction of the avalanche photodiode in the fourth embodiment. FIG. 10 is a cross-sectional view schematically showing the configuration of the avalanche photodiode in the fifth embodiment of the present invention. FIG. 11 is a cross-sectional view schematically showing the configuration of the avalanche photodiode in the sixth embodiment of the present invention. FIG. 12 is a cross-sectional view schematically showing a configuration of a conventional avalanche photodiode.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, an avalanche photodiode (APD) according to Embodiment 1 of the present invention will be described with reference to FIG. This APD first includes an n-type contact layer 102 made of an n-type semiconductor and formed on a substrate 101. A multiplication layer 103 made of an undoped semiconductor is formed on the n-type contact layer 102. For example, the multiplication layer 103 should just be comprised from the semiconductor which does not produce ionization by a hole collision at the time of a voltage application.

  An electric field control layer 104 made of a p-type semiconductor is formed on the multiplication layer 103. An electron transit layer 105 made of a semiconductor is formed on the electric field control layer 104. On the electron transit layer 105, a light absorption layer 106 made of a semiconductor is formed. A p-type contact layer 107 made of a p-type semiconductor is formed on the light absorption layer 106.

  In addition to the above-described configuration, in the present invention, the p-type contact layer 107 has a smaller area than the layer below the electron transit layer 105. For example, in plan view, each layer has a circular shape, each center is disposed on the same axis, and the p-type contact layer 107 has a smaller area than the other layers. In this structure, the p-type contact layer 107 is disposed inside the region of the light absorption layer 106 in plan view. Further, the electron transit layer 105 has a larger band gap energy than the light absorption layer 106. Note that electrodes (not shown) are electrically connected to the n-type contact layer 102 and the p-type contact layer 107, respectively.

  This will be described in more detail below. In the APD, when the voltage to the element is increased from 0 V to the reverse voltage, the multiplication is performed while depleting the n-type contact layer 102 and the p-type electric field control layer 104 first. The electric field strength of the layer 103 increases. When the applied voltage becomes larger than the voltage at which the electric field control layer 104 is completely depleted, an electric field starts to be generated in the electron transit layer 105 and the light absorption layer 106, and the photocarriers generated in the light absorption layer 106 begin to drift. At this voltage, the APD can operate at high speed, and this voltage is called an on-voltage.

  When a voltage higher than the above-described ON voltage is applied, the electric field strengths of the multiplication layer 103, the electron transit layer 105, and the light absorption layer 106 increase. In a normal APD operation, the breakdown voltage is a voltage at which the electric field intensity of the multiplication layer 103 is an electric field intensity causing an avalanche breakdown. In this case, the electric field intensity profile in the vertical direction at the center of the element is shown by a solid line in FIG. Further, the dotted line in FIG. 2 shows the electric field intensity profile in the vertical direction at the edge portion 111 of the APD described above. Due to the effect of the electron transit layer 105, it is possible to suppress a local increase in the electric field strength of the multiplication layer 103 even in a portion immediately below the edge portion 111.

  In the basic element structure of the present invention, as shown in FIG. 1, the p-type contact layer 107 has an area smaller than that of the region below the light absorption layer 106, so that the element is parallel to the plane of the substrate 101. The electric field is concentrated on the central portion in the horizontal direction, and the electric field on the side surface of the element is relaxed. When a multistage mesa structure for relaxing this electric field is used, an edge electric field is generated immediately below the edge portion 111 of the p-type contact layer 107. When this edge electric field reaches the multiplication layer 103, the electric field strength of the multiplication layer 103 locally rises only at the portion to which the edge electric field reaches, and induces edge breakdown. I need it.

  As a technique for suppressing edge breakdown in the multiplication layer 103, it is known to spatially separate the edge portion and the multiplication layer 103. However, when the thickness of the light absorption layer 106 is increased, the light receiving sensitivity and the APD band are largely converted according to the film thickness. This is because, as shown in FIG. 3, both electrons and holes drift in the light absorption layer 106, so that holes having a lower saturation speed than the electrons limit the bandwidth of the entire device. For this reason, changing the film thickness of the light absorption layer 106 for the purpose of suppressing edge breakdown in the APD affects the design items of the most important characteristics in the APD such as sensitivity and bandwidth.

  In order to prevent the influence described above, an electron transit layer 105 is provided between the edge portion and the multiplication layer 103. The electron transit layer 105 can spatially separate the edge portion and the multiplication layer 103, and as a result, edge breakdown can be suppressed. In addition, by forming the electron transit layer 105 with a material having a larger band gap than the material constituting the light absorption layer 106, the breakdown voltage against edge breakdown is increased. For example, when the light absorption layer 106 is made of Ge, the electron transit layer 105 is made of a material having a larger band gap than the material forming the light absorption layer 106, such as SiGe, so that the breakdown voltage against edge breakdown is reduced. Can be high.

  By the way, the thickness of the electron transit layer 105 does not affect the sensitivity, and when there is no avalanche multiplication in the multiplication layer 103, the carriers traveling in the electron transit layer 105 are only electrons having a relatively high saturation speed. is there. On the other hand, when there is avalanche multiplication in the multiplication layer 103, holes drift in the electron transit layer 105.

  On the other hand, in the present invention, the electron transit layer 105 is made of a material different from that of the light absorption layer 106, and the electron transit layer 105 is made of an arbitrary material having a higher hole saturation rate than the light absorption layer 106. can do. By making the electron transit layer 105 have a higher hole saturation rate than the light absorption layer 106, the influence of the change in the thickness of the electron transit layer 105 on the band characteristics of the entire APD is described above. By changing the film thickness, it is possible to reduce the thickness compared to a known technique for suppressing edge breakdown. The present invention has such advantages.

  In the APD in the first embodiment, for example, the substrate 101 is made of high-resistance silicon, the n-type contact layer 102 is made of n-type silicon, the multiplication layer 103 is made of silicon, and the electric field control layer 104 may be composed of p-type silicon, the electron transit layer 105 may be composed of SiGe, the light absorption layer 106 may be composed of Ge, and the p-type contact layer 107 may be composed of p-type Ge. SiGe is known to have a higher hole saturation rate than Ge.

  Each layer described above may be formed by growing Si or Ge by, for example, a well-known CVD (Chemical Vapor Deposition) method. Further, as the n-type dopant, for example, arsenic (As) may be used, and as the p-type dopant, for example, boron (B) may be used. Needless to say, if the substrate 101 is a high resistance or anti-insulating substrate, it is advantageous in securing high frequency characteristics.

  After a material for each layer is crystal-grown on the substrate 101 to form a laminated structure, each layer may be patterned by a well-known photolithography technique, dry etching technique / wet etching technique to form an element structure. Moreover, what is necessary is just to form an electrode by vapor deposition. For example, the p-type contact layer 107 may be processed into a mesa shape having a circular shape in plan view by a commonly used reactive ion etching technique.

  Thereafter, the light absorption layer 106 and lower layers are processed into a mesa shape having a larger area than the p-type contact layer 107 in a plan view. In this process, after the p-type contact layer 107 is etched, a resist pattern is formed again. However, this resist pattern may be formed in a mesa shape larger than the p-type contact layer 107. By making the light absorption layer 106 and its lower layer larger than the p-type contact layer 107, the side electric field of the element during the APD operation can be reduced, and a structure capable of high reliability can be realized.

In this processing, the resist pattern having the same shape may be etched from the light absorption layer 106 to the surface of the n-type contact layer 102 with a mixed gas of CF ₄ and O ₂ . The n-type contact layer 102 has a larger area than the mesa of the multiplication layer 103, the electric field control layer 104, the electron transit layer 105, and the light absorption layer 106. One electrode pad can be formed on the n-type contact layer 102 around the mesa. The other electrode pad may be formed on the p-type contact layer 107.

After the above mesa shape processing, metal wiring is formed. For example, each electrode pad described above is formed of titanium (Ti) / aluminum (Al) using electron beam vapor deposition, and then a surface protection film made of an insulating material such as SiO ₂ or SiN is formed. After the surface protective film is formed, through holes reaching the electrode pads described above are formed in the surface protective film, and gold (Au) is used by using an electron beam evaporation method or a plating method so as to be connected to each electrode pad. Each wiring may be formed by

  As described above, according to the present invention, the electron transit layer 105 having a band gap energy larger than that of the light absorption layer 106 is provided between the light absorption layer 106 and the multiplication layer 103. Therefore, the mesa type APD Therefore, it is possible to realize high-speed and high-sensitivity operation while suppressing malfunction due to edge breakdown while suppressing deterioration of the element.

[Embodiment 2]
Next, APD in Embodiment 2 of this invention is demonstrated using FIG. The APD includes an n-type contact layer 202 made of an n-type semiconductor and formed on a substrate 201. On the n-type contact layer 202, a multiplication layer 203 made of an undoped semiconductor is formed.

  An electric field control layer 204 made of a p-type semiconductor is formed on the multiplication layer 203. An electron transit layer 205 made of a semiconductor is formed on the electric field control layer 204. On the electron transit layer 205, a light absorption layer 206 made of a semiconductor is formed. A p-type contact layer 207 made of a p-type semiconductor is formed on the light absorption layer 206.

  The p-type contact layer 207 has a smaller area than the layer below the electron transit layer 205. For example, in a plan view, each layer has a circular shape, each center is disposed on the same axis, and the p-type contact layer 207 has a smaller area than the other layers. In this structure, the p-type contact layer 207 is disposed inside the region of the light absorption layer 206 in plan view. The electron transit layer 205 has a larger band gap energy than the light absorption layer 206. Note that electrodes (not shown) are electrically connected to the n-type contact layer 202 and the p-type contact layer 207, respectively.

The configuration described above is the same as that of the first embodiment. In the second embodiment, the electron transit layer 205 is p-type by adding acceptor impurities. The acceptor impurity concentration of the electron transit layer 205 is 5 × 10 ¹⁷ cm ⁻³ or less. The materials constituting the other layers are the same as those in the first embodiment.

  The operation principle of the APD in the second embodiment will be described below. In the APD of the second embodiment, when increasing the voltage to the element from 0 V to the reverse voltage, first, the n-type contact layer 202 and the electric field control layer 204 are depleted while increasing. The electric field strength of the double layer 203 increases. When the applied voltage becomes larger than the voltage at which the electric field control layer 204 is completely depleted, depletion in the electron transit layer 205 starts.

  After the electron transit layer 205 is completely depleted, an electric field starts to be generated in the light absorption layer 206, and the photocarriers generated in the light absorption layer 206 begin to drift. At this voltage, the APD can operate at high speed. This voltage is a so-called on-voltage. When a voltage higher than the on-voltage is applied, the electric field strengths of the multiplication layer 203, the electron transit layer 205, and the light absorption layer 206 increase. In a normal APD operation, a voltage at which the electric field strength of the multiplication layer 203 becomes an electric field strength causing an avalanche breakdown is a breakdown voltage. The electric field intensity profile in the vertical direction at the center of the element in this case is shown by the solid line in FIG. Further, the dotted line in FIG. 5 shows the electric field intensity profile in the vertical direction at the peripheral portion (edge portion) of the p-type contact layer 207 described above.

In the second embodiment, edge breakdown in the multiplication layer 203 can be suppressed as in the first embodiment, and edge breakdown in the electron transit layer 205 and the light absorption layer 206 can also be suppressed. Furthermore, by making the electron transit layer 205 a p-type having a low concentration of 5 × 10 ¹⁷ cm ⁻³ or less, an electric field can be efficiently applied to the multiplication layer 203 as compared with the first embodiment. Even in the same voltage state, the electric field strength in the light absorption layer 206 can be further reduced.

However, when the impurity concentration in the electron transit layer 205 is set to a high value exceeding 5 × 10 ¹⁷ cm ⁻³ , even if the electric field strength in the multiplication layer 203 reaches an element voltage at which the electric field strength causes an avalanche breakdown, There is a concern that the electron transit layer 205 is not completely depleted, the electric field strength in the light absorption layer 206 becomes zero, and the photocarrier does not drift. For this reason, there is an upper limit to the impurity concentration of the electron transit layer 205 in the second embodiment.

  The fact that the electric field strength described here can be made smaller has the effect of improving the degree of freedom in structural design. In the second embodiment, the effect of suppressing edge breakdown in the light absorption layer 206 can be further increased as compared with the first embodiment.

In the APD according to the second embodiment, for example, the substrate 201 is made of high-resistance silicon, the n-type contact layer 202 is made of n-type silicon, the multiplication layer 203 is made of silicon, and the electric field control layer 204 is composed of p-type silicon, the electron transit layer 205 is composed of p ⁻ —SiGe, the light absorption layer 206 is composed of Ge, and the p-type contact layer 207 is composed of p-type Ge. That's fine.

  Each layer described above may be formed by growing Si or Ge by, for example, a well-known CVD method. Further, for example, As may be used as the n-type dopant, and boron B may be used as the p-type dopant.

  After a material for each layer is crystal-grown on the substrate 201 to form a laminated structure, each layer may be patterned by a well-known photolithography technique, dry etching technique / wet etching technique to form an element structure. Moreover, what is necessary is just to form an electrode by vapor deposition. For example, the p-type contact layer 207 may be processed into a circular mesa shape in plan view by a commonly used reactive ion etching technique.

  Thereafter, the light absorption layer 206 and the lower layer are processed into a mesa shape having a larger area than the p-type contact layer 207 in a plan view. In this process, a resist pattern is formed again after the etching process of the p-type contact layer 207, but this resist pattern may be formed in a mesa shape larger than the p-type contact layer 207. By making the light absorption layer 206 and its lower layer larger than the p-type contact layer 207, the side electric field of the element during the APD operation can be reduced, and a structure capable of high reliability can be realized.

In this processing, the resist pattern having the same shape may be etched from the light absorption layer 206 to the surface of the n-type contact layer 202 with a mixed gas of CF ₄ and O ₂ . For example, the n-type contact layer 202 has a larger area than the mesa of the multiplication layer 203, the electric field control layer 204, the electron transit layer 205, and the light absorption layer 206. One electrode pad can be formed on the n-type contact layer 202 around the mesa. The other electrode pad may be formed on the p-type contact layer 207.

After the above mesa shape processing, metal wiring is formed. For example, each electrode pad described above is formed by Ti / Al using electron beam evaporation, and then a surface protective film made of an insulating material such as SiO ₂ or SiN is formed. After the surface protective film is formed, through holes reaching the electrode pads described above are formed in the surface protective film, and each wiring is formed by Au using an electron beam evaporation method or a plating method so as to be connected to each electrode pad. May be formed.

  As described above, in the second embodiment as well, in the mesa type APD, as well as the first embodiment described above, while suppressing the deterioration of the element, the malfunction due to the edge breakdown is suppressed. High speed and high sensitivity operation can be realized.

[Embodiment 3]
Next, APD in Embodiment 3 of this invention is demonstrated using FIG. 6A and FIG. 6B. This APD first includes an n-type contact layer 302 made of an n-type semiconductor formed on a substrate 301. On the n-type contact layer 302, a multiplication layer 303 made of an undoped semiconductor is formed.

  An electric field control layer 304 made of a p-type semiconductor is formed on the multiplication layer 303. On the electric field control layer 304, an electron transit layer 305 made of a semiconductor is formed. On the electron transit layer 305, a light absorption layer 306 made of a semiconductor is formed. A p-type contact layer 307 made of a p-type semiconductor is formed on the light absorption layer 306. Further, the electron transit layer 305 has a larger band gap energy than the light absorption layer 306. Note that electrodes (not shown) are electrically connected to the n-type contact layer 302 and the p-type contact layer 307, respectively.

  The configuration described above is the same as that of the first embodiment. In the third embodiment, for example, as shown in FIG. 6A, the p-type contact layer 307 has a smaller area than the layer below the electron transit layer 305, and the light absorption layer 306 has the p-type contact layer 307. And the same area. For example, in plan view, each layer has a circular shape, each center is disposed on the same axis, and the p-type contact layer 307 and the light absorption layer 306 have a smaller area than the other layers. In this structure, the p-type contact layer 307 and the light absorption layer 306 are arranged inside the region of the electron transit layer 305 in plan view.

  In Embodiment 3, for example, as shown in FIG. 6B, the electron transit layer 305 includes a lower portion 305a and an upper portion 305b having a smaller area than the lower portion 305a, and the upper portion 305b is a p-type contact layer. 307 and the light absorption layer 306 have the same area, and the lower part 305a has the same area as the layer below the electron transit layer 305. Also in this case, the p-type contact layer 307 and the light absorption layer 306 have a smaller area than the layer below the electron transit layer 305.

  In the APD of the third embodiment, when increasing the voltage to the element from 0 V to the reverse voltage, first, while depleting the n-type contact layer 302 and the electric field control layer 304, The electric field strength of the multiplication layer 303 increases. When the applied voltage becomes larger than the voltage at which the electric field control layer 304 is completely depleted, depletion in the electron transit layer 305 and the light absorption layer 306 starts. This voltage is the on-voltage, and the APD can operate at high speed at the on-voltage. When a voltage higher than the on-voltage is applied, the electric field strengths of the multiplication layer 303, the electron transit layer 305, and the light absorption layer 306 increase.

  In a normal APD operation, a voltage at which the electric field strength of the multiplication layer 303 becomes an electric field strength causing an avalanche breakdown is a breakdown voltage. In this case, the electric field intensity profile in the vertical direction at the center of the element is shown by the solid line in FIG. Also, the dotted line in FIG. 7 shows the electric field strength profile in the vertical direction of the peripheral edge (edge part) of the p-type contact layer 307 (light absorption layer 306) of the APD described above. Further, an electric field distribution in the vertical direction outside the p-type contact layer 307 (light absorption layer 306) is shown by a one-dot chain line in FIG.

  In the third embodiment, the electric field strength in the vertical direction at the end face portion of the multiplication layer 303 shown by the one-dot chain line in FIG. 7 rises to a voltage at which the electric field control layer 304 is completely depleted. Is applied, the electric field strength outside the edge does not increase further as shown by the alternate long and short dash line. This is because no charge is present above the electric field control layer 304 in the portion indicated by the alternate long and short dash line in FIG.

  Thus, according to the third embodiment, the electric field strengths at the end face portions of the multiplication layer 303 and the electron transit layer 305 can be reduced. Further, since the light absorption layer 306 is processed so as to have the same shape as the p-type contact layer 307 in plan view, no edge electric field is generated in principle in the light absorption layer 306. Therefore, edge breakdown in the light absorption layer 306 can be suppressed.

  As shown by the solid line and the dotted line in FIG. 7, in the third embodiment, unlike the first and second embodiments, the edge electric field of the light absorption layer 306 is not generated. And the same electric field strength at the end face. On the other hand, the electron transit layer 305 may generate a constant edge electric field. For example, when Ge is used as the light absorption layer 306, the electron transit layer 305 is made of a material constituting the light absorption layer 306, such as SiGe. By using a material having a large band gap, it is possible to increase the breakdown voltage against edge breakdown.

  In Embodiment 3, as shown in FIG. 6B, even if a part (or all) of the electron transit layer 305 is processed by etching to have the same area as the p-type contact layer 307 (light absorption layer 306), the effect is lost. I will not. As described above, in the third embodiment, the mesa-shaped processing conditions of the p-type contact layer 307 and the light absorption layer 306 do not require high etching controllability in the depth direction, and device fabrication is facilitated.

  Also in the third embodiment, edge breakdown in the multiplication layer 303 can be suppressed, and edge breakdown in the electron transit layer 305 and the light absorption layer 306 can be suppressed as in the first embodiment. In particular, compared with the first and second embodiments, the edge breakdown in the light absorption layer 306 can be completely avoided in the third embodiment. The fact that the electric field strength at the edge portion described here can be made smaller has the effect of improving the degree of freedom in structural design.

  In the APD according to the third embodiment, for example, the substrate 301 is made of high-resistance silicon, the n-type contact layer 302 is made of n-type silicon, the multiplication layer 303 is made of silicon, and the electric field control layer 304 may be composed of p-type silicon, the electron transit layer 305 may be composed of SiGe, the light absorption layer 306 may be composed of Ge, and the p-type contact layer 307 may be composed of p-type Ge. The structure of these materials is the same as that of the first embodiment described above.

  Each layer described above may be formed by growing Si or Ge by, for example, a well-known CVD method. Further, for example, As may be used as the n-type dopant, and boron B may be used as the p-type dopant.

  After the material for each layer is crystal-grown on the substrate 301 to form a laminated structure, each layer may be patterned by a well-known photolithography technique, dry etching technique / wet etching technique to form an element structure. Moreover, what is necessary is just to form an electrode by vapor deposition. For example, the p-type contact layer 307 and the light absorption layer 306 may be processed into a mesa shape having a circular shape in plan view by a commonly used reactive ion etching technique.

  Thereafter, the electron transit layer 305 and its lower layer are processed into a mesa shape having a larger area than the p-type contact layer 307 and the light absorption layer 306 in plan view. In this processing, after the p-type contact layer 307 and the light absorption layer 306 are etched, a resist pattern is formed again. This resist pattern is formed in a mesa shape larger than the p-type contact layer 307 and the light absorption layer 306. do it. By making the electron transit layer 305 and the layer below this area larger than the p-type contact layer 307 and the light absorption layer 306, the side electric field of the element during the APD operation can be reduced, and a highly reliable structure can be realized. .

In this processing, the resist pattern having the same shape may be etched from the electron transit layer 305 to the surface of the n-type contact layer 302 with a mixed gas of CF ₄ and O ₂ . For example, the n-type contact layer 302 has a larger area than the mesa of the multiplication layer 303, the electric field control layer 304, and the electron transit layer 305. One electrode pad can be formed on the n-type contact layer 302 around the mesa. The other electrode pad may be formed on the p-type contact layer 307.

After the above mesa shape processing, metal wiring is formed. For example, each electrode pad described above is formed by Ti / Al using electron beam evaporation, and then a surface protective film made of an insulating material such as SiO ₂ or SiN is formed. After the surface protective film is formed, through holes reaching the electrode pads described above are formed in the surface protective film, and each wiring is formed by Au using an electron beam evaporation method or a plating method so as to be connected to each electrode pad. May be formed.

[Embodiment 4]
Next, APD in Embodiment 4 of this invention is demonstrated using FIG. The APD first includes an n-type contact layer 402 made of an n-type semiconductor and formed on a substrate 401. On the n-type contact layer 402, a multiplication layer 403 made of an undoped semiconductor is formed. For example, the multiplication layer 403 should just be comprised from the semiconductor which does not produce ionization by a hole collision at the time of a voltage application.

An electric field control layer 404 made of a p-type semiconductor is formed on the multiplication layer 403. An electron transit layer 405 made of a semiconductor is formed on the electric field control layer 404. On the electron transit layer 405, a light absorption layer 406 made of a p-type semiconductor is formed. In Embodiment 4, the light absorption layer 406 is made p-type by adding an acceptor impurity. For example, the acceptor impurity concentration of the light absorption layer 406 may be 5 × 10 ¹⁵ cm ⁻³ or more. The acceptor impurity concentration in the light absorption layer 406 may be 5 × 10 ¹⁵ cm ⁻³ or more as long as impurities can be introduced. A p-type contact layer 407 made of a p-type semiconductor is formed on the light absorption layer 406.

  The p-type contact layer 407 has a smaller area than the layer below the electron transit layer 405. For example, in a plan view, each layer is circular, each center is disposed on the same axis, and the p-type contact layer 407 has a smaller area than the other layers. Further, the electron transit layer 405 has a larger band gap energy than the light absorption layer 406. Note that electrodes (not shown) are electrically connected to the n-type contact layer 402 and the p-type contact layer 407, respectively.

  The fourth embodiment described above is the same as the first embodiment described above except for the light absorption layer 406.

  The operation principle as the APD in the fourth embodiment will be described below. In the APD of the fourth embodiment, when increasing the voltage to the element from 0 V to the reverse voltage, first, while depleting the n-type contact layer 402 and the electric field control layer 404, The electric field strength of the multiplication layer 403 increases. When the applied voltage becomes larger than the voltage at which the electric field control layer 404 is completely depleted, depletion in the electron transit layer 405 and the light absorption layer 406 starts. At this voltage, the APD can operate at high speed (ON voltage).

  When a voltage higher than the ON voltage is applied, the electric field strengths of the multiplication layer 403, the electron transit layer 405, and the light absorption layer 406 increase. In a normal APD operation, the breakdown voltage is a voltage at which the electric field intensity of the multiplication layer 403 becomes an electric field intensity causing an avalanche breakdown.

In the third embodiment, for example, the light absorption layer 406 is doped with an acceptor impurity of 1 × 10 ¹⁷ cm ⁻¹ or more. For this reason, even when a voltage higher than an electric field is generated in the electron transit layer 405, the light absorption layer 406 is not completely depleted up to a certain voltage, and is divided into a depleted region and a region that maintains electrical neutrality. . As a result, in the fourth embodiment, the electric field strength of the light absorption layer 406 can be kept small even at the operating voltage of the APD.

  In this case, the electric field intensity profile in the vertical direction at the center of the element is shown by a solid line in FIG. Further, a vertical electric field intensity profile at the peripheral edge portion (edge portion) of the p-type contact layer 407 is shown by a dotted line in FIG. Compared with the above-described embodiment, the electric field strength of the light absorption layer 406 can be remarkably reduced, so that edge breakdown can be suppressed even when an edge electric field is generated in the light absorption layer 406.

  In the fourth embodiment, the carrier transport mechanism in the light absorption layer 406 can be changed depending on the doping concentration of the acceptor impurity. When the entire region of the light absorption layer 406 is depleted at a desired APD operating voltage, electrons are injected into the multiplication layer 403 by normal electron and hole drift transport, and holes are injected into the p-type contact layer 407. Move to the side. On the other hand, when a part of the light absorption layer 406 is depleted at a desired APD operating voltage, in the portion where the light absorption layer 406 is depleted, the electron / hole drift movement is maintained and the electrical neutrality is maintained. Electrons are injected into the multiplication layer 403 side by electron diffusion. This carrier movement is the same as the operation principle of MUTC-PD (modified uni-traveling photodiode) (Non-patent Document 7).

  As described above, in the fourth embodiment, the depletion layer width as a whole of the APD becomes small regardless of whether the doping controllability to the light absorption layer 406 is good or not, so that the operating voltage of the APD can be lowered. . The impurity concentration of the light absorption layer 406 is a design matter, and is optimized in consideration of controllability in device fabrication, layer thickness controllability in crystal growth, and operating voltage design as a device without detracting from the essence of the present invention. It is what is done.

However, when the impurity concentration in the light absorption layer 406 is low such that it is less than 5 × 10 ¹⁵ cm ⁻³ , the light absorption layer 406 is easily depleted with respect to voltage application to the element. Therefore, when the carrier transport mechanism in Embodiment 4 is used, the impurity concentration of the light absorption layer 406 has a lower limit of 5 × 10 ¹⁵ cm ⁻³ or more.

In the APD according to the fourth embodiment, for example, the substrate 401 is made of high-resistance silicon, the n-type contact layer 402 is made of n-type silicon, the multiplication layer 403 is made of silicon, and the electric field control layer 404 is composed of p-type silicon, the electron transit layer 405 is composed of SiGe, the light absorption layer 406 is composed of p ⁻ —Ge, and the p-type contact layer 407 is composed of p-type Ge. That's fine.

  Each layer described above may be formed by growing Si or Ge by, for example, a well-known CVD method. Further, as the n-type dopant, for example, As may be used, and as the p-type dopant, for example, B may be used.

  After the material for each layer is crystal-grown on the substrate 401 to form a laminated structure, each layer may be patterned by a well-known photolithography technique, dry etching technique / wet etching technique to form an element structure. Moreover, what is necessary is just to form an electrode by vapor deposition. For example, the p-type contact layer 407 may be processed into a circular mesa shape in plan view by a commonly used reactive ion etching technique.

  Thereafter, the light absorption layer 406 and lower layers thereof are processed into a mesa shape having a larger area than the p-type contact layer 407 in a plan view. In this process, a resist pattern is formed again after the etching process of the p-type contact layer 407. The resist pattern may be formed in a mesa shape larger than the p-type contact layer 407. By making the light absorption layer 406 and its lower layer larger than the p-type contact layer 407, the side electric field of the element during the APD operation can be reduced, and a structure capable of high reliability can be realized.

In this processing, the resist pattern having the same shape may be etched from the light absorption layer 406 to the surface of the n-type contact layer 402 with a mixed gas of CF ₄ and O ₂ . The n-type contact layer 402 has a larger area than the mesa of the multiplication layer 403, the electric field control layer 404, the electron transit layer 405, and the light absorption layer 406. One electrode pad can be formed on the n-type contact layer 402 around the mesa. The other electrode pad may be formed on the p-type contact layer 407.

After the above mesa shape processing, metal wiring is formed. For example, each electrode pad described above is formed by Ti / Al using electron beam evaporation, and then a surface protective film made of an insulating material such as SiO ₂ or SiN is formed. After the surface protective film is formed, through holes reaching the electrode pads described above are formed in the surface protective film, and each wiring is formed by Au using an electron beam evaporation method or a plating method so as to be connected to each electrode pad. May be formed.

[Embodiment 5]
Next, APD in Embodiment 5 of this invention is demonstrated using FIG. The APD includes an n-type contact layer 502 made of an n-type semiconductor and formed on a substrate 501. A multiplication layer 503 made of an undoped semiconductor is formed on the n-type contact layer 502. For example, the multiplication layer 503 may be made of a semiconductor that does not cause ionization due to hole collision when a voltage is applied.

  On the multiplication layer 503, an electric field control layer 504 made of an n-type semiconductor is formed. Further, an electron transit layer 505 made of a semiconductor is formed on the electric field control layer 504. On the electron transit layer 505, a light absorption layer 506 made of a semiconductor is formed. A p-type contact layer 507 made of a p-type semiconductor is formed on the light absorption layer 506.

  The p-type contact layer 507 has a smaller area than the layer below the electron transit layer 505. For example, in plan view, each layer has a circular shape, each center is disposed on the same axis, and the p-type contact layer 507 has a smaller area than the other layers. The electron transit layer 505 has a larger band gap energy than the light absorption layer 506. Note that electrodes (not shown) are electrically connected to the n-type contact layer 502 and the p-type contact layer 507, respectively.

  In the APD according to the fifth embodiment, for example, the substrate 501 is made of high-resistance InAs, the n-type contact layer 502 is made of n-type InAs, and the multiplication layer 503 is made of InAs. The layer 504 is composed of n-type InAs, the electron transit layer 505 is composed of InAs, the light absorption layer 506 is composed of GaSb, and the p-type contact layer 507 is composed of p-type GaSb. In the fifth embodiment, as described above, a group III-V compound semiconductor is used.

  The operation principle of the APD in the fifth embodiment is the same as that in the above-described embodiment. In the fifth embodiment, as described above, the following layers are composed of InAs from the electron transit layer 505 and the light absorption layer 506 is composed of GaSb, so that the entire element is composed of two kinds of material systems. This has the effect of simplifying the crystal growth.

  Here, GaSb constituting the light absorption layer 506 has a larger band gap than InAs constituting the multiplication layer 503. Therefore, in the above-described embodiment, a low-high electric field profile has been obtained in which the electric field strength of the light absorption layer is reduced and the electric field strength of the multiplication layer is increased in the operating state. The electric field profile is “High-low”.

  In the fifth embodiment, InAs and GaSb may be grown by, for example, molecular beam epitaxy (MBE). The n-type dopant may be silicon (Si), and beryllium (Be) may be used as the p-type dopant.

  After the material for each layer is crystal-grown on the substrate 501 to form a laminated structure, each layer may be patterned by a well-known photolithography technique, dry etching technique / wet etching technique to form an element structure. Moreover, what is necessary is just to form an electrode by vapor deposition.

  For example, the p-type contact layer 507 may be processed into a mesa shape having a circular shape in plan view by a commonly used reactive ion etching technique using chlorine (Cl) gas. Thereafter, the light absorption layer 506 and lower layers thereof are processed into a mesa shape having a larger area than the p-type contact layer 507 in a plan view. In this processing, a resist pattern is formed again after the etching processing of the p-type contact layer 507, but this resist pattern may be formed in a mesa shape larger than the p-type contact layer 507. By making the light absorption layer 506 and its lower layer larger than the p-type contact layer 507, the side electric field of the element during the APD operation can be reduced, and a structure capable of high reliability can be realized.

  In this processing, the resist pattern having the same shape may be etched from the light absorption layer 506 to the surface of the n-type contact layer 502 with Cl gas. The n-type contact layer 502 has a larger area than the mesa of the multiplication layer 503, the electric field control layer 504, the electron transit layer 505, and the light absorption layer 506. One electrode pad can be formed on the n-type contact layer 502 around the mesa. The other electrode pad may be formed on the p-type contact layer 507.

After processing the mesa shape, a metal wiring is formed. For example, each electrode pad described above is formed by Ti / Au using electron beam evaporation, and then a surface protective film made of an insulating material such as SiO ₂ is formed. After the surface protective film is formed, through holes reaching the electrode pads described above are formed in the surface protective film, and each wiring is formed by Au using an electron beam evaporation method or a plating method so as to be connected to each electrode pad. May be formed.

[Embodiment 6]
Next, APD in Embodiment 6 of this invention is demonstrated using FIG. The APD includes an n-type contact layer 602 made of an n-type semiconductor and formed on a substrate 601. On the n-type contact layer 602, a multiplication layer 603 made of an undoped semiconductor is formed. For example, the multiplication layer 603 may be made of a semiconductor that does not cause ionization due to hole collision when a voltage is applied.

  An electric field control layer 604 made of a p-type semiconductor is formed on the multiplication layer 603. An electron transit layer 605 made of a semiconductor is formed on the electric field control layer 604. On the electron transit layer 605, a light absorption layer 606 made of a semiconductor is formed. A p-type contact layer 607 made of a p-type semiconductor is formed on the light absorption layer 606.

  The p-type contact layer 607 has a smaller area than the layer below the electron transit layer 605. For example, in plan view, each layer has a circular shape, each center is disposed on the same axis, and the p-type contact layer 607 has a smaller area than the other layers. Further, the electron transit layer 605 has a band gap energy larger than that of the light absorption layer 606. Note that electrodes (not shown) are electrically connected to the n-type contact layer 602 and the p-type contact layer 607, respectively.

  In the APD according to the sixth embodiment, for example, the substrate 601 is made of high resistance silicon, the n-type contact layer 602 is made of n-type silicon, the multiplication layer 603 is made of silicon, and the electric field control layer. 604 is made of p-type silicon, the electron transit layer 605 is made of Si, the light absorption layer 606 is made of Ge, and the p-type contact layer 607 is made of p-type Ge. Si also has a higher hole saturation rate than Ge.

  Each layer described above may be formed by growing Si or Ge by, for example, a well-known CVD method. Further, as the n-type dopant, for example, As may be used, and as the p-type dopant, for example, B may be used.

  The APD of the sixth embodiment is the same as the first embodiment described above except that the electron transit layer 605 is made of Si, and details of the manufacturing method and the like are omitted. In the sixth embodiment, since the electron transit layer 605 is composed of the same Si (semiconductor) as the lower layer, a manufacturing method such as crystal growth can be further simplified.

  As described above, according to the present invention, an electron transit layer is provided between the light absorption layer and the multiplication layer, and the electron transit layer has a larger band gap energy than the light absorption layer. Therefore, it is possible to operate with higher speed and higher sensitivity while suppressing deterioration of the element.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious.

  For example, in the above-described embodiment, Si, SiGe, and Ge have been used as the material constituting the APD. It can be used as a light absorption layer. For example, for communication, the light absorption layer may be made of InGaAs or the like. Further, the multiplication layer may be made of InP, InAlAs, or InAs, which has a larger band gap than that of the light absorption layer and is excellent in gain band seat, and its generality is not lost.

  DESCRIPTION OF SYMBOLS 101 ... Board | substrate, 102 ... N-type contact layer, 103 ... Multiplication layer, 104 ... Electric field control layer, 105 ... Electron travel layer, 107 ... P-type contact layer, 111 ... Edge part.

Claims (8)

An n-type contact layer made of an n-type semiconductor formed on a substrate;
A multiplication layer made of an undoped semiconductor formed on the n-type contact layer;
An electric field control layer made of an n-type or p-type semiconductor formed on the multiplication layer;
An electron transit layer made of a semiconductor formed on the electric field control layer;
A light absorption layer made of a semiconductor formed on the electron transit layer;
A p-type contact layer made of a p-type semiconductor formed on the light absorption layer, and
The p-type contact layer has a smaller area than the layer below the electron transit layer,
The avalanche photodiode is characterized in that the electron transit layer has a larger band gap energy than the light absorption layer. The avalanche photodiode according to claim 1,
The avalanche photodiode is characterized in that the electron transit layer is made of a semiconductor having a higher hole saturation speed than the light absorption layer. The avalanche photodiode according to claim 1 or 2,
The electron transit layer is made p-type by adding an acceptor impurity,
The avalanche photodiode is characterized in that an acceptor impurity concentration of the electron transit layer is 5 × 10 ¹⁷ cm ⁻³ or less. The avalanche photodiode according to any one of claims 1 to 3,
The light absorption layer is made p-type by adding an acceptor impurity,
The avalanche photodiode is characterized in that the acceptor impurity concentration of the light absorption layer is 5 × 10 ¹⁵ cm ⁻³ or more. The avalanche photodiode according to any one of claims 1 to 4,
The avalanche photodiode is characterized in that the n-type contact layer, the multiplication layer, the electric field control layer, and the electron transit layer are made of the same semiconductor. The avalanche photodiode according to any one of claims 1 to 5,
The light absorption layer is made of germanium,
The multiplication layer is made of silicon. An avalanche photodiode. The avalanche photodiode according to any one of claims 1 to 6,
The avalanche photodiode is characterized in that the light absorption layer has the same area as the p-type contact layer. The avalanche photodiode according to claim 7,
The electron transit layer is composed of a lower part and an upper part having a smaller area than the lower part,
The upper portion has the same area as the p-type contact layer and the light absorption layer;
The avalanche photodiode, wherein the lower part has the same area as a layer below the electron transit layer.

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