JP2018142656A - Electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic device which has excellent mechanical strength and reduction of height of a packaging structure.SOLUTION: An electronic device is an electronic device having a through electrode substrate. The through electrode substrate includes: an organic insulation layer; a plurality of through electrodes passing through a lower surface from an upper surface of the organic insulation layer; a semiconductor chip embedded in an inner part of the organic insulation layer; a lower wiring layer provided onto the lower surface of the organic insulation layer; and an upper wiring layer provided onto the upper surface of the organic insulation layer. Each of the through electrodes includes a taper shape in which a diameter is reduced toward the lower surface from the upper surface, and is constructed so as to electrically connect the lower wiring layer with the upper wiring layer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic device.

  Until now, various developments have been made on techniques for manufacturing an electronic device having a package-on-package structure. There exists a thing of patent document 1 as this kind of technique. This document discloses a stacked package structure in which an upper semiconductor package is stacked on a lower semiconductor package. According to this document, in a lower semiconductor package, a semiconductor chip formed on a lower package substrate is embedded with a lower molding material, and a package connection portion (via) penetrating the lower molding material is formed. Have been described. It is also described that the lower package substrate is a package substrate (paragraph 0021), the lower molding material is epoxy molding compound or polyimide (paragraph 0024), and a laser drilling process is used for the opening for forming the via. (Paragraph 0091).

JP 2012-119688 A

  However, as a result of examination by the inventor, the electronic device described in the above document has room for improvement in terms of reducing the height of the package structure because a thick package substrate is used. It has been found.

The package substrate has a structure in which build-up layers are formed on both surfaces of a core layer, like a generally known printed circuit board (PCB).
As a result of earnestly examining the package structure that does not use the package substrate having such a thickness, the present inventor has reduced the package structure in the electronic device by using the through electrode substrate that does not use the package substrate. I found out that it could be realized.
In such a through electrode substrate, an upper wiring layer and a lower wiring layer are formed on the upper surface and the lower surface of the organic insulating layer, respectively, and there are through electrodes that electrically connect the semiconductor chip and the wiring layer in the organic insulating layer. By embedding in the inside, the mechanical strength of the whole substrate can be improved as compared with a structure without these. In addition, by configuring the through electrode in a tapered shape, the mechanical strength of the entire substrate can be increased by increasing the contact area by increasing the installation area of the through electrode, the upper wiring layer, and the installation area.
As a result of further earnest research based on such knowledge, the use of the through electrode substrate as described above without using the package substrate improves the mechanical strength of the through electrode substrate, while improving the package structure. The inventors have found that a reduction in height can be realized, and have completed the present invention.

According to the present invention,
An electronic device comprising a through electrode substrate,
The through electrode substrate is
An organic insulating layer;
A plurality of through electrodes penetrating from the upper surface to the lower surface of the organic insulating layer;
A semiconductor chip embedded in the organic insulating layer;
A lower wiring layer provided on the lower surface of the organic insulating layer;
An upper wiring layer provided on the upper surface of the organic insulating layer,
The penetrating electrode has a tapered shape with a diameter decreasing from the upper surface toward the lower surface, and is configured to electrically connect the lower wiring layer and the upper wiring layer Is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the electronic device excellent in mechanical strength and the low profile of a package structure is provided.

It is process sectional drawing which shows an example of the manufacturing method of the electronic device which concerns on this embodiment. It is process sectional drawing which shows an example of the manufacturing method of the electronic device which concerns on this embodiment. It is sectional drawing which shows the structure of the electronic device which concerns on this embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.
In the present embodiment, description will be made by defining the front-rear, left-right, up-down directions as shown. However, this is provided for the sake of convenience in order to briefly explain the relative relationship between the components. Therefore, the direction at the time of manufacture and use of the product which implements the present invention is not limited.

An outline of the electronic apparatus of this embodiment will be described.
The electronic device according to the embodiment includes the following through electrode substrate. The through electrode substrate includes an organic insulating layer, a plurality of through electrodes penetrating from the upper surface to the lower surface of the organic insulating layer, a semiconductor chip embedded in the organic insulating layer, and a lower layer provided on the lower surface of the organic insulating layer A wiring layer and an upper wiring layer provided on the upper surface of the organic insulating layer can be included. Further, the through electrode has a tapered shape with a diameter decreasing from the upper surface to the lower surface of the organic insulating layer, and can be configured to electrically connect the lower wiring layer and the upper wiring layer.

  The electronic device of this embodiment can have a package-on-package structure in which another semiconductor package is stacked on the through electrode substrate.

  By using the through electrode substrate of this embodiment, a package-on-package can be configured without using a package substrate having a thick film structure having a core layer or a build-up layer. For this reason, it is possible to reduce the height of the entire package structure, that is, to reduce the height of the electronic device.

  In the through electrode substrate of this embodiment, in addition to the structure in which the upper wiring layer and the lower wiring layer are formed on the upper surface and the lower surface of the organic insulating layer, respectively, the semiconductor chip and the wiring layer are electrically connected in the organic insulating layer. Since the through electrode to be embedded has a structure embedded therein, it is possible to exhibit excellent mechanical strength as compared with a structure having no through electrode.

  Since the through electrode in the through electrode substrate of the present embodiment is configured in a tapered shape, the mechanical strength of the entire substrate is increased by increasing the base electrode adhesion force by increasing the installation area with the through electrode, the upper wiring layer, and the installation area. Can be increased. In addition, since the through electrode is formed in a tapered shape, the metal is easily attached to the side wall of the opening by sputtering or the like in the opening where the metal constituting the through electrode is embedded, so that the metal embedding property is improved. Can do. Thereby, the connection reliability of the through electrode substrate can be improved.

  As described above, by adopting the through electrode substrate of the present embodiment, an electronic device that is excellent in mechanical strength and has a low-profile package-on-package structure can be realized.

Hereinafter, the electronic device of this embodiment will be described in detail after describing the manufacturing method.
FIG. 2 is a process cross-sectional view illustrating an example of a method for manufacturing an electronic device according to the present embodiment. FIG. 1 is a diagram for specifically explaining a part of the manufacturing process of the electronic device shown in FIG. FIG. 3A is a cross-sectional view showing the configuration of the electronic device of this embodiment. FIG. 3B is an enlarged view of a part of the electronic device shown in FIG.

An overview of the manufacturing process of the electronic device 100 of this embodiment will be described.
The electronic device 100 of the present embodiment includes a step of preparing a support base (substrate 202) (FIG. 2A), a step of installing a semiconductor chip 210 on the substrate 202 (FIG. 2B), and a semiconductor. A step of disposing the photosensitive resin layer 220 on the substrate 202 so as to embed the chip 210 (FIG. 2C), and a step of forming a through electrode (via 242) in the photosensitive resin layer 220 (FIG. 2). (D)), the step of forming the upper wiring layer 250 on the upper surface side of the photosensitive resin layer 220 (FIG. 2E), the step of separating the substrate 202 (FIG. 2F), the photosensitive resin layer A step of forming a lower wiring layer 252 on the lower surface side of 220 (FIG. 2G). Thereby, a through electrode substrate 200 as shown in FIG. 2G can be obtained.

  Thereafter, the electronic device 100 of the present embodiment includes a step of dividing the through electrode substrate 200 into a plurality of parts (FIG. 2H), a step of mounting the semiconductor package 300 on the separated through electrode substrate 200, including. Thereby, a semiconductor package 300 having a package-on-package structure as shown in FIG. 3A can be obtained.

Next, the manufacturing process of the electronic device 100 of this embodiment will be described in detail.
The steps shown in FIGS. 2A to 2D will be specifically described with reference to FIG.

  First, as shown in FIG. 2A, a substrate 202 is prepared as a support base material. As the supporting base material, the substrate 202 may be used alone, but an interposer (silicon interposer 206) or a semiconductor wafer may be formed on the substrate 202 via an adhesive layer 204. When the substrate 202 is used alone, a heat-peelable adhesive layer (not shown) for bonding the semiconductor chip 210 may be formed on the surface of the substrate 202.

  Further, as the interposer, a substrate having only wiring can be used and used as rewiring means for the semiconductor chip 210. That is, it is possible to convert the pad interval of the semiconductor chip 210 and the pad interval and pins suitable for processing. Thereby, the three-dimensional mounting using TSV can be used efficiently. For example, it is possible to apply an electrode wiring design of a chip such as a memory lip or a logic chip without excessive change. Since the design burden is reduced, productivity efficiency can be increased.

  Although it does not specifically limit as said interposer, An organic resin substrate, a ceramic substrate, a silicon substrate, a glass substrate, etc. are used. A glass substrate is preferable from the viewpoint of low cost and excellent characteristics in a high frequency region. A silicon substrate is preferable from the viewpoints of high density, high speed, power saving, heat dissipation, and the like. The interposer of this embodiment is preferably made of silicon (silicon interposer 206) or glass.

  In addition, as the semiconductor wafer, a plurality of semiconductor elements may be formed. When a semiconductor wafer is used, a wiring layer (redistribution layer) for adjusting the electrode interval of the semiconductor element and an electrode pad electrically connected to the semiconductor element may be formed on the surface of the semiconductor wafer.

  As the adhesive layer 204, a known adhesive can be used. For example, an epoxy adhesive can be used.

  Subsequently, the semiconductor chip 210 is placed on the substrate 202 (FIG. 2B). At this time, a plurality of semiconductor chips 210 may be installed on the substrate 202 in the in-plane direction. A plurality of semiconductor chips 210 can be arranged apart from each other. As a result, the upper and side surfaces of the semiconductor chip 210 and the space between the semiconductor chips 210 can be embedded with the photosensitive resin layer 220. The two or more semiconductor chips 210 may use the same or different types of semiconductor chips. In FIG. 2B, the semiconductor chip 210 may have an electrode for external connection. You may arrange | position so that the surface in which the electrode of the semiconductor chip 210 was formed opposes the one surface side of the board | substrate 202. FIG.

  Subsequently, as illustrated in FIG. 1A, a photosensitive resin layer 220 is disposed on the substrate 202 so as to embed the semiconductor chip 210 installed on the substrate 202. A photosensitive resin film can be used as the photosensitive resin layer 220 (FIG. 2C).

  In the present embodiment, the semiconductor chip 210 may be a logic chip or a memory chip, or may be an LSI chip in which a memory circuit and a logic circuit are mixed. In addition, a memory chip may be stacked on the logic chip. The semiconductor chip 210 may be an FPGA chip having ADC and DAC circuits, or an integrated circuit chip such as a data converter chip. Instead of the semiconductor chip 210, other various electronic components may be used.

  In the present embodiment, for example, a wafer-like substrate having a circular shape or a square shape can be used as the substrate 202. By using a wafer-like substrate, productivity can be increased by increasing the area. Examples of the material for the substrate include metals, glass, semiconductors, and organic resins. Further, the rectangular substrate 202 may be a substrate used for a panel level package (PLP). The PLP process can obtain a panel size package having a larger area than a circular wafer. By using the PLP process, the productivity of the semiconductor package can be improved more efficiently than the wafer level process.

  In addition, the disposing step of disposing the photosensitive resin layer 220 on the substrate 202 includes a pasting step in which the film-like photosensitive resin layer 220 is attached to the substrate 202 or a photosensitive resin composition formed by applying and drying a varnish-like photosensitive resin composition. A coating process for forming the resin layer 220 on the substrate 202 may be included. By using the pasting step, the productivity of the electronic device manufacturing method can be increased. In addition, the photosensitive resin layer 220 can be made thicker.

  The affixing step includes a step of forming a photosensitive resin layer 220 on a carrier base material (not shown), and a step of attaching the photosensitive resin layer 220 with a carrier base material on the substrate 202, Separating. Thereby, the handleability of the photosensitive resin layer 220 can be improved and the manufacturing efficiency of an electronic device can be improved.

  The step of forming the photosensitive resin layer 220 on the carrier substrate includes, for example, preparing a resin varnish by dissolving and dispersing a photosensitive resin composition described later in a solvent and the like, and using various coater apparatuses The method of drying this after apply | coating to a carrier base material, the method of spraying the resin varnish to a carrier base material using a spray apparatus, and drying this are mentioned. Among these, it is preferable to apply a resin varnish to a carrier substrate using various coaters such as a spin coater, a comma coater, and a die coater, and then dry the resin varnish. Thereby, the photosensitive resin layer 220 (photosensitive resin film) with a carrier base material which has no void and has a uniform thickness can be efficiently produced. In addition, the said coating process can use the coating method using the above various coater apparatuses and spray apparatuses.

  The said photosensitive resin film can be obtained by performing a solvent removal process with respect to the coating film (resin film) obtained, for example by apply | coating a varnish-like photosensitive resin composition. The photosensitive resin film may have a solvent content of 10% by weight or less with respect to the entire photosensitive resin composition. For example, the solvent removal treatment can be performed under conditions of 80 ° C. to 150 ° C. and 5 minutes to 30 minutes. Thereby, it becomes possible to remove the solvent sufficiently while suppressing the curing of the photosensitive resin composition.

  The photosensitive resin layer 220 with a carrier substrate may have a sheet shape or a roll shape that can be wound.

  In the present embodiment, as the carrier substrate, for example, a polymer film or a metal foil can be used. The polymer film is not particularly limited. For example, polyolefin such as polyethylene and polypropylene, polyester such as polyethylene terephthalate and polybutylene terephthalate, release paper such as polycarbonate and silicone sheet, heat resistance such as fluorine resin and polyimide resin. A thermoplastic resin sheet having The metal foil is not particularly limited. For example, copper and / or a copper-based alloy, aluminum and / or an aluminum-based alloy, iron and / or an iron-based alloy, silver and / or a silver-based alloy, gold and a gold-based alloy. Zinc and zinc-based alloys, nickel and nickel-based alloys, tin and tin-based alloys, and the like. Among these, a sheet made of polyethylene terephthalate is most preferable because it is inexpensive and easy to adjust the peel strength. Thereby, it becomes easy to peel a carrier base material from moderate intensity | strength from the photosensitive resin layer 220 with a carrier base material.

  The film thickness of the photosensitive resin layer 220 can be designed according to the final film thickness of the cured film. The lower limit of the film thickness of the photosensitive resin layer 220 is, for example, 50 μm or more, preferably 60 μm or more, and more preferably 70 μm or more. Thereby, the thick photosensitive resin layer 220 can be formed. The embedding property of the semiconductor chip 210 in the photosensitive resin layer 220 can be improved, and the mechanical strength can be improved. On the other hand, the upper limit value of the film thickness of the photosensitive resin layer 220 is not particularly limited, but may be, for example, 300 μm or less, 250 μm or less, or 200 μm or less. As a result, the electronic device can be made thinner.

For the step of attaching the photosensitive resin layer 220, a known laminating method can be used. For example, a vacuum laminator can be used. For example, laminating can be performed on a table at a predetermined temperature by using a sticking roll having a predetermined pressure in a vacuum chamber having a predetermined degree of vacuum.
The laminating method is not particularly limited, but may be, for example, a batch type, or the substrate is continuously supplied by continuously supplying the photosensitive resin layer 220 and using a vacuum laminating apparatus, a vacuum becquerel apparatus, or the like. 202 may be laminated.

  In the manufacturing method of the electronic device 100 of the present embodiment, a heat treatment (heating laminating step) is performed in which the photosensitive resin layer 220 is heated during the laminating step of laminating the photosensitive resin layer 220 that is a photosensitive resin film on the semiconductor chip 210. May be performed.

In addition, since the time for the heat treatment varies depending on the type of resin used and the like, it is not particularly limited. For example, the heat treatment can be performed by treating for 10 seconds to 60 seconds.
Moreover, the pressure to pressurize is not particularly limited, but is preferably 0.2 MPa or more and 5 MPa or less, and more preferably 0.4 MPa or more and 1 MPa or less.

The lower limit value of the temperature in the heat laminating step according to the present embodiment is, for example, 40 ° C. or higher, preferably 50 ° C. or higher, more preferably 60 ° C. or higher. Thereby, the embedding property of the photosensitive resin layer 220 can be improved. On the other hand, the upper limit value of the temperature in the heating laminating step can be set lower than, for example, the curing temperature in the later-described curing step. Specifically, the upper limit value of the temperature in the heating laminating step is, for example, 150 ° C. or less, preferably 140 ° C. or less, more preferably 130 ° C. or less. Thereby, progress of hardening of the photosensitive resin layer 220 can be suppressed, and process storability can be improved.
Therefore, the photosensitive resin film of this embodiment is suitable for the photosensitive resin film for step embedding used for the heating lamination process of 40 degreeC or more and 150 degrees C or less, for example.

  Next, in the method for manufacturing the electronic device 100 shown in FIG. 2D, as shown in FIG. 1B to FIG. 1D, the photosensitive resin layer 220 is subjected to an exposure process after the placement step. Process.

  That is, in the exposure step, a mask 230 is disposed in a predetermined region on the photosensitive resin layer 220 as shown in FIG. An exposure process is performed on the photosensitive resin layer 220 through the mask 230.

  In this embodiment, the photosensitive resin layer 220 can be composed of a negative photosensitive resin composition. In this case, the photosensitive resin layer 220 in the mask formation region (light blocking region that is not exposed to irradiation) An opening 240 (as shown in FIG. 1 (c)) can be formed. By adopting a method of opening by such a photoresist method, the opening diameter can be made smaller than in the case of the method of opening by laser irradiation, so that the density of the semiconductor package can be increased. . Further, by adopting a photoresist method in a wafer process or a panel process, pattern formation such as openings 240 is collectively performed on the photosensitive resin layer 220 formed on a large-area substrate such as a wafer. Is possible. Thereby, productivity of a manufacturing process can be improved.

In the present embodiment, the following conditions can be used as an example of the exposure conditions of the exposure process in the photoresist method.
First, the photosensitive resin layer 220 before exposure processing is prepared. For example, in the case of the pasting step, the carrier base material is peeled from the photosensitive resin sheet with a carrier base material to prepare a photosensitive resin layer 220 having a thickness of 50 μm. In the coating process, the varnish of the photosensitive resin composition is coated on a silicon wafer using a spin coater, pre-baked using a hot plate at 120 ° C. for 5 minutes, and a coating film having a thickness of 50 μm ( A photosensitive resin layer 220) is obtained. The photosensitive resin layer 220 prepared as described above is subjected to step exposure at 50 to 1250 mJ / cm ² with an I-line stepper while keeping the exposure time constant. Thereafter, post-exposure heating is performed on a hot plate at 80 ° C. for 5 minutes. The photosensitive resin layer 220 is developed using an organic solvent such as PGMEA. Then, the cured film in which the pattern is formed is obtained by curing at 200 ° C. for 90 minutes. In the present embodiment, the aspect ratio (opening height / opening width) of the opening under the above exposure conditions may be 3. The opening width of the opening may be 50 μm. In the present embodiment, the exposure interval in the step exposure may be set to 20 [mJ / cm ² ], for example, but may be an arbitrary numerical value. The opening width may be the minimum opening width of the opening in FIG.
The exposure amount that satisfies the exposure condition in which the average angle formed by the bottom surface of the cured film of the photosensitive resin layer 220 and the side surface of the opening 240 is closest to a right angle (90 degrees) is defined as the optimum exposure amount.
Then, by adopting an overexposure exposure condition that is an exposure amount larger than the optimum exposure amount, the tapered opening 240 can be formed.
As the exposure wavelength, for example, an ultraviolet ray of 365 nm can be used.

In the present embodiment, by setting the upper limit of the exposure amount to, for example, 1250 mJ / cm ² or less, the opening 240 having a tapered shape is formed within a range in which the patterning property of the photosensitive resin layer 220 is not deteriorated. be able to. Therefore, according to the present embodiment, it is possible to suppress a decrease in patterning property such that the pattern is crushed by overexposure.

In the present embodiment, the exposure amount (overexposure amount) in the overexposure is not particularly limited as long as it is larger than the optimal exposure amount and 1250 mJ / cm ² or less. In the exposure amount ratio (overexposure exposure amount / optimum exposure amount) of the overexposure amount with respect to the optimum exposure amount, the lower limit value thereof may be, for example, 1.1 or more, 1.2 or more, or 1.3 or more. On the other hand, the upper limit value may be, for example, 3.0 or less, 2.5 or less, or 2.0 or less. By setting the overexposure amount within the above exposure amount range, the taper angle can be controlled to be small. In addition, the patterning property of the photosensitive resin layer 220 can be improved.

  Next, in the method for manufacturing an electronic device according to the present embodiment, after the exposure process, the photosensitive resin layer 220 is subjected to post-exposure heat treatment. It can include a developing process for performing a developing process and a curing process for performing a curing process on the photosensitive resin layer 220 after the developing process.

  In the present embodiment, the post-exposure heat treatment may be performed on the photosensitive resin layer 220 under predetermined conditions. The temperature of the post-exposure heat treatment is not particularly limited, but may be, for example, 50 ° C. or higher and 150 ° C. or lower, and preferably 80 ° C. or higher and 120 ° C. or lower. The post-exposure heat treatment time can be, for example, from 1 minute to 10 minutes. Although it is not completely cured by the post-exposure heat treatment, the degree of curing of the photosensitive resin layer 220 can be controlled.

  Subsequently, the photosensitive resin layer 220 is developed. As the developer, for example, an organic solvent or a water-soluble developer can be used. Thereby, as shown in FIG.1 (c), the some opening part 240 can be formed in the photosensitive resin layer 220 by patterning. The opening 240 can be a through-hole penetrating from the front surface to the back surface of the photosensitive resin layer 220. The opening 240 may be provided around the semiconductor chip 210, but may be provided so as to form an opening on the top surface of the semiconductor chip 210.

  Subsequently, after the opening 240 is formed, the photosensitive resin layer 220 is cured by performing a curing process under a predetermined heating condition. The temperature of the curing treatment of the photosensitive resin layer 220 is not particularly limited, but may be, for example, 160 ° C. or higher and 250 ° C. or lower, and preferably 180 ° C. or higher and 230 ° C. or lower. The time for the curing treatment can be, for example, 30 minutes or more and 120 minutes or less. For example, warping can be suppressed by curing at a low temperature. For example, the curing temperature may be set according to the heat resistance of the semiconductor chip. By the curing treatment, a resin-based curing reaction that is not cured by the post-exposure heat treatment can be sufficiently advanced.

  In the present embodiment, the shape of the opening 240 in the photosensitive resin layer 220 can be a tapered shape or a rectangular shape as shown in FIG. For example, the opening 240 may have a tapered shape that decreases in diameter in the exposure irradiation direction in the exposure process. That is, when the surface on which the semiconductor chip 210 is installed on the substrate 202 is the installation surface and the surface opposite to the installation surface is the top surface, the opening diameter on the top surface side of the opening 240 is large, and the installation surface side The tapered shape of the opening 240 can be configured such that the opening diameter of the opening 240 becomes small. Thereby, since the semiconductor chips 210 can be arranged with high density, the mounting density can be increased.

  Next, as shown in FIG. 1D, the method for manufacturing the electronic device 100 according to the present embodiment includes a via formation step of forming a via 242 in the through hole (opening 240) formed in the photosensitive resin layer 220. Can be included.

The via forming step can be performed, for example, by the following steps. First, a seed layer (not shown) is formed on the surface of the patterned photosensitive resin layer 220. The seed layer is formed on the upper surface of the photosensitive resin layer 220 as well as the inside (side wall and bottom surface) of the opening 240. The seed layer can be formed by a method such as sputtering.
As the metal constituting the seed layer, for example, copper, gold, silver, nickel or the like is used. You may use 1 type, or 2 or more types of these.
The seed layer may have a film thickness of, for example, 100 nm to 5000 nm or 300 nm to 3000 nm.

  The seed layer may be made of the same metal as the via 242 (through electrode), but may be made of a different metal having good adhesion to the via 242. For example, a copper seed layer may be formed as the seed layer.

  Subsequently, a patterned resist layer in which predetermined openings are formed is formed on the surface of the seed layer on the photosensitive resin layer 220. That is, a resist layer is formed on the photosensitive resin layer 220 in a region excluding the opening 240. The opening of the resist layer is configured to communicate with the opening 240 of the photosensitive resin layer 220. For example, a film-like resist layer can be used. A pre-patterned film-like resist layer may be laminated, or after laminating the film-like resist layer, the opening shape may be patterned in the resist layer using a drill, laser, photolithography, or the like. .

  Subsequently, the opening 240 (through portion) is embedded with a metal layer. For example, an electrolytic plating method can be used. As a material constituting the metal layer, for example, copper, gold, silver, nickel or the like is used. You may use 1 type, or 2 or more types of these. As a result, a via 242 (through electrode) can be formed inside the opening 240. The via 242 can be made of copper, for example.

  The film thickness of the via 242 (plated metal layer) may be, for example, 1 μm to 150 μm, 3 μm to 100 μm, or 5 μm to 50 μm when penetrating the photosensitive resin layer 220. In addition, the thickness of the via extending from the top surface of the semiconductor chip 210 to the upper surface of the photosensitive resin layer 220 may be, for example, 30 μm to 200 μm, 40 μm to 150 μm, or 50 μm to 120 μm.

  Thereafter, the resist layer is removed by peeling or the like. Thereafter, the seed layer on the photosensitive resin layer 220 is removed. For example, flash etching or the like can be used.

  As described above, the via 242 can be formed in the photosensitive resin layer 220 as shown in FIG.

  In the present embodiment, the tapered shape is a shape in which the opening 240 is tapered with respect to the exposure direction. That is, in the opening 240, the width of the lower end portion is narrower than the width of the upper end portion.

  In the present embodiment, the lower limit value of the taper angle of the opening 240 having a tapered shape may be, for example, 45 degrees or more, 70 degrees or more, more preferably 75 degrees or more, and further preferably 80. More than degrees. Thereby, since the interval between the vias 242 can be reduced, the mounting density of the vias 242 can be increased. On the other hand, the upper limit value of the taper angle may be smaller than 90 degrees, may be 89 degrees or less, and may be 88 degrees or less. This makes it easier for spatter to adhere to the side walls in the opening 240, so that generation of voids in the via 242 can be suppressed. In addition, since the contact area between the photosensitive resin layer 220 and the upper layer (for example, an interlayer insulating layer, an upper wiring layer, etc.) can be increased, the adhesion with the upper layer can be improved.

  In this embodiment, for example, by appropriately selecting the type and amount of each component contained in the photosensitive resin composition constituting the photosensitive resin layer 220, the method for preparing the photosensitive resin composition, the exposure conditions, and the like. The taper angle can be controlled. Among these, for example, adopting a highly reactive epoxy resin, adopting an overexposure amount that is an exposure amount higher than the optimum exposure amount, and the like, while the photosensitive resin layer 220 is a thick film, the opening The shape of the part 240 can be a tapered shape, and can be cited as an element for setting the taper angle in a desired numerical range.

  In the present embodiment, the via formation step may include a step of forming a via (not shown) on the semiconductor chip 210. That is, the step of forming the opening 240 in the photosensitive resin layer 220 on the top surface of the semiconductor chip 210 and embedding the metal layer in the opening 240 may be performed. As a result, a connection via for connecting to the embedded semiconductor chip 210 can be formed in the photosensitive resin layer 220.

  As described above, a structure in which the semiconductor chip 210, the connection via, the through electrode (via 242), and the like are embedded in the photosensitive resin layer 220 can be realized.

Here, the photosensitive resin composition which comprises the photosensitive resin film (photosensitive resin layer 220) of this embodiment is demonstrated.
The photosensitive resin composition of this embodiment can contain an epoxy resin, a hardening | curing agent, and a photosensitive agent. Moreover, as a photosensitive resin composition of this embodiment, a negative photosensitive resin composition is preferable from a viewpoint of realization of a high aspect opening structure. The cured product of the photosensitive resin composition of the present embodiment can constitute an organic insulating layer of the through electrode substrate 200 included in the electronic device 100.

  Each component of the photosensitive resin composition of this embodiment is demonstrated.

(Epoxy resin)
As the epoxy resin, for example, one having two or more epoxy groups in one molecule can be used. For example, phenol novolac type epoxy resin, cresol novolac type epoxy resin, cresol naphthol type epoxy resin, biphenyl type epoxy resin, biphenyl aralkyl type epoxy resin, phenoxy resin, naphthalene skeleton type epoxy resin, bisphenol A type epoxy resin, bisphenol A diglycidyl Ether type epoxy resin, bisphenol F type epoxy resin, bisphenol F diglycidyl ether type epoxy resin, bisphenol S diglycidyl ether type epoxy resin, glycidyl ether type epoxy resin, cresol novolac type epoxy resin, aromatic polyfunctional epoxy resin, aliphatic Examples thereof include an epoxy resin, an aliphatic polyfunctional epoxy resin, an alicyclic epoxy resin, and a polyfunctional alicyclic epoxy resin. These may be used alone or in combination.

Moreover, as said epoxy resin, a polyfunctional epoxy resin more than trifunctional can be included.
The polyfunctional epoxy resin is not particularly limited. For example, 2- [4- (2,3-epoxypropoxy) phenyl] -2- [4- [1,1-bis [4-([2,3 -Epoxypropoxy] phenyl) ethyl] phenyl] propane, phenol novolac type epoxy, tetrakis (glycidyloxyphenyl) ethane, α-2,3-epoxypropoxyphenyl-ω-hydropoly (n = 1-7) {2- (2 , 3-epoxypropoxy) benzylidene-2,3-epoxypropoxyphenylene}, 1-chloro-2,3 epoxypropane · formaldehyde · 2,7-naphthalenediol polycondensate, dicyclopentadiene type epoxy resin and the like. These may be used alone or in combination.

  In the present embodiment, the lower limit of the content of the epoxy resin is, for example, 40% by weight or more, preferably 45% by weight or more, and more preferably 50% by weight with respect to the entire solid content of the photosensitive resin composition. % By weight or more. Thereby, in the hardened | cured material of the photosensitive resin composition, heat resistance and mechanical strength can be improved. On the other hand, the upper limit of the content of the epoxy resin is, for example, 80% by weight or less, preferably 75% by weight or less, and more preferably 70% by weight with respect to the entire solid content of the photosensitive resin composition. % Or less. Thereby, patterning property can be improved in the photosensitive resin composition.

  In the present embodiment, the “solid content of the photosensitive resin composition” refers to a non-volatile content in the photosensitive resin composition, and refers to a remaining portion excluding volatile components such as water and a solvent. Moreover, in this embodiment, content with respect to the whole caliber part of the photosensitive resin composition refers to content with respect to the whole solid content except the solvent of the photosensitive resin composition, when a solvent is included.

(Curing agent)
Although it will not specifically limit as a hardening | curing agent if it accelerates | stimulates the polymerization reaction of an epoxy resin, For example, the hardening | curing agent which has a phenolic hydroxyl group can be included. Specifically, a phenol resin can be used. As a phenol resin, it can select suitably from well-known things, For example, a novolak type phenol resin, a resol type phenol resin, a trisphenyl methane type phenol resin, and an aryl alkylene type phenol resin can be used. From the viewpoint of good development characteristics, a novolac type phenol resin can be used.

  In the present embodiment, the curing agent is preferably a novolac type phenol resin having good development characteristics. Moreover, as a compounding quantity, when the whole epoxy resin is 100 weight part, content of a phenol resin is 25 to 100 weight part, for example, Preferably it is 30 to 90 weight part More preferably, it is 35 parts by weight or more and 80 parts by weight or less. By mix | blending within said range, the heat resistance and intensity | strength of hardened | cured material improve.

(Photosensitive agent)
As the photosensitive agent, a photoacid generator can be used. As a photo-acid generator, the photo-acid generator which generate | occur | produces an acid by irradiation of actinic rays, such as an ultraviolet-ray, is contained. Examples of photoacid generators include onium salt compounds, such as diazonium salts, iodonium salts such as diaryliodonium salts, sulfonium salts such as triarylsulfonium salts, triarylbililium salts, benzylpyridinium thiocyanate, dialkylphenacyl. Examples thereof include cationic photopolymerization initiators such as sulfonium salts and dialkylhydroxyphenylphosphonium salts. As the photosensitive agent, since the photosensitive composition is in contact with a metal, a photosensitizer that does not generate hydrogen fluoride due to decomposition, such as a methide salt type or a borate salt type, is preferable.

  In the present embodiment, the lower limit of the content of the photosensitive agent is, for example, 0.3% by weight or more, preferably 0.5% by weight or more, based on the entire solid content of the photosensitive resin composition. More preferably, it is 1% by weight or more. Thereby, patterning property can be improved in the photosensitive resin composition. On the other hand, the upper limit of the content of the curing agent is, for example, 5% by weight or less, preferably 4.5% by weight or less, more preferably, based on the entire solid content of the photosensitive resin composition. 4% by weight or less. Thereby, the long-term storage property before hardening of the photosensitive resin composition can be improved.

(Other additives)
In addition to the above components, the photosensitive resin composition of the present embodiment can contain other additives as necessary. Examples of the other additives include antioxidants, fillers such as silica, surfactants, sensitizers, filming agents, adhesion assistants, and the like.

  Examples of the surfactant include a fluorine-based surfactant, a silicon-based surfactant, an alkyl-based surfactant, and an acrylic surfactant.

The adhesion aid is not particularly limited, and for example, a silane coupling agent such as amino silane, epoxy silane, acrylic silane, mercapto silane, vinyl silane, ureido silane, or sulfide silane can be used. These may be used alone or in combination of two or more. Among these, it is more preferable to use epoxysilane from the viewpoint of effectively improving the adhesion to other members.
Examples of the aminosilane include bis (2-hydroxyethyl) -3-aminopropyltriethoxysilane, γ-aminopropyltriethoxysilane, γ-aminopropyltrimethoxysilane, γ-aminopropylmethyldiethoxysilane, and γ-aminopropyl. Methyldimethoxysilane, N-β (aminoethyl) γ-aminopropyltrimethoxysilane, N-β (aminoethyl) γ-aminopropyltriethoxysilane, N-β (aminoethyl) γ-aminopropylmethyldimethoxysilane, N -Β (aminoethyl) γ-aminopropylmethyldiethoxysilane, N-phenyl-γ-amino-propyltrimethoxysilane and the like can be mentioned. Examples of the epoxy silane include γ-glycidoxypropyltrimethoxysilane, γ-glycidoxypropylmethyldiethoxysilane, β- (3,4-epoxycyclohexyl) ethyltrimethoxysilane, and γ-glycidylpropyltrimethoxysilane. Etc. Examples of the acrylic silane include γ- (methacryloxypropyl) trimethoxysilane, γ- (methacryloxypropyl) methyldimethoxysilane, and γ- (methacryloxypropyl) methyldiethoxysilane. Examples of mercaptosilane include 3-mercaptopropyltrimethoxysilane. Examples of vinyl silane include vinyl tris (β-methoxyethoxy) silane, vinyl triethoxy silane, and vinyl trimethoxy silane. Examples of ureidosilane include 3-ureidopropyltriethoxysilane. Examples of the sulfide silane include bis (3- (triethoxysilyl) propyl) disulfide, bis (3- (triethoxysilyl) propyl) tetrasulfide, and the like.

(solvent)
The photosensitive resin composition of this embodiment can contain a solvent. As this solvent, any solvent can be used without particular limitation as long as it can dissolve each component of the photosensitive resin composition and does not react with each component.
Examples of the solvent include acetone, methyl ethyl ketone, toluene, propylene glycol methyl ethyl ether, propylene glycol dimethyl ether, propylene glycol 1-monomethyl ether 2-acetate, diethylene glycol ethyl methyl ether, diethylene glycol monoethyl ether acetate, diethylene glycol monobutyl ether acetate, One or more selected from organic solvents such as benzyl alcohol, propylene carbonate, ethylene glycol diacetate, propylene glycol diacetate, and propylene glycol monomethyl ether acetate can be included.

  The preparation method of the photosensitive resin composition of this embodiment is not specifically limited, Generally it can manufacture by a well-known method. For example, the following method is mentioned. A photosensitive resin composition is obtained by blending the raw material and the solvent and mixing them uniformly.

  Subsequently, returning to FIG. 2E from FIG. 1D, the upper wiring layer 250 is formed on the upper surface side of the photosensitive resin layer 220. The upper wiring layer 250 may be formed so as to cover a region where the plurality of semiconductor chips 210 are installed, or may be formed so as to cover the entire upper surface of the photosensitive resin layer 220. The upper wiring layer 250 can function as a rewiring layer that can change the wiring pitch to an appropriate width. Specifically, the upper wiring layer 250 can include an insulating layer, a wiring layer, and a connection via. The upper wiring layer 250 may be a single layer or a plurality of layers. The upper wiring layer 250 can be formed using, for example, a photolithography method and a metal plating method.

  Subsequently, as shown in FIG. 2F, the supporting base material (substrate 202) is separated. For example, in the case of the step of installing the semiconductor chip 210 on the substrate 202 through the heat peelable adhesive layer, the heat peelable adhesive layer and the semiconductor resin 210 are removed from the photosensitive resin layer 220 and the semiconductor chip 210 by heat treatment. The substrate 202 can be peeled off. In the case where the semiconductor chip 210 is installed on the substrate 202 via an interposer (silicon interposer 206) or a semiconductor wafer, the adhesive layer 204 is attached from the interposer or the semiconductor wafer by heat treatment or physical means. And the substrate 202 can be peeled off. Thereby, the lower surface side of the photosensitive resin layer 220 is exposed.

  Subsequently, as shown in FIG. 2G, a lower wiring layer 252 is formed on the lower surface side of the photosensitive resin layer 220 (for example, the lower surface of the photosensitive resin layer 220 or the lower surface of the interposer). The lower wiring layer 252 can be formed in the same manner as the upper wiring layer 250.

  Thus, a through electrode substrate 200 as shown in FIG. 2G is obtained. In the through electrode substrate 200, the upper wiring layer 250 and the lower wiring layer 252 are electrically connected by the through electrode (via 242).

  Thereafter, as shown in FIG. 2H, solder bumps 260 are formed as external terminals on the lower wiring layer 252 of the through electrode substrate 200. Also, a solder resist layer (not shown) may be formed so as to cover a part of the conductive circuit pattern of the upper wiring layer 250 and the lower wiring layer 252 and the solder bump 260. On the other hand, in the through electrode substrate 200, when a semiconductor wafer is formed on the lower surface side of the photosensitive resin layer 220 via a wiring layer, solder bumps may be formed on the upper wiring layer 250.

  Subsequently, as shown in FIG. 2H, the through electrode substrate 200 can be divided into pieces by dividing the through electrode substrate 200 into a plurality of pieces. For example, dicing can be used as the dividing means.

Thereafter, the semiconductor package 300 can be mounted on the upper wiring layer 250 of the separated through electrode substrate 200.
As described above, an electronic device 100 having a package-on-package structure as shown in FIG. 3A can be obtained.

  According to the manufacturing method of the electronic device 100 of the embodiment, since a thick film packaging substrate such as a printed circuit board (PCB) is not used, the structure of the through electrode substrate 200 with a reduced height can be realized. it can. By using such a through electrode substrate 200, it is possible to reduce the height of the package-on-package structure.

  In addition, the method for manufacturing the electronic device 100 according to the present embodiment can be applied to a wafer level process or a panel level process using a large-area substrate.

  Further, in this embodiment, by adopting the photosensitive resin layer 220 composed of the photosensitive resin composition, the semiconductor chip 210 placement step, the semiconductor chip 210 filling step, the via 242 formation step, the upper wiring layer, and the like. The manufacturing process up to the wiring formation process of 250 and the upper wiring layer 250 can be collectively performed at a wafer level or a panel level process. Thereby, the process productivity can be greatly increased. Further, the cost can be reduced.

[Electronic device]
The structure of the electronic device 100 of this embodiment will be described.

  As shown in FIG. 3A, the electronic device 100 according to this embodiment includes a through electrode substrate 200. The through electrode substrate 200 includes an organic insulating layer (photosensitive resin layer 220), a plurality of through electrodes (vias 242) penetrating from the upper surface to the lower surface of the organic insulating layer, and a semiconductor chip 210 embedded in the organic insulating layer. And a lower wiring layer 252 provided on the lower surface of the organic insulating layer, and an upper wiring layer 250 provided on the upper surface of the organic insulating layer.

  In the electronic device 100 of this embodiment, a package structure such as a package-on-package is configured by the above-described through electrode substrate 200 without using a thick film package substrate having a core layer or a build-up layer. For this reason, in the electronic device 100, the overall height of the package structure can be reduced.

  In addition, as shown in FIG. 3A, the electronic device 100 according to this embodiment can have a package-on-package structure in which a semiconductor package 300 is mounted on a through electrode substrate 200. For example, the electronic device 100 of the present embodiment can further include a semiconductor package 300 mounted on the upper wiring layer 250 of the through electrode substrate 200. Thereby, the multifunctionalization of the electronic device 100 can be realized. In addition, the mounting density of the electronic device 100 can be increased.

  As the semiconductor package 300, a known package structure can be used. For example, QFP (Quad Flat Package), SOP (Small Outline Package), BGA (Ball Grid Array), CSP (Chip Size Package), QFN (Quad Flat). A non-leaded package (SON), a small outline non-leaded package (SON), an LF-BGA (Lead Frame BGA), or the like can be used.

  In the present embodiment, for example, as shown in FIG. 3A, the semiconductor package 300 has a semiconductor chip 310 mounted on a substrate 320, and the substrate 320 and the semiconductor chip 310 are bonded to each other via bonding wires 330. You may have the structure to do. In the semiconductor package 300, a plurality of semiconductor chips 310 may be provided, and a plurality of semiconductor chips 310 may be arranged in the planar direction or the stacking direction. Further, the semiconductor chip 310 and the bonding wire 330 may be sealed with a sealing material layer 340. The sealing material layer 340 can be formed, for example, by curing a known sealing resin composition. In addition, solder bumps 360 may be formed on the substrate 320 of the semiconductor package 300 as external terminals. The semiconductor package 300 can be bump-connected to the through electrode substrate 200 via the solder bump 360.

  In addition, the electronic device 100 of the present embodiment can include solder bumps 260 provided on the lower surface of the lower wiring layer 252 of the through electrode substrate 200. As a result, the solder bump 260 functions as an external terminal, thereby enabling external connection with other electronic components.

  Such an electronic device 100 can further include, for example, a mother board that is bump-connected to the lower wiring layer 252 of the through electrode substrate 200 via the solder bumps 260. Thereby, the mechanical strength of the electronic device 100 can be increased, and further multifunctionalization can be realized. At this time, in the through electrode substrate 200, the side surfaces and upper and lower surfaces thereof may be sealed together with the semiconductor package 300 with a sealing material layer formed by curing a known sealing resin composition. Thereby, the connection reliability and mechanical strength of the electronic device 100 can be improved.

  The through electrode substrate 200 included in the electronic device 100 of the present embodiment has an organic layer in addition to the structure in which the upper wiring layer 250 and the lower wiring layer 252 are formed on the upper and lower surfaces of the organic insulating layer (photosensitive resin layer 220), respectively. Since the semiconductor chip 210 and the through electrode (via 242) for electrically connecting the wiring layers are embedded in the insulating layer, the mechanical strength is excellent as compared with a structure without these. be able to.

  Moreover, in embodiment, the organic insulating layer in the said penetration electrode substrate 200 can be comprised with the hardened | cured material of the above-mentioned photosensitive resin composition. Accordingly, since a method of opening by a photoresist method can be adopted, the opening diameter, in other words, the via diameter of the via 242 can be made smaller than in the method of opening by laser irradiation. The integration density of the semiconductor chips 210 and the vias 242 can be increased in the plane of the through electrode substrate 200. Moreover, the mechanical strength of the through electrode substrate 200 can be increased by curing the photosensitive resin composition.

  Further, as shown in FIG. 3B, the through electrode (via 242) in the through electrode substrate 200 has a tapered shape whose diameter decreases from the upper surface to the lower surface of the organic insulating layer (photosensitive resin layer 220). And the upper wiring layer 250 and the lower wiring layer 252 can be electrically connected. For this reason, the mechanical strength of the entire through electrode substrate 200 can be increased by increasing the installation area of the via 242 and the upper wiring layer 250 and increasing the adhesion between them.

  As described above, the electronic device 100 according to the present embodiment includes the through electrode substrate 200 as described above, thereby realizing a package-on-package structure with excellent mechanical strength and a reduced height.

  In the electronic device 100 of this embodiment, the lower limit value of the aspect ratio (height H / diameter W) of the through electrode (via 242) may be, for example, 2.0 or more, and preferably 2.5 or more. More preferably, it may be 3.0 or more. Thereby, it is possible to increase the density of the arrangement of the through electrodes in the through electrode substrate 200. On the other hand, the upper limit value of the aspect ratio is not particularly limited, but may be, for example, 10 or less, preferably 9 or less, and more preferably 8 or less. Thereby, an electrical resistance value can be lowered. By setting the aspect ratio within the above range, the balance between high density and high transmission speed can be improved.

  In the present embodiment, for example, by improving the patterning characteristics of the photosensitive resin composition, the opening 240 having a high aspect ratio can be formed in the opening process shown in FIG. Further, by using the photosensitive resin composition, the thick photosensitive resin layer 220 can be formed. In this case, for example, by using a negative photosensitive resin composition, patterning with high resolution and high aspect ratio becomes possible.

  Moreover, the lower limit of the film thickness of the organic insulating layer (photosensitive resin layer 220) in the through electrode substrate 200 of the present embodiment may be, for example, 50 μm or more, more preferably 60 μm or more, and still more preferably. It is good also as 70 micrometers or more. Thereby, the mechanical strength of the through electrode substrate 200 can be improved. In addition, the embedding property of the semiconductor chip 210 can be improved. On the other hand, the upper limit value of the film thickness of the organic insulating layer may be, for example, 300 μm or less, more preferably 250 μm or less, and even more preferably 200 μm or less. Thereby, the height of the electronic device 100 can be reduced.

  Further, the lower limit value of the taper angle of the through electrode (via 242) in the through electrode substrate 200 may be, for example, 45 degrees or more, may be 70 degrees or more, more preferably 75 degrees or more, and still more preferably. Is 80 degrees or more. Thereby, since the space | interval of penetration electrodes can be narrowed, the mounting density of a penetration electrode can be raised. On the other hand, the upper limit value of the taper angle may be smaller than 90 degrees, may be 89 degrees or less, and may be 88 degrees or less. As a result, the contact area between the through electrode and the upper wiring layer 250 is increased and the adhesion is improved, so that the mechanical strength of the entire through electrode substrate 200 can be increased. Since sputtering easily adheres to the side wall in the opening 240, the metal embedding property in the opening 240 is improved, and the connection reliability of the through electrode can be improved.

In the present embodiment, the cross-sectional shape of the through electrode (via 242) is not particularly limited when viewed from the film thickness direction of the through electrode substrate 200, that is, the direction perpendicular to the upper surface thereof. Examples thereof include polygonal shapes such as hexagons and octagons, and among these, circular shapes may be used.
The through electrode (via 242) is, for example, a conductive frustum made of one or more metals selected from the group consisting of copper, gold, silver, nickel, and the like. Specifically, the conductive frustum Or a conductive polygonal frustum, more specifically, a copper frustum (copper pillar).

  In the present embodiment, as shown in FIG. 3B, since the through electrode (via 242) has a tapered shape, the interval between the through electrodes is narrow on the upper surface side of the photosensitive resin layer 220, and the photosensitive resin layer 220 is formed. The lower surface side of is configured such that the interval between the through electrodes is widened. At this time, the through electrode substrate 200 can be configured such that the space between the top surface of the semiconductor chip 210 and the lower surface of the upper wiring layer 250 is embedded by the organic insulating layer (photosensitive resin layer 220). As described above, by installing the semiconductor chip 210 on the lower surface side (the lower wiring layer 252 side) where the interval between the through electrodes is wide, the mounting density of the through electrodes and the semiconductor chips 210 can be increased.

  In the electronic device 100 of the present embodiment, as shown in FIG. 3B, a plurality of semiconductor chips 210 are embedded in an organic insulating layer (photosensitive resin layer 220) so as to be separated from each other in a plane. It may be configured as follows. At this time, it is possible to adopt a configuration in which a gap between adjacent semiconductor chips 210 is buried with an organic insulating layer (photosensitive resin layer 220). For this reason, by appropriately controlling the material, film thickness, and lamination conditions of the photosensitive resin layer 220, it is possible to realize a structure in which the embedding property of the plurality of semiconductor chips 210 is good. Thereby, the mounting density of the semiconductor chip 210 can be increased.

  In the electronic device 100 of the present embodiment, as shown in FIG. 3A, the wirings constituting the lower wiring layer 252 may be formed to the outside of the semiconductor chip 210 in a sectional view. As a result, the inter-electrode pitch width of the structure in which the plurality of semiconductor chips 210 are mounted at high density can be expanded to the optimum pitch width for connection to the solder bumps 260. That is, the mounting density of the semiconductor chip 210 can be increased.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  EXAMPLES Hereinafter, although this invention is demonstrated in detail with reference to an Example, this invention is not limited to description of these Examples at all.

[Preparation of photosensitive resin composition]
The raw materials of each component blended according to Table 1 were dissolved in propylene glycol monomethyl ether acetate (PGMEA) to obtain a mixed solution. Thereafter, the mixed solution was filtered through a 0.2 μm polypropylene filter to obtain a negative photosensitive resin composition (Samples 1 and 2).
The detail of the raw material of each component in Table 1 is as follows.
(Epoxy resin)
Epoxy resin 1: polyfunctional epoxy resin (EPICLON N-740, manufactured by DIC Corporation)
Epoxy resin 2: bisphenol A type epoxy resin (LX-01, manufactured by Daiso Corporation)
Epoxy resin 3: bisphenol F type epoxy resin (EPICLON 830CRP, manufactured by DIC Corporation)
(Curing agent)
Curing agent 1: Novolac type phenolic resin (PR-55617, manufactured by Sumitomo Bakelite Co., Ltd.)
(Photosensitive agent)
Photosensitizer 1: Cationic photopolymerization initiator (CPI310B, manufactured by San Apro Co., Ltd.)
(Adhesion aid)
Adhesion aid 1: γ-glycidylpropyltrimethoxysilane (KBM-403E, manufactured by Shin-Etsu Chemical Co., Ltd.)
(Surfactant)
Surfactant 1: Polyacrylate-based surface conditioner (BYK-365N, manufactured by BYK Japan)

  Using the obtained photosensitive resin composition, a pattern was formed according to the following procedure, and the following evaluation was performed.

(Creation of photosensitive resin layer (photosensitive resin sheet) with carrier substrate)
The obtained photosensitive resin composition was applied on a carrier substrate using a bar coater so that the film thickness after drying was a predetermined thickness (90 μm, 125 μm), and dried at 120 ° C. for 10 minutes. Then, the protective base material was affixed on the other surface and the carrier base material of the photosensitive resin layer (photosensitive resin film), and the photosensitive resin sheet was created. A PET film (trade name Unipeel, film thickness 38 μm) manufactured by Unitika Co., Ltd. was used as the carrier base material, and a PET film (trade name Purex, film thickness 38 μm) manufactured by Teijin DuPont Co., Ltd. was used as the protective base material.

(Lamination on wafer)
The protective substrate is peeled from the obtained photosensitive resin sheet, and a plurality of photosensitive resin layers of the photosensitive resin sheet are arranged in the in-plane direction of the wafer surface (thickness: 100 μm, length: 10 mm, width 10 mm). Subsequently, using a vacuum pressure laminator (MVLP-500 / 600II, manufactured by Meiki Seisakusho), the wafer, the photosensitive resin layer, and the carrier base material are heated at 80 ° C. and 0.4 MPa for 30 seconds. After pressing, the carrier substrate was peeled from the laminate, and a photosensitive resin layer was laminated on the wafer.

(Exposure, post-exposure heating, development, curing)
Subsequently, the photosensitive resin layer was exposed at 300 mJ / cm ² with an I-line stepper. Then, after exposure for 5 minutes at 120 ° C. on a hot plate, heating was performed. Next, the unexposed portion was dissolved and removed by spray development with PGMEA (propylene glycol monomethyl ether acetate) for 90 seconds. Then, the hardened | cured material of the negative photosensitive resin composition in which the pattern was formed was obtained by making it harden | cure for 90 minutes at 200 degreeC.
The obtained pattern was a rectangle of length: 300 μm × width: 50 μm in the top view of the cured product. The center in the longitudinal direction (longitudinal direction) of this pattern was cut so as to be orthogonal to the longitudinal direction, and the cross-sectional shape was observed for the opening in the obtained sectional view.

  Moreover, using the obtained photosensitive resin composition, the through electrode substrate 200 and the electronic device 100 shown in FIG. 3 were manufactured by carrying out the steps shown in FIG. 2 in the same manner as in the above embodiment.

According to the present embodiment, by using the thick photosensitive resin layer made of the photosensitive resin composition of Samples 1 and 2, the entire bare chip is embedded regardless of whether the film thickness is 90 μm or 125 μm. It has been found that a gap between adjacent bare chips can be embedded.
It was also found that a tapered opening can be formed even when a thick photosensitive resin layer made of the photosensitive resin composition of Samples 1 and 2 is used. Thereby, it was found that a structure excellent in metal embedding characteristics such as good sputtering characteristics can be obtained in the formed opening. It turned out that such a photosensitive resin composition can be used suitably for said through-electrode board | substrate and an electronic device.

  As described above, the present invention has been described more specifically based on the embodiments. However, these are exemplifications of the present invention, and various configurations other than the above can be adopted.

DESCRIPTION OF SYMBOLS 100 Electronic device 200 Through-electrode board | substrate 202 Substrate 204 Adhesive layer 206 Silicon interposer 210 Semiconductor chip 220 Photosensitive resin layer (organic insulating layer)
230 Mask 240 Opening 242 Via 250 Upper wiring layer 252 Lower wiring layer 260 Solder bump 300 Semiconductor package 310 Semiconductor chip 320 Substrate 330 Bonding wire 340 Sealing material layer 360 Solder bump

Claims (12)

An electronic device comprising a through electrode substrate,
The through electrode substrate is
An organic insulating layer;
A plurality of through electrodes penetrating from the upper surface to the lower surface of the organic insulating layer;
A semiconductor chip embedded in the organic insulating layer;
A lower wiring layer provided on the lower surface of the organic insulating layer;
An upper wiring layer provided on the upper surface of the organic insulating layer,
The penetrating electrode has a tapered shape with a diameter decreasing from the upper surface toward the lower surface, and is configured to electrically connect the lower wiring layer and the upper wiring layer . The electronic device according to claim 1,
The said organic insulating layer is an electronic device comprised with the hardened | cured material of the photosensitive resin composition. The electronic device according to claim 1, wherein
An electronic device in which the thickness of the pre-organic insulating layer is 50 μm or more and 300 μm or less. The electronic device according to any one of claims 1 to 3,
An electronic device, wherein the through electrode has an aspect ratio (height / diameter) of 2.0 or more. The electronic device according to any one of claims 1 to 4,
The electronic device in which the taper angle of the through electrode is less than 90 degrees and 45 degrees or more. An electronic device according to any one of claims 1 to 5,
An electronic device in which a space between a top surface of the semiconductor chip and a lower surface of the upper wiring layer is embedded by the organic insulating layer. The electronic device according to any one of claims 1 to 6,
A plurality of the semiconductor chips are embedded in the organic insulating layer so as to be separated from each other in a plane,
An electronic device, wherein a gap between adjacent semiconductor chips is buried by the organic insulating layer. The electronic device according to any one of claims 1 to 7,
The photosensitive resin composition constituting the organic insulating layer is:
Epoxy resin,
A curing agent;
And an electronic device. The electronic device according to any one of claims 1 to 8,
An electronic device comprising solder bumps provided on the lower surface of the lower wiring layer of the through electrode substrate. The electronic device according to any one of claims 1 to 9,
The electronic device in which the wiring constituting the lower wiring layer is formed to the outside of the semiconductor chip in a sectional view. The electronic device according to any one of claims 1 to 10,
An electronic device further comprising a semiconductor package mounted on the upper wiring layer of the through electrode substrate. The electronic device according to any one of claims 1 to 11,
An electronic device further comprising a mother board connected to the lower wiring layer of the through electrode substrate.

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