JP2018107221A - Multilayer circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a suppression effect of electromagnetic interference (EMI) noise in a multilayer circuit board.SOLUTION: A load 21 and a bypass capacitor 31 are mounted on a first layer 11 of a multilayer circuit board 1. The bypass capacitor 31 is electrically connected to a first land 41 and a second land 42. A first connection wiring 51 and a second connection wiring 52 electrically connect the load 21 and the bypass capacitor 31. A first through wiring 61 is connected to the first land 41 via a power supply side electrode terminal 71 of the first connection wiring 51 in a state of penetrating into the multilayer circuit board 1. A second through wiring 62 is connected to the second land 42 via a ground side electrode terminal 72 of the second connection wiring 52 in a state of penetrating into the multilayer circuit board 1 in the vicinity of the first through wiring 61.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a multilayer circuit board provided with an integrated circuit such as an LSI (Large Scale Integrated Circuit), in particular, to reduce EMI (electro-magnetic interference).

  In recent years, an EMI noise problem has become apparent due to an increase in signal transmission speed accompanying an improvement in processing capability of electronic devices. The EMI noise is a power supply noise that is a fluctuation in the power supply voltage inside the integrated circuit, propagates to the power supply wiring of the substrate on which the integrated circuit is mounted, and the power supply noise is radiated to the space as an electromagnetic wave by the movement of the power supply wiring of the substrate as an antenna. Means a phenomenon. In the future, it is presumed that the power supply noise tends to become larger as the integrated circuit is further increased in speed, increased in pin count, and increased in current. Therefore, the problem of EMI noise is regarded as important. As a general measure against EMI, a bypass capacitor is arranged on a substrate (for example, Patent Document 1).

JP 2001-144205 A

  Simply connecting the bypass capacitor to the power supply line and GND (ground) does not necessarily reduce EMI. Since the power supply line includes an impedance component depending on the frequency, it is necessary to dispose a bypass capacitor that is not easily affected by the impedance component in a high frequency band (Patent Document 1, etc.).

  However, the effect of reducing EMI is limited only by changing the placement of the bypass capacitor depending on the frequency band.

  In view of the above circumstances, an object of the present invention is to improve the effect of suppressing EMI noise in a multilayer circuit board.

  Therefore, in one aspect of the multilayer circuit board of the present invention, a load and a bypass capacitor are mounted. The bypass capacitor is electrically connected to the first land and the second land. The multilayer circuit board further includes a first connection wiring, a second connection wiring, a first through wiring, and a second through wiring. The first connection wiring and the second connection wiring electrically connect the load and the bypass capacitor. The first through wiring is connected to the first land through a power supply side electrode terminal of the first connection wiring in a state of penetrating the multilayer circuit board. The second through wiring is connected to the second land through a ground-side electrode terminal of the second connection wiring in a state of penetrating the multilayer circuit board in the vicinity of the first through wiring.

  In one aspect of the multilayer circuit board, an interval between the first land and the second land is narrower than an interval between the first connection wiring and the second connection wiring.

  In one aspect of the multilayer circuit board, the width of the first connection wiring is narrower than the width of the connection portion between the power supply side electrode terminal and the first land.

  In one aspect of the multilayer circuit board, the width of the second connection wiring is narrower than the width of the connection portion between the ground-side electrode terminal and the second land.

  In one aspect of the multilayer circuit board, the first through wiring and the second through wiring are embedded with a conductive material.

  According to the present invention described above, the effect of suppressing EMI noise in the multilayer circuit board can be improved.

The top view of the multilayer circuit board which is one Embodiment of this invention. The perspective view of the said multilayer circuit board.

  Embodiments of the present invention will be described below with reference to the drawings.

  The multilayer circuit board 1 of the present embodiment shown in FIG. 1 is an aspect of a multilayer circuit board having a specification in which an applied voltage is 5 V or less, for example. A load 21 and a bypass capacitor 31 are mounted on the multilayer circuit board 1.

  Examples of the load 21 include well-known surface-mounted integrated circuits exemplified by SOP (Small Outline Package), QFP (Quad Flat Package), and the like. The load 21 is mounted on the first layer 11 of the multilayer circuit board 1, for example.

  As the bypass capacitor 31, for example, a known bypass capacitor of 1005 size (1 mm × 0.5 mm) can be mentioned. The bypass capacitor 31 is mounted on the first layer 11 of the multilayer circuit board 1, for example.

  The load 21 and the bypass capacitor 31 are electrically connected by the first connection wiring 51 and the second connection wiring 52. The first connection wiring 51 and the second connection wiring 52 have substantially the same length.

  One end of the first connection wiring 51 is connected to the load 21 while the other end is connected to the first land 41. The first connection wiring 51 is configured such that the width of the first connection wiring 51 is narrower than the width of the connection portion between the power supply side electrode terminal 71 and the first land 41. The width of the connection portion between the power supply side electrode terminal 71 and the first land 41 may be equal to the width of the first land 41.

  One end of the second connection wiring 52 is connected to the load 21, while the other end is connected to the second land 42. The second connection wiring 52 is configured such that the width of the second connection wiring 52 is narrower than the width of the connection portion between the ground-side electrode terminal 72 and the second land 42. The width of the connection portion between the ground-side electrode terminal 72 and the second land 42 may be equal to the width of the second land 42.

  A bypass capacitor 31 is electrically connected to the first land 41 and the second land 42. The first land 41 is connected to the first through wiring 61 through the power supply side electrode terminal 71. On the other hand, the second land 42 is connected to the second through wiring 62 via the ground-side electrode terminal 72.

  The first land 41 and the second land 42 are arranged so that the distance L1 between the first land 41 and the second land 42 is narrower than the distance L2 between the first connection wiring 51 and the second connection wiring 52. For example, the interval L1 is set to 0.1 mm to 0.2 mm in order to strengthen the capacitive coupling between the first land 41 and the second land 42.

  As illustrated in FIG. 2, the first through wiring 61 penetrates the multilayer circuit board 1, and one end of the first through wiring 61 is exposed from the through hole 111 of the first layer 11. It is connected to the first land 41 via the power supply side electrode terminal 71. On the other hand, the other end of the first through wiring 61 is in a state in which the first through wiring 61 is electrically connected to the power supply layer (any one of the first layer 11 to the Nth layer 1N) of the multilayer circuit board 1. It is connected to the N layer 1N (where N is a natural number of 2 or more).

  The second through-wiring 62 has one end of the second through-wiring 62 passing through the multilayer circuit board 1 in parallel with the first through-wiring 61 in the vicinity of the first through-wiring 61 and the ground-side electrode of the second connection wiring 52 The terminal 72 is connected to the second land 42. On the other hand, the other end of the second through wiring 62 is exposed from the through hole 1N1 of the Nth layer 1N and is electrically connected to GND.

  The first through wiring 61 and the second through wiring 62 are arranged in parallel to the stacking direction of the multilayer circuit board 1. The first through wiring 61 and the second through wiring 62 electrically connect at least two or more layers of the layers (the first layer 11 to the Nth layer 1N) constituting the multilayer circuit board 1. The interval between the first through wiring 61 and the second through wiring 62 is set to, for example, 0.10 mm to 0.50 mm.

  The first through wiring 61 and the second through wiring 62 are embedded in the multilayer circuit board 1 with a conductive material. For example, the first through wiring 61 and the second through wiring 62 are embedded by any one or combination of electrolytic plating, electroless plating, and filling plating using a known conductive material.

  The operation of the multilayer circuit board 1 will be described with reference to FIGS. In FIG. 1, a solid black arrow indicates a “charge supply path”. A black broken line arrow indicates a “decoupling route to GND”. A white solid arrow indicates a “noise propagation path from the load”. A white broken line arrow indicates a “noise decoupling path to the outside”.

  In the multilayer circuit board 1, the bypass capacitor 31 is connected to the power source and the GND via the first through wiring 61 and the second through wiring 62, and the first through wiring 61 and the second through wiring 62 are located at positions close to each other. Are arranged in parallel to the stacking direction of the multilayer circuit board 1. According to this aspect, since the reverse magnetic flux canceling effect between the first through wiring 61 and the second through wiring 62 is generated, it is possible to supply power with low impedance. Further, since the area of the power supply loop is reduced between the first through wiring 61 and the second through wiring 62, the inductance can be reduced. And the supply amount and supply speed of electric charge (black practice arrow of FIG. 1) improve by the fall of the inductance which prevents operation | movement of a transient electric charge. Therefore, the decoupling effect in the high frequency region of the bypass capacitor 31 (white broken line arrow in the figure) can be improved.

  In particular, the first land 41 and the second land 42 are arranged so that the distance L1 between the first land 41 and the second land 42 is narrower than the distance L2 between the first connection wiring 51 and the second connection wiring 52. A decrease in the inductance component of the first connection wiring 51 and the second connection wiring 52 is suppressed. As a result, it is possible to prevent a reduction in the blocking performance (black broken line arrows and white broken line arrows in the figure) of noise (for example, propagation path noise indicated by white practice arrows in the figure).

  Further, the distance L1 between the first land 41 and the second land 42 shown in FIG. 1 is set to about 0.1 mm to 0.2 mm, for example, so that the capacity between the first land 41 and the second land 42 is increased. Coupling becomes strong and the parasitic inductance component resulting from the mounting state can be reduced.

  Furthermore, when the first connection wiring 51 is configured such that the width of the first connection wiring 51 is narrower than the width of the connection portion between the power-side electrode terminal 71 and the first land 41, the load 21 is increased due to an increase in inductance component. The high-frequency noise component that enters is blocked (black broken arrow in the figure).

  And if the 2nd connection wiring 52 is comprised so that the width | variety of the 2nd connection wiring 52 may become narrower than the width | variety of the connection part of the ground side electrode terminal 72 and the 2nd land 42, the said high frequency noise component similarly Is cut off.

  Further, the first through wiring 61 and the second through wiring 62 are embedded in the multilayer circuit board 1 with a conductive material, so that parasitic inductance components derived from the first through wiring 61 and the second through wiring 62 can be reduced. Therefore, the high frequency noise bypass effect of the bypass capacitor 31 in the multilayer circuit board 1 can be increased.

  As described above, according to the multilayer circuit board 1, the arrangement of the bypass capacitor 31, the first through wiring 61, and the second through wiring 62 and the mode of the conductive pattern are optimized. The suppression effect is improved.

DESCRIPTION OF SYMBOLS 1 ... Multilayer circuit board, 11 ... 1st layer, 1N ... N-th layer, 111, 1N1 ... Through hole 21 ... Load 31 ... Bypass capacitor 41 ... 1st land, 42 ... 2nd land 51 ... 1st connection wiring, 52 ... 2nd connection wiring 61 ... 1st penetration wiring, 62 ... 2nd penetration wiring 71 ... Power supply side electrode terminal, 72 ... Grounding side electrode terminal

Claims (5)

A load mounted on a multilayer circuit board;
A bypass capacitor mounted on the multilayer circuit board;
A first land and a second land to which the bypass capacitor is electrically connected; and
A first connection wiring and a second connection wiring for electrically connecting the load and the bypass capacitor;
A first through wiring connected to the first land via a power supply side electrode terminal of the first connection wiring in a state of penetrating the multilayer circuit board;
A multilayer circuit board comprising: a second through wiring connected to the second land via a ground-side electrode terminal of the second connection wiring in a state of penetrating the multilayer circuit board in the vicinity of the first through wiring .   2. The multilayer circuit board according to claim 1, wherein an interval between the first land and the second land is narrower than an interval between the first connection wiring and the second connection wiring.   3. The multilayer circuit board according to claim 1, wherein a width of the first connection wiring is narrower than a width of a connection portion between the power-side electrode terminal and the first land.   4. The multilayer circuit board according to claim 1, wherein a width of the second connection wiring is narrower than a width of a connection portion between the ground-side electrode terminal and the second land.   5. The multilayer circuit board according to claim 1, wherein the first through wiring and the second through wiring are embedded with a conductive material. 6.

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