JP2018092991A - Semiconductor device, electronic apparatus, semiconductor device manufacturing method, wafer and wafer manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve characteristics and/or credibility of a semiconductor device.SOLUTION: A semiconductor device comprises a first substrate having a first semiconductor element, a second substrate having a second semiconductor element, a first wiring structure arranged between the first substrate and the second substrate and a second wiring structure arranged between the first wiring structure and the second substrate. The first wiring structure includes an insulator film; and the insulator film has a first groove, a second groove and a third groove on a surface facing the second wiring structure; and a first part composed of a conductor is arranged in the first groove, and a second part composed of a dielectric substance is arranged in the second groove, and a third part composed of a conductor is arranged in the third groove; and the second part lies between the first part and the third part; and the first part is joined to a fourth part of the second wiring structure, which is composed of a conductor.SELECTED DRAWING: Figure 1

Description

  The present technology relates to a semiconductor device.

  It is known that in a wiring having a damascene structure, dishing and erosion that occur during flattening processing by the CMP method are suppressed by arranging a dummy pattern.

  Patent Document 1 discloses that the wiring layer is constituted by an electrode pad having one surface located on the same plane as the surface of the interlayer insulating film, and a dummy electrode disposed around the electrode pad. ing.

  Patent Document 2 discloses forming dummy wirings in a scribe region.

JP 2012-256736 A JP2015-213134A

  The present inventor has found a problem that the presence of the dummy pattern of Patent Document 1 can deteriorate the characteristics and / or reliability of the semiconductor device.

  SUMMARY An advantage of some aspects of the invention is that it provides a technique advantageous in improving characteristics and / or reliability of a semiconductor device.

  Means for solving the above-described problems include a first substrate having a first semiconductor element, a second substrate having a second semiconductor element, and a first substrate disposed between the first substrate and the second substrate. A semiconductor device comprising: a wiring structure; and a second wiring structure disposed between the first wiring structure and the second substrate, wherein the first wiring structure includes an insulator film, and the insulator A first groove, a second groove, and a third groove are provided on a surface of the film facing the second wiring structure, and a first portion made of a conductor is provided in the first groove. A second portion made of a dielectric is provided in the second groove, and a third portion made of a conductor is provided in the third groove, The second part is located between the first part and the third part, and the first part is a fourth part made of a conductor of the second wiring structure. Characterized in that it is joined to.

  Means for solving the above-described problems include a step of preparing a first substrate having a first semiconductor element, a first component including a first wiring structure disposed on the first substrate, and a second semiconductor element. Preparing a second component including a second wiring structure including a second wiring structure disposed on the second substrate, the first component and the second component, and the first substrate and the second component. Bonding with the second substrate so that the first wiring structure and the second wiring structure are located, wherein the first part of the prepared first component is provided. The one wiring structure includes an insulating film, and a first groove, a second groove, and a third groove are provided on a surface of the insulating film that faces the second wiring structure at the joining stage. A first portion made of a conductor is located in one groove, and a dielectric made in the second groove. A second part is located, a third part made of a conductor is located in the third groove, the second part is located between the first part and the third part, In the joining, the first part is joined to a fourth part made of a conductor having the second wiring structure.

  Means for solving the above problem is a wafer comprising a substrate having a semiconductor element and a wiring structure disposed on the substrate, wherein the wiring structure has a distance to the surrounding atmosphere of less than 100 nm. A first groove, a second groove, and a third groove are provided on the surface of the insulator film, and the first groove is made of a conductor. A first portion is provided, a second portion made of a dielectric is provided in the second groove, and a third portion made of a conductor is provided in the third groove. The second part is located between the first part and the third part, and the distance of the first part and the third part to the atmosphere is less than 100 nm. To do.

  According to the present invention, characteristics and / or reliability of a semiconductor device can be improved.

FIG. 10 is a schematic diagram illustrating a semiconductor device. FIG. 6 is a schematic diagram illustrating a method for manufacturing a semiconductor device. FIG. 6 is a schematic diagram illustrating a method for manufacturing a semiconductor device. FIG. 6 is a schematic diagram illustrating a method for manufacturing a semiconductor device. FIG. 10 is a schematic diagram illustrating a semiconductor device. FIG. 6 is a schematic diagram illustrating a method for manufacturing a semiconductor device.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. Note that, in the following description and drawings, common reference numerals are given to common configurations over a plurality of drawings. Therefore, a common configuration is described with reference to a plurality of drawings, and a description of a configuration with a common reference numeral is omitted as appropriate. In addition, about the element which attached | subjected the code | symbol which is the same name but different, it can distinguish and modify with 1st, 2nd ... as needed.

<First Embodiment>
FIG. 1A shows a cross-sectional view of an example of a semiconductor device IC provided in the semiconductor device IS of this embodiment. Although the semiconductor device of this example is an imaging device and the semiconductor device IC has a structure for the imaging device, the semiconductor device is not limited to the imaging device, and may be an arithmetic device, a storage device, or a control device.

  The semiconductor device IS includes a substrate 100 having a semiconductor element and a substrate 200 having a semiconductor element. The semiconductor device IS includes a wiring structure 110 disposed between the substrate 100 and the substrate 200, and a wiring structure 210 disposed between the wiring structure 110 and the substrate 200. The wiring structure 110 and the wiring structure 210 are bonded at the bonding interface 300.

  The wiring structure 110 includes an insulator film 130 having a groove 131, a groove 132, and a groove 133. The surface of the insulator film 130 that faces the wiring structure 210 is a facing surface 301. The groove 131, the groove 132, and the groove 133 are concave portions provided on the facing surface 301. The outside of the concave portion of the facing surface 301 is a flat portion. In the groove 131, a conductor portion 141 which is a portion made of a conductor is provided. In the groove 132, a dielectric portion 152, which is a portion made of a dielectric, is provided. In the groove 133, a conductor portion 143 which is a portion made of a conductor is provided. The dielectric portion 152 is located between the conductor portion 141 and the conductor portion 143. The conductor portions 141 and 142 are part of the wiring structure 110. Thus, by disposing a portion made of a dielectric instead of a conductor in the groove 132 between the groove 131 where the conductor portion 141 is arranged and the groove 133 where the conductor portion 143 is arranged, the wiring structure 110 wiring capacity can be reduced. Therefore, the electrical characteristics of the wiring structure 110 can be improved.

  The wiring structure 210 includes an insulator film 230 having a groove 231, a groove 232, and a groove 233. A surface of the insulator film 230 that faces the wiring structure 110 is a facing surface 302. The groove 231, the groove 232, and the groove 233 are concave portions provided on the facing surface 302. The outside of the concave portion of the facing surface 302 is a flat portion. In the groove 231, a conductor portion 241 which is a portion made of a conductor is provided. In the groove 232, a dielectric portion 252 which is a portion made of a dielectric is provided. In the groove 233, a conductor portion 243 which is a portion made of a conductor is provided. The dielectric portion 252 is located between the conductor portion 241 and the conductor portion 243. The conductor parts 241 and 243 are a part of the wiring structure 110. In this way, the dielectric portion 252 which is a portion made of a dielectric instead of a conductor is disposed in the groove 232 between the groove 231 where the conductor portion 241 is arranged and the groove 233 where the conductor portion 243 is arranged. As a result, the wiring capacity of the wiring structure 210 can be reduced. Therefore, the electrical characteristics of the wiring structure 110 can be improved.

  In this example, the conductor portion 141 is bonded to the conductor portion 241, and the conductor portion 143 is bonded to the conductor portion 243. The insulator film 130 is bonded to the insulator film 230. The conductor part 141 is joined to the conductor part 241, and the conductor part 143 is joined to the conductor part 243, whereby the wiring structure 110 and the wiring structure 210 are electrically and mechanically coupled. Thus, the semiconductor device IC has a configuration in which the circuit of the substrate 100 and the circuit of the substrate 200 are electrically connected. Each of the conductor parts 141, 143, 241, and 243 can include, for example, a barrier metal layer and a copper layer. Mainly the copper layer can form the bonds described above. The barrier metal layer is disposed between the copper layer and the insulator films 130 and 230. The barrier metal layer is a conductor layer mainly composed of a conductor material different from copper, for example, a layer of tantalum, a tantalum compound, titanium, or a titanium compound.

  The dielectric constituting the dielectric portions 152 and 252 may be the same material as the insulator constituting the insulator films 130 and 230. The dielectric can also be called an insulator. The dielectric constituting the dielectric portions 152 and 252 in this example is a gas. This gas may be air or an inert gas, but may be other gases. The dielectric constituting the dielectric parts 152 and 252 may be solid. The groove 132 may be provided with a vacuum part which is a part constituted by a vacuum, instead of the dielectric part 152 which is a part constituted by a dielectric. Similarly, the dielectric portion 252 may be a vacuum portion. The first meaning of “vacuum” is that the dielectric constituting the dielectric portions 152 and 253 is a gas having a pressure lower than atmospheric pressure. The second meaning of vacuum is a space in which a substance exhibiting at least one of the properties of gas, liquid and solid does not exist. In the case where the dielectric parts 152 and 253 are vacuum parts, the dielectric parts 152 and 253 are configured by a vacuum having the first meaning. That is, even if the dielectric portions 152 and 253 are vacuum portions, gas as a dielectric exists. When the dielectric portions 152 and 252 are made of gas, the dielectric portions 152 and 252 can be referred to as gap portions or space portions. If the dielectric portions 152 and 252 are void portions, the stress generated at the bonding interface 300 can be relaxed by the void portions. For example, the thermal expansion of the insulator films 130 and 230 and the thermal expansion of the conductor portions 141, 143, 241, and 243 can be absorbed by the deformation of the gap portion. Therefore, the reliability of bonding at the bonding interface 300 can be improved.

  In this example, the flat portion of the facing surface 301 of the insulator film 130 and the flat portion of the facing surface 302 of the insulator film 230 are in contact with each other to form the bonding interface 300. However, the adhesive layer can be provided between the facing surface 301 of the insulator film 130 and the facing surface 302 of the insulator film 230. In that case, the bonding interface 300 is formed between the adhesive layer and the facing surface 301 and between the adhesive layer and the facing surface 302, respectively.

  The dielectric constant of the dielectric portion 152 is preferably lower than the dielectric constant of the insulator film 130. Even if the dielectric constant of the dielectric portion 152 is the same as or higher than the dielectric constant of the insulator film 130, the groove 132 is more than the portion made of a conductor like the groove 131 and the groove 133. The wiring capacity of the wiring structure 110 can be reduced. Similarly, the dielectric constant of the dielectric portion 252 is preferably lower than the dielectric constant of the insulator film 230. If the dielectric parts 152 and 252 are made of gas, it is easy to make the dielectric constants of the dielectric parts 152 and 252 lower than the dielectric constants of the insulator films 130 and 230. The dielectric constants of the insulator films 130 and 230 are, for example, 2 or more and 5 or less, and the dielectric constants of the dielectric portions 152 and 252 are 1 or more and 3 or less. The dielectric parts 152 and 252 may be made of both solid and gas. The dielectric portions 152 and 252 made of both solid and gas may be formed of a solid layer and a gas layer, or may be formed of a porous body. The dielectric portion in this example is in contact with the insulator film, and the dielectric portion and the insulator film form an interface. In the grooves 132 and 232, a conductor may be provided in addition to the dielectric portion.

  FIG. 1B shows an example of the configuration of an imaging system SYS including the photoelectric conversion device IS. The imaging system SYS may further include at least one of an optical system OU, a control device CU, a processing device PU, a display device DU, and a storage device MU. Details regarding the imaging system SYS will be described later.

  Details of the semiconductor device IC will be described below. The substrate 100 is made of a semiconductor such as silicon and has a front surface and a back surface. The substrate 100 mainly made of a semiconductor can also be referred to as a semiconductor substrate. A transfer transistor is disposed on the surface of the substrate 100. The transfer transistor includes an n-type semiconductor region 103 that forms a source, an n-type semiconductor region 104 that forms a drain, and a gate electrode 105 that forms a gate. In the substrate 100, an active region having semiconductor regions 103 and 104 is defined by a device isolation part 106 in a semiconductor layer such as silicon.

  In the substrate 100, the semiconductor region 103 is a cathode of a photodiode. The semiconductor region 104 is a floating diffusion. The photodiode can have a buried structure.

  The wiring structure 110 includes interlayer insulating films 111 and 112, a contact layer 114 including a plurality of contact plugs, and a wiring layer 115 including a plurality of wirings. The wiring layer 115 in this example is a copper wiring layer having a single damascene structure, but may be a copper wiring layer having a dual damascene structure or an aluminum wiring layer. Further, the wiring structure 110 includes a connecting portion 121 that connects the conductor portion 141 and the wiring of the wiring layer 115, and a connecting portion 123 that connects the conductor portion 143 and the wiring of the wiring layer 115. The number of wiring layers included in the wiring structure 110 can be arbitrarily set.

  The substrate 200 is made of a semiconductor such as silicon and has a front surface and a back surface. The substrate 200 mainly made of a semiconductor layer can also be referred to as a semiconductor substrate. An amplification transistor is disposed on the surface of the substrate 200. The amplifying transistor includes an n-type semiconductor region 203 that forms a source, an n-type semiconductor region 204 that forms a drain, and a gate electrode 205 that forms a gate. In the substrate 200, an active region having semiconductor regions 203 and 204 is defined by a device isolation part 206 in a semiconductor layer such as silicon.

  The wiring structure 210 includes interlayer insulating films 211 and 212, a contact layer 214 including a plurality of contact plugs, and wiring layers 215 and 225 including a plurality of wirings. The wiring layer 215 in this example is a copper wiring layer having a single damascene structure, and the wiring layer 225 is a copper wiring layer having a dual damascene structure, but the wiring layers 215 and 225 may be aluminum wiring layers. Furthermore, the wiring structure 210 includes a connecting portion 221 that connects the conductor portion 241 and the wiring of the wiring layer 225, and a connecting portion 223 that connects the conductor portion 243 and the wiring of the wiring layer 225. The number of wiring layers included in the wiring structure 210 can be arbitrarily set.

  The wiring structure 110 and the wiring structure 210 are electrically connected via the conductor portions 141, 143, 241, and 243. Thereby, the semiconductor region 104 and the gate electrode 205 are electrically connected. The charge generated by photoelectric conversion in the photodiode and accumulated in the n-type semiconductor region 103 is transferred to the n-type semiconductor region 104 through a transfer channel formed by the gate electrode 105. A potential based on the charge transferred to the n-type semiconductor region 104 is transmitted to the gate electrode 205 through the wiring structure 110 and the wiring structure 210. The potential transmitted to the gate electrode 205 is output as an amplified pixel signal by an amplification transistor that forms a readout circuit such as a source follower circuit.

  On the back side of the substrate 100, a dielectric film 160, a color filter array 170 including a plurality of color filters, and a microlens array 180 including a plurality of microlenses are arranged in this order. The plurality of color filters and the plurality of microlenses each correspond to one photodiode, that is, are arranged for each pixel, but may be provided for each of the plurality of pixels.

Second Embodiment
As a second embodiment, a method for manufacturing the semiconductor device IS described in the first embodiment will be described with reference to FIGS. In the manufacturing method of the semiconductor device IS, it is not necessary to go through all the steps for reaching each step in the following description in the following order, omit at least one step, change the order of steps, A predetermined process for reaching a certain stage can be outsourced.

  FIGS. 2A to 2D show steps a to d for manufacturing the component 12 to be the member 120.

  In step a shown in FIG. 2A, first, the element isolation portion 106 is formed on the substrate 10 which is a semiconductor wafer such as silicon. The element isolation unit 106 includes an insulator such as silicon oxide and has, for example, a LOCOS or STI structure. Then, a well (not shown) of any conductivity type is formed on the substrate 10. After that, n-type semiconductor regions 103 and 104 and a p-type semiconductor region (not shown) that form photoelectric conversion elements and transistors are formed. Further, the gate electrode 105 of the transfer transistor is formed. For example, the gate electrode 105 is formed by depositing and patterning a polysilicon layer, and gate electrodes and wirings other than the gate electrode 105 are also formed from the polysilicon layer.

  Next, the wiring structure 11 is formed on the surface of the substrate 10. Specifically, first, an interlayer insulating film 111 is formed so as to cover the gate electrode 105. The interlayer insulating film 111 is, for example, a silicon oxide film. A contact hole is formed in the interlayer insulating film 111, and a barrier metal film and a tungsten film are formed in the contact hole. The contact layer 114 is formed by removing excess portions of the barrier metal film and the tungsten film. Then, an interlayer insulating film 112 is formed on the interlayer insulating film 111 and the contact layer 114. The interlayer insulating film 112 may be a single layer film of a silicon oxide layer, or may be a multilayer film of a silicon oxide layer and a silicon carbide layer and / or a silicon nitride layer. The interlayer insulating film 112 may include a low-k insulating layer having a dielectric constant of 3.8 or less. A trench is formed in the interlayer insulating film 112, and the wiring layer 115 is formed by a single damascene method. The interlayer insulating film 112 can also include a diffusion prevention layer of a metal such as copper, an etching stop layer when forming a trench, and a cap layer for chemical mechanical polishing (CMP) processing.

  Further, an insulator film 130 is formed on the interlayer insulating film 112 and the wiring layer 115. The insulator film 130 may be a single layer film of a silicon oxide layer, or may be a multilayer film of a silicon oxide layer and a silicon carbide layer and / or a silicon nitride layer. The insulator film 130 has an upper surface 31 that becomes the opposing surface 301. The upper surface 31 can also be referred to as an outer surface. The surface on the substrate 10 side of the insulator film 130 can be referred to as a lower surface or an inner surface.

  A mask 310 having a predetermined pattern is formed on the upper surface 31 of the insulator film 130, the insulator film 130 is etched using the mask 310, and a plurality of grooves (trench) including grooves 131, 132, 133 are formed on the upper surface 31. Form. Further, holes 116 and 118 (via holes) located between the grooves 131 and 133 and the wiring layer 115 are formed. The order of forming the grooves 131 and 133 and the holes 116 and 118 is not limited. In other words, either trench first or via first may be used. Here, an example of via first is shown. The mask 310 can be formed by patterning a photoresist, or may be a hard mask obtained by patterning an inorganic material.

  In step b shown in FIG. 2B, a conductor material comprising a barrier metal film (not shown) having a copper diffusion preventing function so as to fill a plurality of grooves including the grooves 131, 132, and 133, and a copper film. Is deposited. By subjecting the conductor material to a polishing process such as chemical mechanical polishing (CMP), excess barrier metal films and copper films outside the grooves 131, 132, and 133 are removed. Thus, the conductor parts 141, 142, and 143 including the barrier metal layer and the copper layer are formed in the grooves 131, 132, and 133 by the dual damascene method, respectively. In addition, connection portions 121 and 123 including a barrier metal layer and a copper layer are formed in the holes 116 and 118.

  In addition, before forming the insulator film 130 in which the grooves 131, 132, and 133 are formed, the connection portions 121 and 123 are formed in the interlayer insulating film, whereby the conductor portions 141, 142, and 143 are formed by a single damascene method. Can be formed. In that case, it is not necessary to provide the holes 116 and 118 in the insulator film 130 in the step a.

  Next, in step c shown in FIG. 2C, the mask 320 is formed so that the conductor portion 142 which is a part of the plurality of conductor portions arranged in each of the plurality of grooves is exposed. . The mask 320 can be formed by patterning a photoresist.

  Next, in step d shown in FIG. 2D, the conductor portion 142 in the trench 132 is removed by wet etching using a chemical solution such as sulfuric acid using the mask 320. Thereby, the inside of the groove 132 becomes a gap as the dielectric part 152.

  The component 12 having the wiring structure 11 on the substrate 10 can be prepared through the above steps a to d. Since the component 12 has the wiring structure 11 on the substrate 10 which is a semiconductor wafer such as silicon, it can be called a wafer.

  Until the later-described bonding stage (stage i), the flat portions of the upper surface 31 serving as the opposing surfaces 301 of the conductor portions 141 and 143 and the insulator film 130 may be covered with a protective film. The thickness of the protective film can be less than 100 nm, and even less than 10 nm. Therefore, the conductor portions 141 and 143 may have a distance to the surrounding atmosphere of less than 100 nm, or even less than 10 nm. The upper surface 31 serving as the opposing surface 301 of the insulator film 130 may also have a distance to the surrounding atmosphere of less than 100 nm, or even less than 10 nm. Although the oxidation of the conductor portions 141 and 143 can be suppressed by the protective film, the protective film is not essential. When the protective film is not provided, the upper surface 31 and the conductor portions 141 and 143 of the insulator film 130 are exposed to the surrounding atmosphere, and the upper surface 31 and the conductor portions 141 and 143 of the insulator film 130 are exposed. The distance to the surrounding atmosphere is zero.

  By disposing the groove 132 between the groove 131 and the groove 133, it is possible to suppress the occurrence of erosion due to dishing during the CMP process in the step b. By suppressing the occurrence of dishing, the flatness of the flat portions of the upper surfaces of the conductor portions 141 and 143 and the upper surface 31 of the insulator film 130 can be improved. Further, by suppressing the occurrence of erosion, the flatness of the composite surface including the upper surfaces of the conductor portions 141 and 143 and the upper surface 31 of the insulator film 130 which is the opposing surface 301 can be improved. Since the conductor portion 142 formed in the groove 132 is removed in step d, the groove 132 can be referred to as a dummy groove. A plurality of groove patterns including the grooves 131, 132, and 133 may be appropriately designed in order to suppress the occurrence of dishing and erosion.

  FIGS. 3E to 3H show stages e to h for producing the second part to be the second member 220.

  In step e shown in FIG. 3E, first, an element isolation portion 206 is formed on a substrate 20 such as a silicon wafer. The element isolation unit 206 includes an insulator such as silicon oxide and has, for example, a LOCOS or STI structure. Then, an arbitrary conductivity type well (not shown) is formed on the substrate 20. After that, n-type semiconductor regions 203 and 204 constituting the source and drain of the transistor and a p-type semiconductor region (not shown) are formed. Further, the gate electrode 205 of the amplification transistor is formed. For example, the gate electrode 205 is formed by depositing and patterning a polysilicon layer, and gate electrodes and wirings other than the gate electrode 205 are also formed from the polysilicon layer.

  Next, the wiring structure 21 is formed on the surface of the substrate 20. Specifically, first, an interlayer insulating film 211 is formed so as to cover the gate electrode 205. The interlayer insulating film 211 is a silicon oxide film, for example. Contact holes are formed in the interlayer insulating film 211, and a barrier metal film and a tungsten film are formed in the contact holes. The contact layer 214 is formed by removing excess portions of the barrier metal film and the tungsten film. Then, an interlayer insulating film 212 is formed on the interlayer insulating film 211 and the contact layer 214. The interlayer insulating film 212 may be a single layer film of a silicon oxide layer, or may be a multilayer film of a silicon oxide layer and a silicon carbide layer and / or a silicon nitride layer. The interlayer insulating film 212 may include a low-k insulating layer having a dielectric constant of 3.8 or less. A trench is formed in the interlayer insulating film 212, and the wiring layer 215 is formed by a single damascene method. The interlayer insulating film 212 can also include a diffusion prevention layer of metal such as copper, an etching stop layer when forming a trench, and a cap layer for chemical mechanical polishing (CMP) processing.

  Further, an insulator film 230 is formed on the interlayer insulating film 212 and the wiring layer 215. The insulator film 230 may be a single layer film of a silicon oxide layer, or may be a multilayer film of a silicon oxide layer and a silicon carbide layer and / or a silicon nitride layer. The insulator film 230 has an upper surface 32 that becomes the opposing surface 302. The upper surface 32 can also be referred to as an outer surface. The surface of the insulator film 230 on the substrate 20 side can be referred to as a lower surface or an inner surface. A mask 320 having a predetermined pattern is formed on the upper surface 32 of the insulator film 230, the insulator film 230 is etched using the mask 320, and a plurality of grooves (trench) including grooves 231, 232, and 233 on the upper surface 31. Form. Further, holes 216 and 218 (via holes) located between the grooves 231 and 233 and the wiring layer 215 are formed. The order of forming the grooves 231 and 233 and the holes 216 and 218 is not limited. In other words, either trench first or via first may be used. Here, an example of via first is shown. The mask 320 may be formed by patterning a photoresist, or may be a hard mask obtained by patterning an inorganic material.

  In step f shown in FIG. 3 (f), a conductor material comprising a barrier metal film (not shown) having a copper diffusion preventing function so as to fill a plurality of grooves including the grooves 231, 232, and 233, and a copper film. Is deposited. By subjecting the conductor material to a polishing process such as chemical mechanical polishing (CMP), excess barrier metal films and copper films outside the grooves 231, 232, and 233 are removed. As described above, the conductor portions 241, 242, and 243 including the barrier metal layer and the copper layer are formed in the grooves 231, 232, and 233 by the dual damascene method, respectively. In addition, connection portions 221 and 223 including a barrier metal layer and a copper layer are formed in the holes 216 and 218.

  In addition, before forming the insulator film 230 in which the grooves 231, 232, and 233 are formed, the conductor portions 241, 242, and 243 are formed by a single damascene method by forming the connection portions 221 and 223 in the interlayer insulating film. Can be formed. In that case, it is not necessary to provide the holes 216 and 218 in the insulator film 230 in the step e.

  Next, in step g shown in FIG. 3G, the mask 320 is formed so that the conductor portion 242 which is a part of the plurality of conductor portions arranged in each of the plurality of grooves is exposed. . The mask 320 can be formed by patterning a photoresist.

  Next, in step h shown in FIG. 3H, the conductor portion 242 in the groove 232 is removed by wet etching using a chemical solution such as sulfuric acid using the mask 320. Thereby, the inside of the groove 232 becomes a gap as the dielectric portion 252.

  Through the above steps e to h, the component 22 having the wiring structure 21 on the substrate 20 can be prepared. Since the component 22 has the wiring structure 21 on the substrate 20 which is a semiconductor wafer such as silicon, it can be called a wafer.

  Until the later-described bonding stage (stage i), the conductor portions 241 and 243 and the upper surface 32 of the insulator film 230 may be covered with a protective film. The thickness of the protective film can be less than 100 nm, and even less than 10 nm. Therefore, the conductor portions 241 and 243 may have a distance to the surrounding atmosphere of less than 100 nm, more preferably less than 10 nm, corresponding to the thickness of the protective film. The upper surface 32 of the insulator film 230 can also have a distance to the surrounding atmosphere of less than 100 nm, or even less than 10 nm, corresponding to the thickness of the protective film. Although the oxidation of the conductor portions 241 and 243 can be suppressed by the protective film, the protective film is not essential. When the protective film is not provided, the upper surface 32 and the conductor portions 241 and 243 of the insulator film 230 are exposed to the surrounding atmosphere, and the upper surface 32 and the conductor portions 241 and 243 of the insulator film 230 are exposed. The distance to the surrounding atmosphere is zero.

  By disposing the groove 232 between the groove 231 and the groove 233, the occurrence of erosion due to dishing during the CMP process in the step f can be suppressed. By suppressing the occurrence of dishing, the flatness of the flat portions of the upper surfaces of the conductor portions 241 and 243 and the upper surface 31 of the insulator film 230 can be improved. Further, by suppressing the occurrence of erosion, the flatness of the composite surface including the upper surfaces of the conductor portions 242 and 243 and the upper surface 31 of the insulator film 230 which is the facing surface 302 can be improved. Since the conductor portion 242 formed in the groove 232 is removed in the step h, the groove 232 can be called a dummy groove. A plurality of groove patterns including the grooves 231, 232, and 233 may be appropriately designed in order to suppress the occurrence of dishing and erosion.

  4 (i) and 4 (j) show stages i and j for manufacturing a semiconductor device.

  The component 12 and the component 22 are bonded so that the wiring structures 11 and 21 are located between the substrate 10 and the substrate 20 and the wiring structure 11 and the wiring structure 21 face each other. As described above, when the upper surfaces of the insulator films 130 and 230 and the conductor portions 141, 143, 241, and 243 are covered with the protective film, the protective film is preferably removed. However, if the thickness of the protective film is less than 10 nm, the conductor portions 141 and 143 and the conductor portions 241 and 243 can be joined without removing the protective film.

  In the bonding method, the surfaces of the component 12 and the component 22 are subjected to plasma activation processing, and the component 12 and the component 22 are temporarily joined. In the present embodiment, dishing of the conductor portions 141, 143, 241, 243 and erosion of the opposing surfaces 301, 302 can be suppressed. Therefore, the flatness of the bonding interface 300 at the time of bonding can be improved, and the bonding strength can be improved. Thereafter, for example, heat treatment at 350 ° C. is performed to join the insulator film 130 and the insulator film 230, the conductor portion 141 and the conductor portion 241 are joined, and the conductor portion 143 and the conductor portion 243. And join. The conductor portions 141, 143, 241, and 243 are provided only at necessary places. Since the conductor portions 142 and 242 of the grooves 132 and 232 between them are removed in the steps d and h, the influence of the expansion of the conductor portions 141 and 143 during the heat treatment is reduced and the deterioration of the adhesiveness is prevented. effective.

  Next, in step j shown in FIG. 4 (j), after the component 12 and the component 22 are bonded together, the substrate 10 is thinned to form a light receiving surface in the vicinity of the photoelectric conversion portion. Thinning can be performed by CMP or etching. Thereafter, a dielectric film 160, a color filter array 170, and a microlens array 180 are formed on the light receiving surface of the substrate 10. The dielectric film 160 may include a surface protective layer, a planarization layer, and an antireflection layer.

  Thereafter, in the dicing stage, the composite of the component 12 and the component 22 is diced to divide the composite into a plurality of semiconductor device ICs. By dicing, the substrates 10 and 20 become the substrates 100 and 200 in the respective semiconductor device ICs. The wiring structures 11 and 21 become the wiring structures 110 and 210 in the respective semiconductor device ICs. Further, if necessary, the semiconductor device IC is packaged in a packaging stage.

  In this way, the semiconductor device IS described in the first embodiment can be obtained. According to this embodiment, since the wiring capacitance can be reduced, the electrical characteristics of the semiconductor device can be improved. In addition, since stress at the bonding interface 300 can be relaxed, the reliability of bonding can be improved, and the manufacturing yield can be improved.

<Third Embodiment>
As a third embodiment, a modification of the method for manufacturing the semiconductor device IS described in the first embodiment and / or the semiconductor device IS described in the second embodiment will be described with reference to FIG.

  In the example shown in FIG. 5A, conductor portions 142, 144, 146, and 149 are shown as other portions made of the conductor in the plurality of grooves provided in the insulator film 130. Dielectric portions 151, 155, 157, and 158 are shown as other portions made of a dielectric in a plurality of grooves provided in the insulating film 130. FIG. 5A shows conductor portions 242, 245, 246, and 248 as other portions made of the conductor in the plurality of grooves provided in the insulator film 230. Dielectric parts 251, 254, 257, and 259 are shown as other parts made of a dielectric in a plurality of grooves provided in the insulating film 230. The conductor portions 141 and 143 in the first embodiment can be replaced with any of the conductor portions 142, 144, 146, and 149. Similarly, the conductor portions 241 and 243 can be replaced with any of the conductor portions 242, 245, 246, and 248.

  The conductor portion 144 and the dielectric portion 254, the dielectric portion 155 and the conductor portion 245, and the conductor portion 146 and the conductor portion 246 face each other. The dielectric portion 157 and the dielectric portion 257, the dielectric portion 158 and the conductor portion 248, and the conductor portion 149 and the dielectric portion 259 face each other. The dielectric portion 151 and the insulator film 230, and the conductor portion 142 and the insulator film 230 face each other. In this example, the conductor portions 144, 146, 149 and the dielectric portions 155, 157, 158 partially face the insulator film 230, but they may not face the insulator film 230. . The dielectric portion 251 and the insulator film 130, and the conductor portion 242 and the insulator film 130 face each other. In this example, the conductor portions 242, 245, 246, 248 and the dielectric portions 254, 257, 259 are partially opposed to the insulator film 130, but they may not be opposed to the insulator film. Good. The fact that the dielectric part and the insulator part are partially opposed to the insulator film means that the width of the dielectric part and the insulator part that these dielectric parts and the insulator part originally face, This is due to misalignment of time.

  Note that the term “opposite” includes both a case where a member different from the two parts is interposed between the two parts and a case where nothing is interposed between the two parts. A pair of a dielectric part and a conductor part, a pair of a dielectric part and a dielectric part, a pair of a conductor part and a conductor part, a pair of a dielectric part and an insulator film, a conductor part, At least one of the sets of insulator films may be in contact with each other. Furthermore, these mutually contacting sets may be joined together. Bonding is a kind of contact and means a case where a bonding force is generated between two portions.

  The relationship in which the dielectric portion is located between the plurality of conductor portions described in the first embodiment may be satisfied as long as at least one of the wiring structure 110 and the wiring structure 210 is satisfied. The structure of the portion facing the dielectric portion can be appropriately changed as in this example. For example, there may be another dielectric part or a conductor part between the dielectric part and the conductor parts on both sides of the dielectric part. In this case, another conductor portion may face the dielectric member or the dielectric film without facing the conductor portion.

  In the example shown in FIG. 5B, a hole 117 reaching the lower wiring layer 115 is provided continuously to the groove 132. The wiring layer 115 is an aluminum wiring layer. If the wiring layer 115 is a copper wiring layer, if there is a hole 117 under the groove 132 from which the conductor portion is removed, the wiring layer 115 is affected by the etchant through the hole 117. On the other hand, in this example, the wiring layer 115 is an aluminum wiring layer, and an etchant having a higher etching rate with respect to copper than aluminum (for example, 10 times or more) is used. That is, the wiring layer 115 itself is used as an etching stopper. By doing so, damage to the wiring layer 115 can be reduced.

  Step c1 shown in FIG. 5 (c1) is a step corresponding to step c or step g in the second embodiment, and in this example, a modification based on step c will be described. A conductor portion 142 including a barrier metal layer 1421 and a copper layer 1422 is disposed in the trench 132 by the damascene method.

  Stage c2 shown in FIG. 5C2 is a stage corresponding to stage d or stage h of the second embodiment, and in this example, a modification based on stage d will be described. In step c2, the copper layer 1422 is removed while the barrier metal layer 1421 remains in the conductor portion 142 formed in step c1. By using an etchant having an etching rate higher than that of the barrier metal layer 1421 with respect to the copper layer 1422 (eg, 10 times or more), the barrier metal layer 1421 can be left. Thereby, a void portion can be formed in the portion where the copper layer 1422 was present. Since the barrier metal layer 1421 which is a conductor remains, the effect of reducing the wiring capacity is reduced, but since the gap can be formed, the stress can be relaxed. Further, by leaving the barrier metal layer 1421, contamination of the insulator film 130 due to the etchant during the removal of the copper layer 1422 can be suppressed.

  In the example described with reference to FIGS. 5C1 and 5C2, a hole 117 that reaches the lower wiring layer 115 continuously to the groove 132 can be provided as in the example of FIG. By leaving the barrier metal layer 1421 at the bottom of the hole 117, damage to the wiring layer 115 during etching of the copper layer 1422 can be reduced regardless of the type of conductive material of the wiring layer 115.

  Step d1 shown in FIG. 5 (d1) and step d2 shown in FIG. 5 (d2) can be included after step d or step h in the second embodiment. In this example, the steps are included after step d. explain. In step d1, the dielectric material 350 is embedded in the groove 132 in which the gap is formed in step d. The dielectric material 350 can be formed by forming a spin-on-glass (SOG) material into a film by a coating method such as a spin coating method and curing it by heating. By forming the dielectric material 350 using a coating method, the upper surface of the dielectric material 350 is planarized. However, the present invention is not limited to this, and the dielectric material 350 can be formed using a CVD method.

  In step d2, a portion of the dielectric material 350 embedded in step d1 located outside the trench 132 is removed by a CMP method or an etch back method. If the upper surface of the dielectric material 350 is flattened by a coating method in step d1, this removal step can be performed well. In the step d2, the dielectric material 350 needs to be removed at least in a portion located on the conductor portions 141 and 142. A portion of the dielectric material 350 located in the groove 132 becomes a solid dielectric portion 152. By making the dielectric portion 152 solid, the bonding area at the bonding interface 300 is increased, and the bonding strength can be increased. If a material having a dielectric constant lower than that of the insulator film 130 is used for the dielectric material 350, the balance between reduction in capacitance and improvement in bonding strength can be optimized. If a porous material is used for the dielectric material 350, the dielectric material portion 152 is advantageously affected by the deformation due to thermal expansion of the conductor portions 141 and 142.

  Thus, by making the dielectric part 152 solid, the bonding area at the bonding interface 300 increases, and the bonding strength can be increased. If a material having a dielectric constant lower than that of the insulator film 130 is used for the dielectric material 350, the balance between reduction in capacitance and improvement in bonding strength can be optimized.

  The stage e1 shown in FIG. 5 (e1) and the stage e2 shown in FIG. 5 (e2) are stages that can be included after the stage d or the stage h in the second embodiment. explain. In step e1, a dielectric film 360 is formed to cover the groove 132 and the conductor portions 141 and 142 in which the voids are formed in step d. The dielectric film 360 along the shape of the groove 132 can be formed using a CVD method.

  In step e2, the portions of the dielectric film 360 formed in step e1 located on the conductor portions 141 and 142 are removed to form openings 361 and 362 on the conductor portions 141 and 142. The conductor portions 141 and 143 are joined to the conductor portions 241 and 243 through the openings 361 and 362. The openings 361 and 362 may be partially removed by etching the dielectric film 360 using a mask (not shown). The dielectric film 360 remains in the groove 132. The dielectric film 360 has a portion that covers an outer portion (flat portion) of the groove 132 and a portion that is located in the groove 132. The portion remaining in the groove 132 becomes a solid dielectric portion 152, and a void portion may remain in the groove 132 by controlling the thickness of the dielectric film 360 according to the dimension of the groove 132. Therefore, it is advantageous for stress relaxation and capacity reduction. The dielectric film 360 left on the insulator film 130 after the formation of the openings 361 and 362 may be an adhesive layer for increasing the bonding strength of the bonding interface 300. In addition, the dielectric film 360 may be a diffusion preventing layer or a protective film for the metal of the conductor portion of the wiring structure 21 bonded on the insulator film 130. The thickness of the dielectric film 360 is preferably less than 100 nm.

<Fourth embodiment>
A modification of the method for manufacturing the semiconductor device IS described in the second embodiment will be described. This example relates to a configuration of a scribe region to be diced in a composite of the component 12 and the component 22.

  FIG. 6A shows a state in which the component 12 and the component 22 are arranged to face each other immediately before the stage i shown in FIG. The component 12 has a scribe region 410 between the device region 411 and the device region 412. In each of the device region 411 and the device region 412, the above-described conductor portions 141 and 143 and the dielectric portion 152 are disposed. In the scribe region 410, a dielectric portion 451 disposed in the groove 431 of the insulator film 130 and a dielectric portion 452 disposed in the groove 432 of the insulator film 130 are disposed. The dielectric portions 451 and 452 are located between the conductor portions 141 and 143 in the device region 411 and the conductor portions 141 and 143 in the device region 412. There is no conductor portion between the dielectric portion 451 and the dielectric portion 452. In this example, the conductor portion disposed in the groove of the insulator film 130 is not disposed in the scribe region 410 in the state before stage i.

  The component 22 has a scribe area 420 between the device area 421 and the device area 422. In each of the device region 421 and the device region 422, the above-described conductor portions 241 and 243 and the dielectric portion 252 are arranged. The dielectric portions 453 and 454 are located between the conductor portions 241 and 243 in the device region 421 and the conductor portions 241 and 243 in the device region 422. In the scribe region 420, a dielectric portion 453 disposed in the groove 433 of the insulator film 230 and a dielectric portion 454 disposed in the groove 434 of the insulator film 230 are disposed. There is no conductor portion between the dielectric portion 453 and the dielectric portion 454. In this example, the scribe region 420 is not provided with the conductor portion arranged in the groove of the insulator film 230.

  In the state before stage d, the conductor portions are arranged in the grooves 431 and 432. Accordingly, dishing and erosion in the vicinity of the scribe region 410 in the device regions 411 and 412 can be suppressed even when the conductor portion is formed in the groove by the damascene method using the CMP method. Similarly, in the state before stage h, by providing the conductor portions in the grooves 433 and 434, dishing and erosion in the vicinity of the scribe region 420 in the device regions 421 and 422 can be suppressed.

  The conductor portions disposed in the grooves 431 and 432 are removed in step d, and the conductor portions disposed in the grooves 433 and 434 are removed in step h. As a result, the state shown in FIG.

  FIG. 6B shows the state of the stage j shown in FIG. The device region 411 of the component 12 and the device region 421 of the component 22 are joined, and the device region 412 of the component 12 and the device region 422 of the component 22 are joined. Then, the scribe area 410 and the scribe area 420 are joined. In this example, the dielectric portion 451 of the scribe region 410 and the dielectric portion 453 of the scribe region 420 face each other, and the dielectric portion 452 of the scribe region 420 and the dielectric portion 454 of the scribe region 420 face each other. However, the dielectric portions 451 and 452 may face the insulator film 130, and the dielectric portions 453 and 454 may face the insulator film 230. Thereafter, a color filter array, a microlens array, etc. (not shown) are formed.

  FIG. 6 (c) shows the dicing stage after stage j. The component 12 is cut at the scribe region 410 and the component 22 is cut at the scribe region 420 by the dicing method. Thus, the semiconductor device IC is divided into a semiconductor device IC in which the device region 411 and the device region 421 are joined, and a semiconductor device IC in which the device region 412 and the device region 422 are joined.

  In this embodiment, in the scribe regions 410 and 420, the inside of the groove is not a conductor portion but a dielectric portion. Therefore, the conductor portions existing in the scribe regions 410 and 420 can be reduced or eliminated as much as possible. Therefore, it is possible to reduce an unfavorable influence that the conductor portions of the scribe regions 410 and 420 have on the dicing. Undesirable influences include damage to the dicing saw, difficulty in dicing, and contamination by the conductor in removing the conductor portion.

  The imaging system SYS illustrated in FIG. 1B may be an electronic device such as an information terminal having a camera and a photographing function. In addition, the imaging system SYS can be a transportation device such as a vehicle, a ship, or a flying object. The imaging system SYS as a transportation device is suitable for a device that transports the photoelectric conversion device IS and a device that assists and / or automates driving (maneuvering) by a photographing function.

  The semiconductor device IS can further include not only the semiconductor chip IC but also a package PKG that accommodates the semiconductor chip IC. The package PKG of the semiconductor device IS as the photoelectric conversion device can include a base body on which the semiconductor chip IC is fixed and a lid body such as glass facing the semiconductor chip IC. The terminal provided on the base and the terminal provided on the semiconductor chip IC are connected by a connecting member such as a bonding wire or a bump.

  The optical system OU forms an image on the semiconductor device IS as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control unit CU controls the semiconductor device IS and is a semiconductor device such as an ASIC. The processing unit PU processes a signal output from the semiconductor device IS, and is a semiconductor device such as a CPU or an ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device DU is an EL display device or a liquid crystal display device that displays an image obtained by the semiconductor device IS. The storage device MU stores an image obtained by the semiconductor device IS, and is a volatile memory such as SRAM or DRAM, or a nonvolatile memory such as flash memory or hard disk drive.

  The embodiments described above can be modified as appropriate without departing from the spirit of the present invention. The contents of the present disclosure include not only what is clearly stated in the above description but also all matters that can be grasped from the description of the drawings and the description of the manufacturing process.

IS Semiconductor device 100, 200 Substrate 110, 210 Wiring structure 130 Insulator film 301 Opposing surface 131, 132, 133 Groove 141, 143, 241 Conductor part 152 Dielectric part

Claims (20)

A first substrate having a first semiconductor element;
A second substrate having a second semiconductor element;
A first wiring structure disposed between the first substrate and the second substrate;
A second wiring structure disposed between the first wiring structure and the second substrate;
A semiconductor device comprising:
The first wiring structure includes an insulator film;
A first groove, a second groove, and a third groove are provided on a surface of the insulator film facing the second wiring structure;
In the first groove, a first portion made of a conductor is provided,
A second portion made of a dielectric material is provided in the second groove,
A third portion made of a conductor is provided in the third groove,
The second part is located between the first part and the third part;
The semiconductor device according to claim 1, wherein the first portion is bonded to a fourth portion made of a conductor having the second wiring structure.   2. The semiconductor device according to claim 1, wherein the third portion is bonded to a portion made of a conductor of the second wiring structure.   The semiconductor device according to claim 1, wherein a dielectric constant of the second portion is lower than a dielectric constant of the insulator film.   The semiconductor device according to claim 1, wherein the dielectric is a gas.   5. The semiconductor according to claim 1, wherein the dielectric is a dielectric film having a portion that covers an outer portion of the plurality of grooves of the insulator film, and the second portion. 6. apparatus. The first portion is made of copper;
A conductor layer mainly composed of a conductor material different from copper is disposed between the first portion and the insulator film,
The semiconductor device according to claim 1, wherein the second portion forms an interface with the insulator film.   7. The semiconductor device according to claim 1, wherein the second portion is opposed to a portion made of a conductor of the second wiring structure.   The semiconductor device according to claim 1, wherein the second portion is opposed to a portion formed of an insulator of the second wiring structure. The second wiring structure includes an insulator film having a fourth groove and a fifth groove,
The fourth portion is provided in the fourth groove,
The semiconductor device according to claim 1, wherein the second groove opposes the fifth groove.   The semiconductor device according to claim 1, wherein the first semiconductor element is a photodiode, and the second semiconductor element is a transistor. A semiconductor device comprising the first substrate and the second substrate;
A package containing the semiconductor device;
The semiconductor device according to claim 1, comprising: A semiconductor device according to any one of claims 1 to 11,
A processing device for processing a signal output from the semiconductor device;
Electronic equipment comprising. Providing a first substrate having a first semiconductor element and a first component including a first wiring structure disposed on the first substrate;
Preparing a second substrate having a second semiconductor element and a second component including a second wiring structure disposed on the second substrate;
Bonding the first component and the second component such that the first wiring structure and the second wiring structure are positioned between the first substrate and the second substrate;
A method of manufacturing a semiconductor device having
The first wiring structure of the prepared first component includes an insulator film;
A first groove, a second groove, and a third groove are provided on a surface of the insulator film facing the second wiring structure in the bonding step;
A first portion made of a conductor is located in the first groove,
A second portion made of a dielectric material is located in the second groove,
A third portion made of a conductor is located in the third groove,
The second part is located between the first part and the third part;
In the bonding, the first portion is bonded to a fourth portion made of a conductor having the second wiring structure. The step of preparing the first part includes:
Disposing a conductor material in the first groove and the second groove;
Polishing the conductor material; and
The semiconductor device according to claim 13, further comprising a step of removing the conductor material in the second groove while leaving the conductor material in the first groove after the polishing process. Manufacturing method. The second groove is provided in a scribe region;
The composite of the first part and the second part obtained by the joining is cut in the scribe region, and a first chip including the first part and a second chip including the third part are obtained. The method for manufacturing a semiconductor device according to claim 13, comprising: The second wiring structure of the prepared second component includes a second insulator film having a fourth groove and a fifth groove;
The fourth portion is located in the fourth groove,
A fifth portion made of a dielectric or vacuum is located in the fifth groove,
The method for manufacturing a semiconductor device according to claim 13, wherein the second groove and the fifth groove face each other in the bonding.   The method of manufacturing a semiconductor device according to claim 16, wherein, in the bonding, the second portion and the second insulator film face each other. A substrate having a semiconductor element;
A wiring structure disposed on the substrate,
The wiring structure includes an insulator film having a surface whose distance to the surrounding atmosphere is less than 100 nm,
A first groove, a second groove, and a third groove are provided on the surface of the insulator film,
In the first groove, a first portion made of a conductor is provided,
A second portion made of a dielectric material is provided in the second groove,
A third portion made of a conductor is provided in the third groove,
The second part is located between the first part and the third part;
A wafer characterized in that the distance between the first portion and the third portion to the atmosphere is less than 100 nm.   The wafer of claim 18, wherein the second portion is a void. A method of manufacturing a wafer according to claim 18 or 19,
Disposing a conductor material in the first groove, the second groove and the third groove;
Polishing the conductor material; and
Removing the conductor material in the second groove while leaving the conductor material in the first groove after the polishing process.

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