JP7452260B2 - Semiconductor module and semiconductor module manufacturing method - Google Patents

Description

The present invention relates to a semiconductor module and a method for manufacturing a semiconductor module.

Conventionally, a first semiconductor chip section and a second semiconductor chip section stacked on the first semiconductor chip section are provided, and a first connection section of the first semiconductor chip section and a second connection section of the second semiconductor chip section are provided. A semiconductor module has been proposed in which a connecting portion is joined and electrically connected (for example, see Patent Document 1).

Japanese Patent Application Publication No. 2018-182038

A first form of the semiconductor module disclosed in this specification includes a first semiconductor layer having a first circuit, a first wiring electrically connected to the first circuit, and a plurality of semiconductor layers connected to the first wiring. a first wiring layer having one connection portion and a recess disposed between the plurality of first connection portions; a plurality of second connection portions each connected to the plurality of first connection portions; The semiconductor device includes a second wiring layer having a second wiring connected to the second connection portion, and a second semiconductor layer having a second circuit electrically connected to the second wiring.

Further, a second embodiment of the semiconductor module disclosed in this specification includes a first semiconductor layer provided with a first circuit, a first wiring layer provided with a first wiring to which a signal is input from the first circuit, and a first wiring layer provided with a first wiring to which a signal is input from the first circuit. a second wiring layer provided with a second wiring that transmits a signal input from the first wiring, a second semiconductor layer provided with a second circuit to which a signal is inputted from the second wiring, the first wiring and the second wiring. and a recess provided between the plurality of connection parts.

Further, a third embodiment of the semiconductor module disclosed in this specification includes a first semiconductor layer having a first circuit, a first wiring electrically connected to the first circuit, and a first wiring connected to the first wiring. a first wiring layer having a first connection part and a recess; a second connection part connected to the first connection part; a second wiring connected to the second connection part; and a convex part accommodated in the recess. and a second semiconductor layer having a second circuit electrically connected to the second wiring.

Further, a first embodiment of the method for manufacturing a semiconductor module disclosed in this specification includes a first semiconductor layer having a first circuit, a first wiring layer having a first surface exposed to the outside, and a first wiring layer having a first surface exposed to the outside. A first wiring layer in a first semiconductor chip portion including a first wiring layer electrically connected to a first wiring layer and a plurality of first connection parts disposed on a first surface and connected to the first wiring. a second wiring layer having a second surface exposed to the outside, forming a recess between the plurality of first connection portions on one surface; a second wiring layer having a plurality of second connection parts disposed at corresponding positions in the second plane, and a second wiring connected to the plurality of second connection parts, and a second wiring layer; the first surface and the first surface so that each of the plurality of second connection parts in the second semiconductor chip section including the second semiconductor layer having the second circuit electrically connected to the second connection part is connected to the corresponding first connection part. The second semiconductor chip section includes stacking the second semiconductor chip section on the first semiconductor chip section with two sides facing each other.

Furthermore, a second embodiment of the method for manufacturing a semiconductor module disclosed in this specification includes a first semiconductor layer having a first circuit, a first wiring layer having a first surface exposed to the outside, and a first wiring layer having a first surface exposed to the outside. In a first semiconductor chip section including a first wiring layer electrically connected to a circuit and a first wiring layer having a plurality of first connection parts disposed on a first surface and connected to the first wiring. A second wiring layer having a concave portion formed on the first surface and a second surface exposed to the outside, wherein the second wiring layer is arranged on the second surface and corresponds to each of the plurality of first connection portions. a second wiring layer having a plurality of second connection parts disposed at in-plane positions and a second wiring connected to the plurality of second connection parts; and a second wiring layer electrically connected to the second wiring. forming a convex portion that can be accommodated by the concave portion at a position corresponding to the concave portion on a second surface of the second semiconductor chip portion including a second semiconductor layer having two circuits; and accommodating the convex portion in the concave portion. and a second semiconductor chip section is placed on the first semiconductor chip section with the first surface and the second surface facing each other so that each of the plurality of second connection sections is connected to the corresponding first connection section. including laminating.

1 is a diagram showing a stacked structure of a first embodiment of a semiconductor module disclosed in this specification. 2 is a diagram showing a cross section taken along line XX of the semiconductor module of the first embodiment in FIG. 1. FIG. 2 is a diagram showing an XX-ray exploded cross section of the semiconductor module of the first embodiment in FIG. 1. FIG. (A) is a diagram showing the first surface of the semiconductor module of the first embodiment, and (B) is a diagram showing the second surface. (A) is a diagram showing the distance between the first connecting parts along the surface of the first surface, and (B) is a diagram showing the distance between the second connecting parts along the surface of the second surface. be. (A) is a diagram showing the first surface of a modification of the semiconductor module of the first embodiment, and (B) is a diagram showing the second surface. FIG. 3 is a diagram showing a cross section of a second embodiment of the semiconductor module disclosed in this specification. FIG. 7 is a diagram showing a cross section of a third embodiment of a semiconductor module disclosed in this specification. FIG. 7 is a diagram showing a cross section of a fourth embodiment of a semiconductor module disclosed in this specification. FIG. 7 is a diagram showing a cross section of a fifth embodiment of a semiconductor module disclosed in this specification. FIG. 7 is a diagram showing a cross section of a sixth embodiment of a semiconductor module disclosed in this specification. FIG. 2 is a diagram (part 1) showing the manufacturing process of the first embodiment of the semiconductor module disclosed in this specification. FIG. 2 is a diagram (part 2) showing the manufacturing process of the first embodiment of the semiconductor module disclosed in this specification. FIG. 3 is a diagram (part 3) illustrating the manufacturing process of the first embodiment of the semiconductor module disclosed in this specification. FIG. 4 is a diagram (part 4) showing the manufacturing process of the first embodiment of the semiconductor module disclosed in this specification. FIG. 5 is a diagram (part 5) showing the manufacturing process of the second embodiment of the semiconductor module disclosed in this specification. It is a figure which shows the manufacturing process of 2nd Embodiment of the semiconductor module disclosed in this specification.

Hereinafter, a preferred first embodiment of the semiconductor module disclosed in this specification will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the invention described in the claims and equivalents thereof.

FIG. 1 is a diagram showing a stacked structure of a first embodiment of a semiconductor module disclosed in this specification. FIG. 2 is a diagram showing a cross section taken along line XX of the semiconductor module of the first embodiment shown in FIG. FIG. 3 is a diagram showing an XX-line exploded cross section of the semiconductor module of the first embodiment shown in FIG.

The semiconductor module 1 of this embodiment is an imaging device as an example, and generates an image based on received light. The semiconductor module 1 includes a first semiconductor chip section 10 and a second semiconductor chip section 20 stacked on the first semiconductor chip section 10. The semiconductor module 1 has a stacked structure in which a first semiconductor chip section 10 is stacked on a second semiconductor chip section 20. The first semiconductor chip section 10 has a pixel region 111 in which pixels 1111 including photoelectric conversion elements that convert received light into electrical signals are arranged in a two-dimensional array. The second semiconductor chip section 20 has a logic circuit area 211 that processes electrical signals generated by the pixels 1111 of the pixel area 111. The logic circuit area 211 includes, for example, a circuit that converts each of the electrical signals generated by the plurality of pixels 1111 arranged in the pixel area 111 from analog to digital.

The semiconductor module 1 separately includes a first semiconductor chip section 10 having a pixel region 111 and a second semiconductor chip section 20 having a logic circuit region 211. Thereby, the semiconductor module 1 can arrange more pixels 1111 in the pixel area 111 and generate a high-resolution image. Furthermore, the semiconductor module 1 can arrange more circuits in the logic circuit area 211 and process electrical signals generated by the pixel area 111 at high speed.

The first semiconductor chip section 10 has a first semiconductor layer 11 and a first wiring layer 12.

The first semiconductor layer 11 is formed using a semiconductor such as a silicon substrate. The first semiconductor layer 11 includes a pixel region 111 and an electrode pad 17 arranged on the light-receiving surface, and a via 16.

The pixel area 111 has a plurality of pixels 1111 arranged in a two-dimensional array. The plurality of pixels 1111 generate electrical signals representing an image by converting received light into electrical signals. Each pixel 1111 has a drive circuit (an example of a first circuit) 1111a that drives a photoelectric conversion element included in the pixel 1111. Further, a control circuit (not shown) that scans each pixel 1111 may be arranged in the first semiconductor layer 11.

Via 16 is formed using a conductor such as copper. The via 16 penetrates the first semiconductor layer 11 , one end extends into the first wiring layer 12 , and the other end is electrically connected to the electrode pad 17 . The pixel region 111 and the electrode pad 17 are electrically connected via wiring (not shown). Electric signals generated by the pixels 1111 arranged in the pixel region 111 are input to the first wiring layer 12 via the drive circuit 1111a, the electrode pads 17, and the vias 16.

The first wiring layer 12 is formed using an electrical insulator such as silicon dioxide. The first wiring layer 12 has a first surface 121 and a second surface 122. The second semiconductor chip section 20 is arranged on the first surface 121. The first semiconductor layer 11 is arranged on the second surface 122. A plurality of first wirings 13 are arranged inside the first wiring layer 12 . The first wiring 13 is formed using a conductor such as copper, for example.

FIG. 4(A) is a diagram showing the first surface 121 of the semiconductor module 1 of the first embodiment. On the first surface 121, a plurality of first connecting portions 14 are arranged to be exposed. The first connection portion 14 is formed using a conductor such as copper, for example. In the example shown in FIG. 4(A), the first connecting portion 14 has a rectangular shape when viewed from above. The plurality of first connecting portions 14 are arranged in a two-dimensional array on the first surface 121 at the same intervals in the X direction and the Y direction perpendicular to the X direction. Each of the plurality of first connection parts 14 is electrically connected to the pixel 1111 of the pixel region 111 via the first wiring 13, the via 16, and the like. One first connection portion 14 is electrically connected to one or more pixels 1111.

On the first surface 121 , a recess 15 is arranged between the plurality of first connection parts 14 . In the example shown in FIG. 4(A), one recess 15 is arranged between two to four first connection parts 14. The recess 15 protrudes from the first surface 121 of the first wiring layer 12 toward the second surface 222 to the inside of the first wiring layer 12 . In the example shown in FIG. 4(A), the recess 15 has the shape of a square pyramid, and the sides of the square pyramid are indicated by chain lines. The plurality of recesses 15 are arranged in a two-dimensional array in the X direction and the Y direction on the first surface 121. One first connection portion 14 is surrounded by a plurality of recesses 15 . In the example shown in FIG. 4(A), one first connection portion 14 is surrounded by eight recesses 15. In the example shown in FIG.

The second semiconductor chip section 20 has a second semiconductor layer 21 , a second wiring layer 22 , and a third wiring layer 26 .

The second semiconductor layer 21 is formed using a semiconductor such as a silicon substrate. The second semiconductor layer 21 has a logic circuit region 211 and a via 27 . The via 27 penetrates the second semiconductor layer 21, one end extends to the inside of the second wiring layer 22, and the other end extends to the inside of the third wiring layer 26. .

The logic circuit area 211 has a circuit that converts each of the electrical signals generated by the plurality of pixels 1111 arranged in the pixel area 111 from analog to digital. The logic circuit area 211 outputs an analog electrical signal representing the image generated by the pixel area 111 as a digital electrical signal. The logic circuit area 211 (which is an example of the second circuit) and the electrode pad 28 are electrically connected via wiring (not shown) included in the third wiring layer 26.

The second wiring layer 22 is formed using an electrical insulator such as silicon dioxide. The second wiring layer 22 has a first surface 121 and a second surface 222. The second semiconductor layer 21 is arranged on the first surface 121. The first semiconductor chip section 10 is arranged on the second surface 222. Specifically, the first surface 121 of the first wiring layer 12 is arranged on the second surface 222 of the second wiring layer 22 . The electrically insulating portion of the second wiring layer 22 is joined to the electrically insulating portion of the first wiring layer 12 . A plurality of second wirings 23 are arranged inside the second wiring layer 22 . The second wiring 23 is formed using a conductor such as copper, for example. The logic circuit area 211 and the second wiring 23 are electrically connected via wiring (not shown) included in the third wiring layer 26 and vias 27.

FIG. 4(B) is a diagram showing the second surface 222 of the semiconductor module 1 of the first embodiment. On the second surface 222, a plurality of second connecting portions 24 are arranged to be exposed. The plurality of second connection parts 24 are arranged at positions within the second surface 222 corresponding to each of the plurality of second connection parts 14. The second connection portion 24 is formed using a conductor such as copper, for example. The plurality of second connecting portions 24 are joined to and electrically connected to the corresponding first connecting portions 14 . In the semiconductor module 1, the first connecting portion 14 and the second connecting portion 24 are bonded and integrated to function as a connecting portion that electrically connects the first wiring 13 and the second wiring 23. The second connecting portion 24 preferably has the same shape as its corresponding first connecting portion 14 in plan view. In the example shown in FIG. 4(B), the second connecting portion 24 has the same rectangular shape as the first connecting portion 14 when viewed from above. The plurality of second connection parts 24 are arranged in a two-dimensional array at the same intervals in the X direction and the Y direction on the second surface 222, corresponding to the first connection parts 14 arranged on the first surface 121. There is. Each of the plurality of second connection parts 24 is electrically connected to the via 27 via the second wiring 23.

On the second surface 222 , a convex portion 25 is arranged between the plurality of second connecting portions 24 . In the example shown in FIG. 4(B), one convex portion 25 is arranged between two to four second connecting portions 24. In the example shown in FIG. The convex portion 25 protrudes from the second surface 222 of the second wiring layer 22 to the inside of the first wiring layer 12 . The convex portion 25 has a shape that can be accommodated in the concave portion 15. It is preferable that each of the plurality of convex parts 25 is accommodated in its corresponding concave part 15, and the concave part 15 and the convex part 25 are joined. In the example shown in FIG. 4(B), the convex portion 25 has a quadrangular pyramid shape corresponding to the concave portion 15, and the sides of this quadrangular pyramid are shown by solid lines. The convex portions 25 are arranged in a two-dimensional array in the X direction and the Y direction on the second surface 222. One second connection portion 24 is surrounded by a plurality of convex portions 25 . In the example shown in FIG. 4(B), one second connection portion 24 is surrounded by eight convex portions 25. In the example shown in FIG.

By joining the first surface 121 of the first wiring layer 12 and the second surface 222 of the second wiring layer 22, the first semiconductor chip section 10 and the second semiconductor chip section 20 are joined. The second wiring 23 of the second wiring layer 22 receives an electrical signal from the first wiring 13 of the first wiring layer 12, and this electrical signal is transmitted to the logic circuit of the second semiconductor layer 21 via the third wiring layer 26. It is transmitted to area 211.

The third wiring layer 26 is formed using an electrical insulator such as silicon dioxide. The third wiring layer 26 has an electrode pad 28 and an electrode pad 29. Electrode pad 28 and electrode pad 29 are electrically connected via wiring (not shown).

In the semiconductor module 1, each of the electrical signals generated by the plurality of pixels 1111 arranged in the pixel region 111 is transmitted to the drive circuit 1111a, the electrode pad 17, the via 16, the first wiring 13, and the first connection portion. 14, the second connection portion 24, the second wiring 23, the via 27, and the third wiring layer 26, the signal is transmitted to the logic circuit area 211. Furthermore, electrical signals output from the logic circuit area 211 are extracted from the plurality of electrode pads 29.

As described above, it is preferable that the semiconductor module 1 be able to generate high-resolution images and process signals generated from the images at high speed. From the viewpoint of generating a high-resolution image, many pixels 111 are arranged in the pixel area 111. From the viewpoint of reading out the signals of many pixels 111, it is preferable that the signals of these pixels 111 be read out in parallel. From the viewpoint of reading signals from a plurality of pixels 111 in parallel, the semiconductor module 1 includes a first semiconductor chip section 10 having a plurality of first connection sections 14 on a first surface 121 of a first wiring layer 12, and a second wiring layer 12. It has a laminated structure with a second semiconductor chip section 20 having a plurality of second connection sections 24 on the second surface 222 of the layer 22 . From the viewpoint of processing the signals generated by the pixels 111 at high speed, it is preferable that the number of pairs of the first connection section 14 and the second connection section 24 is large. If possible, it is preferable that the signal of one pixel 111 be read out via a pair of the first connection part 14 and the second connection part 24 corresponding only to this pixel. On the other hand, the dimensions of the semiconductor module 1 are restricted by standards, so there is an upper limit. Therefore, when a large number of first connection parts 14 are arranged on the first surface 121 of the first wiring layer 12, the interval between adjacent first connection parts 14 must become narrow. When the distance between adjacent first connecting portions 14 becomes narrower, there is a higher possibility that the adjacent first connecting portions 14 will be short-circuited than before. Next, how the recessed portion 15 prevents short circuit between adjacent first connecting portions 14 will be described below with reference to FIG. 5(A).

FIG. 5(A) is a diagram showing the distance between the first connecting portions 14 along the surface of the first surface 121. As shown in FIG. 5A, the recess 15 increases the distance between two adjacent first connecting portions 14 along the surface of the first surface 121. As shown in FIG. By disposing the recess 15 on the first surface 121, the distance L1 between the two adjacent first connecting portions 14 along the surface of the first surface 121 is the same as that between the two adjacent first connecting portions 14 when the recess 15 is not disposed. The distance is longer than the distance L2 between one connection part 14. This means that by arranging the recess 15 between the plurality of first connection parts 14, the surface area of the first surface 121 between the plurality of first connection parts 14 is increased compared to when the recess 15 is not arranged. It can also be said that it will expand. In this specification, the recesses 15 do not include recesses that create surface roughness in areas of the first surface 121 where the recesses 15 are not arranged. For example, the depth h1 of the recess 15 is about twice to 200 times the arithmetic mean roughness of the region of the first surface 121 where the recess 15 is not arranged.

In the manufacturing process of the semiconductor module 1, before the first semiconductor chip section 10 and the second semiconductor chip section 20 are bonded, the surface oxide film of the first connection section 14 exposed on the first surface 121 is, for example, , removed by activation treatment such as plasma. At this time, fine particles of a conductor such as copper forming the surface of the first connecting portion 14 are generated and adhere to the first surface 121 . When a conductive structure connecting two adjacent first connection parts 14 is formed by these conductor particles, the two first connection parts 14 are short-circuited by this structure. As a result, the electrical signals generated in the pixel region 111 may not be properly sent to the logic circuit region 211.

In the semiconductor module 1, the recess 15 is arranged between the two adjacent first connection parts 14 on the first surface 121, thereby increasing the distance between the two adjacent first connection parts 14, and thereby achieving the above-described effect. This suppresses the formation of such a structure, and prevents the two first connecting portions 14 from shorting. From the above-mentioned viewpoint, it is preferable that the distance L1 is 1.2 to 2.5 times the distance L2. Since the distance L1 is 1.2 times or more the distance L2, it is possible to suppress short-circuiting between the two first connecting portions 14. On the other hand, if the distance L1 is longer than 2.5 times the distance L2, the number of first connecting portions 14 arranged on the first surface 121 may decrease.

Next, how the convex portion 25 prevents a short circuit between adjacent second connecting portions 24 will be described below with reference to FIG. 5(B).

FIG. 5(B) is a diagram showing the distance between the second connecting portions 24 along the surface of the second surface 222. FIG. As shown in FIG. 5(B), the convex portion 25 increases the distance between two adjacent first connecting portions 14 along the surface of the second surface 222. As shown in FIG. By disposing the convex portion 25 on the second surface 222, the distance L3 between two adjacent second connecting portions 24 along the surface of the second surface 222 is equal to the distance L3 between two adjacent second connecting portions 24 when the convex portion 25 is not disposed. This distance is longer than the distance L4 between the two second connecting portions 24. This means that by disposing the convex portion 25 between the plurality of second connecting portions 24, the convex portion 25 covers the surface area of the second surface 222 between the plurality of second connecting portions 24. It can also be said that the expansion will be greater than if it were not done. In this specification, the convex portion 25 does not include a convex portion that forms surface roughness in a region of the second surface 222 where the convex portion 25 is not arranged. For example, the height h2 of the convex portion 25 is about twice to 200 times the arithmetic mean roughness of the area on the second surface 222 where the convex portion 25 is not arranged.

In the semiconductor module 1, the convex portion 25 is arranged between the two adjacent second connecting portions 24 on the second surface 222, so that the distance between the two adjacent second connecting portions 24 is expanded. This suppresses the formation of the above-described structure and prevents the two second connecting portions 24 from shorting. From the above-mentioned viewpoint, it is preferable that the distance L3 is 1.2 to 2.5 times the distance L4 from the same viewpoint as explained for the distance L1.

Next, how the recessed portion 15 and the convex portion 25 reduce the positional deviation between the first connecting portion 14 and the second connecting portion 24 will be described below.

During the manufacturing process, the semiconductor module 1 has a first surface 121 and a second surface 222 such that each of the plurality of second connection sections 24 is joined to and electrically connected to the corresponding first connection section 14. The first semiconductor chip section 10 is stacked and formed on the second semiconductor chip section 20 so as to face each other. At this time, the recess 15 on the first surface 121 of the first semiconductor chip section 10 and the recess 15 on the second surface 222 of the second semiconductor chip section 20 are such that the first semiconductor chip section 10 is located on the second semiconductor chip section 20. It has the function of adjusting the alignment position when stacked on the substrate. That is, when the first surface 121 of the first semiconductor chip section 10 and the second surface 222 of the second semiconductor chip section 20 are brought close to each other, the apexes of each of the plurality of convex parts 25 are accommodated in the corresponding concave part 15. , each of the plurality of convex portions 25 is accommodated in its corresponding concave portion 15, so that the first semiconductor chip portion 10 is guided in a predetermined positional relationship with respect to the second semiconductor chip portion 20. . As a result, the position of each of the plurality of first connection parts 14 on the first surface 121 of the first semiconductor chip section 10 coincides with the position of the corresponding second connection part 24. Thereby, good bonding and electrical connection can be obtained between the first connecting portion 14 and the second connecting portion 24 corresponding to the first connecting portion 14. As the alignment position shift when the first semiconductor chip section 10 is stacked on the second semiconductor chip section 20, for example, a distance about the size of the recess 15 may be allowed.

The shape of the convex portion 25 is not particularly limited as long as it can be accommodated in the concave portion 15. It is particularly preferable that the convex portion 25 has a shape that fits into the concave portion 15 from the viewpoint of ensuring the bonding strength between the first semiconductor chip portion 10 and the second semiconductor chip portion 20 and reducing the amount of misalignment. Further, it is preferable that the convex portion 25 has a tapered shape from the viewpoint of reducing the amount of positional deviation. The convex portion 25 may have a shape other than a quadrangular pyramid. For example, the convex portion 25 may have a shape such as a triangular pyramid, a pentagonal pyramid, or a cone.

According to the semiconductor module of the present embodiment described above, since the recessed portion is provided between the plurality of first connection portions, it is possible to prevent the first connection portions of the first wiring layer from being short-circuited. Further, according to the semiconductor module of the present embodiment, since the convex portion is provided between the plurality of second connection portions, it is possible to prevent the second connection portions of the second wiring layer from being short-circuited. Further, according to the semiconductor module of the present embodiment, the semiconductor module includes a recess disposed on the first surface of the first wiring layer and a protrusion disposed on the second surface of the second wiring layer and accommodated in the recess. , displacement of the first connection part and the second connection part is prevented, and good bonding and electrical connection can be obtained between the first connection part and the second connection part.

In recent years, as the resolution of imaging devices, which are an example of semiconductor modules, has improved, there has been a demand for an increase in the number of pixels arranged in a pixel region. As the number of pixels increases, a corresponding increase in the number of first connection parts and second connection parts is required. As the number of first connecting parts and second connecting parts increases, the distance between adjacent first connecting parts and the distance between adjacent second connecting parts decrease. In the semiconductor module of this embodiment, even if the distance between adjacent first connecting portions and the distance between adjacent second connecting portions are reduced, the first connecting portion and the second connecting portion corresponding to the first connecting portion are A good bond and electrical connection is provided between the two connections.

FIG. 6(A) is a diagram showing the first surface of a modified example of the semiconductor module of the first embodiment, and FIG. 6(B) is a diagram showing the second surface.

In the semiconductor module of this modification, one first connection portion 14 is surrounded by four recesses 15, as shown in FIG. 6(A). In the first surface 121, a recess 15 is arranged between two adjacent first connecting portions 14 in the X direction and in the Y direction perpendicular to the In the direction (the 45 degree direction in FIG. 6A), the recess 15 is not disposed between two adjacent first connecting portions 14.

Further, as shown in FIG. 6(B), in the semiconductor module of this modification, one second connection portion 24 is surrounded by four convex portions 25. As shown in FIG. In the second surface 222, a convex portion 25 is arranged between two adjacent second connecting portions 24 in the X direction and the Y direction, but in the X direction or in a direction crossing the X direction (see FIG. In B), the convex portion 25 is not arranged between two adjacent second connecting portions 24 in the 45 degree direction).

According to the semiconductor module of this modification described above, the number of recesses 15 on the first surface 121 is reduced, so the area of the flat region on the first surface 121 is increased. Similarly, since the number of convex portions 25 on the second surface 222 is reduced, the area of the flat region on the second surface 222 is increased. Since the area of the bonding region between the flat region on the first surface 121 and the flat region on the second surface 222 increases, the bonding strength between the first semiconductor chip section 10 and the second semiconductor chip section 20 can be further increased. can be improved.

Next, other embodiments of the above-described semiconductor module will be described below with reference to FIGS. 7 to 11. Regarding the points not particularly described in other embodiments, the detailed explanation regarding the above-mentioned first embodiment applies as appropriate. Moreover, the same components are given the same reference numerals.

FIG. 7 is a diagram showing a cross section of a second embodiment of the semiconductor module disclosed in this specification. In the semiconductor module 2 of this embodiment, the cross-sectional shapes of the concave portions 15a and the convex portions 25a are rectangular. Since the recessed portion 15a has a rectangular cross-sectional shape, the two adjacent first recesses along the surface of the first surface 121 are The distance between the connecting parts 14 is further increased. Thereby, it is possible to further prevent the formation of a structure that connects the two first connecting portions 14.

Further, since the convex portion 25a has a rectangular cross-sectional shape, the distance between the two adjacent second connecting portions 24 along the surface of the second surface 222 is greater than when the cross-sectional shape is a triangle. Increase the distance. Thereby, it is possible to further prevent the formation of a structure that connects the two second connecting portions 24.

According to the semiconductor module of the present embodiment described above, since the cross section of the recess disposed between the plurality of first connection portions is rectangular, short-circuiting between the first connection portions of the first wiring layer is further reduced. Prevented. Further, according to the semiconductor module of the present embodiment, since the convex portion disposed between the plurality of second connection portions has a rectangular cross section, short circuits between the second connection portions of the second wiring layer are prevented. further prevented.

FIG. 8 is a diagram showing a cross section of a third embodiment of the semiconductor module disclosed in this specification. In the semiconductor module 3 of this embodiment, if a structure is formed between two adjacent first connection parts 14 and there is a relatively high possibility that these two first connection parts 14 will be short-circuited, the recessed part is arranged between these two first connection parts 14. On the other hand, if there is a relatively low possibility that the two first connections 14 will be short-circuited, the recess is not disposed between these two first connections 14 . Similarly, if a structure is formed between two adjacent second connection parts 24 and there is a relatively high possibility that these two second connection parts 24 will be short-circuited, the convex part The second connecting portion 24 is disposed between two second connecting portions 24 . On the other hand, if the possibility of short-circuiting of the two second connection parts 24 is relatively low, the convex part is not arranged between these two second connection parts 24. Specifically, in the semiconductor module 3 of this embodiment, the recess 15b is arranged at a location where the straight-line distance between two adjacent first connection parts 14 is shorter than a predetermined threshold value. This straight line distance corresponds to distance L2 in FIG. 5(A). The recessed portion 15b is not arranged at a location where the straight-line distance between two adjacent first connecting portions 14 is equal to or greater than a predetermined threshold value. Similarly, in the semiconductor module 3 of this embodiment, the convex portion 25b is arranged at a location where the straight-line distance between two adjacent second connection portions 24 is shorter than a predetermined threshold value. This straight line distance corresponds to distance L4 in FIG. 5(B). The convex portion 25b is not arranged at a location where the straight-line distance between two adjacent second connecting portions 24 is equal to or greater than a predetermined threshold value. This threshold value can be determined based on, for example, the dimensions of the first connecting portion 14 and the second connecting portion 24 and the interval at which the first connecting portion 14 and the second connecting portion 24 are arranged. Further, in the semiconductor module 3 of this embodiment, the cross-sectional shapes of the concave portions 15a and the convex portions 25a are rectangular. Note that the recessed portion 15b is arranged in a region where the areal density of the first connection portions 14 on the first surface 121 is smaller than a predetermined threshold, and similarly, the convex portion 25b is arranged in a region where the surface density of the first connection portions 14 on the first surface 121 is smaller than a predetermined threshold. The area density of the portions 24 may be arranged in a region smaller than a predetermined threshold value.

According to the semiconductor module of the present embodiment described above, the recesses are arranged at locations where there is a relatively high possibility that two adjacent first connection parts will be short-circuited, so the number of recesses formed is reduced. Thereby, it is possible to simplify the design and inspection process of semiconductor modules and improve productivity. Similarly, according to the semiconductor module of this embodiment, the protrusions are arranged at locations where the possibility of short-circuiting between the two second connection parts is relatively high, so the number of protrusions formed is reduced. By doing so, it is possible to simplify the design and inspection process of semiconductor modules and improve productivity.

FIG. 9 is a diagram showing a cross section of a fourth embodiment of the semiconductor module disclosed in this specification. In the semiconductor module 4 of this embodiment, the first wiring layer 12 has the same number of recesses 15c as the plurality of first connection parts 14a, and the second wiring layer 22 has the same number of recesses 15c as the plurality of second connection parts 24a. It has a convex portion 25c. Each of the plurality of first connection parts 14a is arranged in one recess 15c, and each of the plurality of second connection parts 24a is arranged in one protrusion 25c. The concave portion 15c and the convex portion 25c have a quadrangular pyramid shape similarly to the first embodiment described above.

With each of the plurality of protrusions 25 accommodated in the corresponding recess 15, the first connection part 14a and the second connection part 24a are joined and electrically connected.

In the semiconductor module 4 of this embodiment, by adjusting the dimensions of the recess 15c, the dimensions of the first connecting portion 14a can be made larger than in the first embodiment. Similarly, in the semiconductor module 4 of this embodiment, by adjusting the dimensions of the convex portion 25c, the dimensions of the second connecting portion 24a can be made larger than in the first embodiment. Thereby, in the semiconductor module 1 of this embodiment, the bonding strength between the first connection part 14a and the second connection part 24a can be made greater than that of the first embodiment.

Furthermore, according to the semiconductor module of the present embodiment, by adjusting the dimensions and arrangement intervals of the recesses, the intervals at which the first connection parts are arranged can be made shorter than in the first embodiment. Similarly, in the semiconductor module of this embodiment, by adjusting the dimensions and arrangement intervals of the convex parts, the intervals at which the second connection parts are arranged can be made shorter than in the first embodiment. As a result, in the semiconductor module of this embodiment, the number of first connection parts arranged on the first surface and the number of second connection parts arranged on the second surface are increased compared to the first embodiment described above. be able to.

Note that in the semiconductor module of this embodiment, the first connection portions may not be arranged in all the recesses. Similarly, the second connection portions may not be arranged on all the convex portions. In this case, one of the plurality of first connection parts is disposed in the recess, and one second connection connected to one of the first connection parts 1 is placed in the convex part accommodated in the recess. section is placed.

FIG. 10 is a diagram showing a cross section of a fifth embodiment of the semiconductor module disclosed in this specification. In the semiconductor module 5 of this embodiment, the second wiring layer 22 does not have a convex portion. The recess 15 of the first wiring layer 12 is hollow.

According to the semiconductor module of the present embodiment described above, since the recessed portion is provided between the plurality of first connection portions, a short circuit between the first connection portions included in the first wiring layer is prevented.

FIG. 11 is a diagram showing a cross section of a sixth embodiment of the semiconductor module disclosed in this specification. The semiconductor module 6 of this embodiment includes a pixel arrangement region 6a where the pixel region 111 is arranged when viewed from above, and a non-pixel arrangement region 6b where the pixel region 111 is not arranged. In the semiconductor module 6 of this embodiment, the concave portion 15d and the convex portion 25d accommodated in the concave portion 15d are arranged in the non-pixel arrangement region 6b. That is, the concave portion 15d and the convex portion 25d are not arranged in the pixel arrangement region 6a.

In the semiconductor module 6 of this embodiment, since the recessed portion 15d is not arranged in the first surface 121 portion of the pixel arrangement region 6a, a larger number of recesses are provided in the first surface 121 portion of the pixel arrangement region 6a than in the first embodiment. It becomes possible to arrange the first connection part 14. Furthermore, in the semiconductor module of this embodiment, since the convex portion 25d is not arranged on the second surface 222 of the pixel arrangement region 6a, the second surface 222 of the pixel arrangement region 6a has a larger area than the first embodiment. It becomes possible to arrange many second connection parts 24.

On the first surface 121, a larger number of first connection portions 14 are arranged corresponding to the number of pixels 1111 arranged in the pixel area 111, and on the second surface 222, a larger number of second connection portions 24 are arranged. This is preferable from the viewpoint of transmitting the electrical signals generated in the pixels 1111 to the logic circuit area 211 at high speed, since electrical signals can be simultaneously sent from more pixels 1111 to the first connection section 14 and the second connection section 24. .

According to the semiconductor module of this embodiment, by arranging more first connection parts and second connection parts connected to the first connection parts, electrical signals generated by pixels in the pixel area can be transmitted at higher speed. can be sent to the logic circuit area. Further, according to the semiconductor module of the present embodiment, the semiconductor module includes a recess disposed on the first surface of the first wiring layer and a protrusion disposed on the second surface of the second wiring layer and accommodated in the recess. , displacement of the first connection part and the second connection part is prevented, and good bonding and electrical connection can be obtained between the first connection part and the second connection part.

Next, a preferred first embodiment of the semiconductor module manufacturing method disclosed in this specification will be described below with reference to FIGS. 12 to 16. The first embodiment of the method for manufacturing a semiconductor module is a description of manufacturing the first embodiment of the semiconductor module described above.

First, as shown in FIG. 12A, a first semiconductor chip section 10 having a first semiconductor layer 11 and a first wiring layer 12 disposed on the first semiconductor layer 11 is prepared. The first semiconductor layer 11 is formed using a semiconductor such as a silicon substrate, and includes a pixel region 111 arranged on a light-receiving surface, an electrode pad 17, and a via 16. The first wiring layer 12 is formed using an electrical insulator such as silicon dioxide, and includes a plurality of first connection parts 14 arranged on a first surface 121 and a plurality of first wirings 13 arranged inside. and has.

Next, as shown in FIG. 12(B), a resist layer 30 is formed on the first surface 121 of the first wiring layer 12.

Next, as shown in FIG. 12C, the resist layer 30 is patterned using a lithography technique to form a plurality of openings 302 in the resist layer 30. The first surface 121 of the first wiring layer 12 is exposed through the plurality of openings 302.

Next, as shown in FIG. 13(D), using the resist layer 30 as a mask and using an etching technique, the portions of the first surface 121 exposed from the plurality of openings 302 are etched to form a plurality of recesses. 15 is formed on the first surface 121. As the dry etching technique, for example, isotropic dry etching can be used.

Next, as shown in FIG. 13E, the resist layer 30 is removed from the first surface 121 to obtain the first semiconductor chip section 10 in which a plurality of recesses 15 are formed on the first surface 121. Then, the surface oxide film of each of the plurality of first connection parts 14 is removed. The surface oxide film of the first connection portion 14 is removed, for example, by subjecting the first surface 121 of the first wiring layer 12 to activation treatment such as plasma. At this time, since the distance between two adjacent first connection parts 14 is long, a structure that short-circuits between the two first connection parts 14 by conductive particles generated by activation treatment such as plasma is used. The formation of is prevented.

Next, as shown in FIG. 14F, a third wiring layer 26, a second semiconductor layer 21 disposed on this third wiring layer 26, and a second semiconductor layer 21 disposed on this second semiconductor layer 21 are formed. A second semiconductor chip section 20 having two wiring layers 22 is prepared. The third wiring layer 26 is formed using an electrical insulator such as silicon dioxide, and has an electrode pad 28 and an electrode pad 29. The second semiconductor layer 21 is formed using a semiconductor such as a silicon substrate, and has a logic circuit region 211 and a via 27. The second wiring layer 22 is formed using an electrical insulator such as silicon dioxide, and includes a plurality of second connection parts 24 arranged on the second surface 222 and a plurality of second wirings 23 arranged inside. and has.

Next, as shown in FIG. 14(G), an electrically insulating insulating layer 31 is formed on the second surface 222 of the second wiring layer 22. The insulating layer 31 is formed using, for example, a chemical vapor deposition method such as a plasma chemical vapor deposition method, or a physical vapor deposition method such as an activation treatment using a plasma or the like. As a material for forming the insulating layer 31, for example, silicon dioxide can be used. Further, as the material for forming the insulating layer 31, a material having a different etching rate from that of the electrical insulator of the second wiring layer 22 may be used.

Next, as shown in FIG. 14(H), a resist layer 32 is formed on the insulating layer 31.

Next, as shown in FIG. 15(I), the resist layer 32 is patterned using lithography technology, and a plurality of resist patterns 321 are formed on the insulating layer 31. The portion where the resist layer 32 has been removed is exposed from the insulating layer 31. The plurality of resist patterns 321 are formed at positions on the insulating layer 31 that correspond to the positions of the plurality of recesses 15 on the first surface 121 of the first semiconductor chip section 10 .

Next, as shown in FIG. 15(J), the insulating layer 31 is etched using an etching technique using the plurality of resist patterns 321 as a mask until the second surface 222 of the second wiring layer 22 is exposed. , a plurality of convex portions 25 are formed on the second wiring layer 22. As the dry etching technique, it is preferable to use isotropic dry etching, for example. Note that if the second wiring layer 22 is formed of an electrical insulating layer and an etching stopper layer disposed on the electrical insulating layer, exposure of the second surface 222, which is the surface of the etching stopper layer, can be avoided. This detection makes it easier to determine whether the etching of the insulating layer 31 is complete.

Next, as shown in FIG. 15(K), the resist pattern 321 on each of the plurality of convex portions 25 is removed, and the second semiconductor chip portion has a plurality of convex portions 25 formed on the second surface 222. 20 is obtained. Then, the surface oxide film of each of the plurality of second connection portions 24 is removed. The surface oxide film of the second connection portion 24 is removed, for example, by subjecting the second surface 222 of the second wiring layer 22 to activation treatment using plasma or the like. At this time, since the distance between two adjacent second connection parts 24 is long, a structure that short-circuits the two second connection parts 24 by conductive particles generated by activation treatment such as plasma is used. The formation of is prevented.

Next, as shown in FIG. 16, each of the plurality of recesses 15 in the first semiconductor chip section 10 accommodates a protrusion 25 corresponding to this recess 15, and each of the plurality of first connection parts 14 The first semiconductor chip section 10 is stacked on the second semiconductor chip section 20 with the first surface 121 and the second surface 222 facing each other so as to be electrically connected to the corresponding second connection section 24 . Then, by heating the stacked body of the first semiconductor chip section 10 and the second semiconductor chip section 20, each of the plurality of first connection sections 14 is joined to the corresponding second connection section 24, and, After electrical connection, the semiconductor module 1 shown in FIG. 2 is obtained. Further, by heating the stacked body of the first semiconductor chip section 10 and the second semiconductor chip section 20, the electric insulator portion of the first wiring layer 12 of the first semiconductor chip section 10 and the second semiconductor chip The portion 20 and the electrical insulator portion of the second wiring layer 22 are bonded to each other. Note that in this specification, "above" in the case where the first semiconductor chip section 10 is stacked on the second semiconductor chip section 20 is relative; This includes that the chip portions 20 are stacked.

According to the semiconductor module manufacturing method of the present embodiment described above, the semiconductor module is provided with a recessed portion disposed between a plurality of first connection portions, and a short circuit between the first connection portions of the first wiring layer is prevented. is obtained. Further, according to the method for manufacturing a semiconductor module of the present embodiment, the semiconductor module includes a convex portion disposed between the plurality of second connection portions, and prevents a short circuit between the second connection portions included in the second wiring layer. module is obtained. Further, according to the semiconductor module manufacturing method of the present embodiment, the convex portion disposed on the second surface of the second wiring layer and accommodated in the concave portion is provided in the concave portion disposed on the first surface of the first wiring layer. Therefore, a semiconductor module is obtained in which positional deviation between the first connection part and the second connection part is prevented, and good bonding and electrical connection are obtained between the first connection part and the second connection part. .

Next, a second preferred embodiment of the semiconductor module manufacturing method disclosed in this specification will be described below with reference to FIG. 17. The second embodiment of the method for manufacturing a semiconductor module is a description of manufacturing the fifth embodiment of the semiconductor module described above.

First, the first semiconductor chip section 10 shown in FIG. 13(E) and the second semiconductor chip section 20 shown in FIG. 14(F) are prepared. Next, the surface oxide film of each of the plurality of second connection portions 24 on the second surface 222 of the second semiconductor chip portion 20 is removed. Next, as shown in FIG. 17, the first surface 121 and the second The first semiconductor chip section 10 is stacked on the second semiconductor chip section 20 with the surfaces 222 facing each other. Then, by heating the stacked body of the first semiconductor chip section 10 and the second semiconductor chip section 20, each of the plurality of first connection sections 14 is joined to the corresponding second connection section 24, and, After electrical connection, the semiconductor module 5 shown in FIG. 10 is obtained.

According to the semiconductor module manufacturing method of the present embodiment described above, the semiconductor module is provided with a recessed portion disposed between a plurality of first connection portions, and a short circuit between the first connection portions of the first wiring layer is prevented. is obtained.

In the present invention, the semiconductor module and the method for manufacturing the semiconductor module of the embodiments described above can be modified as appropriate without departing from the spirit of the present invention. Moreover, the constituent features of one embodiment can be applied to other embodiments as appropriate.

For example, although the semiconductor module is an imaging device in the embodiments described above, the semiconductor module may be another semiconductor device such as a storage device.

1 semiconductor module 10 first semiconductor chip section 11 first semiconductor layer 111 pixel region 1111 pixel 1111a drive circuit 12 first wiring layer 121 first surface 122 second surface 13 wiring 14, 14a first connection section 15, 15a, 15b, 15c, 15d recess 16 via 17 electrode pad 20 second semiconductor chip section 21 second semiconductor layer 211 logic circuit area 22 second wiring layer 221 first surface 222 second surface 23 wiring 24, 24a second connection section 25, 25a, 25b, 25c, 25d convex portion 26 third wiring layer 27 via 28 electrode pad 29 electrode pad 30 resist layer 301, 302, 303 opening 31 insulating layer 32 resist layer 321 resist pattern

Claims (11)

a first semiconductor layer having a first circuit;
A first wiring layer including a first wiring electrically connected to the first circuit, a plurality of first connection parts connected to the first wiring, and a recess in which the first connection part is provided . ,
a second connection portion each connected to the first connection portion ; a second wiring connected to the second connection portion; and a convex portion provided with the second connection portion and housed in the recess. a second wiring layer having;
a second semiconductor layer having a second circuit electrically connected to the second wiring;
A semiconductor module comprising: The first wiring layer has a first surface on which the first connection portion and the recess are arranged,
2. The semiconductor module according to claim 1 , wherein the second wiring layer has a second surface opposite to the first surface on which the second connection portion is arranged. 3. The semiconductor module according to claim 1 , wherein the recess increases the distance between the plurality of first connection parts. The semiconductor module according to any one of claims 1 to 3, wherein the first wiring layer has a second recess arranged between the plurality of first connections . The second wiring layer has a second convex portion arranged between the plurality of second connection portions and accommodated in the second recessed portion arranged between the plurality of first connection portions. The semiconductor module according to item 4 . The second recessed portion disposed between the plurality of first connection portions increases the surface area of the first wiring layer between the plurality of first connection portions by arranging the second recessed portion. 6. The semiconductor module according to claim 4, wherein the semiconductor module is enlarged compared to a case where the second recess is not provided . The first semiconductor layer includes a plurality of pixels each having a photoelectric conversion element electrically connected to the plurality of first connection parts, and each of the signals generated by the plurality of pixels is transmitted to the first semiconductor layer. According to any one of claims 1 to 6, the signal is transmitted to the second circuit via a circuit, the first wiring, the first connection part, the second connection part, and the second wiring. The semiconductor module described. a first semiconductor layer provided with a first circuit;
a first wiring layer provided with a first wiring to which a signal is input from the first circuit;
a second wiring layer provided with a second wiring that transmits a signal input from the first wiring;
a second semiconductor layer provided with a second circuit into which a signal is input from the second wiring;
Prepare,
The first wiring layer has a plurality of first connection parts connected to the first wiring, and a recess in which the first connection parts are provided,
The second wiring layer is provided with a second connection part each connected to the first connection part, a second wiring connected to the second connection part, and the second connection part, and in the recess. A semiconductor module having a convex portion to be accommodated . a first semiconductor layer having a first circuit;
a first wiring layer having a first wiring electrically connected to the first circuit, a first connection part connected to the first wiring, and a recess in which the first connection part is provided ;
a second connection part connected to the first connection part; a second wiring connected to the second connection part;
a second wiring layer having a convex portion provided with the second connection portion and accommodated in the concave portion;
a second semiconductor layer having a second circuit electrically connected to the second wiring;
A semiconductor module comprising: a first semiconductor layer having a first circuit; a first wiring layer having a first surface exposed to the outside and having a first wiring electrically connected to the first circuit; forming a plurality of recesses in which each of a plurality of first connection portions connected to the first wiring is provided in the first surface of the first semiconductor chip portion including the first wiring;
a second wiring layer having a second surface exposed to the outside, the second wiring layer being disposed on the second surface and disposed at a position within the second surface that corresponds to each of the plurality of first connection portions; a second wiring layer including a plurality of second connection parts, a convex part in which the second connection parts are provided and can be accommodated by the recess, and a second wiring connected to the plurality of second connection parts; , each of the plurality of second connection parts in a second semiconductor chip section including a second semiconductor layer having a second circuit electrically connected to the second wiring is connected to the corresponding first connection part. The first semiconductor is placed on the second semiconductor chip portion with the first surface and the second surface facing each other so that each of the convex portions is accommodated in the corresponding concave portion. stacking the chip parts;
A method for manufacturing a semiconductor module including: a first semiconductor layer having a first circuit; a first wiring layer having a first surface exposed to the outside and having a first wiring electrically connected to the first circuit; forming a plurality of recesses in which each of a plurality of first connection portions connected to the first wiring is provided in the first surface of the first semiconductor chip portion including the first wiring;
a second wiring layer having a second surface exposed to the outside, a second wiring layer having a second wiring ; and a second semiconductor layer having a second circuit electrically connected to the second wiring; forming a plurality of convex portions that can be accommodated by the concave portions at positions corresponding to the concave portions on the second surface of the second semiconductor chip portion including the concave portions, each of the convex portions including: forming a plurality of convex portions, each of which is provided with a second connection portion arranged at a position within the second surface corresponding to the plurality of first connection portions and connected to the second wiring; ,
The first surface and the second surface are opposed to each other so that the convex portion is accommodated in the recessed portion, and each of the plurality of first connecting portions is connected to the corresponding second connecting portion, stacking the first semiconductor chip section on the second semiconductor chip section;
A method for manufacturing a semiconductor module including:

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