JP2018078281A - Photoelectric conversion device and imaging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric conversion device capable of obtaining excellent signals.SOLUTION: A photoelectric conversion device comprises plural units each having an electric charge generation region arranged in a semiconductor layer. The plural units includes first and second units. Each of the first and second units has an electric charge holding region for holding an electric charge transferred from the electric charge generation region, a dielectric region being positioned on the electric charge generation region and surrounded by an insulator layer, and a first light-shielding layer covering the electric charge holding region between the insulator layer and the semiconductor layer, and having an opening on the electric charge generation region. The electric charge generation region of the first unit receives light via the opening, and the electric charge generation region of the second unit is covered with a second light-shielding layer.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a light shielding layer in a photoelectric conversion device.

  In the photoelectric conversion device, black level correction can be realized by correcting a signal from a pixel having a photoelectric conversion unit that receives light using a signal from a pixel having a light-shielded photoelectric conversion unit. A pixel having a photoelectric conversion unit that receives light is referred to as an effective pixel or a light reception pixel, and a pixel having a light-shielded photoelectric conversion unit is referred to as an optical black (OB) pixel or a light shielding pixel.

  In the solid-state imaging device described in the first embodiment of Patent Document 1, an optical waveguide is formed on the photoelectric conversion unit in both the effective pixel region and the OB pixel region. A light shielding film is disposed between the conversion units.

  The solid-state imaging device described in the fourth embodiment of Patent Document 1 has a global shutter function, and both the effective pixel region and the OB pixel region have a light shielding film formed on the charge storage unit, and the OB pixel region. In FIG. 2, a light shielding film extends on the photoelectric conversion portion.

JP 2012-156334 A

  When the present inventors examined a light guide (optical waveguide), the technique of Patent Document 1 found a problem that black level correction accuracy was not sufficient. Due to this problem, the quality (for example, image quality) of a signal obtained through black level correction cannot be improved. Therefore, an object of the present invention is to provide a photoelectric conversion device that can obtain a good signal.

  A first means for solving the above problem is a photoelectric conversion device including a plurality of units each having a charge generation region arranged in a semiconductor layer, wherein the plurality of units include a first unit and a second unit. Each of the first unit and the second unit includes a charge holding region that holds charges transferred from the charge generation region, and is positioned on the charge generation region and surrounded by an insulator layer. A first light-shielding layer that covers the charge retention region between the insulator layer and the semiconductor layer and has an opening on the charge generation region, the first unit The charge generation region of the second unit receives light through the opening, and the charge generation region of the second unit is covered with a second light shielding layer.

  A second means for solving the above problem is a photoelectric conversion device including a plurality of units, the plurality of units including a first unit and a second unit, and each of the first unit and the second unit. Includes an n-type first impurity region disposed in a semiconductor layer, an n-type second impurity region disposed in the semiconductor layer and transferring charges from the first impurity region, and the first A dielectric region located on one impurity region and surrounded by an insulator layer, covers the second impurity region between the insulator layer and the semiconductor layer, and is disposed on the first impurity region. A first light shielding layer having an opening, wherein the first impurity region of the first unit receives light through the opening, and the first impurity region of the second unit is covered with a second light shielding layer. It is characterized by being characterized.

  A third means for solving the above problem is a photoelectric conversion device including a plurality of units each having a charge generation region arranged in a semiconductor layer, wherein the plurality of units are a first unit and a second unit. Each of the first unit and the second unit includes a charge detection region for detecting a charge transferred from the charge generation region, and is positioned on the charge generation region and surrounded by an insulator layer. A dielectric region, and in the intermediate region located between the first unit and the second unit, the semiconductor layer extends over the area larger than the area of the charge generation region. A first light-shielding layer positioned between the semiconductor layer and the semiconductor layer, wherein the intermediate region and the charge generation region of the second unit are on the side of the semiconductor layer with respect to the insulator layer Opposite side Characterized in that it is covered with the second shielding layer positioned.

  ADVANTAGE OF THE INVENTION According to this invention, the photoelectric conversion apparatus which can obtain a favorable signal can be provided.

FIG. 3 is a schematic diagram illustrating a photoelectric conversion device and an imaging system. FIG. 3 is a schematic diagram illustrating a configuration of a pixel unit. The cross-sectional schematic diagram for demonstrating a photoelectric conversion apparatus. FIG. 2 is a schematic plan view for explaining a photoelectric conversion device. The cross-sectional schematic diagram for demonstrating a photoelectric conversion apparatus. Sectional schematic diagram for demonstrating the manufacturing method of a photoelectric conversion apparatus. Sectional schematic diagram for demonstrating the manufacturing method of a photoelectric conversion apparatus. Sectional schematic diagram for demonstrating the manufacturing method of a photoelectric conversion apparatus. Sectional schematic diagram for demonstrating the manufacturing method of a photoelectric conversion apparatus. The cross-sectional schematic diagram for demonstrating a photoelectric conversion apparatus. FIG. 2 is a schematic plan view for explaining a photoelectric conversion device. The cross-sectional schematic diagram for demonstrating a photoelectric conversion apparatus.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. Note that, in the following description and drawings, common reference numerals are given to common configurations over a plurality of drawings. Therefore, a common configuration is described with reference to a plurality of drawings, and a description of a configuration with a common reference numeral is omitted as appropriate.

  A configuration of the photoelectric conversion device IS will be described with reference to FIG. The photoelectric conversion device IS includes a plurality of pixel units UNT in a semiconductor chip IC. Each of the plurality of pixel units UNT includes a charge generation unit arranged in the semiconductor layer. The pixel unit UNT is arranged in the light receiving region PXR and the light shielding region OBR of the photoelectric conversion device IS. The pixel unit UNT includes not only a main unit for generating basic information of pixels in an image obtained by the photoelectric conversion device IS but also a sub unit that is a unit having a similar configuration to the main unit. . The main unit is a light receiving unit disposed in the light receiving region PXR, and the sub unit is a light shielding unit disposed in the light shielding region OBR. As shown in the example of FIG. 1A, an intermediate region DMR can be provided between the light receiving region PXR and the light shielding region OBR. In this example, the pixel unit UNT is also provided in the intermediate region DMR. The pixel unit UNT (dummy unit) arranged in the intermediate region DMR is also a sub unit. The photoelectric conversion device IS can have a peripheral region PRR outside the pixel region where the pixel unit UNT is disposed.

  FIG. 1B shows an example of the configuration of an imaging system SYS including the photoelectric conversion device IS. The imaging system SYS may further include at least one of an optical system OU, a control device CU, a processing device PU, a display device DU, and a storage device MU. Details regarding the imaging system SYS will be described later.

<First Embodiment>
A first embodiment of the photoelectric conversion device IS will be described with reference to FIGS.

  FIG. 2A shows an example of a circuit diagram of the pixel unit. The pixel unit may include a charge generation unit 2, a charge holding unit 5, a charge detection unit 3, and a charge discharge unit 11 as a pixel circuit. A signal based on the charge of the charge detection unit 3 is output from the pixel unit to the signal output line 10. The pixel circuit of the pixel unit further includes a control unit for switching connection (transfer) / non-connection (non-transfer) of each unit handling these charges or for signal amplification. Specific examples of the control unit include the first transfer gate 4, the second transfer gate 6, the third transfer gate 1, the reset transistor 7, the amplification transistor 8, and the selection transistor 9. Each gate is composed of a MOS gate, and the transistor is composed of a MOSFET. The charge generation unit 2, the charge holding unit 5, the charge detection unit 3, and the charge discharge unit 11 can also be regarded as the source and / or drain of a transistor including a transfer gate as a gate.

  The charge generation unit 2 can generate a signal charge corresponding to the amount of light received by the charge generation unit 2. However, the charge generation unit 2 generates noise charge that becomes a dark current even if light is not incident by the light shielding layer. A photodiode can be used for the charge generation unit 2. The charge holding unit 5 is connected to the charge generation unit 2 through the first transfer gate 4. The charge holding unit 5 functions as a ground capacitor, and the charge holding unit 5 temporarily accumulates the charge transferred from the charge generation unit 2. The charge detection unit 3 converts the charge transferred from the charge holding unit 5 into a voltage signal. The charge detection unit 3 includes an impurity region arranged in the semiconductor layer, and has a capacitance including a parasitic capacitance generated at this node. The impurity region constituting the charge detection unit 3 is a floating diffusion (FD) region. The charge detection unit 3 is connected to the charge holding unit 5 through the second transfer gate 6. The charge detection unit 3 is also connected to the source of the reset transistor 7 and the gate of the amplification transistor 8. A power supply voltage is supplied from the power supply line 12 to the drain of the amplification transistor 8. The power supply voltage is also supplied from the power supply line 12 to the drain of the reset transistor 7. The amplification transistor 8 forms a source follower circuit. By turning on the reset transistor 7, the voltage of the charge detection unit 3 is reset to a reset voltage (in this case, a power supply voltage). At this time, a reset signal corresponding to the reset voltage is output to the source of the amplification transistor 8.

  When the second transfer gate 6 is turned on and charges are transferred from the charge holding unit 5 to the charge detection unit 3, a signal voltage corresponding to the transferred charge amount is output to the source of the amplification transistor 8.

  The source of the amplification transistor 8 is connected to the drain of the selection transistor 9. The source terminal of the selection transistor 9 is connected to the signal output line 10. When the selection transistor 9 is turned on, a reset signal or a pixel signal is output to the signal output line 10. In this way, the signal is read from the pixel.

  A charge discharging unit 11 is further connected to the charge generating unit 2 via the third transfer gate 1. When the third transfer gate 1 is turned on, the charge accumulated in the charge generation unit 2 is discharged to the charge discharge unit 11. The impurity region constituting the charge discharging unit 11 is an overflow drain (OFD) region. A voltage capable of discharging charges from the charge generation unit 2 is applied to the charge discharging unit 11. In this example, a power supply voltage is supplied to the charge discharging unit 11 from the power supply line 12, but the connection relation is not shown in FIG.

  By simultaneously discharging charges to the charge discharging unit 11 for all the pixels and then transferring the charges generated by the charge generating unit 2 to the charge holding unit 5, a constant and constant exposure time is set for all the pixels. An electronic shutter (global electronic shutter) is realized. As a result, a shift in exposure timing that occurs in order to sequentially read out charges from each pixel is suppressed, and image distortion is reduced. In addition, the pixel circuit for realizing the global electronic shutter and the driving method thereof are not limited to those described above, and various changes can be made.

  FIG. 2B is a plan view of the vicinity of the semiconductor layer of the pixel unit in the light receiving region PXR and the light shielding region OBR of the present embodiment. Hereinafter, the pixel unit in the light receiving region PXR is referred to as a light receiving unit PXL, and the pixel unit in the light shielding region OBR is referred to as a light shielding unit OBA.

  First, the correspondence relationship between the circuit shown in FIG. 2A and the structure shown in FIG. In FIG. 2B, the element region 100 (active region) surrounded by a solid line is an element isolation region formed of an insulator. FIG. 2B shows a charge generation region 102 as an impurity region constituting the charge generation unit 2 and a charge holding region 105 as an impurity region constituting the charge holding unit 5. Furthermore, a charge detection region 103 as an impurity region constituting the charge detection unit 3 and a charge discharge region 111 as an impurity region constituting the charge discharge unit 11 are shown. In this example, since electrons are handled as signal charges, each of the charge generation region 102, the charge holding region 105, the charge detection region 103, and the charge discharge region 111 is an n-type impurity region. When holes are handled as signal charges, the conductivity type of these impurity regions is the opposite p-type.

  FIG. 2B also shows the gate electrode 104 of the first transfer gate 4, the gate electrode 106 of the second transfer gate 6, and the gate electrode 101 of the third transfer gate 1. Furthermore, the gate electrode 107 of the reset transistor 7 and the gate electrode 108 of the amplification transistor 8 are shown. The gate electrode 104 of the first transfer gate 4 is disposed between the charge generation region 102 and the charge holding region 105. The gate electrode 106 of the second transfer gate 6 is disposed between the charge holding region 105 and the charge detection region 103. A gate electrode 107 of the reset transistor 7 is disposed adjacent to the charge detection region 103. An impurity region 112 serving as the drain of the reset transistor 7 is disposed on the opposite side of the charge detection region 103 with the gate electrode 107 interposed therebetween. This impurity region 112 is shared with the drain of the amplification transistor 8. The gate electrode 108 of the amplification transistor 8 is disposed adjacent to the impurity region 112. An impurity region 113 serving as the source of the amplification transistor 8 is disposed on the opposite side of the impurity region 112 across the gate electrode 108. In this figure, the selection transistor 9 is not shown. For example, the selection transistor 9 can be disposed on the opposite side of the reset transistor 7 with the amplification transistor 8 interposed therebetween. The source of the selection transistor 9 can be made common to the impurity region 113 that becomes the source of the amplification transistor 8. A gate electrode 101 of the third transfer gate 1 is disposed adjacent to the charge generation region 102. The gate electrode 101 is disposed in a portion different from the side where the gate electrode 104 is disposed in the charge generation region 102. On the opposite side of the charge generation region 102 with the gate electrode 101 interposed therebetween, a charge discharge region 111 constituting a part of the charge discharge portion 11 is disposed. This charge drain region 111 becomes the drain of a transistor having the third transfer gate 1 as a gate.

  The light receiving unit PXL and the light shielding unit OBA have a lower light shielding layer 109 that covers at least the charge holding region 105. In the light receiving unit PXL and the light shielding unit OBA, the lower light shielding layer 109 has an opening 190 on the charge generation region 102. The charge generation region 102 of the light receiving unit PXL can receive light from the subject through the opening 190. Therefore, the charge generation region of the light receiving unit PXL is a photoelectric conversion region. Then, a signal based on the signal charge generated in the charge generation region 102 of the light receiving unit PXL can be processed as an image signal. The shapes of the openings 190 in the light receiving unit PXL and the light shielding unit OBA are most preferably the same, but they may be different. The area of the opening 190 in the light shielding unit OBA is preferably 0.8 times or more and 1.2 times or less than the area of the opening 190 in the light receiving unit PXL. This rule is that if one radius of two circles is not less than 0.9 times and not more than 1.1 times the other radius, the area of one of the two circles is not less than about 0.8 times the area of the other and Based on being 1.2 times or less. In this example, the lower light shielding layer 109 covers part of the gate electrodes 104, 106, and 101 in addition to the charge holding region 105. The lower light shielding layer 109 does not cover the portion of the gate electrode 104, 106, 101 where the contact plug is disposed. In this way, even when a polysilicon gate electrode that is transmissive to visible light is used, it is unnecessary for the semiconductor layer 200 (described later in FIGS. 3A to 3C) via the gate electrode. Incident light can be suppressed. Further, as understood from the positional relationship between the outline of the charge generation region 102 and the opening 190 in FIG. 2B, the area of the opening 190 in plan view is smaller than the area of the charge generation region 102 in plan view. In this way, the lower light shielding layer 109 covers the periphery of the charge generation region 102, and unnecessary light can be further prevented from entering the semiconductor layer 200 through the gate electrode.

  In the light receiving unit PXL and the light shielding unit OBA, the lower light shielding layer 109 has an opening 191 on the gate electrodes 104, 106, 107, 108, the charge detection region 103, and the impurity regions 112, 113. Contact plugs are connected to the gate electrodes 104, 106, 107, 108, the charge detection region 103, and the impurity regions 112, 113 through the opening 191. The lower light shielding layer 109 has an opening 192 on the gate electrodes 104 and 101 and the charge discharge region 111. Contact plugs are connected to the gate electrodes 104 and 101 and the charge discharging region 111 through the opening 192. In FIG. 2B, the contact plug is indicated by a black circle. The openings 191 and 192 are different from the opening 190 and are provided in the lower light shielding layer 109 in a shape different from the opening 190 so that a plurality of contact plugs are arranged.

  A dielectric region 130 is disposed on the charge generation region 102 so as to at least partially overlap the charge generation region 102. A dielectric film 110 is disposed on the charge generation region 102 so as to at least partially overlap the dielectric region 130. The dielectric film 110 is located between the dielectric region 130 and the charge generation region 102. Details of the dielectric region 130 and the dielectric film 110 will be described later.

  3A and 3B show the cross-sectional structure taken along line XY in FIG. FIG. 3C shows a cross-sectional structure in the peripheral region PRR of FIG.

  In the present embodiment, a multilayer wiring structure including wiring layers 2161, 2162, 2163 and interlayer insulating layers 2141, 2142, 2143, 2144 is disposed on the semiconductor layer 200. Hereinafter, the wiring layers 2161, 2162, and 2163 are collectively referred to as a wiring layer 216X, and the interlayer insulating layers 2141, 2142, 2143, and 2144 are collectively referred to as an interlayer insulating layer 214X.

  In this example, the pixel unit UNT will be described as an example in which there are three wiring layers. However, the pixel unit UNT may have four or more wiring layers, or two wiring layers.

  The interlayer insulating layer 214X is an insulator layer for insulating the wiring layer from other layers. An interlayer insulating layer 2141 is located between the semiconductor layer 200 and the wiring layer 2161, an interlayer insulating layer 2142 is located between the wiring layer 2161 and the wiring layer 2162, and an interlayer is interposed between the wiring layer 2162 and the wiring layer 2163. An insulating layer 2143 is located. Silicon oxide (SiO) having a refractive index of about 1.5 can be used for the interlayer insulating layer 214X. The interlayer insulating layer 214X preferably contains silicon (Si), oxygen (O), and hydrogen (H). Hydrogen contained in the interlayer insulating layer 214X is useful for terminating the semiconductor layer 200 with hydrogen. The interlayer insulating layer 214X can further contain carbon (C). An insulator layer containing silicon (Si), oxygen (O), carbon (C), and hydrogen (H) can exhibit a low dielectric constant (low-k) of less than 4.0 and less than 3.0. By using a low dielectric constant material for the interlayer insulating layer, the RC delay of the wiring structure can be reduced and the operation speed can be increased.

  The lower light shielding layer 109 is disposed between the interlayer insulating layer 214 </ b> X and the semiconductor layer 200 and covers the charge holding region 105. In this example, the lower light shielding layer 109 is disposed between the wiring layer 2161 and the semiconductor layer 200, and is disposed between the interlayer insulating layer 2141 and the semiconductor layer 200 through which a contact plug (not shown) passes.

  The light receiving unit PXL and the light shielding units OBA and OBB include a dielectric region 130 disposed on the charge generation region 102. The dielectric region 130 is surrounded by an interlayer insulating layer 214X disposed on the semiconductor layer 200. The planar shape of the dielectric region 130 is circular, but may be a square, rectangle, ellipse, ellipse, polygon, or the like. In particular, the dielectric region 130 is preferably surrounded by interlayer insulating layers 2142 and 2143 located between the plurality of wiring layers 2161, 2162 and 2163. This is because the loss of light due to the presence of the wiring layers 2161, 2162, and 2163 can be suppressed by arranging the dielectric region 130 around the plurality of wiring layers 2161, 2162, and 2163.

  A hole 218 is provided in the interlayer insulating layer 214X. A dielectric region 130 is located in the hole 218. As a result, the dielectric region 130 is surrounded by the interlayer insulating layer 214X. The dielectric region 130 is preferably formed by embedding a dielectric material constituting the dielectric region 130 in a hole 218 formed through the plurality of interlayer insulating layers 214X of the multilayer wiring structure. However, the dielectric region 130 can be formed first, and an interlayer insulating layer can be formed around it.

  The dielectric region 130 is preferably made of a material having a higher refractive index than the material forming the interlayer insulating layer 214X. In this way, light incident obliquely at a predetermined angle with respect to the interface between the dielectric region 130 and the interlayer insulating layer 214X is totally reflected at the interface. Therefore, the light incident on the dielectric region 130 is prevented from leaking to the interlayer insulating layer 214 </ b> X, and more incident light reaches the charge generation region 102. In this way, the dielectric region 130 forms a light guide (optical waveguide) having a core-clad structure together with the interlayer insulating layer 214X. In the light guide, the dielectric region 130 is a core, and the interlayer insulating layer 214X is a clad. For example, the material of the dielectric region 130 can be silicon nitride (SiN) having a refractive index of approximately 2.0. Dielectric region 130 preferably contains silicon (Si), nitrogen (N), and hydrogen (H). Hydrogen contained in the dielectric region 130 is useful for terminating the semiconductor layer 200 with hydrogen. Note that the material of the interlayer insulating layer 214X and the dielectric region 130 is not limited to a combination of silicon oxide and silicon nitride. In configuring the light guide, it is sufficient that the materials are combined so that the refractive index of the dielectric region 130 is higher than the refractive index of the interlayer insulating layer, and any material can be selected. The material of the dielectric region 130 may be silicon oxynitride (SiON) having a refractive index of approximately 1.8, or an organic film material and a material in which particles such as titanium oxide are mixed in the organic film material. Note that the dielectric region 130 does not necessarily form a light guide, and the dielectric region 130 may be silicon oxide like the interlayer insulating layer 214X. Since the interface exists between the dielectric region 130 and the interlayer insulating layer 214X, it can optically have a light guiding function as a barrier. In addition, since the dielectric region 130 is disposed through the plurality of interlayer insulating layers 214, the number of interfaces to the charge generation region 102 can be reduced, which is advantageous in improving sensitivity.

  The dielectric region 130 as a light guide has a function of collecting incident light on the charge generation region 102. In the light receiving unit PXL, since the amount of light incident on the charge generation region 102 is increased by the dielectric region 130, the sensitivity is improved as compared with the case where the dielectric region 130 is not provided. In particular, when the area of the charge generation region 102 is small or when the F number of the camera lens when the imaging device is used for the camera is large, the sensitivity may decrease. On the other hand, by providing the dielectric region 130, it is possible to suppress this influence.

  The interlayer insulating layer may be formed of a laminated film made of different materials. In that case, the dielectric region 130 may be configured so that the refractive index of the dielectric region 130 is higher than the refractive index of the surrounding interlayer insulating layer. . The dielectric region 130 has a forward tapered shape whose diameter decreases from the incident surface side toward the output surface side. As a result, a large amount of incident light can be condensed on the charge generation region 102 via the dielectric region 130. A configuration in which the diameter of the dielectric region 130 is gradually reduced may be employed.

  The dielectric film 110 disposed between the dielectric region 130 and the charge generation region 102 can function as an antireflection film that prevents reflection between the dielectric region 130 and the charge generation region 102. Further, it can also function as an etching stopper when forming the hole 218 during manufacturing.

  Further, as understood from the positional relationship between the contour of the dielectric film 110 and the opening 190 in FIG. 2B, the area of the opening 190 in plan view is smaller than the area of the dielectric film 110 in plan view. By doing so, the dielectric film 110 covers the end of the lower light shielding layer 109. As a result, the dielectric film 110 extends between the dielectric region 130 and the charge generation region 102 and between the interlayer insulating layer 214X and the lower light shielding layer 109, and a part of the lower light shielding layer 109 is formed. It is arranged to cover. The dielectric film 110 can include a material having a higher refractive index than the interlayer insulating layer 214X. In particular, the interlayer insulating layer 214X preferably has a higher refractive index than that of the portion disposed on the charge holding region 105. With such a structure, light leaked from the dielectric region 130 can be prevented from entering the charge holding region 105.

  In the present embodiment, the distance between the charge holding region 105 and the lower light shielding layer 109 is smaller than the distance between the dielectric region 130 and the charge generation region 102. By doing so, it is possible to suppress stray light or light emitted from the dielectric region 130 from entering the charge holding region 105 through the lower light shielding layer 109 and the semiconductor layer 200 and lowering the signal accuracy. it can. In this example, by providing the dielectric film 110, the dielectric region 130 is further away from the semiconductor layer 200 than the lower light shielding layer 109 by a distance corresponding to at least the thickness of the dielectric film 110.

  The lower light shielding layer 109 covers the charge holding region 105, and an opening 190 is formed on the charge generation region 102. The dielectric film 110 is disposed so as to cover the entire charge generation region 102 and a part of the lower light shielding layer 109. In addition to the portion indicated by the solid line in FIG. 2B, an element isolation region formed of an insulator is disposed. The lower light-shielding layer 109 is disposed so as to overlap with a part of the charge generation region 102 in a plan view, and a portion overlapping with another part of the charge generation region 102 in a plan view is opened. The lower light shielding layer 109 is disposed so as to cover at least a part of the charge holding region 105 and the gate electrode 104 of the transistor that transfers charges from the charge generation region 102 to the charge holding region 105. A portion of the lower light shielding layer 109 overlapping the charge generation region 102 has a portion extending from the gate electrode 104 and a portion extending from the gate electrode 101. The lower light-shielding layer 109 suppresses the incidence of light on the charge holding region 105 and suppresses the generation of noise in the charge holding region 105 due to the incident light and the generation of noise. The lower light shielding layer 109 is preferably formed using a material that does not transmit visible light, such as tungsten, tungsten silicide, tungsten oxide, aluminum, or an alloy film thereof. The thickness of the lower light shielding layer 109 is preferably 10 nm or more and 1000 nm or less, for example, 100 nm or more and 200 nm or less. Since the lower light-shielding layer 109 is formed on the gate electrode and the other portion at the same time, the lower light-shielding layer 109 is formed to have unevenness due to the thickness of the gate electrode.

  FIG. 2B shows a lower surface 131 and an upper surface 132 of the dielectric region 130. The lower surface 131 is a light emitting surface, and the upper surface 132 of the dielectric region 130 is a light incident surface. As shown in FIG. 2, the entire lower surface 131 of the dielectric region 130 is disposed in the charge generation region 102 in plan view, but at least a part of the lower surface 131 overlaps the charge generation region 102. It suffices if the dielectric region 130 is disposed on the substrate.

  In this example, the entire lower surface 131 of the dielectric region 130 is disposed so as to be included in the opening 190 in plan view, but at least a part of the lower surface 131 may be disposed in the opening 190. In this example, the entire upper surface 132 of the dielectric region 130 is disposed so as to include the entire opening 190 in plan view, but at least a part of the upper surface 132 may be disposed so as to overlap the opening 190. That's fine. As in this example, the width of the dielectric region 130 having a forward taper is determined by the width of the upper surface 132. However, increasing the width of the dielectric region 130 larger than the width of the opening 190 is effective in improving the light utilization efficiency. is there. In particular, it is effective in improving the light utilization efficiency that the entire lower surface 131 is included in the opening 190 and the entire upper surface 132 includes the entire opening 190 in plan view.

  A dielectric material film 133 made of the same material as that of the dielectric region 130 is provided on the interlayer insulating layer 214X. In the light receiving region PXR, a plurality of dielectric regions 130 are connected by a dielectric material film 133 between adjacent light receiving units PXL. Since the dielectric region 130 needs to be surrounded by the interlayer insulating layer 214X, a portion of the dielectric material constituting the dielectric region 130 and the dielectric material film 133 that is farther from the upper surface of the interlayer insulating layer 2144 Is regarded as a dielectric material film 133. That is, the dielectric region 130 is covered with the dielectric material film 133. 3A and 3B, a convenient boundary between the dielectric region 130 and the dielectric material film 133 is indicated by a dotted line. This dotted line becomes the upper surface 132 of the dielectric region 130 described above. In an actual device, there may be no interface between the dielectric region 130 and the dielectric material film 133. The dielectric material film 133 may be omitted.

  A silicon oxynitride layer 228 and an intermediate layer 229 are disposed on the dielectric region 130 with a dielectric material film 133 interposed therebetween. The intermediate layer 229 is an inorganic material layer made of silicon oxide or silicon nitride, and has a function of adjusting the distance between the layer above the intermediate layer 229 and the semiconductor layer 200. The silicon oxynitride layer 228 functions as an antireflection layer for suppressing reflection between the intermediate layer 229 made of silicon oxide and the dielectric material film 133 or the dielectric region 130. In the light receiving unit PXL and the light shielding unit OBA, the dielectric region 130 is located between the intermediate layer 229 that is an inorganic material layer and the semiconductor layer 200.

  In the present embodiment, the dielectric region 130 is also provided in the light receiving unit PXL and the light shielding unit OBA. In addition, an opening 190 is provided in the light-receiving unit PXL and the light-shielding unit OBA in the lower light-shielding layer 109 positioned between the interlayer insulating layer 214X that is an insulator layer surrounding the dielectric region 130 and the semiconductor layer 200. Yes. As a result, the difference between the light receiving unit PXL and the light shielding unit OBA due to the influence of the dielectric region 130 on the pixel circuit can be reduced. The influence of the dielectric region 130 and the lower light shielding layer 109 on the pixel circuit includes an optical influence. For example, when the dielectric region 130 is provided in the light receiving unit PXL and the light utilization efficiency is higher than when the dielectric region 130 is not provided, light leakage under the lower light shielding layer 109 may increase. Therefore, the closer the lower light shielding layer 109 is to the semiconductor layer 200, the greater the interaction between the semiconductor layer 200 and the lower light shielding layer 109.

  The influence of the dielectric region 130 and the lower light shielding layer 109 on the pixel circuit includes an electrical influence. In particular, if the dielectric constants of the dielectric region 130 and the insulating layer surrounding the dielectric region 130 are different, whether the dielectric region 130 is on the charge generation region 102 or whether there is an insulating layer instead of the dielectric region 130, The dielectric constant on the charge generation region 102 is different. As a result, the capacitance (for example, parasitic capacitance) of the pixel circuit may differ depending on the presence / absence of the opening 190 and the presence / absence of the dielectric region 130.

  Examples of the influence of the dielectric region 130 and the lower light shielding layer 109 on the pixel circuit include a physical or chemical influence. In particular, there are differences in interface states due to hydrogen termination depending on the presence / absence of the opening 190 and the presence / absence of the dielectric region 130, and differences in defect density due to etching damage when the opening 190 and the dielectric region 130 are formed. These are differences at the atomic level of the semiconductor layer 200. In regions that handle charges, such as the charge generation region 102, the charge holding region 105, and the charge detection region 103, such a difference at the atomic level can greatly affect the output signal from the pixel circuit.

  In this example, as shown in FIGS. 3A and 3B, the light receiving unit PXL and the light shielding unit OBA can have the same structure from the semiconductor layer 200 to the intermediate layer 229. In particular, the lower light shielding layer 109 has a structure in which both the light receiving region PXR and the light shielding region OBR have an opening 190 on the charge generation region 102, and both the light receiving region PXR and the light shielding region OBR have a dielectric region 130 and a dielectric film 110. For this reason, the amount of hydrogen supplied by the hydrogen sintering effect to the charge generation region 102 is not different or slightly different between the light generation region 102 in the light shielding region OBR and the light receiving region PXR. Further, the damage received by the charge generation region 102 in the manufacturing process is not different or slightly different between the light receiving region PXR and the light shielding region OBR. Therefore, the difference in the characteristics of the charge generation region 102 between the light receiving unit PXL and the light shielding unit OBA can be reduced.

  The light shielding unit OBA in the light shielding region OBR includes an upper light shielding layer 231 for shielding the charge generation region 102 from light. The upper light shielding layer 231 is disposed farther from the semiconductor layer 200 than the lower light shielding layer 109. That is, the distance between the upper light shielding layer 231 and the semiconductor layer 200 is larger than the distance between the lower light shielding layer 109 and the semiconductor layer 200. The light shielding units OBA and OBB include the upper light shielding layer 231. The opening 190 of the lower light shielding layer 109 is located between the charge generation region 102 and the upper light shielding layer 231. Thereby, the charge generation region 102 of the light shielding unit OBA is shielded by the upper light shielding layer 231 even if the opening 190 is provided in the lower light shielding layer 109. Thereby, the reference signal for black level correction can be obtained from the light shielding unit OBA.

  The upper light shielding layer 231 is made of a light shielding material and is made of a metal material or an organic material having a low light transmittance (10% or less) such as black. The material of the upper light shielding layer 231 is preferably a material having a high reflectance of light having a wavelength of 400 to 600 nm. In this example, the main component of the upper light shielding layer 231 is aluminum. The upper light shielding layer 231 is disposed so as to overlap the entire surface of the charge generation region 102 of the light shielding region OBR. It is preferable that the upper light shielding layer 231 is disposed on the entire light shielding region OBR. The upper light shielding layer 231 may constitute a wiring for transmitting a power supply voltage or a signal.

  The main component of the lower light shielding layer 109 and the main component of the lower wiring layer 2161 may be different from each other. This is because an appropriate material for the wiring layer 2161 and an appropriate material for the lower light shielding layer 109 are different. Similarly, the main component of the upper light shielding layer 231 and the main component of the upper wiring layer 2163 may be different from each other. This is because an appropriate material for the wiring layer 2163 and an appropriate material for the upper light shielding layer 231 are different. In this example, the main component of the lower light shielding layer 109 is tungsten, the main component of the upper light shielding layer 231 is aluminum, and the main component of the wiring layers 2161, 2162, and 2163 is copper.

  In the present embodiment, the upper light shielding layer 231 is provided above the dielectric region 130. That is, the dielectric region 130 is located between the upper light shielding layer 231 and the charge generation region 102. By doing so, it is possible to reduce the difference in the influence of the presence of the dielectric region 130 on the charge generation region 102 between the light receiving unit PXL and the light shielding unit OBA. This is because the upper light shielding layer 231 disposed above the dielectric region 130 does not easily affect the dielectric region 130 and the charge generation region 102.

  The upper light shielding layer 231 is disposed on the intermediate layer 229. That is, in the light shielding unit OBA, the intermediate layer 229 that is an inorganic material layer is located between the upper light shielding layer 231 and the dielectric region 130.

  The lower light shielding layer 109 covers the charge holding region 105. The lower light shielding layer 109 has an opening 190 on the charge generation region 102. The dielectric film 110 is disposed so as to cover the entire charge generation region 102 and a part of the lower light shielding layer 109. On the other hand, in the light shielding region OBR, similarly to the light receiving region PXR, the gate electrode 101, the dielectric region 130, the gate electrode 104, the charge holding region 105, the gate electrode 107, the gate electrode 108, the lower light shielding layer 109, the dielectric film 110, A charge detection region 103 is disposed. However, the charge generation region 102 of the light shielding region OBR is shielded by the upper light shielding layer 231. Therefore, the signal from the charge generation region 102 can be processed as a reference signal for black level correction.

  An upper light shielding layer 231 for light shielding is disposed in the light shielding unit OBA. However, the structure between the charge generation region 102 of the light shielding unit OBA and the upper light shielding layer 231 is the same as or slightly different from the structure from the semiconductor layer 200 to the intermediate layer 229 in the light receiving unit PXL. As a result, the signal obtained from the light shielding unit OBA can be expected to improve accuracy as a reference signal for correcting the black level.

  As shown in FIG. 3B, a light shielding unit OBB can be provided in the light shielding region OBR in addition to the light shielding unit OBA. The light shielding unit OBB has a charge holding region 105 that holds charges transferred from the charge generation region 102 of the light shielding unit OBB. The light shielding unit OBB has a dielectric region 130 located on the charge generation region 102 of the light shielding unit OBB and surrounded by the interlayer insulating layer 214X. In the light shielding unit OBB, the lower light shielding layer 109 covers the charge holding region of the light shielding unit OBB between the interlayer insulating layer 214X and the semiconductor layer 200. Further, in the light shielding unit OBB, the lower light shielding layer 109 covers the charge generation region 102 between the dielectric region 130 and the semiconductor layer 200. That is, in the light shielding unit OBB, the lower light shielding layer 109 covers not only the charge holding region 105 but also the charge generation region 102. An upper light shielding layer 231 is disposed on the dielectric region 130 in the same manner as the light shielding unit OBA. The dielectric region 130 is covered with the upper light shielding layer 231 and shielded from light. The upper light shielding layer 231 in the light shielding unit OBB is configured by a light shielding film 230 continuous with the upper light shielding layer 231 in the light shielding unit OBA.

  The light shielding unit OBB is different from the light shielding unit OBA only in that the lower light shielding layer 109 does not have an opening corresponding to the opening 190 of the light shielding unit OBA on the charge generation region 102 in the light shielding unit OBB. In the light shielding unit OBB, the lower light shielding layer 109 can have openings corresponding to the openings 191 and 192 of the light shielding unit OBA. In the light shielding unit OBB, since the light shielding area of the semiconductor layer 200 is increased by the lower light shielding layer 109 on the charge generation region 102, the light shielding performance is high, and the black level optical accuracy is higher than that of the light shielding unit OBA. Become. However, in the reproducibility of the noise component of the light receiving unit PXL, the light shielding unit OBB is inferior to the light shielding unit OBA having the opening 190 similarly to the light receiving unit PXL. Therefore, the black level correction using the signal from the light shielding unit OBA and the black level correction using the signal from the light shielding unit OBB are preferably used or combined as necessary. Although the light shielding unit OBA and the light shielding unit OBB can be mixed in the light shielding region OBR as in this example, the light shielding unit OBA may be provided alone without disposing the light shielding unit OBB in the light shielding region OBR. Further, in the light shielding unit OBB, the upper light shielding layer 231 can be omitted if only the lower light shielding layer 109 is sufficient to shield the charge generation region 102.

  Details of the structure of the pixel unit UNT will be described. 3A and 3B, the charge generation region 102 in the semiconductor layer 200 is, for example, an n-type impurity region. In each of the plurality of pixel units UNT, the n-type impurity region as the charge generation region 102 is a charge collection region, and each has substantially the same impurity concentration. Specifically, if the maximum concentration of n-type impurities in the charge generation region 102 of the light receiving unit PXL is Cnmax, the maximum concentration of n-type impurities in the pixel units UNT other than the light receiving unit PXL is Cnmax / 2 (half). Above, it is 2 * Cnmax (2 times) or less. The photodiode constituting the charge generation unit 2 forms a pn junction with the n-type charge generation region 102 on the side and the lower side of the n-type charge generation region 102 in addition to the n-type charge generation region 102. A charge generation region which is an impurity region. The range of the charge generation region is a range in which charges collected in the n-type charge generation region 102 which is a charge collection region are generated. This range is determined by the potential distribution in the semiconductor layer 200. A region that generates charges that are not collected in the n-type charge generation region 102 that is a charge collection region is not a charge generation region in the pixel circuit. In this example, a p-type impurity region 205 is disposed above the charge generation region 102, that is, between the charge generation region 102 and the surface of the semiconductor layer 200, so that the charge generation region 102 is embedded in a photodiode structure. It is said.

  With this structure, noise generated at the interface between the semiconductor layer 200 and the insulating film disposed on the surface thereof can be suppressed. The charge holding region 105 is, for example, an n-type impurity region, and a p-type impurity region 206 is disposed between the charge holding region 105 and the surface of the semiconductor layer 200 so that the charge holding region 105 has a buried structure. Yes. With such a structure, noise in the charge holding region 105 can be reduced.

  A protective film 211 is disposed on the charge generation region 102. As the protective film 211, a layer having a refractive index lower than that of the semiconductor layer 200, for example, a film including a silicon nitride layer (SiN) having a refractive index of approximately 2.0 can be used. In addition to the silicon nitride layer, the protective film 211 may be a multilayer film further including a layer having a refractive index lower than that of the silicon nitride layer, for example, a silicon oxide layer having a refractive index of approximately 1.5. The protective film 211 is located between the dielectric film 110 and the semiconductor layer 200 and extends between the lower light shielding layer 109 and the semiconductor layer 200. The protective film 211 covers the charge holding region 105 and the gate electrodes 101, 104, and 106 between the lower light shielding layer 109 and the semiconductor layer 200. The protective film 211 also covers the charge discharge region 111, the charge detection region 103, and the impurity regions 112 and 113. The protective film 211 can be used as an etching stop film when forming a contact hole for a contact plug.

  A side wall 212 is disposed between the protective film 211 and the lower light shielding layer 109. The sidewall 212 is an insulator such as silicon oxide or silicon nitride, and covers the uneven step portion of the protective film 211 formed by the gate electrodes 101, 104, and 106. The side walls 212 relieve the unevenness of the base of the lower light shielding layer 109, and the unevenness of the upper surface of the lower light shielding layer 109 is also reduced accordingly. Thereby, generation of stray light having strong directivity on the upper surface of the lower light shielding layer 109 is suppressed.

  Between the protective film 211 and the dielectric film 110, an insulator film 213 which is a single layer film of a silicon oxide layer is disposed. The insulating film 213 extends between the interlayer insulating layer 2141 and the lower light shielding layer 109 so as to cover the lower light shielding layer 109 from between the dielectric film 110 and the lower light shielding layer 109. However, in FIGS. 3A and 3B, the insulator film 213 and the interlayer insulating layer 2141 are shown integrally.

  On the semiconductor layer 200, contact plugs 2191 for connecting the wiring layer 2161 to the semiconductor layer 200 and the gate electrode and via plugs 2192 and 2193 for connecting the wiring layer 216X to each other are arranged. The main component of the contact plug 2191 is tungsten, and the main component of the via plugs 2192 and 2193 is copper. The wiring layer 2162 and the via plug 2192, and the wiring layer 2163 and the via plug 2193 are integrally formed by a dual damascene structure. The wiring layer 2163 can have a barrier metal portion made of tantalum, titanium and / or a nitride thereof in addition to the conductive portion mainly composed of copper.

  As a main component of the wiring layer 216X, copper can be preferably used, but aluminum, tungsten, polysilicon, or the like may be used. Note that the wiring layer 2161 and the lower light shielding layer 109 may be connected to apply a voltage to the lower light shielding layer 109 (not shown). Alternatively, a contact (not shown) may be formed and connected between the lower light shielding layer 109 and the semiconductor layer 200.

  Diffusion prevention layers 2171, 2172, and 2173 (hereinafter collectively referred to as diffusion prevention layer 217X) are used to suppress the diffusion of Cu in wiring layer 216X into interlayer insulating layer 214X, in particular, to interconnect layer 216X and interlayer insulating layer 214X. It is arranged between. The diffusion prevention layer 217X is provided in contact with the wiring layer 216X. As the diffusion preventing layer 217X, for example, an insulator layer such as silicon nitride (SiN) or silicon carbide (SiC) is used. As a material of the diffusion preventing layer 217X, silicon nitride carbide (SiCN) can be used. Silicon nitride carbide (SiCN) may be classified as silicon carbide if it contains more carbon than nitrogen, and may be classified as silicon nitride if it contains more nitrogen than carbon. The diffusion prevention layer 217X surrounds the dielectric region 130 like the interlayer insulating layer 214X. The refractive index of the diffusion preventing layer 217X may be different from the refractive index of the dielectric region 130 or may be the same as the refractive index of the dielectric region 130. When the refractive index of the diffusion preventing layer 217X is higher than the refractive index of the interlayer insulating layer 214X, the thickness of the diffusion preventing layer 217X is made smaller than the thickness of the interlayer insulating layer 214X, so that the diffusion preventing layer 217X extends from the dielectric region 130. Light leakage to the can be suppressed. The interface formed by the diffusion prevention layer 217X and the interlayer insulating layer 214X can reflect light toward the charge generation region 102. Therefore, disposing the dielectric region 130 instead of the diffusion prevention layer 217X above the charge generation region 102 can reduce the number of interfaces to the charge generation region 102, which is advantageous for improving the sensitivity. In order to obtain this effect, if the dielectric region 130 is surrounded by a plurality of insulator layers (the diffusion prevention layer 217X and the interlayer insulating layer 214X), the refractive index and dielectric constant of the dielectric region 130 can be reduced by the interlayer insulation. It need not be lower than layer 214X.

  The light receiving unit PXL further includes an in-layer lens 240 as well as the dielectric region 130 as an optical system disposed immediately above the charge generation region 102. Further, the color filter 250 and the microlens 251 may be provided above the intralayer lens 240. The in-layer lens 240 is arranged for each light receiving unit PXL on the silicon nitride layer 242 that continuously covers the light receiving region PXR.

  Between the dielectric region 130 and the intralayer lens 240, an antireflection silicon oxynitride layer 228, an intermediate layer 229, and an antireflection layer silicon oxynitride layer 243 are disposed. The silicon oxynitride layers 228 and 243 have a refractive index of approximately 1.6 to 1.7, for example. As the intermediate layer 229, silicon oxide (SiO) having a refractive index of about 1.5 can be used. The intermediate layer 229 can be used as an interlayer insulating layer in the peripheral region PRR. Further, a silicon oxynitride layer 241 may be further formed above the inner lens 240. By adopting such an antireflection structure, it is possible to improve the transmittance of incident light and thus improve the sensitivity.

  A planarizing layer 244 made of an organic material (resin) is disposed between the inner lens 240 and the color filter 250, and between the color filter 250 and the microlens 251, the organic material (resin) is made. A planarization layer 245 is provided. The color filter 250 and the microlens 251 are made of an organic material. Note that the planarization layer 245 and the microlens 251 can be integrally formed. In the case where the inner lens 240 is not provided in the silicon nitride layer 242, the planarization layer 244 can be omitted.

  FIG. 3C shows a cross-sectional structure of the peripheral region PRR. In FIG. 3C, a P-type MOS transistor in the peripheral region PRR is taken as an example. This p-type MOS transistor can constitute a CMOS circuit together with an n-type MOS transistor. A p-type impurity region 208 which is a source / drain of the MOS transistor is formed in an impurity region 207 which is an n-type well. The plurality of MOS transistors are isolated from each other by an element isolation region 114 having an STI structure or a LOCOS structure. A side spacer 116 is formed on the side wall of the gate electrode 115 of the MOS transistor by etching a film common to the protective film 211 in the pixel unit UNT. The impurity region 208 is formed using the side spacer 116 so as to have an LDD structure. A silicide region 117 of a refractory metal such as cobalt silicide or nickel silicide is provided on the impurity region 208 to be the source / drain and the upper surface of the gate electrode 115, and the electric resistance between the contact plug 2190 and the impurity region 208 is increased. Reduce. The protective film 118 can be an etching stop film used when forming a contact hole for the contact plug 2190, or can be a diffusion preventing film that prevents diffusion of metal from the silicide region 117. The protective film 118 is formed by etching a film common to the dielectric film 110. The dielectric material film 133 for constituting the light guide path of the light receiving unit PXL and the light shielding units OBA, OBB formed after the formation of the interlayer insulating layer 2144 is removed in the peripheral region PRR. Intermediate layer 229 is disposed on interlayer insulating layer 2144, and via plug 2194 is provided through intermediate layer 229 and interlayer insulating layer 2144. The via plug 2194 is provided with an input or output electrode 2164. The electrode 2164 is formed by etching a common conductor film with the upper light shielding layer 231. As described above, in the step of forming the upper light shielding layer 231, a conductive member constituting the electrode 2164 and the wiring of the peripheral region PRR can be formed at the same time. In the peripheral region PRR, the intermediate layer 229 functions together with the interlayer insulating layer 2144 as an interlayer insulating layer between the electrode 2164 and a wiring layer in the same layer as the electrode 2164 and the wiring layer 2163. A passivation film which is a stacked film of the silicon oxynitride layer 241, the silicon nitride layer 242, and the silicon oxynitride layer 243 is formed so as to cover the electrode 2164 and the wiring (not shown). The silicon nitride layer 242 of the passivation film is a layer constituting the inner lens 240 in the pixel region. On the electrode 2164, an opening 260 for connection to the outside is provided in the passivation film.

Second Embodiment
A second embodiment will be described with reference to FIGS. 4 and 5. This embodiment relates to an intermediate region DMR between the light receiving region PXR and the light shielding region OBR, as described with reference to FIG.

  FIG. 4 shows the semiconductors of the dummy light-receiving unit DML and the dummy light-shielding units DMA and DMB arranged in the intermediate region DMR in addition to the light-receiving unit PXL of the light-receiving region PXR and the light-shielding units OBA and OBB of the light-shielding region OBR described in the first embodiment. The top view of the layer vicinity is shown. FIG. 5 is a cross-sectional view of the light receiving unit PXL, the dummy light receiving unit DML, the dummy light shielding units DMA and DMB, and the light shielding units OBA and OBB. Since the light receiving unit PXL and the light shielding units OBA and OBB may be the same as those in the first embodiment, detailed description thereof will be omitted. Although the opening 191 in FIG. 2B is described as the opening 193 in FIG. 4, the function and shape of the opening 193 may be the same as the function and shape of the opening 191.

  The dummy light receiving unit DML and the dummy light shielding units DMA and DMB are arranged between the light receiving unit PXL and the light shielding units OBA and OBB. The dummy light receiving unit DML and the dummy light shielding units DMA and DMB are auxiliary pixel units UNT provided for the purpose of improving the characteristics of the light receiving unit PXL and / or the light shielding units OBA and OBB.

  The dummy light-receiving unit DML, the dummy light-shielding unit DMA, and the DMB itself can be configured such that signals cannot be obtained from them. For example, neither the amplification transistor 8 nor the selection transistor 9 may be connected to the signal output line 10 in the dummy light receiving unit DML and the dummy light shielding units DMA and DMB. Alternatively, even if the dummy light receiving unit DML and the dummy light shielding units DMA and DMB output signals to the signal output line 10, they may not be used for signal processing. Alternatively, even if the signals from the dummy light receiving unit DML, the dummy light shielding unit DMA, and DMB are subjected to signal processing, they need not be reflected in the image. However, if signals from the dummy light receiving unit DML, the dummy light shielding unit DMA, and DMB are useful, the information may be incorporated into the image.

  The charge holding regions 105 of the dummy light receiving unit DML and the dummy light shielding units DMA and DMB are covered with the lower light shielding layer 109 in the same manner as the light receiving unit PXL and the light shielding units OBA and OBB. In the dummy light-receiving unit DML and the dummy light-shielding unit DMA, the lower light-shielding layer 109 has an opening 190 on the charge generation region 102, like the light-receiving unit PXL and the light-shielding unit OBA. In the dummy light shielding unit DMB, the lower light shielding layer 109 covers the charge generation region 102 as in the light shielding unit OBB. The dummy light receiving unit DML does not have an upper light shielding layer, and the charge generation region 102 of the dummy light receiving unit DML can receive light through the opening 190.

  Since the lower light-shielding layer 109 of the dummy light-receiving unit DML and the dummy light-shielding unit DMA has the opening 190, the light that can reach the light-shielding unit OBA due to the reflection of light at the lower light-shielding layer 109 can be reduced. This is because by providing the opening 190, the area of the lower light shielding layer 109 can be reduced, and reflection of light by the lower light shielding layer 109 on the charge generation region 102 can be suppressed. Further, by providing the opening 190, the light incident on the dummy light receiving unit DML and the dummy light shielding unit DMA can be absorbed by the charge generation region 102 of the dummy light receiving unit DML and the dummy light shielding unit DMA.

  The dummy light shielding units DMA and DMB have an upper light shielding layer 232 arranged farther from the semiconductor layer 200 than the lower light shielding layer 109. That is, the distance between the upper light shielding layer 232 and the semiconductor layer 200 in the dummy light shielding units DMA and DMB is larger than the distance between the lower light shielding layer 109 and the semiconductor layer 200 in the light shielding units OBA and OBB and the dummy light shielding units DMA and DMB. By this upper light shielding layer 232, the charge generation region 102 of the dummy light shielding unit DMA having the opening 190 in the lower light shielding layer 109 is shielded from light. Further, in the dummy light shielding unit DMB having the charge generation region 102 covered with the lower light shielding layer 109 by the upper light shielding layer 232, the light shielding performance in the charge generation region 102 is enhanced.

  The upper light shielding layer 232 of the dummy light shielding units DMA and DMB is formed of a light shielding film 230 continuous with the upper light shielding layer 231 of the light shielding units OBA and OBB. By making the light shielding film 230 continuous, that is, not dividing, it is possible to prevent extra light from entering the charge generation region 102 of the light shielding unit OBA from the slit formed by being divided. By disposing the dummy light shielding units DMA and DMB between the light receiving unit PXL and the light shielding unit OBA, the light shielding units OBA can be separated from the light receiving unit PXL by the size of the dummy light shielding units DMA and DMB. Therefore, it is possible to prevent light incident between the light shielding film 230 and the semiconductor layer 200 from entering the charge generation region 102 of the light shielding unit OBA.

  The upper light shielding layer 232 is disposed closer to the semiconductor layer 200 than the upper light shielding layer 231. That is, the distance between the upper light shielding layer 232 and the semiconductor layer 200 in the dummy light shielding units DMA and DMB is smaller than the distance between the upper light shielding layer 231 and the semiconductor layer 200 in the light shielding units OBA and OBB. By doing so, the entrance of light from the light receiving region PXR to the portion between the light shielding film 230 and the semiconductor layer 200 is narrowed, so that intrusion of light into the light shielding region OBR can be reduced. As a result, the black level correction accuracy can be improved.

  A dielectric region 130 surrounded by an insulating layer such as an interlayer insulating layer 214X and a diffusion prevention layer 217X as provided in the light receiving unit PXL is disposed on the charge generation region 102 of the dummy light receiving unit DML. Not. Therefore, the interlayer insulating layer 214X and the diffusion prevention layer 217X cover the charge generation region 102 of the dummy light receiving unit DML. The interlayer insulating layer 214X and the diffusion preventing layer 217X cover the entire opening 190 of the lower light shielding layer 109 in the dummy light receiving unit DML. Similarly, the dielectric region 130 surrounded by an insulating layer such as the interlayer insulating layer 214X and the diffusion prevention layer 217X as provided in the light shielding units OBA and OBB is a charge generation region of the dummy light shielding units DMA and DMB. It is not arranged on 102. Therefore, the interlayer insulating layer 214 </ b> X and the diffusion prevention layer 217 </ b> X cover the charge generation regions 102 of the dummy light shielding units DMA and DMB between the upper light shielding layer 232 and the semiconductor layer 200. The interlayer insulating layer 214X and the diffusion prevention layer 217X cover the entire opening 190 of the lower light shielding layer 109 in the dummy light shielding unit DMA.

  In this way, by not providing the dielectric region 130 in the dummy light receiving unit DML and the dummy light shielding units DMA and DMB, the light is propagated to the light shielding units OBA and OBB via the dielectric region 130 of the pixel unit UNT other than the light receiving unit PXL. Can reduce the possibility of It can be considered that the distance between the adjacent dielectric regions 130 between the light receiving unit PXL and the light shielding units OBA and OBB is increased by the amount of the pixel unit UNT in which the dielectric region 130 is not provided. It can be said that the light propagation from the light receiving unit PXL to the light shielding unit OBA is suppressed by separating the light receiving unit PXL from the light shielding units OBA and OBB.

  In this example, not only the dielectric region 130 but also the dielectric material film 133 is not provided in the dummy light receiving unit DML and the dummy light shielding units DMA and DMB. By doing in this way, possibility that light will propagate to the light-shielding units OBA and OBB through the dielectric material film 133 can be reduced. Further, by not providing the dielectric material film 133 in the dummy light shielding units DMA and DMB, the upper light shielding layer 232 can be closer to the semiconductor layer 200 than the upper light shielding layer 231 by at least the thickness of the dielectric material film 133. it can. Therefore, as described above, it is possible to reduce the entry of light into the light shielding region OBR.

  When the dielectric region 130 is not provided in the dummy light receiving unit DML and the dummy light shielding units DMA and DMB, the dielectric film 110 as an etching stop film may not be provided. In particular, in the dummy light shielding unit DMB in which the lower light shielding layer 109 covers the charge generation region 102, the dielectric film 110 may not be provided. However, considering that light is absorbed in the charge generation region 102 of the dummy light receiving unit DML and the dummy light shielding unit DMA as described above, the dielectric film 110 is provided on the dummy light receiving unit DML and the dummy light shielding unit DMA. Is preferred. In this example, the dielectric film 110 functioning as an antireflection film is disposed on the charge generation region 102 of the dummy light receiving unit DML and the dummy light shielding unit DMA through the opening 190. By doing so, absorption in the charge generation region 102 can be suppressed, and reflection of light on the surface of the semiconductor layer 200 can be suppressed.

  In this example, the light shielding unit OBA is disposed between the light shielding unit OBB and the light receiving unit PXL. Conversely, the light shielding unit OBB may be disposed between the light shielding unit OBA and the light receiving unit PXL. The closer to the end of the light shielding film 230 on the light receiving region PXR side, the easier the light reaches from the light receiving region PXR side to the portion between the light shielding film 230 and the semiconductor layer 200. Therefore, the light-blocking unit OBB in which the charge generation region 102 is double-shielded by the upper light-shielding layer 231 and the lower light-shielding layer 109 can be sufficiently shielded even if it is close to the light receiving region PXR side. Further, the light shielding unit OBA in which the lower light shielding layer 109 has the opening 190 on the charge generation region 102 is sufficiently away from the light receiving region PXR side so that the upper light shielding layer 231 can sufficiently shield the light from the light shielding region PXR.

<Third Embodiment>
As a third embodiment, a manufacturing method of the photoelectric conversion device IS will be described. 6-9 is sectional drawing showing the manufacturing method of photoelectric conversion apparatus IS.

  In step a shown in FIG. 6A, after the semiconductor layer 200 is prepared as a silicon wafer, the charge discharge region 111, the charge generation region 102, the charge holding region 105, and the gate electrodes 101, 104, and 106 of each transistor are formed. .

  Next, a protective film 211 is formed over the charge generation region 102, the gate electrode of each transistor, and the source and drain of each transistor. For the protective film 211, silicon nitride can be used. The protective film 211 can be used as a film for forming a side spacer 116 (see FIG. 3C) of a transistor (not shown) disposed in the peripheral region PRR outside the pixel region.

  Next, in step b shown in FIG. 6B, an insulator film such as a silicon oxide film is formed on the protective film 211, and this insulator film is etched back to form a sidewall 212 (FIG. 3A). , (B)). A light shielding material film such as a tungsten film serving as the lower light shielding layer 109 is formed on the protective film 211 through the sidewall 212 so as to cover at least the charge generation region 102, the gate electrode 104, and the charge holding region 105. Next, a portion of the light shielding material film that overlaps the charge generation region 102 in plan view is removed, and a part of the charge generation region 102 and the charge holding region 105 are covered, and a lower light shielding layer having an opening 190 on the charge generation region 102 109 is formed. Dry etching can be used to remove the light shielding material.

  Next, in step c shown in FIG. 6C, an insulator film such as a silicon oxide film is formed on the lower light shielding layer 109, and further, the lower light shielding on the charge generation region 102 is interposed through this insulator film. A dielectric film 110 such as a silicon nitride film is formed so as to cover the opening 190 of the layer 109. Dry etching can be used for patterning the dielectric film 110.

  Next, in step d shown in FIG. 7A, contact plugs 2190 and 2191 (see FIGS. 3A to 3C), an interlayer insulating layer 214X, a diffusion prevention layer 217X, and a wiring layer 216X are formed by a known method. Via plugs 2192 and 2193 are formed. The wiring layer 216X mainly composed of copper and the via plug can be formed by a dual damascene method.

  Thereafter, in step e shown in FIG. 7B, a light guide path hole 218 is formed in the interlayer insulating layer 214X and the diffusion prevention layer 217X where the light guide path is to be formed, that is, on the charge generation region 102. . The hole 218 is formed in the light receiving unit PXL and the light shielding units OBA and OBB, and is not formed in the dummy light receiving unit DML and the dummy light shielding units DMA and DMB. As a method for forming the hole 218, dry etching can be used. When forming the hole 218, the dielectric film 110 functions as an etching stop film. By stopping the etching with the dielectric film 110, it is possible to suppress an increase in noise due to etching damage in the charge generation region 102. The dielectric film 110 as an etching stop film may be over-etched. The dielectric film 110 may be any material that is less likely to be etched than the interlayer insulating layer 2141 with respect to the etching conditions for etching the interlayer insulating layer 2141. If the interlayer insulating layer 2141 is a material containing silicon oxide as a main component (may be a glass-based material such as BPSG, PSG, or NSG), a silicon nitride film or a silicon carbide film is used as the dielectric film 110. Can be used. The dielectric film 110 may be partially or entirely removed by etching.

  Next, in step f shown in FIG. 7C, a high refractive index material having a higher refractive index than that of the interlayer insulating layer 214X is embedded in the hole 218 as a dielectric material, and planarized to obtain a dielectric as a light guide. A body region 130 is formed. As a method of embedding a high refractive index material, a high-density plasma CVD method or an organic material spin coating method can be used. The planarization can be performed using a CMP method or an etch back method. Of the embedded dielectric material, the portion located outside the hole 218 after planarization is a dielectric material film 133 as a residual film of the dielectric material. It is also possible to remove the dielectric material film 133 by planarizing the dielectric material until the interlayer insulating layer 2144 is exposed.

  Next, in step g shown in FIG. 8A, a silicon oxynitride layer 228 is formed on the dielectric material film 133. Note that the wiring layer 216b shown in FIG. 8A is equivalent to the wiring layer 2162 in the other drawings. In FIG. 7C, the portion where the silicon oxynitride layer 228 is formed is indicated by the reference numeral of the silicon oxynitride layer 228. However, the silicon oxynitride layer 228 is not yet formed in step f of FIG. However, the silicon oxynitride layer 228 is formed in this step g.

  Next, in step h shown in FIG. 8B, the silicon oxynitride layer 228 and the dielectric material film 133 are removed by etching in the dummy light receiving unit DML and the dummy light shielding units DMA and DMB. Thereby, a slit 134 is formed in the dielectric material film 133 between the light receiving region PXR and the light shielding region OBR.

  Next, in step i shown in FIG. 8C, an intermediate layer 229 such as a silicon oxide film is formed. The silicon oxynitride layer 228 suppresses the reflection of incident light compared to the structure in which the intermediate layer 229 is provided in contact with the dielectric material film 133 (or the dielectric region 130), thereby suppressing the charge generation region 102 in the light receiving unit PXL. It is possible to increase the amount of light incident on the.

  Next, in step j shown in FIG. 9A, a light shielding film 230 is formed which becomes the upper light shielding layer 231 of the light shielding units OBA and OBB and the upper light shielding layer 232 of the dummy light shielding units DMA and DMB. The light shielding film 230 only needs to be able to reflect or absorb light traveling toward the charge generation region 102. As the material of the light shielding film 230, a metal that reflects light or an organic material that absorbs light is suitable. In this embodiment, it is an aluminum film. Due to the formation of the slit 134 in the dielectric material film 133 in the step h, the intermediate layer 229 has a level difference in the dummy light shielding units DMA and DMB that is lower than the light shielding units OBA and OBB. Therefore, the upper light shielding layer 232 is disposed closer to the semiconductor layer 200 than the upper light shielding layer 231.

  The light shielding film 230 is patterned to remove the light shielding film 230 from above the light receiving unit PXL and the dummy light receiving unit DML. In the patterning of the light shielding film 230, a conductive member constituting the electrode 2164 (see FIG. 3C) and the wiring of the peripheral region PRR can be formed at the same time.

  Next, in step k shown in FIG. 9B, a silicon nitride film is formed on the silicon oxynitride layer 243. By processing the silicon nitride film so as to have the inner lens 240 by the etch back method, the silicon nitride layer 242 having the inner lens 240 is formed. A silicon oxynitride layer 241 is formed over the silicon nitride layer 242. The silicon oxynitride layer 243, the silicon nitride layer 242, and the silicon oxynitride layer 241 function as a passivation film.

  Next, in step l shown in FIG. 9C, a planarization layer 244, a color filter 250, a planarization layer 245, and a microlens 251 are formed on the passivation film. The color filter 250 and the micro lens 251 can be formed by photolithography of a photosensitive resin.

<Fourth embodiment>
A fourth embodiment of the photoelectric conversion device IS will be described with reference to FIG. In addition, the same code | symbol is attached | subjected about the component similar to the said 1st Embodiment, and description is abbreviate | omitted or simplified. The configuration of the light receiving unit PXL is the same as that of the first embodiment.

  In the fourth embodiment, the inner lens 240 is formed on the dielectric region 130 in the light shielding region OBR as in the light receiving region PXR. Similar to the light receiving region PXR, an antireflection silicon oxynitride layer 228, an intermediate layer 229, a silicon nitride layer 242 having an inner lens 240, and an antireflection silicon oxynitride layer 241 are formed.

  The difference from the first embodiment is that the upper light shielding layer 233 is formed on the inner lens 240 in the light shielding region OBR via the silicon oxynitride layer 241 instead of the upper light shielding layer 231. Other configurations may be the same as those in the first embodiment. In particular, the lower light shielding layer 109 covering the charge holding region 105 in the light shielding unit OBA has an opening 190 on the charge generation region 102, and the lower light shielding layer 109 covering the charge holding region 105 in the light shielding unit OBB has the charge generation region 102. cover. A dielectric region 130 can be disposed on the charge generation region 102 in the light shielding unit OBA and on the charge generation region 102 in the light shielding unit OBB.

  As a manufacturing process (not shown) of the fourth embodiment, after planarizing the light guide, a silicon oxynitride layer 228 is formed, and an intermediate layer 229 is formed thereon. A silicon nitride layer 242 having an inner lens 240 is formed on the silicon oxynitride layer 243, and a silicon oxynitride layer 241 is formed thereon. Next, a light shielding film to be the upper light shielding layer 233 is formed in the light shielding region OBR. Further, a passivation film (silicon nitride layer or silicon oxynitride layer) (not shown) may be formed on the upper light shielding layer 233, and the color filter 250 and the microlens 251 may be provided. As an effect of the present embodiment, the hydrogen termination effect of the semiconductor layer 200 due to the hydrogen sinter from the silicon nitride layer 242 (particularly the thick inner lens 240) can be expected in the light shielding region OBR as well as the light receiving region PXR, and the black level is corrected. Further improvement in accuracy can be expected. This is because the upper light-shielding layer 233 is disposed above the silicon nitride layer 242 instead of below the silicon nitride layer 242, so that the supply of hydrogen from the silicon nitride layer 242 to the semiconductor layer 200 that has been hindered by the upper light-shielding layer 231 in the first embodiment. This is because it can be increased.

<Fifth Embodiment>
A fifth embodiment of the photoelectric conversion device IS will be described with reference to FIG. In addition, the same code | symbol is attached | subjected about the component similar to the said 1st Embodiment, and description is abbreviate | omitted or simplified. The configuration of the light receiving unit PXL is substantially the same as that of the first embodiment. In the light receiving unit PXL, the first embodiment is that the lower light shielding layer 109 that covers the charge holding region 105 is formed of the same layer as the wiring layer 2161. And different. The distance between the lower light shielding layer 109 and the charge holding region 105 is larger than the distance between the charge generation region 102 and the dielectric region 130. Further, the second embodiment is different from the first embodiment in that a planarization layer 246 is provided between the intermediate layer 229, the silicon nitride layer 242, and the silicon oxynitride layer 243. The planarization layer 246 is, for example, a silicon oxide layer, and extends between the electrode 2164, the silicon nitride layer 242, and the silicon oxynitride layer 243 in the peripheral region PRR illustrated in FIG .

  In the fifth embodiment, in the light shielding unit OBA, the lower light shielding layer 109 is formed of the same layer as the wiring layer 2161. The upper light shielding layer 231 is formed of the same layer as the wiring layer 2162. The upper light shielding layer 231 is provided below the dielectric region 130. That is, the upper light shielding layer 231 is disposed between the dielectric region 130 and the charge generation region 102. Although the dielectric region 130 is surrounded by the interlayer insulating layers 2143 and 2144, the interlayer insulating layers 2142 and 2141 do not have a hole for the dielectric region 130 and do not surround the dielectric region 130. In this embodiment, since the configuration between the charge generation region 102 and the dielectric region 130 is different between the light receiving unit PXL and the light shielding unit OB, the accuracy of the black level reference signal due to the degree of dark current can be reduced. . In particular, the main factors are the presence of the dielectric region 130 (hydrogen termination effect) and the influence of damage to the semiconductor layer 200 when opening the interlayer insulating layer. However, since the upper light shielding layer 231 can be brought close to the opening 190 of the lower light shielding layer 109, there is an advantage that light entering the charge generation region 102 of the light shielding units OBA and OBB via the interlayer insulating layer can be reduced. Therefore, sufficient accuracy of the black level signal can be ensured also in this embodiment.

  In this embodiment, the distance between the charge holding region 105 and the lower light shielding layer 109 is smaller than the distance between the dielectric region 130 and the charge generation region 102. Therefore, there is a possibility that the amount of light emitted from the dielectric region 130 is incident on the charge holding region 105 from between the lower light shielding layer 109 and the semiconductor layer 200. In this respect, it can be said that the first embodiment is superior.

<Sixth Embodiment>
In the light shielding unit OBA, a light shielding layer that shields the charge holding region 105 (corresponding to the lower light shielding layer 109 in the above-described embodiment) and a light shielding layer that shields the charge generation region 102 (corresponding to the upper light shielding layer 231 in the above-described embodiment). ) Can be interchanged. In this case, in the light receiving unit PXL and the light shielding unit OBA, the light shielding layer that shields the charge holding region 105 has the opening 190 on the charge generation region 102 and the dielectric region 130 as described in the above embodiment. It is the same. In the light shielding unit OBA, the black level correction accuracy is improved by providing the opening 190 in the light shielding layer that shields the charge holding region 105 from light. This is because the difference between the light receiving unit PXL and the light shielding unit OBA due to the optical, electrical or chemical influence from the dielectric region 130 to the semiconductor layer 200 through the opening 190 can be eliminated or reduced. It is. In the light shielding unit OBA, the light shielding layer that shields the charge generation region 102 is located between the opening 190 and the charge generation region 102. The light shielding layer that shields the charge generation region 102 is the same as that of the fifth embodiment in that it is located between the dielectric region 130 and the charge generation region 102. As in the light receiving unit PXL of the first embodiment, a light shielding layer that shields the charge holding region 105 may be closer to the semiconductor layer 200 than the dielectric region 130. Alternatively, as in the light receiving unit PXL of the fifth embodiment, the dielectric region 130 may be closer to the semiconductor layer 200 than the light shielding layer that shields the charge holding region 105. In the present embodiment, it is possible to eliminate or reduce the difference in distance between the semiconductor layer 200 and the dielectric region 130 between the light receiving unit PXL and the light shielding unit OBA, as compared with the fifth embodiment. This is more advantageous than the fifth embodiment.

<Seventh embodiment>
The seventh embodiment will be described with reference to FIGS. 11 and 12. This embodiment relates to an intermediate region DMR between the light receiving region PXR and the light shielding region OBR, as described with reference to FIG. The photoelectric conversion device IS in this embodiment also includes a plurality of units each having a charge generation region 102 arranged in the semiconductor layer 200. The plurality of units include a light receiving unit PXL and a light shielding unit OBC. Each of the light receiving unit PXL and the light shielding unit OBC has a charge detection region 103 for detecting the charge transferred from the charge generation region 102. Each of the light receiving unit PXL and the light shielding unit OBC has a dielectric region 130 located on the charge generation region 102 and surrounded by an insulating layer such as an interlayer insulating layer 214X. The semiconductor layer 200 has an intermediate region DMR located between the light receiving unit PXL and the light shielding unit. The intermediate region DMR is covered with a lower light shielding layer 109 located between the interlayer insulating layer 214X and the semiconductor layer 200 over an area larger than the area of the charge generation region 102. The charge generation region 102 and the intermediate region DMR of the light shielding unit OBC are covered with upper light shielding layers 231 and 232 located on the opposite side of the semiconductor layer 200 from the interlayer insulating layer 214X.

  FIG. 11 is a plan view of the vicinity of the semiconductor layers of the dummy light shielding units DMC and DMD arranged in the intermediate region DMR in addition to the light receiving unit PXL of the light receiving region PXR and the light shielding unit OBC of the light shielding region OBR described in the first embodiment. ing. FIG. 12 is a cross-sectional view of the light receiving unit PXL, the dummy light shielding units DMC and DMD, and the light shielding unit OBC. In the present embodiment, the dummy light-shielding unit DMD disposed between the light-receiving unit PXL and the light-shielding unit has the lower light-shielding layer 109 that covers the charge generation region 102, and is common to the dummy light-shielding unit DMB of the second embodiment. . In the present embodiment, the configurations of the light receiving unit PXL and the light shielding unit are different from those of the first to sixth embodiments. In the present embodiment, the light receiving unit PXL and the light shielding unit OBC do not have the charge holding region 105, and accordingly, the gate electrode 104 of the first transfer gate 4 and the lower light shielding layer 109 covering the charge holding region 105 do not exist. A transfer gate electrode 106 corresponding to the second transfer gate 6 is disposed between the charge generation region 102 and the charge detection region 103. The gate electrode 106 transfers charges from the charge generation region 102 to the charge detection region 103. Further, the gate electrode 101 of the third transfer gate 1 may be omitted.

  The dummy light shielding units DMC and DMD are arranged between the light receiving unit PXL and the light shielding unit OBC. The dummy light shielding units DMC and DMD are auxiliary pixel units UNT provided for the purpose of improving the characteristics of the light receiving unit PXL and / or the light shielding unit OBC.

  The dummy light shielding units DMC and DMD themselves can be configured such that signals cannot be obtained from them. For example, the dummy light shielding units DMC and DMD need not have the amplification transistor 8 and the selection transistor 9 connected to the signal output line 10. Alternatively, even if the dummy light shielding units DMC and DMD output a signal to the signal output line 10, they may not be used for signal processing. Alternatively, even if the signals from the dummy light shielding units DMC and DMD are signal-processed, they need not be reflected in the image. However, if the signals from the dummy light shielding units DMC and DMD are useful, the information may be incorporated into the image.

  The charge generation region 102 of the dummy light shielding unit DMD is covered with the lower light shielding layer 109. The charge generation region 102 of the dummy light shielding unit DMC is not covered with the lower light shielding layer 109 like the light receiving unit PXL. The dummy light shielding unit DMC has an upper light shielding layer 233, and the DMD has an upper light shielding layer 232. The charge generation region 102 of the dummy light shielding unit DMC is shielded by the upper light shielding layer 233, and the charge generation region 102 of the dummy light shielding unit DMD is shielded by the upper light shielding layer 232 and the lower light shielding layer 109.

  Since the dummy light-shielding unit DMD has the lower light-shielding layer 109, it is possible to prevent light that has entered under the upper light-shielding layer 232 from entering the semiconductor layer 200. Thereby, the incidence of light on the light shielding unit OBC via the semiconductor layer 200 can be suppressed.

  In the example shown in FIG. 11, the lower light shielding layer 109 that covers the semiconductor layer 200 in the intermediate region DMR has an opening 191 on the gate electrodes 106, 107, and 108. When the gate electrodes 106, 107, 108 and the lower light shielding layer 109 overlap, the height of the base of the interlayer insulating layer 214X increases accordingly. As a result, a difference in level is likely to occur in the base of the interlayer insulating layer 214X between the light receiving region PXR and the intermediate region DMR, and the flatness of the interlayer insulating layer 214X decreases. Since the lower light shielding layer 109 has openings on the gate electrodes 106, 107, and 108, the flatness of the interlayer insulating layer 214X is improved. As a modification of this example, in the intermediate region DMR, the lower light shielding layer 109 may cover not only the charge generation region 102 but also the gate electrodes 106, 107 and 108. By doing in this way, the light-shielding performance with respect to the semiconductor layer 200 by the lower light shielding layer 109 improves.

  The dummy light shielding units DMD and DMC have upper light shielding layers 232 and 233 arranged farther from the semiconductor layer 200 than the lower light shielding layer 109. That is, the distance between the upper light shielding layers 232 and 233 and the semiconductor layer 200 in the dummy light shielding units DMD and DMC is larger than the distance between the lower light shielding layer 109 and the semiconductor layer 200 in the light shielding unit OBC and dummy light shielding unit DMD. The upper light shielding layer 232 is located on the side opposite to the semiconductor layer 200 side with respect to the interlayer insulating layer 214X. The charge generation region 102 of the dummy light-shielding unit DMC that does not have the lower light-shielding layer 109 is shielded by the upper light-shielding layer 233. Further, in the dummy light shielding unit DMD having the charge generation region 102 covered with the lower light shielding layer 109 by the upper light shielding layer 232, the light shielding performance in the charge generation region 102 is enhanced.

  The upper light shielding layers 233 and 232 of the dummy light shielding units DMC and DMD are formed of a light shielding film 230 continuous with the upper light shielding layer 231 of the light shielding unit OBC. By making the light shielding film 230 continuous, that is, by not dividing, it is possible to prevent extra light from entering the charge generation region 102 of the light shielding unit OBC from the slit formed by being divided. By disposing the dummy light shielding units DMC and DMD between the light receiving unit PXL and the light shielding unit OBC, the light shielding units OBC can be separated from the light receiving unit PXL by the size of the dummy light shielding units DMD and DMC. Therefore, it is possible to suppress the light incident between the light shielding film 230 and the semiconductor layer 200 from entering the charge generation region 102 of the light shielding unit OBC.

  The upper light shielding layer 232 is disposed closer to the semiconductor layer 200 than the upper light shielding layers 231 and 233. That is, the distance between the upper light shielding layer 232 and the semiconductor layer 200 in the dummy light shielding unit DMD is smaller than the distance between the upper light shielding layer 231 in the light shielding unit OBC and the upper light shielding layer 233 and the semiconductor layer 200 in the dummy light shielding unit DMC. By doing so, the entrance of light from the light receiving region PXR to the portion between the light shielding film 230 and the semiconductor layer 200 is narrowed, so that intrusion of light into the light shielding region OBR can be reduced. As a result, the black level correction accuracy can be improved.

  A dielectric region 130 surrounded by an insulating layer such as an interlayer insulating layer 214X or a diffusion prevention layer 217X as provided in the light receiving unit PXL is disposed on the charge generation region 102 of the dummy light shielding unit DMD. Not. Therefore, the interlayer insulating layer 214X and the diffusion prevention layer 217X cover the charge generation region 102 of the dummy light shielding unit DMD. The interlayer insulating layer 214X and the diffusion prevention layer 217X cover the entire lower light shielding layer 109 in the dummy light shielding unit DMD. Similarly, the dielectric region 130 surrounded by an insulating layer such as the interlayer insulating layer 214X and the diffusion prevention layer 217X as provided in the light shielding unit OBC is above the charge generation region 102 of the dummy light shielding unit DMD. Is not arranged. Therefore, the interlayer insulating layer 214X and the diffusion prevention layer 217X cover the charge generation region 102 of the dummy light shielding unit DMD between the upper light shielding layer 232 and the semiconductor layer 200. The interlayer insulating layer 214X and the diffusion prevention layer 217X cover the entire lower light shielding layer 109 in the dummy light shielding unit DMD.

  Thus, by not providing the dielectric region 130 in the dummy light shielding unit DMD, the possibility of propagation to the light shielding unit OBC via the dielectric region 130 of the pixel unit UNT other than the light receiving unit PXL can be reduced. It can be considered that the distance between the adjacent dielectric regions 130 between the light receiving unit PXL and the light shielding unit OBC is increased by the pixel unit UNT in which the dielectric region 130 is not provided. It can be said that the light propagation from the light receiving unit PXL to the light shielding unit OBC is suppressed by separating the light receiving unit PXL and the light shielding unit OBC.

  In this example, not only the dielectric region 130 but also the dielectric material film 133 is not provided in the dummy light shielding unit DMD. By doing in this way, possibility that light will propagate to the light-shielding unit OBC through the dielectric material film 133 can be reduced. Further, by not providing the dielectric material film 133 in the dummy light shielding unit DMD, the upper light shielding layer 232 can be made closer to the semiconductor layer 200 than the upper light shielding layer 231 by at least the thickness of the dielectric material film 133. Therefore, as described above, it is possible to reduce the entry of light into the light shielding region OBR.

  When the dielectric region 130 is not provided in the dummy light shielding unit DMD, the dielectric film 110 as an etching stop film may not be provided. In the dummy light shielding unit DMD in which the lower light shielding layer 109 covers the charge generation region 102, the dielectric film 110 is not provided. However, considering that the thickness of the lower light shielding layer 109 is larger than that of the other units on the charge generation region 102 of the dummy light shielding unit DMD as described above, the dummy light shielding unit DMD includes a dielectric film. 110 is preferably not provided. In this example, the dielectric film 110 that functions as an antireflection film is disposed on the charge generation region 102 of the dummy light shielding unit DMC. By doing so, absorption in the charge generation region 102 can be suppressed, and reflection of light on the surface of the semiconductor layer 200 can be suppressed.

  The dummy light shielding unit DMC is provided with a dielectric region 130 as in the light receiving unit PXL. The dielectric region 130 of the dummy light shielding unit DMC can also be referred to as a dummy dielectric region. The distance between the dielectric region 130 of the dummy light shielding unit DMC and the dielectric region 130 of the light receiving unit PXL is larger than the distance between the dielectric region 130 of the dummy light shielding unit DMC and the dielectric region 130 of the light shielding unit OBC. Can be small. In this example, the dummy light shielding unit DMC is adjacent to the light receiving unit PXL, and the dummy light shielding unit DMD is located between the dummy light shielding unit DMC and the light shielding unit OBC. By disposing the dielectric region 130 in the dummy light-shielding unit DMC disposed closer to the light-receiving unit PXL than to the dummy light-shielding unit DMD, a sudden increase in the upper layer of the interlayer insulating layer 2144 between the light-receiving region PXR and the intermediate region DMR. It can suppress that a height difference arises. Thereby, the flatness of the upper layer of the interlayer insulating layer 2144 can be improved. The upper layers of the interlayer insulating layer 2144 are the dielectric film 110, the silicon oxynitride layer 228, and the intermediate layer 229. If the flatness of the upper layer of the interlayer insulating layer 2144 can be improved, the shape of the dielectric region 130 of the dummy light shielding unit DMC may be different from the shape of the dielectric region 130 of the light receiving unit PXL or the dielectric region 130 of the light shielding unit OBC. Good. A lower light shielding layer 109 may be provided below the dielectric region 130 and the dielectric film 110 of the dummy light shielding unit DMC. However, in this case, the height of the base of the dielectric film 110 differs between the dummy light-shielding unit DMC and the light-receiving unit PXL, and the flatness of the interlayer insulating layer 214X can be lowered. Therefore, it is preferable not to provide the lower light shielding layer 109 in the dummy light shielding unit DMC provided with the dielectric region 130. The dummy light shielding unit DMC can also be arranged in the intermediate region DMR of the first to sixth embodiments. For example, the dummy light shielding unit DMC can be arranged between the dummy light shielding unit DMA and the light receiving unit PXL of the second embodiment. When the dummy light-shielding unit DMC is arranged between the dummy light-shielding unit DMC and the light-receiving unit PXL of the second embodiment, an intermediate region DMR similar to that of the present embodiment is obtained.

  Up to this point, the example in which the dummy light shielding units DMC and DMD in the intermediate region DMR have the charge generation region 102 has been described. However, since the light shielding units DMC and DMD do not read signals, the charge generation region 102 may be omitted. In this case, the intermediate region DMR is covered with the lower light shielding layer 109 located between the interlayer insulating layer 214X and the semiconductor layer 200 over an area larger than the area of the charge generation region 102 of the light receiving unit PXL or the light shielding unit OBC. It only has to be. By doing so, even if there is no charge generation region 102 in the intermediate region DMR, the same effect as when the charge generation region 102 is present is obtained. Here, since the two dummy light shielding units DMD are arranged, the intermediate region DMR is covered with the lower light shielding layer 109 over an area larger than twice the area of the charge generation region 102.

  In the second embodiment, the area of the charge holding region 105 is larger than the area of the charge generation region 102. Therefore, also in the dummy light shielding unit DMA having the opening 190, the semiconductor layer 200 is covered by the lower light shielding layer 109 located between the interlayer insulating layer 214X and the semiconductor layer 200 over an area larger than the area of the charge generation region 102. It has been broken. Therefore, in the second embodiment, not only the dummy light shielding unit DMB but also the dummy light shielding unit DMA has the effect of covering the semiconductor layer 200 with the lower light shielding layer 109 in the intermediate region DMR as in the seventh embodiment. Can be obtained.

<Eighth Embodiment>
A configuration other than the pixel unit UNT of the photoelectric conversion device IS will be described with reference to FIG. The photoelectric conversion device IS can include a peripheral circuit PRC. The peripheral circuit PRC sequentially operates a vertical drive circuit VDC for driving the plurality of pixel units UNT, a signal processing circuit SPC for processing signals obtained from the plurality of pixel units, and a signal processed by the signal processing circuit SPC. And a horizontal scanning circuit HSC for outputting. The peripheral circuit PRC may include an output circuit OPC that outputs a signal generated by the signal processing circuit SPC. The peripheral circuit PRC may include a control circuit CC for controlling the vertical drive circuit VDC, the signal processing circuit SPC, and the horizontal scanning circuit HSC. The signal processing circuit SPC can include an analog-digital converter, and the control circuit CC can include a timing generator. The vertical driving circuit VDC and the horizontal scanning circuit HSC can include a shift register and an address decoder. The output circuit OPC can include an LVDS driver. The peripheral circuit PRC can be arranged in the peripheral region PRR located around the pixel unit UNT in the semiconductor chip IC. However, at least a part of the vertical drive circuit VDC, the signal processing circuit SPC, the horizontal scanning circuit HSC, the control circuit CC, and the output circuit OPC can be provided in a semiconductor chip different from the semiconductor chip having a plurality of pixel units. The another semiconductor chip and a semiconductor chip having a plurality of pixel units can be stacked.

  The imaging system SYS illustrated in FIG. 1B may be an electronic device such as an information terminal having a camera and a photographing function. In addition, the imaging system SYS can be a transportation device such as a vehicle, a ship, or a flying object. The imaging system SYS as a transportation device is suitable for a device that transports the photoelectric conversion device IS and a device that assists and / or automates driving (maneuvering) by a photographing function.

  The photoelectric conversion device IS can further include not only the semiconductor chip IC but also a package PKG that accommodates the semiconductor chip IC. The package PKG includes a bonding wire and a bump for connecting a base to which the semiconductor chip IC is fixed, a lid made of glass or the like facing the semiconductor layer 200, and a terminal provided on the base to a terminal provided on the semiconductor chip IC. And the like.

  The optical system OU forms an image on the photoelectric conversion device IS, and is, for example, a lens, a shutter, or a mirror. The control device CU controls the photoelectric conversion device IS and is a semiconductor device such as an ASIC. The processing device PU processes a signal output from the photoelectric conversion device IS, and is a semiconductor device such as a CPU or an ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device DU is an EL display device or a liquid crystal display device that displays an image obtained by the photoelectric conversion device IS. The storage device MU stores an image obtained by the photoelectric conversion device IS, and is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or hard disk drive.

  As described above, the embodiment according to the present invention relates to the photoelectric conversion device IS including a plurality of pixel units each including the charge generation region 102 arranged in the semiconductor layer 200. Among the plurality of pixel units, the light receiving unit PXL and the light shielding unit OBA include a charge holding region 105 that holds the charge transferred from the charge generation region 102. The light receiving unit PXL and the light shielding unit OBA are located on the charge generation region 102 and include a dielectric region 130 surrounded by an insulating layer such as an interlayer insulating layer 214X and a diffusion prevention layer 217X.

  The light receiving unit PXL and the light shielding unit OBA include a lower light shielding layer 109 that covers the charge holding region 105 between the interlayer insulating layer 214X and the semiconductor layer 200 and has an opening 190 on the charge generation region 102. The charge generation region 102 of the light receiving unit PXL receives light through the opening 190, and the charge generation region 102 of the light shielding unit OBA is covered with the upper light shielding layer 231. Thereby, the photoelectric conversion device IS capable of obtaining a good signal can be provided.

  In addition, dummy light shielding units DMA, DMB, and DMD are provided in the intermediate region DMR located between the light receiving unit PXL and the light shielding units OBA, OBC. In the intermediate region DMR, the semiconductor layer 200 is covered with a lower light shielding layer 109 positioned between the interlayer insulating layer 214X and the semiconductor layer 200 over an area larger than the area of the charge generation region 102. The charge generation region 102 of the intermediate region DMR and the light shielding units OBA, OBC is covered with an upper light shielding layer 231 located on the opposite side of the semiconductor layer 200 from the interlayer insulating layer 214X. Thereby, the photoelectric conversion device IS capable of obtaining a good signal can be provided.

  The embodiments described above can be modified as appropriate without departing from the spirit of the present invention. Note that the disclosure content of this specification includes matters that can be read from the attached drawings even if the matters are not specified in this specification, in addition to the matters specified in this specification.

IS photoelectric conversion device PXL light receiving unit OBA light shielding unit 200 semiconductor layer 102 charge generation region 105 charge holding region 109 lower light shielding layer 190 opening 130 dielectric region 214X interlayer insulating layer 231 upper light shielding layer

Claims (22)

A photoelectric conversion device comprising a plurality of units each having a charge generation region arranged in a semiconductor layer,
The plurality of units includes a first unit and a second unit,
Each of the first unit and the second unit is
A charge holding region for holding charges transferred from the charge generation region;
A dielectric region located on the charge generation region and surrounded by an insulator layer;
A first light-shielding layer that covers the charge retention region between the insulator layer and the semiconductor layer and has an opening on the charge generation region;
The charge generation region of the first unit receives light through the opening;
The photoelectric conversion device, wherein the charge generation region of the second unit is covered with a second light shielding layer.   The photoelectric conversion device according to claim 1, wherein the opening is located between the charge generation region and the second light shielding layer.   The photoelectric conversion device according to claim 1, wherein the dielectric region forms a light guide along with the insulator layer.   4. The photoelectric conversion device according to claim 1, wherein, in the second unit, the dielectric region is located between the second light shielding layer and the charge generation region. 5.   5. The device according to claim 1, wherein, in the first unit and the second unit, a distance between the charge holding region and the first light shielding layer is smaller than a distance between the dielectric region and the charge generation region. Item 1. The photoelectric conversion device according to item 1.   In the first unit and the second unit, a dielectric film is disposed between the dielectric region and the charge holding region, and the dielectric film is formed between the insulating layer and the first light shielding layer. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion device extends in between. In the first unit, the dielectric region is located between the inorganic material layer and the semiconductor layer,
7. The photoelectric conversion device according to claim 1, wherein, in the second unit, the inorganic material layer is located between the second light shielding layer and the dielectric region.   8. The photoelectric conversion device according to claim 1, wherein, in the first unit and the second unit, a width of the dielectric region is larger than a width of the opening.   9. The first light shielding layer according to claim 1, wherein the first light shielding layer has another opening having a different shape from the opening on the charge generation region, and a plurality of contact plugs are arranged in the other opening. The photoelectric conversion apparatus of any one of Claims. The first unit and the second unit include a charge detection region that detects charge transferred from the charge holding region, a first transfer gate that transfers charge from the charge generation region to the charge holding region, and the charge A second transfer gate for transferring charge from the holding region to the charge detection region; and an amplification transistor connected to the charge detection region;
10. The photoelectric conversion device according to claim 1, wherein, in the first unit and the second unit, the first light shielding layer covers the first transfer gate and the second transfer gate. 10. Including a third unit disposed between the first unit and the second unit;
The third unit has a third light shielding layer,
11. The photoelectric conversion device according to claim 1, wherein in the third unit, the insulator layer covers the semiconductor layer between the third light shielding layer and the semiconductor layer. A fourth unit is provided between the first unit and the second unit,
The fourth unit has a fourth light shielding layer,
The distance between the fourth light shielding layer and the semiconductor layer is greater than the distance between the first light shielding layer and the semiconductor layer in the second unit, and the second light shielding layer and the semiconductor layer in the second unit The photoelectric conversion device according to any one of claims 1 to 11, wherein the photoelectric conversion device is smaller than the distance. The photoelectric conversion device according to claim 11, wherein the second light shielding layer and the third light shielding layer are formed of a continuous light shielding film.
Or
The photoelectric conversion device according to claim 12, wherein the second light shielding layer and the fourth light shielding layer are formed of a continuous light shielding film. The plurality of units includes a fifth unit;
The fifth unit is
A charge holding region for holding charges transferred from the charge generation region of the fifth unit;
A dielectric region located on the charge generation region of the fifth unit and surrounded by the insulator layer;
A fifth light-shielding layer that covers the charge retention region of the fifth unit between the insulator layer and the semiconductor layer, and covers the charge generation region between the dielectric region and the semiconductor layer; The photoelectric conversion device according to claim 1, comprising: The plurality of units includes a sixth unit;
The sixth unit is
A charge holding region for holding charges transferred from the charge generation region of the sixth unit;
A sixth light shielding layer that covers the charge retention region of the sixth unit between the insulator layer and the semiconductor layer and has an opening on the charge generation region of the sixth unit;
15. The device according to claim 1, wherein in the sixth unit, the insulator layer covers the entire opening of the sixth light shielding layer, and the charge generation region of the sixth unit receives light through the opening. The photoelectric conversion device according to item. A photoelectric conversion device comprising a plurality of units,
The plurality of units includes a first unit and a second unit,
Each of the first unit and the second unit is
An n-type first impurity region disposed in the semiconductor layer;
An n-type second impurity region disposed in the semiconductor layer and transferring charges from the first impurity region;
A dielectric region located on the first impurity region and surrounded by an insulator layer;
A first light-shielding layer that covers the second impurity region between the insulator layer and the semiconductor layer and has an opening on the first impurity region;
The first impurity region of the first unit receives light through the opening;
The photoelectric conversion device according to claim 1, wherein the first impurity region of the second unit is covered with a second light shielding layer. A photoelectric conversion device comprising a plurality of units,
The plurality of units includes a first unit and a second unit,
Each of the first unit and the second unit is
A charge generation region disposed in the semiconductor layer;
A charge detection region for detecting the charge transferred from the charge generation region;
A dielectric region located on the charge generation region and surrounded by an insulator layer;
In the intermediate region located between the first unit and the second unit, the semiconductor layer is located between the insulator layer and the semiconductor layer over an area larger than the area of the charge generation region. Covered with a first light shielding layer,
The intermediate region and the charge generation region of the second unit are covered with a second light-shielding layer located on a side opposite to the semiconductor layer with respect to the insulator layer. apparatus.   A dummy dielectric region surrounded by the insulator layer is provided between the second light-shielding layer and the semiconductor layer, and between the dummy dielectric region and the dielectric region of the first unit. The photoelectric conversion device according to claim 17, wherein the distance is smaller than a distance between the dummy dielectric region and the dielectric region of the second unit. The insulator layer is located between the first wiring layer and the second wiring layer;
The main component of the first light shielding layer and the main component of the first wiring layer are different from each other,
The photoelectric conversion device according to claim 1, wherein a main component of the second light shielding layer and a main component of the second wiring layer are different from each other. The insulator layer is located between the first wiring layer and the second wiring layer;
The main component of the first light shielding layer is tungsten,
The main component of the second light shielding layer is aluminum,
The photoelectric conversion device according to claim 1, wherein a main component of the first wiring layer and the second wiring layer is copper.   21. The device according to claim 1, wherein the insulator layer satisfies at least one of containing silicon, oxygen, and hydrogen, and the dielectric region containing silicon, nitrogen, and hydrogen. The photoelectric conversion device described in 1. The photoelectric conversion device according to any one of claims 1 to 21,
An optical system that forms an image on the photoelectric conversion device, a control device that controls the photoelectric conversion device, a processing device that processes a signal output from the photoelectric conversion device, and a display device that displays information obtained by the photoelectric conversion device And at least one of storage devices for storing information obtained by the photoelectric conversion device.

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