JP5968481B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  2. Description of the Related Art In recent years, a solid-state imaging device having an optical waveguide has been proposed for a solid-state imaging device that is one of semiconductor devices in order to increase the amount of light incident on a photoelectric conversion unit.

  Patent Document 1 discloses a solid-state imaging device having a waveguide constituted by a low refractive index cladding layer and a high refractive index core layer embedded in a groove surrounded by the cladding layer. As a method for manufacturing such a solid-state imaging device, a method of forming a core layer on the entire surface of a clad layer having an opening corresponding to a photoelectric conversion portion is shown. Examples of the material constituting the core layer include a silicon nitride film (SiN), a silicon oxynitride film (SiON), and a silicon carbide film (SiC).

JP 2010-103458 A

  Patent Document 1 does not disclose the formation of a plug that electrically connects wiring after the waveguide is formed. In the manufacturing method of the solid-state imaging device of the prior art, the present inventors have a problem that it is difficult to form a plug for electrically connecting the conductive members constituting the wiring to each other after the waveguide is formed. I found. Specifically, when a silicon nitride film (SiN), a silicon oxynitride film (SiON), or a silicon carbide film (SiC) is formed as the core layer of the waveguide, a through hole for arranging a plug is formed. The process may be complicated.

  Thus, it has been difficult to form a through hole with the prior art. In view of the above-described problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that enables a through hole to be formed with a small number of steps, or allows a through hole to be formed with a simple process. It is.

  According to an aspect of the present invention, there is provided a method for manufacturing a solid-state imaging device, the first step of forming a conductive member on the second region of the semiconductor substrate including the first region and the second region, and the first step of the semiconductor substrate. A second step of forming a first insulator on the opposite side of the semiconductor substrate with respect to the conductive member on the first region and the second region; and electrically connected to the conductive member A third step of leaving the first insulator at a position where the plug to be disposed is disposed, and forming a first opening in a portion of the first insulator disposed on the first region; Forming a second insulator made of a material different from the first insulator on the inside of one opening and on the portion of the first insulator disposed on the second region; A portion of the second insulator disposed on the second region, wherein the plug is disposed A fifth step of removing the portion disposed above the position and within a predetermined distance from the position where the plug is disposed so that the first insulator is exposed, and after the fifth step, A sixth step of forming a second opening at the position where the plug of the first insulator is disposed, and a seventh step of forming a plug in the second opening, wherein the area of the second opening is: It is smaller than the area of the said part removed by the said 3rd process of a said 2nd insulator, It is characterized by the above-mentioned.

  The manufacturing method of the solid-state imaging device according to another aspect of the present invention includes a first region in which a plurality of photoelectric conversion units are disposed, and a second region in which a circuit for processing signals from the plurality of photoelectric conversion units is disposed. A first step of forming a conductive member on the second region of the semiconductor substrate including: on the first region of the semiconductor substrate; on the second region; A second step of forming a first insulator on a side opposite to the semiconductor substrate; and the first insulator is left at a position where a plug electrically connected to the conductive member is disposed; A third step of forming a plurality of first openings at positions overlapping with each of the plurality of photoelectric conversion portions of the body, the second of the first insulators, and the second of the first insulators A second layer made of a material different from that of the first insulator on a portion disposed on the region; A fourth step of forming an edge, and a portion of the second insulator disposed on the second region, on the position where the plug is disposed, and on which the plug is disposed A fifth step of removing a portion disposed within a predetermined distance from the position so that the first insulator is exposed, and the plug of the first insulator is disposed after the fifth step. A sixth step of forming a second opening at a position and a seventh step of forming a plug in the second opening, wherein the area of the second opening is removed in the third step of the second insulator It is smaller than the area of the said part to be performed.

  According to the present invention, a semiconductor device can be manufactured by a simple process.

FIG. 3 is a diagram illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. FIG. 3 is a diagram illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. FIG. 3 is a diagram illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. FIG. 3 is a diagram illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. 1 is a schematic diagram of a planar structure of a solid-state imaging device according to Embodiment 1. FIG. FIG. 10 is a diagram illustrating a method for manufacturing the solid-state imaging device according to the second embodiment. FIG. 10 is a diagram illustrating a method for manufacturing the solid-state imaging device according to the second embodiment. FIG. 10 is a diagram illustrating a method for manufacturing the solid-state imaging device according to the third embodiment. FIG. 10 is a diagram illustrating a method for manufacturing the solid-state imaging device according to the fourth embodiment. 6 is a schematic diagram of a cross-sectional structure of a solid-state imaging device according to Embodiment 5. FIG. Schematic of the planar structure of the solid-state imaging device of Example 6. FIG.

  The present invention relates to a method for manufacturing a semiconductor device. The present invention is applicable to, for example, a method for manufacturing a solid-state imaging device. A solid-state imaging device is a semiconductor device having a semiconductor substrate on which a plurality of photoelectric conversion units are arranged.

  A preferred embodiment of the present invention will be described by taking a solid-state imaging device manufacturing method as an example. The semiconductor substrate 101 includes an imaging region 103 in which a plurality of photoelectric conversion units 105 are arranged, and a peripheral region 104 in which a circuit for processing a signal from the photoelectric conversion unit 105 is arranged. A conductive member constituting the wiring of the signal processing circuit is disposed on the peripheral region 104. An insulator is disposed on the semiconductor substrate 101. The insulator includes, for example, a plurality of interlayer insulating films 113a to 113e. The fifth interlayer insulating film 113e is disposed on the conductive member included in the second wiring layer 112b.

  A plurality of openings 116 are formed in the insulator. The opening 116 is formed at a position overlapping with the plurality of photoelectric conversion portions 105 in the insulator. A large number of photoelectric conversion units 105 can be arranged in the imaging region 103. At this time, the fifth interlayer insulating film 113e remains on the conductive member included in the second wiring layer 112b.

  Next, the first waveguide member 118 is formed on the insulator in which the opening is formed. The first waveguide member 118 is formed so as to fill the inside of the plurality of openings 116. Further, the first waveguide member 118 is formed on an insulator disposed in the peripheral region 104. At this time, the entire inside of the opening 116 need not be filled. A gap may remain in a part of the opening 116. The material constituting the first waveguide member 118 is different from the material constituting the fifth interlayer insulating film.

  A portion of the first waveguide member 118 disposed in the peripheral region 104 is removed. As a removal method, etching, lift-off, or the like can be used. In a plan view, at least a position where the plug 121 for electrically connecting the conductive member of the second wiring layer 112 and the conductive member of the third wiring layer 112c is disposed, and within a predetermined distance from the position. What is necessary is just to remove the part. It is preferable to remove most of the portion arranged in the peripheral region 104. More preferably, the entire surface of the portion disposed in the peripheral region 104 is removed. The predetermined distance may be determined based on the diameter of the plug 121. Alternatively, the predetermined distance may be determined based on overlay accuracy, minimum design dimension, etc. in the semiconductor process.

  Further, it is preferable to remove all of the first waveguide member 118 in the depth direction. That is, it is preferable to remove the first waveguide member 118 until the underlying fifth interlayer insulating film 113e is exposed.

  Thereafter, a through hole 125 is formed at a position where the plug 121 for electrically connecting the conductive member of the second wiring layer 112 and the conductive member of the third wiring layer 112c of the fifth interlayer insulating film 113e is disposed. Before the formation of the through hole 125, another insulator may be formed on the fifth interlayer insulating film 113e as necessary. In this case, it is preferable that the through hole 125 is also formed in the other insulator.

  The area of the through hole 125 is smaller than the area of the portion where the first waveguide member 118 is removed. In this specification, unless otherwise specified, the area is the area when viewed in a plane parallel to the interface between the semiconductor substrate 101 and the insulator disposed in contact with the semiconductor substrate (the main surface 102 of the semiconductor substrate 101). It is. For example, the area is the area of the region where the through hole 125 is projected on the plane when the through hole 125 is projected onto the plane.

  According to the manufacturing method of the present embodiment, it is easy to form the through hole 125 for arranging the plug 121. The reason for this will be briefly described. The first waveguide member 118 is made of a material different from that of the fifth interlayer insulating film 113e. This is because the first waveguide member 118 embedded in the opening 116 has a refractive index higher than that of the surrounding interlayer insulating film, thereby forming an optical waveguide. As described above, when different materials are stacked at the position where the through hole 125 is formed, it is necessary to form the through hole 125 by a process under a plurality of different conditions. Therefore, before the through hole 125 is formed, the position where the through hole 125 is disposed and the first waveguide member 118 disposed within a predetermined distance from the position where the through hole 125 is disposed are removed. Through holes 125 can be easily formed.

  Note that the present invention can be applied to the case where a through hole is formed at a place where different materials overlap each other as described above.

  In the following description, a case where electrons are signal charges will be described, but holes may be signal charges. When holes are signal charges, the conductivity type of the semiconductor region may be reversed.

  A first embodiment of a method for manufacturing a solid-state imaging device according to the present invention will be described with reference to the drawings. 1 to 4 are schematic views of a cross-sectional structure of the solid-state imaging device in each process of the present embodiment.

  The solid-state imaging device 100 includes a semiconductor substrate 101. The semiconductor substrate is a part of a semiconductor material among members constituting the solid-state imaging device. For example, the semiconductor substrate includes a semiconductor wafer having a semiconductor region formed by a known semiconductor manufacturing process. An example of the semiconductor material is silicon. The interface between the semiconductor material and another material is the main surface 102 of the semiconductor substrate. For example, another material is a thermal oxide film disposed on the semiconductor substrate in contact with the semiconductor substrate.

  In this embodiment, a known semiconductor substrate can be used as the semiconductor substrate 101. A P-type semiconductor region and an N-type semiconductor region are disposed on the semiconductor substrate 101. Reference numeral 102 denotes a main surface of the semiconductor substrate 101. In this embodiment, the main surface 102 is an interface between the semiconductor substrate 101 and a thermal oxide film (not shown) stacked on the semiconductor substrate 101. The semiconductor substrate 101 has an imaging region 103 in which a plurality of pixels are arranged, and a peripheral region 104 in which a signal processing circuit for processing signals from the pixels is arranged. Description of the imaging region 103 and the peripheral region 104 will be described later.

  In the present specification, the plane is a plane parallel to the main surface 102. For example, the main surface 102 in a region where a photoelectric conversion unit, which will be described later, is arranged, or the main surface 102 in the channel of the MOS transistor may be used as a reference. In this specification, a cross section is a plane that intersects a plane.

  In the process shown in FIG. 1A, each semiconductor region is formed in the semiconductor substrate 101, and a gate electrode and a multilayer wiring are formed on the semiconductor substrate 101. In the imaging region 103 of the semiconductor substrate 101, a photoelectric conversion unit 105, a floating diffusion (hereinafter referred to as FD) 106, a well 107 for pixel transistors and source / drain regions are formed. The photoelectric conversion unit 105 is, for example, a photodiode. The photoelectric conversion unit 105 includes an N-type semiconductor region disposed on the semiconductor substrate 101. Electrons generated by photoelectric conversion are collected in the N-type semiconductor region of the photoelectric conversion unit. The FD 106 is an N-type semiconductor region. Electrons generated in the photoelectric conversion unit 105 are transferred to the FD 106 and converted into a voltage. The FD 106 is electrically connected to the input node of the amplification unit. Alternatively, the FD 106 is electrically connected to the signal output line. In this embodiment, the FD 106 is electrically connected to the gate electrode 110b of the amplification transistor via the plug 114. In the pixel transistor well 107, source / drain regions such as an amplifying transistor for amplifying a signal and a reset transistor for resetting an input node of the amplifying transistor are formed. A peripheral transistor well 108 is formed in the peripheral region 104 of the semiconductor substrate 101. In the peripheral transistor well 108, the source / drain regions of the peripheral transistor constituting the signal processing circuit are formed. In addition, an element isolation portion 109 may be formed on the semiconductor substrate 101. The element isolation unit 109 electrically isolates the pixel transistor or the peripheral transistor from other elements. The element isolation unit 109 is STI (Shallow Trench Isolation), LOCOS (LOCAL Oxidation of Silicon), or the like.

  In this step, the transfer gate electrode 110a and the gate electrode 110b are formed. The transfer gate electrode 110a and the gate electrode 110b are arranged on the semiconductor substrate 101 via an oxide film (not shown). The transfer gate electrode 110a controls charge transfer between the photoelectric conversion unit 105 and the FD 106. The gate electrode 110b is a gate of a pixel transistor and a peripheral transistor.

  Further, in this step, a protective layer 111 is formed on the semiconductor substrate 101. For example, the protective layer 111 is a silicon nitride film. The protective layer 111 may be composed of a plurality of layers including a silicon nitride film and a silicon oxide film. The protective layer 111 may have a function of reducing damage given to the photoelectric conversion unit in a later step. Alternatively, the protective layer 111 may have an antireflection function. Alternatively, it may have a function of preventing metal diffusion in the silicide process. Further, an etch stop member 117 is formed on the opposite side of the protective layer 111 from the semiconductor substrate 101. The area of the etch stop member 117 is preferably larger than the area of the bottom of the opening 116 formed thereafter. Note that the protective layer 111 and the etch stop member 117 are not necessarily formed.

  Subsequently, a first wiring layer 112a, a second wiring layer 112b, and a plurality of interlayer insulating films 113a to 113e are formed. In this embodiment, the first wiring layer 112a and the second wiring layer 112b are formed by the damascene method. For convenience, the first to fifth interlayer insulating films 113 a to 113 e are sequentially formed from the side closer to the semiconductor substrate 101.

  A first interlayer insulating film 113 a is formed in the imaging region 103 and the peripheral region 104. If necessary, the surface of the first interlayer insulating film 113a opposite to the semiconductor substrate 101 may be planarized. A through hole is formed in the first interlayer insulating film 113a. A plug 114 that electrically connects the conductive member of the first wiring layer 112 a and the semiconductor region of the semiconductor substrate 101 is disposed in the through hole. The plug 114 is made of a conductive material. For example, the plug 114 is tungsten.

  Next, a second interlayer insulating film 113b is formed on the side opposite to the semiconductor substrate 101 with respect to the first interlayer insulating film 113a. A portion of the second interlayer insulating film 113b corresponding to the region where the conductive member of the first wiring layer 112a is disposed is removed by etching. Thereafter, a metal film serving as a material for the first wiring layer is formed in the imaging region 103 and the peripheral region 104. Thereafter, the metal film is removed by a method such as CMP until the second interlayer insulating film is exposed. By such a procedure, the conductive members constituting the wiring of the first wiring layer 112a are arranged in a predetermined pattern.

  Subsequently, a third interlayer insulating film 113 c and a fourth interlayer insulating film 113 d are formed in the imaging region 103 and the peripheral region 104. Here, a portion of the fourth interlayer insulating film 113d corresponding to the region where the conductive member of the second wiring layer 112b is disposed is removed by etching. Next, a portion of the third interlayer insulating film 113c corresponding to a region where a plug for electrically connecting the conductive member of the first wiring layer 112a and the conductive member of the second wiring layer 112b is disposed is removed by etching. To do. Thereafter, a metal film serving as a material for the second wiring layer and the plug is formed in the imaging region 103 and the peripheral region 104. Thereafter, the metal film is removed by a method such as CMP until the fourth interlayer insulating film is exposed. By such a procedure, the wiring pattern of the second wiring layer 112b and the plug pattern are obtained. In addition, after the third interlayer insulating film 113c and the fourth interlayer insulating film 113d are formed, a plug for electrically connecting the conductive member of the first wiring layer 112a and the conductive member of the second wiring layer 112b is first disposed. A portion corresponding to the region to be removed may be removed by etching.

  Finally, a fifth interlayer insulating film 113e is formed in the imaging region 103 and the peripheral region 104. If necessary, the surface of the fifth interlayer insulating film 113e opposite to the semiconductor substrate 101 may be planarized by a method such as CMP.

  The first wiring layer 112a and the second wiring layer 112b may be formed by a method other than the damascene method. An example of a method other than the damascene method will be described. After the first interlayer insulating film 113a is formed, a metal film serving as a material for the first wiring layer is formed in the imaging region 103 and the peripheral region 104. Next, portions of the metal film other than the region where the conductive member of the first wiring layer 112a is disposed are removed by etching. Thereby, the wiring pattern of the first wiring layer 112a is obtained. Thereafter, a second interlayer insulating film 113b and a third interlayer insulating film 113c are formed, and a second wiring layer 112b is formed in the same manner. After the second wiring layer 112b is formed, a fourth interlayer insulating film 113d and a fifth interlayer insulating film 113e are formed. The surfaces of the third interlayer insulating film 113c and the fifth interlayer insulating film 113e opposite to the semiconductor substrate 101 are planarized as necessary.

  The first wiring layer 112 a and the second wiring layer 112 b are arranged at different heights with respect to the main surface of the semiconductor substrate 101. In this embodiment, the conductive members of the first wiring layer 112a and the second wiring layer 112b are made of copper. The conductive member may be formed of a material other than copper as long as it is a conductive material. Except for the portion electrically connected by the plug, the conductive member of the first wiring layer 112a and the conductive member of the second wiring layer 112b are insulated from each other by the interlayer insulating film 113c. The number of wiring layers is not limited to two, and the wiring layer may be a single layer or three or more layers.

  Further, an etch stop film, a metal diffusion prevention film, or a film having both functions of etch stop and metal diffusion prevention may be disposed between the interlayer insulating films. In this embodiment, the plurality of interlayer insulating films 113a to 113e are silicon oxide films. For the silicon oxide film, the silicon nitride film serves as an etch stop film. Therefore, an etch stop film 115 is disposed between the interlayer insulating films. Note that the etch stop film 115 is not necessarily provided.

  In FIG. 1B, an opening 116 is formed in a region overlapping with the photoelectric conversion portion 105 of the plurality of interlayer insulating films 113a to 113e. When the diffusion preventing film 115 is provided, an opening is formed in the diffusion preventing film 115.

  First, an etching mask pattern (not shown) is stacked on the side opposite to the semiconductor substrate 101 with respect to the interlayer insulating film 113e. The mask pattern for etching is disposed outside the region where the opening 116 is to be disposed. In other words, the etching mask pattern has an opening in a region where the opening 116 is to be disposed. The etching mask pattern is, for example, a photoresist patterned by photolithography and development.

  Subsequently, the plurality of interlayer insulating films 113a to 113e and the diffusion prevention film 115 are etched using the etching mask pattern as a mask. Thereby, the opening 116 is formed. Alternatively, the opening 116 may be formed by etching a plurality of times under different conditions. After the etching, the mask pattern for etching may be removed.

  When the etch stop member 117 is provided, it is preferable that etching is performed until the etch stop member 117 is exposed in the process of FIG. The etch stop member 117 preferably has an etching rate under etching conditions for etching the interlayer insulating film 113a smaller than the etching rate of the interlayer insulating film 113a. When the interlayer insulating film 113a is a silicon oxide film, the etch stop member 117 may be a silicon nitride film or a silicon oxynitride film. Further, the etch stop member 117 may be exposed by multiple times of etching under different conditions.

  Regarding the cross-sectional shape of the opening 116, the opening 116 does not necessarily have to penetrate all of the first to fifth interlayer insulating films 113a to 113e. The recesses of the interlayer insulating films 113a to 113e may be the openings 116. Regarding the planar shape of the opening 116, the boundary of the opening 116 is a closed loop such as a circle or a rectangle. Alternatively, the planar shape of the opening 116 may be a shape like a groove extending over the plurality of photoelectric conversion units 105. That is, in this specification, when a region where the interlayer insulating film 113e is not arranged in a certain plane is surrounded or sandwiched between regions where the interlayer insulating film 113e is arranged, the interlayer insulating film 113e is opened. 116.

  Regarding the position of the opening 116 in the plane, at least a part of the opening 116 is arranged so as to overlap with the photoelectric conversion unit 105 in a plane. That is, when the opening 116 and the photoelectric conversion unit 105 are projected on the same plane, there is a region where both the opening 116 and the photoelectric conversion unit 105 are projected on the same plane.

  In this embodiment, an opening 116 is formed in a region overlapping the photoelectric conversion unit 105, and no opening 116 is formed in the peripheral region 104. However, the opening 116 may be formed in the peripheral region 104. In that case, the density of the openings 116 formed in the imaging region 103 may be higher than the density of the openings 116 formed in the peripheral region 104. The density of the openings 116 can be determined by the number of openings 116 arranged per unit area. Alternatively, the density of the openings 116 can be determined by the ratio of the area occupied by the openings 116.

  In FIG. 1C, the first waveguide member 118 is formed inside the opening 116 and on the fifth interlayer insulating film 113e. Specifically, the first waveguide member 118 a is formed in the imaging region 103 and the peripheral region 104. The first waveguide member 118 can be formed by film formation by CVD or sputtering, or by applying an organic material typified by a polyimide polymer. Note that the first waveguide member 118 may be formed by a plurality of processes having different conditions. For example, in the first process, the first waveguide member 118 is formed under the condition that the adhesion to the base is high, and in the next process, the first guide is formed under the condition that the embedding property inside the opening 116 is high. The waveguide member 118 may be formed. Alternatively, the first waveguide member 118 may be formed by sequentially forming a plurality of different materials. For example, the first waveguide member 118 may be formed by first depositing a silicon nitride film and then depositing an organic material having high embedding performance. 1B, when the first interlayer insulating film 113a is etched until the etch stop member 117 is exposed, the first waveguide member 118 is disposed so as to be in contact with the etch stop member 117. The

  The material of the first waveguide member 118 is preferably a material higher than the refractive index of the interlayer insulating films 113a to 113e. When the interlayer insulating films 113a to 113e are silicon oxide films, examples of the material of the first waveguide member 118 include a silicon nitride film and a polyimide organic material. The silicon nitride film has a refractive index of about 2.0. The refractive index of the surrounding silicon oxide film is about 1.4. Therefore, light reflects at the interface between the first waveguide member 118 and the interlayer insulating films 113a to 113e based on Snell's law. Accordingly, the first waveguide member 118 can be confined inside. In addition, the hydrogen content of the silicon nitride film can be increased, and the dangling bonds of the substrate can be terminated by the hydrogen supply effect. As a result, noise such as white scratches can be reduced. The polyimide organic material has a refractive index of about 1.7. The embedding property of polyimide organic material is superior to that of silicon nitride film. The material of the first waveguide member 118 is preferably selected as appropriate in consideration of the balance between optical characteristics such as a difference in refractive index and advantages in the manufacturing process.

  Here, the positional relationship between the plurality of interlayer insulating films 113a to 113e and the first waveguide member 118 disposed in the opening 116 will be described. In a certain plane, a region where the first waveguide member 118 is disposed is surrounded or sandwiched between regions where the plurality of interlayer insulating films 113a to 113e are disposed. In other words, the first part and the first part of the plurality of interlayer insulating films 113a to 113e are along the direction intersecting the direction in which the photoelectric conversion unit 105 and the first waveguide member 118 disposed in the opening 116 are arranged. A different second portion and a first waveguide member 118 disposed in the opening 116 are arranged. The direction intersecting the direction in which the photoelectric conversion unit 105 and the first waveguide member 118 arranged in the opening 116 are aligned is, for example, a direction parallel to the main surface 102 of the semiconductor substrate 101.

  A first waveguide member 118 is disposed at a position overlapping the photoelectric conversion unit 105 on the semiconductor substrate 101. A plurality of interlayer insulating films 113 a to 113 e are arranged around the first waveguide member 118. The refractive index of the material forming the first waveguide member 118 is preferably higher than the refractive index of the plurality of interlayer insulating films 113a to 113e. With such a refractive index relationship, the amount of light leaking into the plurality of interlayer insulating films 113a to 113e out of the light incident on the first waveguide member 118 can be reduced. Therefore, if at least a part of the first waveguide member 118 overlaps the photoelectric conversion unit 105, the amount of light incident on the photoelectric conversion unit 105 can be increased.

  The refractive index of the first waveguide member 118 is not necessarily higher than that of the plurality of interlayer insulating films 113a to 113e. If the light incident on the first waveguide member 118 does not leak into the surrounding insulator, it functions as an optical waveguide. For example, a reflection member that reflects light may be disposed on the side wall of the opening 116, and the first waveguide member 118 may be embedded in the other part of the opening 116. There may be an air gap between the first waveguide member 118 disposed in the opening 116 and the plurality of interlayer insulating films 113a to 113e. The air gap may be a vacuum or a gas may be provided. In these cases, the refractive index of the material forming the first waveguide member 118 and the refractive index of the material forming the plurality of interlayer insulating films 113a to 113e may have any magnitude relationship.

  In the present embodiment, a silicon oxide film is disposed as the fifth interlayer insulating film 113e on the conductive member of the second wiring layer 112b. A silicon nitride film is disposed as the first waveguide member 118 on the fifth interlayer insulating film 113e. However, the insulator disposed on the conductive member of the second wiring layer 112b is not limited to the silicon oxide film. For example, SiC may be formed on the conductive member of the second wiring layer 112b, and a silicon nitride film may be formed as the first waveguide member 118 on the SiC. Compared to the resistivity of the conductive member, the resistivity of SiC is low enough to function as an insulator.

  Subsequently, in the process illustrated in FIG. 2A, the portion disposed in the peripheral region 104 of the first waveguide member 118 is removed. First, an etching mask (not shown) is stacked on the first waveguide member 118. The etching mask has an opening at the position of the peripheral region 104. Next, the portion disposed in the peripheral region 104 of the first waveguide member 118 is removed by etching.

  At this time, it is preferable that the first waveguide member 118 is etched so that the portion disposed in the peripheral region 104 remains with a predetermined thickness. Thus, the presence of the first waveguide member 118 with a predetermined film thickness can reduce damage to the semiconductor substrate due to etching. Of course, the first waveguide member 118 may be removed until the fifth interlayer insulating film 113e is exposed.

  In the present embodiment, all portions of the first waveguide member 118 disposed in the peripheral region 104 are etched. In other words, no etching mask is provided in the peripheral region 104. Thus, it is preferable that the area of the portion to be etched is large. However, only a part of the portion arranged in the peripheral region 104 may be etched. The area here is an area in a plane.

  Further, the method of removing the portion disposed in the peripheral region 104 of the first waveguide member 118 is not limited to etching. For example, a part of the first waveguide member 118 may be removed by lift-off. Specifically, a base film is formed in the peripheral region 104 before forming the first waveguide member 118. By removing the base film after forming the first waveguide member 118, the first waveguide member 118 disposed thereon is also removed at the same time.

  In this step, a part of the first waveguide member 118 arranged in the imaging region 103 may be removed.

  In the step shown in FIG. 2B, the second waveguide member 122 is formed on the opposite side of the first waveguide member 118 from the semiconductor substrate 101. The second waveguide member 122 is formed in the imaging region 103 and the peripheral region 104. In this embodiment, the difference between the step of forming the first waveguide member 118 and the step of forming the second waveguide member 122 is arranged in the peripheral region 104 of the first waveguide member 118 between the two steps. The step of removing the part is performed. For this reason, the second waveguide member 122 may be formed of the same material as the first waveguide member 118. Alternatively, the second waveguide member 122 may be formed by the same method as when the first waveguide member 118 is formed. Of course, the second waveguide member 122 may be formed of a material different from that of the first waveguide member 118, or the second waveguide member 122 may be formed by a method different from the method of forming the first waveguide member 118. Also good.

  In the present embodiment, the first waveguide member 118 and the second waveguide member 122 are formed of the same material. Specifically, the second waveguide member 122 is made of silicon nitride. In this case, the second waveguide member 122 can be formed by CVD or sputtering. Alternatively, the second waveguide member 122 may be formed by applying an organic material typified by a polyimide polymer.

  In the present embodiment, both the first waveguide member 118 and the second waveguide member are formed by CVD. However, process conditions differ between the two. Note that the second waveguide member 122 may be formed by a plurality of processes having different conditions. Further, the second waveguide member 122 may be formed by sequentially forming a plurality of different materials.

  FIG. 2C shows a planarization process after the second waveguide member 122 is formed. In this embodiment, the surface of the second waveguide member 122 opposite to the semiconductor substrate 101 is flattened by CMP. The planarization can be performed by a known method. For example, planarization may be performed by polishing or etching. Further, the first waveguide member 118 or a member closer to the semiconductor substrate 101 than the second waveguide member may be exposed by planarization. In the present embodiment, the first waveguide member 118 is exposed in the peripheral region 104. The second waveguide member 122 remains in the imaging region 103. However, the second waveguide member 122 may remain in the peripheral region 104.

  In the step of FIG. 4C, the surface of the second waveguide member 122 opposite to the semiconductor substrate 101 does not have to be completely flat. The level difference on the surface opposite to the semiconductor substrate 101 of the second waveguide member 122 before planarization may be reduced by the planarization process. For example, in the peripheral region 104, the total thickness of the first waveguide member 118 and the second waveguide member 122 after planarization is preferably in the range of 200 nm to 500 nm. In addition, in the region where the opening 116 of the imaging region 103 is not arranged, the total thickness of the first waveguide member 118 and the second waveguide member 122 after planarization is in the range of 50 nm to 350 nm. Is preferred.

  In this embodiment, the surface of the second waveguide member 122 opposite to the semiconductor substrate 101 is exposed during the planarization process. When another member is formed on the second waveguide member 122, the exposed surface of the other member is flattened.

  In the step of FIG. 3A, the low refractive index member 123 is formed. The refractive index of the low refractive index member 123 is lower than the refractive index of the member disposed on the semiconductor substrate 101 side with respect to the low refractive index folding member 123 and disposed in contact with the low refractive index member 123. The member disposed on the semiconductor substrate 101 side with respect to the low refractive index member 123 and in contact with the low refractive index member 123 is, in other words, exposed before the low refractive index member 123 is formed. It is a member. In the present embodiment, the first waveguide member 118 and the second waveguide member 122 correspond. That is, in this embodiment, the refractive index of the low refractive index member 123 is lower than the refractive indexes of the first waveguide member 118 and the second waveguide member 122. Specifically, the low refractive index member 123 is formed of a silicon oxynitride film. The refractive index of the silicon oxynitride film is about 1.72. Note that the low refractive index member 123 is not necessarily provided. When the low refractive index member 123 is not provided, the step of FIG.

  In the step of FIG. 3B, the portion formed in the peripheral region 104 of the first waveguide member 118, the portion formed in the peripheral region 104 of the second waveguide member 122, or both are removed. In particular, in this step, the first waveguide member 118 and the second waveguide member 122 disposed within a predetermined distance from the position where the plug 121 described later is disposed and the position where the plug 121 is disposed may be removed. preferable. When the low refractive index member 123 is disposed, the portion disposed in the peripheral region 104 of the low refractive index member 123 is removed.

  Depending on the process prior to this process, either the first waveguide member 118 or the second waveguide member 122 may not be disposed in the peripheral region 104. In such a case, the first waveguide member 118 or the second waveguide member 122 that is disposed in the peripheral region 104 is removed.

  A well-known method can be used for the removal method. For example, in this embodiment, the portions formed in the peripheral region 104 of the first waveguide member 118, the second waveguide member 122, and the low refractive index member 123 are removed by etching.

  In this step, a part of the first waveguide member 118 arranged in the imaging region 103 may be removed.

  In the step of FIG. 3C, a seventh interlayer insulating film 124 is formed. The seventh interlayer insulating film 124 is preferably formed of the same material as the fifth interlayer insulating film 113e. If necessary, the surface of the seventh interlayer insulating film 124 opposite to the semiconductor substrate 101 may be planarized.

  In the process of FIG. 4A, a through hole 125 is formed at a position overlapping a predetermined conductive member of the second wiring layer 112b of the seventh interlayer insulating film 124. The through hole 125 is formed, for example, by etching the seventh interlayer insulating film 124 and the fifth interlayer insulating film 113e.

  In the step of FIG. 4B, the third wiring layer 112c and the intralayer lens 120 are formed. First, the plug 121 is formed in the through hole 125. The plug 121 electrically connects a predetermined conductive member of the second wiring layer 112b and a predetermined conductive member of the third wiring layer 112c. The plug 121 is made of tungsten, for example. The material constituting the plug 121 may be a conductive material.

  Next, the third wiring layer 112c is formed. In the present embodiment, the conductive member of the third wiring layer 112c is made of aluminum. As the method for forming the third wiring layer 112c, the method described in the step of forming the first wiring layer 112a or the first wiring layer 112b is appropriately used. The conductive member of the third wiring layer 112c may be made of a metal other than aluminum.

  In this step, the inner lens 120 is formed. The in-layer lens 120 is disposed corresponding to the photoelectric conversion unit 105. The intralayer lens 120 is formed of, for example, a silicon nitride film. A known method can be used as a method of forming the in-layer lens 120. In this embodiment, the material forming the in-layer lens 120 is also disposed in the peripheral region 104. However, the material forming the inner lens 120 may be disposed only in the imaging region 103.

  Further, an intermediate member having an intermediate refractive index between the inner lens 120 and the seventh interlayer insulating film 124 may be disposed. In this embodiment, a silicon oxynitride film (not shown) is disposed between the inner lens 120 and the seventh interlayer insulating film 124. Specifically, the refractive index of the silicon nitride film (inner lens 120) is about 2.00, the refractive index of the silicon oxynitride film (intermediate member) is about 1.72, and the silicon oxide film (seventh interlayer insulating film 124). Has a refractive index of about 1.45.

  With such a configuration, the reflectance can be reduced. This point will be briefly described. In general, when light travels from a medium having a refractive index n1 to a medium having a refractive index n2, the reflectance increases as the difference between n1 and n2 increases. By disposing an intermediate member having an intermediate refractive index between the inner lens 120 and the seventh interlayer insulating film 124, the difference in refractive index at the interface is reduced. As a result, compared with the case where the inner lens 120 and the seventh interlayer insulating film 124 are arranged in contact with each other, the reflectance when light enters the seventh interlayer insulating film 124 from the inner lens 120 is reduced. be able to. Similarly, the low refractive index member 123 having a refractive index intermediate between the seventh interlayer insulating film 124 and the second waveguide member 122 is arranged, so that the difference in refractive index at the interface is reduced. . As a result, the reflectance when light enters the second waveguide member 122 from the seventh interlayer insulating film 124 can be reduced.

  The degree of reduction in reflectance due to the arrangement of the intermediate member varies depending on the relationship between the film thickness d of the intermediate member, the refractive index N of the intermediate member, and the wavelength p of the incident light. This is because multiple reflected light from a plurality of interfaces cancel each other. Theoretically, when k is an arbitrary integer greater than or equal to 0, the reflectance is most reduced when the condition of the expression (1) is satisfied.

  That is, when the film thickness of the intermediate member is an odd multiple of p / 4N, the reflectance is theoretically reduced most. Therefore, what is necessary is just to set the film thickness of an intermediate member based on said Formula (1). In particular, the film thickness of the intermediate member preferably satisfies the following formula (2). Furthermore, the case where k = 0 in the formula (2) is most preferable.

  For example, the refractive index of the seventh interlayer insulating film 124 is 1.45, the refractive index of the intermediate member is 1.72, the refractive index of the inner lens 120 is 2.00, and the wavelength of incident light is 550 nm. Think. At this time, when the film thickness of the intermediate member is 80 nm, the transmittance of light transmitted from the inner lens 120 to the seventh interlayer insulating film 124 is about 1.00. On the other hand, when the inner lens 120 and the seventh interlayer insulating film 124 are arranged in contact with each other, the transmittance is about 0.97.

  In the step of FIG. 4C, color filters 127a and 127b and a micro lens 128 are formed. First, the eighth insulating film 126 is formed on the opposite side of the intralayer lens 120 from the semiconductor substrate 101. The eighth insulating film 126 is made of, for example, an organic material. If necessary, the surface of the eighth insulating film 126 opposite to the semiconductor substrate 101 is planarized. For example, the eighth insulating film 126 whose surface opposite to the semiconductor substrate 101 is planarized can be formed by applying an organic material constituting the eighth insulating film 126.

  Next, color filters 127a and 127b are formed. The color filters 127 a and 127 b are arranged corresponding to the photoelectric conversion unit 105. The wavelength of light transmitted through the color filter 127a and the wavelength of light transmitted through the color filter 127b may be different. Subsequently, a micro lens 128 is formed on the opposite side of the semiconductor substrate 101 with respect to the color filters 127a and 127b. A known method can be used as a method of forming the microlens 128.

  FIG. 5 is a schematic diagram illustrating a planar structure of the solid-state imaging device according to the present embodiment. Cross sections along the line AB in FIG. 5 are shown in FIGS.

  In FIG. 5, the solid-state imaging device 100 includes an imaging region 103 and a peripheral region 104. The imaging region 103 may further include a light receiving region 103a and a light shielding region 103b. A plurality of pixels are two-dimensionally arranged in the imaging region 103. The photoelectric conversion portions of the pixels arranged in the light shielding region 103b are shielded from light. The signal from such a pixel can be used as a reference for the black level.

  The peripheral area 104 is an area other than the imaging area 103. In the present embodiment, a vertical scanning circuit 302, a horizontal scanning circuit 303, a column amplifier 304, a column ADC (Analog to Digital Converter) 305, a memory 306, a timing generator 307, and a plurality of pads 308 are arranged in the peripheral region 104. The These circuits are circuits for processing signals from the pixels. Note that a part of the above circuit may not be arranged.

  In this embodiment, the region where the first waveguide member 118, the second waveguide member 122, and the low refractive index member 123 are removed is a region 301 outside the dotted line in FIG. If the first waveguide member 118, the second waveguide member 122, and the low refractive index member 123 are at least removed from the region where the through hole 125 is formed to a predetermined distance, the effects of the present invention are eliminated. Can be obtained.

  Further, when the dielectric constant of the first waveguide member 118 is higher than the dielectric constant of the fifth interlayer insulating film 113e, it is desirable that most of the peripheral region 104 is the region 301 as shown in FIG. Furthermore, it is more preferable that the entire surface of the peripheral region 104 is the region 301. This is because the parasitic capacitance between the wirings can be reduced by removing most of the first waveguide member 118 having a high dielectric constant. Alternatively, even when the dielectric constant of the first waveguide member 118 is higher than the dielectric constant of the seventh interlayer insulating film 124, it is desirable that most of the peripheral region 104 is the region 301 as shown in FIG. Furthermore, it is more preferable that the entire surface of the peripheral region 104 is the region 301. This is because the parasitic capacitance between the wirings can be reduced by removing most of the first waveguide member 118 having a high dielectric constant.

  According to the manufacturing method of the present embodiment, it is easy to form the through hole 125 for arranging the plug 121. The reason for this will be briefly described. If the first waveguide member 118, the second waveguide member 122, and the low refractive index member 123 are not removed before forming the seventh interlayer insulating film 124, the fifth interlayer insulating film 113e and the seventh interlayer insulating film 124 are removed. The first waveguide member 118, the second waveguide member 122, and the low refractive index member 123 are disposed between the two. Then, in order to form the through hole 125, a removal process (for example, etching) under conditions suitable for each layer may be required. In contrast, the first waveguide member 118, the second waveguide member 122, and the low refractive index member 123 are removed before the seventh interlayer insulating film 124 is formed, and then the seventh interlayer insulating film 124 is formed. By forming, the fifth interlayer insulating film 113e and the seventh interlayer insulating film 124 are disposed in contact with each other in the region where the through hole 125 is to be formed. By forming the fifth interlayer insulating film 113e and the seventh interlayer insulating film 124 with the same material, the step of forming the through hole 125 can be performed in a single process. Therefore, the through hole 125 can be formed in two removal steps including the previous removal step of the first waveguide member 118. Since it becomes easy to form the through hole 125 in this way, the process is simplified.

  A second embodiment of the method for manufacturing the solid-state imaging device according to the present invention will be described with reference to FIGS. 6 and 7, parts having the same functions as those in FIGS. 1 to 5 are denoted by the same reference numerals, and detailed description thereof is omitted. This embodiment is different from the first embodiment in that the second waveguide member 122 is not formed.

  FIG. 6A shows the same process as the process shown in FIG. That is, FIG. 6A shows a state in which the first waveguide member 118 is formed on the plurality of interlayer insulating films 113a to 113e in which the openings 116 are formed. The steps up to FIG. 6A in the manufacturing method of the present embodiment are the same as the steps of FIG. 1A to FIG.

  In the step of FIG. 6B, the surface of the first waveguide member 118 opposite to the semiconductor substrate 101 is flattened. The planarization of the first waveguide member 118 is performed by, for example, CMP, polishing, or etching. In this embodiment, planarization is performed by CMP.

  In the process of FIG. 6B, the surface of the first waveguide member 118 opposite to the semiconductor substrate 101 does not have to be completely flat. The level difference on the surface opposite to the semiconductor substrate 101 of the first waveguide member 118 before planarization may be reduced by the planarization process. For example, the film thickness of the first waveguide member 118 after being planarized in the peripheral region 104 is preferably in the range of 200 nm to 500 nm. In addition, in the region where the opening 116 of the imaging region 103 is not disposed, the film thickness of the first waveguide member 118 after planarization is preferably in the range of 50 nm to 350 nm.

  In this embodiment, the surface of the first waveguide member 118 opposite to the semiconductor substrate 101 is exposed during the planarization process. When another member is formed on the first waveguide member 118, the exposed surface of the other member is flattened.

  In the step of FIG. 6C, after the first waveguide member 118 is flattened, a step of removing the portion formed in the peripheral region 104 of the first waveguide member 118 is performed. Particularly in this step, it is preferable to remove the position where the plug 121 is disposed and the first waveguide member 118 disposed within a predetermined distance from the position where the plug 121 is disposed. Thereafter, a sixth interlayer insulating film 119 is formed.

  Subsequently, in the process of FIG. 7A, a seventh interlayer insulating film 124 is formed. First, a sixth interlayer insulating film 119 is formed on the first waveguide member 118. The sixth interlayer insulating film 119 is preferably formed of the same material as the fifth interlayer insulating film 113e. In the present embodiment, the sixth interlayer insulating film 119 is a silicon oxide film.

  In the step of FIG. 7B, a through hole 125 for forming a predetermined conductive member of the second wiring layer 112b and a plug 121 that electrically connects the predetermined conductive member of the third wiring layer 112c is formed. . The through hole 125 is formed by etching the seventh interlayer insulating film 124 and the fifth interlayer insulating film 113e.

  In the step of FIG. 7C, the third wiring layer 112c and the intralayer lens 120 are formed. First, the plug 121 is formed in the through hole 125. Next, the third wiring layer 112c is formed. In the present embodiment, the conductive member of the third wiring layer 112c is made of aluminum. As the method for forming the third wiring layer 112c, the method described in the method for forming the first wiring layer 112a or the first wiring layer 112b is appropriately used. Next, the in-layer lens 120 is formed. The in-layer lens 120 is disposed corresponding to the photoelectric conversion unit 105. The intralayer lens 120 is formed of, for example, a silicon nitride film. A known method can be used as a method of forming the in-layer lens 120. Thereafter, if necessary, a color filter, a microlens, or the like is formed on the opposite side of the in-layer lens 120 from the semiconductor substrate 101.

  According to such a process, it becomes easy to form the through hole 125 for arranging the plug 121. The reason for this will be briefly described. If the first waveguide member 118 is not removed before the seventh interlayer insulating film 124 is formed, the fifth interlayer insulating film 113e, the first waveguide member 118, and the seventh interlayer insulating film are formed from the side close to the semiconductor substrate 101. 124 are sequentially stacked. Then, in order to form the through hole 125, three removal steps (for example, etching) under conditions suitable for each layer are required. On the other hand, by removing the first waveguide member 118 first and then forming the seventh interlayer insulating film 124, the region where the through hole 125 is to be formed is the fifth from the side close to the semiconductor substrate 101. An interlayer insulating film 113e and a seventh interlayer insulating film 124 are sequentially stacked. By forming the fifth interlayer insulating film 113e and the seventh interlayer insulating film 124 with the same material, the removal step of forming the through hole 125 can be performed under one condition. Therefore, the through hole 125 can be formed in two removal steps including the removal step of the first waveguide member 118 performed previously.

  A third embodiment of the method for manufacturing the solid-state imaging device according to the present invention will be described with reference to FIG. 8, parts having the same functions as those in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description thereof is omitted. In the present embodiment, the process after removing the portion arranged in the peripheral region of the first waveguide member 118 is different from that in the second embodiment.

  FIG. 8A shows the same process as that shown in FIG. That is, in FIG. 8A, after the surface of the first waveguide member 118 opposite to the semiconductor substrate 101 is flattened, a part of the first waveguide member 118 disposed in the peripheral region 104 is removed. It shows the state that was done. Of the first waveguide member 118, at least a region where a plug is formed in a later step and a region within a predetermined distance from the region are removed. Note that the process up to FIG. 8A in the manufacturing method of the present example is the same as the process up to FIG.

  In FIG. 8B, a through hole 801 is formed in the fifth interlayer insulating film 113e. The through hole 801 is formed on a predetermined conductive member of the second wiring layer 112b. Various methods can be used for forming the through hole 801. In this embodiment, the fifth interlayer insulating film 113e is removed by etching.

  In FIG. 8C, the third wiring layer 112c is formed. In this embodiment, the conductive member included in the third wiring layer 112c is made of aluminum. Of course, the conductive member included in the third wiring layer 112c may be made of copper or another conductive material.

  In this embodiment, after forming the through hole 801, an aluminum film is formed on the entire surface of the semiconductor substrate 101, and a predetermined pattern is obtained by etching. At this time, the plug disposed in the through hole 801 and the conductive member included in the third wiring layer 112c are integrally formed. Thereafter, the in-layer lens 120 is formed. The method for forming the in-layer lens 120 may be the same as in the first or second embodiment.

  According to this embodiment, the step of forming the seventh interlayer insulating film 124 is omitted. Further, the plug and the conductive member of the third wiring layer 112c are integrally formed. Therefore, the manufacturing process can be further simplified.

  A fourth embodiment of the method for manufacturing the solid-state imaging device according to the present invention will be described with reference to FIG. 9, parts having the same functions as those in FIGS. 1 to 8 are denoted by the same reference numerals, and detailed description thereof is omitted. In Example 1, after the second waveguide member 122 was formed, the planarization step shown in FIG. 2C was performed. In this embodiment, the first waveguide member 118 is formed and then planarized, and then the second waveguide member 122 is formed.

  The manufacturing method of this example is the same as the manufacturing method of Example 2 up to the step shown in FIG. In this embodiment, as shown in FIG. 7A, an insulating film 901 is formed on the planarized first waveguide member 118.

  The insulating film 901 may be formed for the purpose of filling a portion of the opening 116 where the first waveguide member 118 is not buried. In this case, the insulating film 901 is preferably made of the same material as the first waveguide member 118. The insulating film 901 may have a function similar to that of the low refractive index member 123 of the first embodiment. Of course, the function of the insulating film 901 is not limited to the above function.

  9B, the portion formed in the peripheral region 104 of the first waveguide member 118 and the portion formed in the peripheral region 104 of the insulating film 901 are removed. In particular, in this step, it is preferable to remove the first waveguide member 118 and the insulating film 901 disposed within a predetermined distance from the position where the plug 121 described later is disposed and the position where the plug 121 is disposed.

  A well-known method can be used for the removal method. For example, in this embodiment, the first waveguide member 118 and the portion formed in the peripheral region 104 of the insulating film 901 are removed by etching.

  In the step of FIG. 9C, a seventh interlayer insulating film 124 is formed. The seventh interlayer insulating film 124 is preferably formed of the same material as the fifth interlayer insulating film 113e. If necessary, the surface of the seventh interlayer insulating film 124 opposite to the semiconductor substrate 101 may be planarized.

  In the subsequent steps, the same steps as those in FIG.

  Another embodiment of the solid-state imaging device to which the manufacturing method of the solid-state imaging device according to the present invention can be applied will be described with reference to FIG. 10, parts having the same functions as those in FIGS. 1 to 9 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In this embodiment, the imaging area 103 includes a light receiving area (effective pixel area) 103a and a light shielding area (optical black pixel area) 103b. An opening 116 is formed corresponding to each of the photoelectric conversion unit 105 a disposed in the light receiving region 103 a and the photoelectric conversion unit 105 b disposed in the light shielding region 103 b, and the first waveguide member 118 is formed inside the opening 116. Is done. That is, an optical waveguide is formed in each of the photoelectric conversion unit 105a and the photoelectric conversion unit 105b.

  A light shielding member 1001 is disposed in the light shielding region 103b. The light shielding member 1001 is disposed on the side opposite to the semiconductor substrate 101 with respect to the first waveguide member 118. The light blocking member 1001 blocks at least a part of the light incident on the photoelectric conversion unit 105b. The light blocking member 1001 preferably blocks all of the light incident on the photoelectric conversion unit 105b. Of course, obliquely incident light or the like may enter the photoelectric conversion unit 105b disposed in the light shielding region 103b. The light shielding member 1001 reduces the amount of light incident on the photoelectric conversion unit 105b compared to the amount of light incident on the photoelectric conversion unit 105a when a uniform amount of light is irradiated on the entire surface of the imaging region 103. What is necessary is just to have the function to do.

  In this embodiment, the light shielding member 1001 is made of aluminum. The light shielding member 1001 may be included in the third wiring layer 112c. That is, it is preferable that the light shielding member 1001 is made of the same material as the conductive member included in the third wiring layer 112c. From the viewpoint of the manufacturing method, it is preferable to form the light shielding member 1001 at the same time when the conductive member included in the third wiring layer 112c is formed. The method for forming the light shielding member 1001 is not limited to this, and various methods may be used.

  In the present embodiment, among the portions disposed in the peripheral region 104 of the first waveguide member 118, at least a position where the plug 121 is disposed and a portion within a predetermined distance from the position where the plug 121 is disposed. Is removed. However, the portion disposed in the light shielding region 103b of the first waveguide member 118 is not removed. The configuration in which the portion disposed in the light shielding region 103b of the first waveguide member 118 is not removed is one embodiment, and the portion disposed in the light shielding region 103b of the first waveguide member 118 as necessary. May be removed.

  Another embodiment of the solid-state imaging device to which the manufacturing method of the solid-state imaging device according to the present invention can be applied will be described with reference to FIG. 11, parts having the same functions as those in FIGS. 1 to 10 are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIGS. 11A to 11C are schematic views of a planar structure of the solid-state imaging device of the present embodiment. In the present embodiment, a part of the first waveguide member 118 disposed in the peripheral region 104 is removed, and another part is not removed. In the present embodiment, at least the first waveguide member 118 disposed in a region where the plug 121 is disposed and a region within a predetermined distance from the region where the plug 121 is disposed is removed. The predetermined distance is indicated by an arrow in FIG. The predetermined distance may be determined based on the planar size of the plug, for example.

  In the region where the first waveguide member 118 is not removed, the first waveguide member 118 is arranged as a pattern 1101 as shown in FIG. The pattern 1101 is arranged in a dot shape in an area separated from the area where the plug 121 is arranged by a predetermined distance. Note that there may be a region 1102 where the pattern 1101 is not disposed in a region separated from the region where the plug 121 is disposed by a predetermined distance. For example, it is preferable that the pattern 1101 is not disposed in a portion where the conductive member of the second wiring layer and the conductive member of the third wiring layer overlap. The reason for this is that an increase in parasitic capacitance can be reduced by arranging the first waveguide member 118 having a high dielectric constant. The first waveguide member 118 having a high dielectric constant means that the dielectric constant is higher than other members disposed between the conductive member of the second wiring layer and the conductive member of the third wiring layer. Means.

  The removal of the first waveguide member 118 means, for example, that the fifth interlayer insulating film 113e is exposed at least immediately after the step of removing the first waveguide member 118. On the other hand, if the first waveguide member 118 is not removed, for example, the fifth interlayer insulation that is disposed on the semiconductor substrate 101 side with respect to the first waveguide member 118 and is in contact with the first waveguide member 118. The film 113e is not exposed.

  FIGS. 11B and 11C show planar variations of the pattern 1101. The pattern 1101 may be configured by a combination of the dot pattern 1101a and the line pattern 1101b.

  As described above, by leaving the first waveguide member 118 in a part of the peripheral region 104, a step between the imaging region 103 and the peripheral region 104 can be reduced. If the entire surface of the first waveguide member 118 disposed in the peripheral region 104 is removed, a step may be generated between the imaging region 103 and the peripheral region 104 after the seventh interlayer insulating film 124 is formed, for example. In this case, there is a possibility that the level difference may not be eliminated by the subsequent planarization process. Here, it is possible to reduce the step by appropriately setting the ratio of the area in which the first waveguide member 118 remains in the peripheral area 104.

DESCRIPTION OF SYMBOLS 100 Solid-state imaging device 101 Semiconductor substrate 103 Imaging area 104 Peripheral area 105 Photoelectric conversion part 112a 1st wiring layer 112b 2nd wiring layer 112c 3rd wiring layer 113a-113e 1st-5th interlayer insulation film 114 Plug 116 Opening 118 1st Waveguide member 119 Sixth interlayer insulating film 121 Plug 125 Through hole 126 Eighth insulating film

Claims (4)

A conductive member is formed on the second region of the semiconductor substrate including a first region in which a plurality of photoelectric conversion units are arranged and a second region in which a circuit for processing signals from the plurality of photoelectric conversion units is arranged. The first step;
A second step of forming a first silicon oxide film including a first portion disposed on the first region of the semiconductor substrate and a second portion disposed on the second region;
The first silicon oxide film is left at a position where a plug electrically connected to the conductive member is disposed, and corresponds to the plurality of photoelectric conversion units, which is the first portion of the first silicon oxide film. A third step of forming a plurality of first openings at positions to be
A fourth step of forming a silicon nitride film on the first region and the second region so as to fill the plurality of first openings and cover the second part of the first silicon oxide film; A portion of the silicon nitride film disposed on the second region, the position where the plug is disposed, and the portion disposed within a predetermined distance from the position where the plug is disposed. A fifth step of removing the first silicon oxide film so as to be exposed;
A sixth step of forming a second silicon oxide film on the first silicon oxide film exposed in the fifth step and the silicon nitride film disposed on the first region;
A seventh step of forming a second opening in a portion of the first silicon oxide film and the second silicon oxide film disposed at a position where the plug is disposed;
Have a, a eighth step of forming a plug in said second opening,
In the fifth step, a portion of the silicon nitride film that is disposed on the first region and that is disposed on a position where the first opening is not formed is left. A method for manufacturing a semiconductor device, characterized in that:   2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a silicon oxynitride film on the silicon nitride film between the fourth step and the fifth step.   In the fifth step, a portion of the silicon oxynitride film disposed on the second region, the position where the plug is disposed, and a predetermined distance from the position where the plug is disposed The method for manufacturing a semiconductor device according to claim 2, wherein a portion disposed in the substrate is removed.   4. The method according to claim 1, further comprising: forming another conductive member connected to the plug and disposed on the opposite side of the semiconductor substrate with respect to the conductive member. A method for manufacturing a semiconductor device according to claim 1.

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