JP2018078110A - Light-emitting device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shield light in the periphery of a display region in a simple manufacturing process.SOLUTION: A light-emitting device 100 includes: a light-emitting element 45 which is disposed in a display region 12 and includes a first electrode E1, a second electrode E2, and a light-emitting functional layer 46; peripheral wiring D which is formed in a periphery of the display region 12 in a plan view and is electrically connected to the second electrode E2; and a filter layer 90 including a first colored layer KR which transmits light having a first wavelength (about 610 nm). The filter layer 90 includes: a first color filter 94R formed from the first colored layer KR and overlapping the light-emitting element 45; and a first layer 96R formed from the first colored layer KR and overlapping the peripheral wiring D.SELECTED DRAWING: Figure 16

Description

  The present invention relates to a light emitting device using a light emitting material such as an organic EL material.

  Conventionally, light emitting devices in which light emitting elements using organic EL materials are arranged in a display region of a substrate have been proposed. The light-emitting element includes an anode electrode and a cathode electrode, and a light-emitting functional layer that emits light according to the current between both electrodes. A potential corresponding to the luminance of light emission is supplied to the anode electrode, and the cathode electrode has a low-side power supply. A potential is supplied. Patent Document 1 discloses a light emitting device in which a power supply conductor (peripheral wiring) that is connected to a light emitting element and supplies a power supply potential is formed around a display region in plan view.

JP 2010-107841 A

  In some cases, light from the observation side is incident around the display area. In the technique of Patent Document 1, since the peripheral wiring is formed around the display area in a plan view, the incident external light is reflected on the surface of the peripheral wiring and perceived by the observer (the reflection of the object on the observation side). Is perceived). As a means for solving the above problems, it is conceivable to form a light shielding member on the peripheral wiring. However, there is a problem that an additional process for forming a light-shielding member that overlaps the peripheral wiring is required, and the manufacturing process becomes complicated. In view of the above circumstances, an object of the present invention is to make it difficult for an observer to perceive reflected light on the surface of a peripheral wiring while suppressing complication of the manufacturing process.

  In order to solve the above problems, a light-emitting device according to a first aspect of the present invention is disposed in a display region, and a current between a first electrode and a second electrode and between the first electrode and the second electrode. A light emitting element including a light emitting functional layer that emits light in response to the light emitting element, a peripheral wiring that is formed around the display region in a plan view and is connected to the second electrode, and a first colored layer that transmits light of the first wavelength. A filter layer comprising a first color filter formed of a first colored layer and overlapping a light emitting element, and a filter layer including a first layer formed of a first colored layer and overlapping peripheral wiring. According to the above configuration, since the first layer overlaps the peripheral wiring, the light traveling from the observation side toward the peripheral wiring and the reflected light on the surface of the peripheral wiring are shielded by the first layer. Therefore, there is an advantage that the reflected light on the surface of the peripheral wiring is hardly perceived by the observer. Moreover, since both the first layer and the first color filter are formed of the first colored layer, they can be formed collectively in a common process. Therefore, there is an advantage that the manufacturing process is simplified compared to the case where the first layer is formed separately from the process of forming the first color filter.

  In a preferred embodiment of the present invention, the filter layer includes a second colored layer that transmits light having a second wavelength different from the first wavelength, and is formed of the second colored layer and overlaps the light emitting element. And a second colored layer formed on the surface of the first layer and overlapping the peripheral wiring. According to the above configuration, since the second layer and the first layer overlap the peripheral wiring, for example, the light shielding performance is improved as compared with the configuration in which the light is shielded by a single layer. Therefore, the effect that the reflected light on the surface of the peripheral wiring is hardly perceived by the observer is particularly remarkable. In addition, since the second layer and the second color filter are both formed of the second colored layer, they can be collectively formed in a common process. Therefore, there is an advantage that the manufacturing process is simplified compared to the case where the second layer is formed separately from the process of forming the second color filter.

  In a preferred aspect of the present invention, the periphery of the second layer is located inside the periphery of the first layer in plan view. According to the above configuration, since the periphery of the first layer and the periphery of the second layer do not overlap in plan view, the side surfaces of the first layer and the second layer are not formed flush with each other. In the configuration in which the side surfaces of the first layer and the second layer are formed flush with each other (that is, the periphery of the second layer and the periphery of the first layer overlap in plan view), the first layer is formed on the surface of the filter layer. And a step corresponding to the sum of the film thicknesses of the second layer. On the other hand, according to the aspect of the present invention, the step corresponding to the film thickness of the first layer and the step corresponding to the film thickness of the second layer are individually formed. It becomes smaller than the sum of the film thickness of the layer and the second layer. That is, the surface of the filter layer is formed flat compared to the configuration in which the side surfaces of the first layer and the second layer are formed flush with each other.

  In a preferred aspect of the present invention, the filter layer includes a third colored layer that transmits light having a third wavelength different from the first wavelength and the second wavelength, and is formed of the third colored layer and overlaps the light emitting element. A three-color filter and a third layer formed on the surface of the second layer by the third colored layer and overlapping the peripheral wiring. According to the above configuration, since the first layer, the second layer, and the third layer overlap with the peripheral wiring, the light shielding performance is improved as compared with, for example, a configuration in which light is shielded by a single layer or two layers. Therefore, the effect that the reflected light on the surface of the peripheral wiring is hardly perceived by the observer is particularly remarkable. In addition, since the third layer and the third color filter are both formed of the third colored layer, they can be collectively formed in a common process. Therefore, there is an advantage that the manufacturing process is simplified compared to the case where the third layer is formed separately from the process of forming the third color filter.

  In a preferred aspect of the present invention, the periphery of the third layer is located inside the periphery of the second layer in plan view. According to the above configuration, the step corresponding to the thickness of the second layer and the step corresponding to the thickness of the third layer are individually formed on the surface of the filter layer. Therefore, compared to a configuration in which the peripheral edges of the second layer and the third layer overlap in plan view (a configuration in which a step corresponding to the sum of the film thicknesses of the second layer and the third layer is generated on the surface of the filter layer), The surface of the filter layer can be flattened.

  In a preferred aspect of the present invention, the filter layer includes an insulating layer in which a plurality of first openings in the display area and a second opening overlapping the peripheral wiring are formed, and the first color filter and the second color filter The third color filter is formed inside the plurality of first openings, and the first layer, the second layer, and the third layer are formed inside the second opening. In the above configuration, the first color filter, the second color filter, and the third color filter are partitioned in the display region by the insulating layer. Since the first layer, the second layer, and the third layer are formed inside the second opening formed in the insulating layer, the first layer, the second layer, and the third layer are arranged on the surface of the insulating layer. Compared with the structure formed in the step, the step on the surface of the filter layer is reduced.

  The light emitting device according to each aspect described above is used in various electronic devices as a display device, for example. Specifically, a head-mounted display device, an electronic viewfinder of an imaging device, and the like can be exemplified as preferred examples of the electronic apparatus of the present invention, but the scope of application of the present invention is not limited to the above examples.

It is a top view of the light-emitting device of 1st Embodiment of this invention. It is a circuit diagram of a pixel. It is sectional drawing of a light-emitting device. It is sectional drawing of a light-emitting device. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is a schematic diagram of a 1st power supply conductor and a 2nd power supply conductor. It is explanatory drawing of the positional relationship of each element formed on a board | substrate. It is explanatory drawing of the effect of a 2nd conductor. It is a top view of each conduction hole formed in a peripheral region. It is sectional drawing of the vicinity of the conduction hole formed in the peripheral region in contrast. It is sectional drawing of the vicinity of the periphery of the light emission functional layer in 1st Embodiment and this invention. It is sectional drawing of a sealing body and a filter layer. It is a top view of a sealing body and a filter layer. It is sectional drawing of the sealing body and filter layer in contrast. It is sectional drawing of the sealing body and filter layer in 2nd Embodiment. It is sectional drawing of the sealing body and filter layer in a modification. It is a schematic diagram of a head-mounted display device as an example of an electronic device.

<First Embodiment>
FIG. 1 is a plan view of a light emitting device 100 according to the first embodiment of the present invention. The light emitting device 100 of the first embodiment is an organic EL device in which a light emitting element using an organic EL material is formed on the surface of the substrate 10. The substrate 10 is a plate-like member (semiconductor substrate) formed of a semiconductor material such as silicon (silicon), and is used as a base (base) on which a plurality of light emitting elements are formed.

  As illustrated in FIG. 1, a display area 12, a peripheral area 14, and a mounting area 16 are defined on the surface of the substrate 10. The display area 12 is a rectangular area in which a plurality of pixels P are arranged. In the display area 12, a plurality of scanning lines 22 extending in the X direction, a plurality of control lines 24 extending in the X direction corresponding to each scanning line 22, and a Y direction intersecting with the X direction are extended. A plurality of signal lines 26 are formed. A pixel P is formed corresponding to each intersection of the plurality of scanning lines 22 and the plurality of signal lines 26. Accordingly, the plurality of pixels P are arranged in a matrix over the X direction and the Y direction.

  The peripheral region 14 is a rectangular frame region that surrounds the display region 12. A drive circuit 30 is installed in the peripheral region 14. The drive circuit 30 is a circuit that drives each pixel P in the display area 12, and includes two scanning line drive circuits 32 and a signal line drive circuit 34. The light emitting device 100 according to the first embodiment is a display device with a built-in circuit in which a drive circuit 30 is configured by active elements such as transistors directly formed on the surface of a substrate 10. It is also possible to form dummy pixels in the peripheral region 14 that do not directly contribute to image display.

  The mounting area 16 is an area on the opposite side of the display area 12 with respect to the peripheral area 14 (that is, outside the peripheral area 14), and a plurality of mounting terminals 36 are arranged. A control signal and a power supply potential are supplied to each mounting terminal 36 from various external circuits (not shown) such as a control circuit and a power supply circuit. The external circuit is mounted on, for example, a flexible wiring board (not shown) joined to the mounting region 16.

  FIG. 2 is a circuit diagram of each pixel (pixel circuit) P in the display area 12. As illustrated in FIG. 2, the pixel P includes a light emitting element 45, a drive transistor TDR, a light emission control transistor TEL, a selection transistor TSL, and a capacitor element C. In the first embodiment, each transistor T (TDR, TEL, TSL) of the pixel P is a P-channel type, but an N-channel transistor can also be used.

  The light emitting element 45 is an electro-optical element in which a light emitting functional layer 46 including a light emitting layer of an organic EL material is interposed between a first electrode (anode) E1 and a second electrode (cathode) E2. The first electrode E1 is individually formed for each pixel P, and the second electrode E2 is continuous over a plurality of pixels P. As understood from FIG. 2, the light emitting element 45 is disposed on a current path connecting the first power supply conductor 41 and the second power supply conductor 42. The first power supply conductor 41 is a power supply wiring to which a higher power supply potential (first potential) VEL is supplied, and the second power supply conductor 42 is supplied with a lower power supply potential (second potential) VCT. Power supply wiring.

  The driving transistor TDR and the light emission control transistor TEL are arranged in series with respect to the light emitting element 45 on a current path connecting the first power supply conductor 41 and the second power supply conductor 42. Specifically, one (source) of the pair of current ends of the driving transistor TDR is connected to the first power supply conductor 41. The light emission control transistor TEL functions as a switch for controlling the conduction state (conduction / non-conduction) between the other (drain) of the pair of current ends of the drive transistor TDR and the first electrode E1 of the light emitting element 45. The drive transistor TDR generates a drive current having a current amount corresponding to the voltage between its gate and source. In a state where the light emission control transistor TEL is controlled to be in the on state, the drive current is supplied from the drive transistor TDR to the light emitting element 45 via the light emission control transistor TEL, so that the light emission element 45 corresponds to the amount of current of the drive current. Emits brightness. In a state where the light emission control transistor TEL is controlled to be in an off state, the light emitting element 45 is turned off by interrupting the supply of the driving current to the light emitting element 45. The gate of the light emission control transistor TEL is connected to the control line 24.

  The selection transistor TSL in FIG. 2 functions as a switch for controlling the conduction state (conduction / non-conduction) between the signal line 26 and the gate of the drive transistor TDR. The gate of the selection transistor TSL is connected to the scanning line 22. The capacitive element C is a capacitance in which a dielectric is interposed between the first electrode C1 and the second electrode C2. The first electrode C1 is connected to the gate of the driving transistor TDR, and the second electrode C2 is connected to the first power supply conductor 41 (the source of the driving transistor TDR). Therefore, the capacitive element C holds the voltage between the gate and the source of the driving transistor TDR.

  The signal line driving circuit 34 supplies a plurality of signal lines 26 for each writing period (horizontal scanning period) with a gradation potential (data signal) corresponding to a gradation specified for each pixel P by an image signal supplied from an external circuit. Is supplied in parallel. On the other hand, each scanning line drive circuit 32 supplies a scanning signal to each scanning line 22 to sequentially select each of the plurality of scanning lines 22 for each writing period. The selection transistor TSL of each pixel P corresponding to the scanning line 22 selected by the scanning line driving circuit 32 is turned on. Therefore, the gradation potential is supplied to the gate of the driving transistor TDR of each pixel P via the signal line 26 and the selection transistor TSL, and the capacitor C holds a voltage corresponding to the gradation potential. On the other hand, when the selection of the scanning line 22 in the writing period is completed, each scanning line driving circuit 32 supplies a control signal to each control line 24, whereby the light emission control transistor of each pixel P corresponding to the control line 24. Control TEL to be on. Accordingly, a drive current corresponding to the voltage held in the capacitor C in the immediately preceding writing period is supplied from the drive transistor TDR to the light emitting element 45 via the light emission control transistor TEL. As described above, each light emitting element 45 emits light at a luminance corresponding to the gradation potential, whereby an arbitrary image specified by the image signal is displayed in the display area 12.

  A specific structure of the light emitting device 100 of the first embodiment will be described in detail below. In each drawing referred to in the following description, the dimensions and scales of each element are different from those of the actual light emitting device 100 for convenience of description. 3 and 4 are cross-sectional views of the light emitting device 100, and FIGS. 5 to 9 show the appearance of the surface of the substrate 10 for each pixel P at each stage of forming each element of the light emitting device 100. FIG. It is the top view illustrated paying attention. A cross-sectional view corresponding to the cross section including the line III-III in FIGS. 5 to 9 corresponds to FIG. 3, and a cross-sectional view corresponding to the cross section along the line IV-IV in FIGS. 5 to 9 corresponds to FIG. 5 to 9 are plan views. From the viewpoint of facilitating visual grasp of each element, each element common to FIG. 3 or FIG. 4 is hatched in the same manner as FIG. 3 or FIG. It is added for convenience.

  As understood from FIGS. 3, 4 and 5, the substrate 10 formed of a semiconductor material such as silicon has an active region 10A (source / drain region) of each transistor T (TDR, TEL, TSL) of the pixel P. ) Is formed. Ions are implanted into the active region 10A. The active layer of each transistor T (TDR, TEL, TSL) of the pixel P exists between the source region and the drain region, and ions of a different type from the active region 10A are implanted, but the illustration is omitted for convenience. Has been. 3 and 4, the surface of the substrate 10 on which the active region 10A is formed is covered with an insulating film L0 (gate insulating film), and the gate G (GDR, GEL, GSL) of each transistor T is insulated. It is formed on the surface of the film L0. The gate G of each transistor T faces the active layer across the insulating film L0. FIG. 4 shows the gate GSL of the selection transistor TSL, the gate GDR of the drive transistor TDR, and the gate GEL of the light emission control transistor TEL.

  3 and 4, a plurality of insulating layers L (LA to LE) and a plurality of wiring layers W (WA to WE) are formed on the surface of the insulating film L0 on which the gate G of each transistor T is formed. ) Are alternately stacked. Each wiring layer W is formed of a low-resistance conductive material containing aluminum, silver, or the like. Each insulating layer L is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). In the following description, a relationship in which a plurality of elements are collectively formed in the same process by selective removal of a conductive layer (single layer or a plurality of layers) is referred to as “formed from the same layer”.

  The insulating layer LA is formed on the surface of the insulating film L0 on which the gate G of each transistor T is formed. As understood from FIGS. 3, 4 and 6, a conductor pattern including a scanning line 22, a control line 24, and a plurality of relay electrodes QA (QA1, QA2, QA3, QA4) on the surface of the insulating layer LA. Is formed from the same layer (wiring layer WA). The scanning line 22 and the control line 24 extend linearly in the X direction across the plurality of pixels P with a space therebetween. Specifically, as illustrated in FIG. 6, the scanning line 22 is formed so as to pass above the gate GSL of the selection transistor TSL and above the gate GDR of the driving transistor TDR, and conducts through the insulating layer LA. It conducts to the gate GSL of the selection transistor TSL through a hole (contact hole) HA1. The conduction hole HA1 is formed so as to overlap the gate GSL and the active layer of the selection transistor TSL in plan view. On the other hand, the control line 24 is formed so as to pass over the gate GEL of the light emission control transistor TEL, and is electrically connected to the gate GEL of the light emission control transistor TEL through the conduction hole HA2 penetrating the insulating layer LA. The conduction hole HA2 is formed so as to overlap the gate GEL and the active layer of the light emission control transistor TEL in plan view.

  The relay electrode QA1 is a wiring that connects the active region 10A of the selection transistor TSL and the gate GDR of the driving transistor TDR, and is located between the scanning line 22 and the control line 24 in plan view as illustrated in FIG. To do. Specifically, as understood from FIGS. 4 and 6, the relay electrode QA1 is electrically connected to the active region 10A of the selection transistor TSL through a conduction hole HA3 penetrating the insulating layer LA and the insulating film L0. It is electrically connected to the gate GDR of the drive transistor TDR through the conduction hole HA4 of the insulating layer LA. Further, as understood from FIG. 6, the relay electrode QA2 is electrically connected to the active region 10A of the selection transistor TSL through a conduction hole HA5 penetrating the insulating layer LA and the insulating film L0. The relay electrode QA3 is electrically connected to the active region 10A (source) of the drive transistor TDR through a conduction hole HA6 that penetrates the insulating layer LA and the insulating film L0. The relay electrode QA4 is electrically connected to the active region 10A (drain) of the light emission control transistor TEL via a conduction hole HA7 penetrating the insulating layer LA and the insulating film L0. As understood from FIG. 6, each of the selection transistor TSL, the drive transistor TDR, and the light emission control transistor TEL is formed so that the channel length is along the Y direction. The drive transistor TDR and the light emission control transistor TEL are arranged along the Y direction, and the selection transistor TSL is shifted in the X direction (the negative side in the X direction in FIG. 6) with respect to the drive transistor TDR and the light emission control transistor TEL. Placed in a different position.

  The insulating layer LB is formed on the surface of the insulating layer LA on which the wiring layer WA is formed. As understood from FIGS. 3, 4 and 7, the conductor pattern including the signal line 26, the first electrode C1, and the plurality of relay electrodes QB (QB1, QB2) is formed on the same layer on the surface of the insulating layer LB. (Wiring layer WB). The signal line 26 extends linearly in the Y direction over the plurality of pixels P, and is electrically insulated from the scanning line 22 and the control line 24 by the insulating layer LA. Specifically, the signal line 26 is formed so as to pass through the active region 10A (source, drain) and the active layer of the selection transistor TSL and the relay electrode QA1 that is conductive to the gate GDR of the driving transistor TDR. , And extends along the channel length direction (Y direction) of the selection transistor TSL and overlaps the selection transistor TSL in plan view. The signal line 26 is formed in an upper layer than the active region 10A (source, drain) of each transistor T (TDR, TEL, TSL) and the gate G of each transistor T. As understood from FIG. 7, the signal line 26 of the wiring layer WB is electrically connected to the relay electrode QA2 of the wiring layer WA through the conduction hole HB1 penetrating the insulating layer LB. That is, the signal line 26 and the active region 10A (source) of the selection transistor TSL are connected via the relay electrode QA2. The first electrode C1 of the wiring layer WB in FIG. 7 is electrically connected to the relay electrode QA1 of the wiring layer WA through a conduction hole HB2 penetrating the insulating layer LB. That is, the first electrode C1 of the capacitive element C and the gate GDR of the drive transistor TDR are connected via the relay electrode QA1. The relay electrode QB1 of the wiring layer WB in FIG. 7 is electrically connected to the relay electrode QA3 of the wiring layer WA via the conductive hole HB3 of the insulating layer LB, and the relay electrode QB2 of the wiring layer WB is connected to the conductive hole HB4 of the insulating layer LB. Through the relay electrode QA4 of the wiring layer WA.

  The insulating layer LC is formed on the surface of the insulating layer LB on which the wiring layer WB is formed. As understood from FIGS. 3, 4 and 8, a conductor pattern including the second electrode C2 is formed from the same layer (wiring layer WC) on the surface of the insulating layer LC. The second electrode C2 is formed in a shape and a position overlapping the first electrode C1 in a plan view (that is, as viewed from a direction perpendicular to the surface of the substrate 10). As understood from FIG. 3, the capacitive element C is constituted by the first electrode C1 and the second electrode C2 and the insulating layer LC therebetween. As illustrated in FIG. 8, the capacitive element C (first electrode C1, second electrode C2) is disposed so as to overlap the drive transistor TDR and the light emission control transistor TEL in plan view.

  As illustrated in FIGS. 3 and 4, the insulating layer LD is formed on the surface of the insulating layer LC on which the wiring layer WC is formed. A planarization process is performed on the surface of the insulating layer LD. For the planarization treatment, a known surface treatment technique such as chemical mechanical polishing (CMP) is arbitrarily employed. As illustrated in FIGS. 3 and 4, a conductor pattern including a first power supply conductor 41, a second power supply conductor 42, and a relay electrode QD1 on the surface of the insulating layer LD highly planarized by the planarization process. Are formed from the same layer (wiring layer WD). As shown in FIG. 3, the first power supply conductor 41 and the second power supply conductor 42 are formed to be separated from each other and electrically insulated. The first power supply conductor 41 is electrically connected to the mounting terminal 36 to which the higher power supply potential VEL is supplied via a wiring (not shown) in the multilayer wiring layer. Similarly, the second power supply conductor 42 is electrically connected to the mounting terminal 36 to which the lower power supply potential VCT is supplied via wiring (not shown) in the multilayer wiring layer. The first power supply conductor 41 and the second power supply conductor 42 of the first embodiment are made of a light-reflective conductive material containing, for example, silver or aluminum and have a thickness of, for example, about 100 nm.

  FIG. 10 is a plan view of the first power supply conductor 41 and the second power supply conductor 42. The first power supply conductor 41 is a power supply line to which the higher power supply potential VEL is supplied as described above. As illustrated in FIG. 10, the first power supply conductor 41 has a substantially rectangular shape formed in a planar shape over substantially the entire display area 12. It is a solid pattern. The solid pattern is not a linear or belt-like pattern or a combination thereof (for example, a lattice pattern), but a planar shape (that is, a solid pattern) that is substantially continuous with no gap so as to fill almost the entire surface of the display region 12. Pattern). The first power supply conductor 41 may be formed individually for each pixel P.

  As understood from FIGS. 4 and 9, the first power supply conductor 41 formed in the display region 12 is connected to the relay electrode via the conduction hole HD1 penetrating the insulating layer LD and the insulating layer LC for each pixel P. Conducts with QA3. That is, as understood from FIG. 4, the active region 10A that functions as the source of the drive transistor TDR is connected to the first power supply conductor 41 via the relay electrode QA3 and the relay electrode QB1. Further, as illustrated in FIG. 9, the first power supply conductor 41 is connected to the second electrode C2 of the capacitive element C through the conduction hole HD2 of the insulating layer LD. That is, the capacitive element C is interposed between the gate GDR and the source (first power supply conductor 41) of the driving transistor TDR. It is also possible to form a plurality of conduction holes HD2 in the insulating layer LD and connect the first power supply conductor 41 and the second electrode C2 of the capacitive element C at a plurality of locations.

  As illustrated in FIG. 9, the first power supply conductor 41 has an opening 41 </ b> A for each pixel P. A relay electrode QD1 is formed in the same layer as the first power supply conductor 41 and the second power supply conductor 42 inside each opening 41A. The relay electrode QD1 and the first power supply conductor 41 are formed away from each other and electrically insulated. As understood from FIGS. 4 and 9, the relay electrode QD1 is electrically connected to the relay electrode QB2 through a conduction hole HD3 penetrating the insulating layer LD and the insulating layer LC.

  The second power supply conductor 42 is a power supply wiring that is formed in the peripheral region 14 and is supplied with the lower power supply potential VCT as described above. As illustrated in FIG. 10, the second power supply conductor 42 of the present embodiment is formed in a rectangular frame shape (closed figure) surrounding the first power supply conductor 41 (display region 12) in plan view. The width (the distance from the inner periphery to the outer periphery) of the second power supply conductor 42 is, for example, 1.5 mm. FIG. 11 is an explanatory diagram of the positional relationship of each element formed on the surface of the insulating layer LD. An enlarged view of the region α in FIG. 10 corresponds to each part ((A) to (D)) in FIG. As can be understood from the part (A) of FIG. 10 and FIG. 11, the display area 12 and the peripheral area are surrounded by the periphery of the first power supply conductor 41 and the inner periphery of the second power supply conductor 42 in plan view. The boundary with the region 14 is located.

  As illustrated in FIGS. 3 and 4, the insulating layer LE is formed on the surface of the insulating layer LD on which the wiring layer WD is formed. On the surface of the insulating layer LE, a conductor pattern including the second conductor 58 shown in FIG. 3 and the relay electrode QE1 shown in FIG. 4 is formed from the same layer (wiring layer WE). The wiring layer WE is formed of, for example, a light shielding conductive material (for example, titanium nitride).

  The relay electrode QE1 is electrically connected to the relay electrode QD1 through a conduction hole penetrating the insulating layer LE. As understood from FIG. 4, the relay electrode QE1 is formed so as to overlap the opening 41A of the first power supply conductor 41 in plan view. That is, the outer peripheral edge of the relay electrode QE1 is located outside the inner peripheral edge of the opening 41A in plan view. Since the relay electrode QE1 is formed of a light-shielding conductive material, the relay electrode QE1 prevents external light from entering the multilayer wiring layer from the opening 41A. Therefore, there is an advantage that current leakage of each transistor T due to light irradiation can be prevented.

  The second conductor 58 is formed on the surfaces of the first power supply conductor 41 and the second power supply conductor 42 as shown in part (B) of FIGS. 10 and 11. In FIG. 10, a part of the second conductor 58 is shown by a solid line, and the other part of the outer shape is expressed by a chain line. As understood from FIG. 10, the second conductor 58 is formed in an annular shape (rectangular frame shape) similar to the second power conductor 42, and the first power conductor 41 and the second power conductor 42 in a plan view. It is formed in a belt shape that overlaps both. Specifically, the inner periphery of the second conductor 58 is located inside the periphery of the first power supply conductor 41 in plan view. That is, the second conductor 58 overlaps a region near the periphery of the first power supply conductor 41. The outer peripheral edge of the second conductor 58 is located outside the outer peripheral edge of the second power supply conductor 42 in plan view. That is, the second conductor 58 overlaps the entire area of the second power supply conductor 42 in plan view. As understood from the above description, the second conductor 58 has a gap region between the first power supply conductor 41 and the second power supply conductor 42 (that is, the boundary between the display region 12 and the peripheral region 14 in a plan view). (Overlapping area).

  A configuration in which the second conductor 58 is not formed is assumed to be proportional (hereinafter referred to as “comparative 1”). FIG. 12 is a cross-sectional view (cross-sectional view in the vicinity of the boundary between the display region 12 and the peripheral region 14) of the first power supply conductor 41 and the second power supply conductor 42 in the comparative example 1. As illustrated in FIG. 12, in the contrast 1, after the formation of the insulating layer LE covering the first power supply conductor 41 and the second power supply conductor 42, the first power supply conductor 41 and the second power supply conductor 42. The edge (corner) e is exposed from the insulating layer LE, and the first power supply conductor 41 and the second power supply conductor 42 may be damaged or corroded. On the other hand, in the first embodiment, the gap overlaps between the first power supply conductor 41 and the second power supply conductor 42 (covers the edge e of the first power supply conductor 41 and the second power supply conductor 42). Since the second conductor 58 is formed, there is an advantage that damage and corrosion of the first power supply conductor 41 and the second power supply conductor 42 due to the exposure from the insulating layer LE can be prevented.

  As shown in part (B) of FIGS. 3 and 11, the second conductor 58 is electrically connected to the second power supply conductor 42 through a conduction hole HE1 penetrating the insulating layer LE. FIG. 13 is a plan view of each conduction hole (HE1, HF1, HG1) formed in the peripheral region 14. FIG. As shown in FIG. 13, the conduction hole HE1 is a through hole obtained by removing a rectangular frame-shaped region surrounding the display region 12 in a plan view in the insulating layer LE. The conduction hole HE1 is formed in the first region S1 in the region overlapping the second power supply conductor 42 in plan view. The first region S1 is a rectangular frame-like region in plan view as shown in FIG. 13, and the inner periphery and the outer periphery of the second power supply conductor 42 in the peripheral region 14 as shown in the part (D) of FIG. Located between and. The width of the first region S1 (the distance from the inner periphery to the outer periphery) is, for example, 0.3 mm. The second conductor 58 is electrically connected to the second power supply conductor 42 over the entire circumference of the peripheral region 14 through the conduction hole HE1.

  As illustrated in FIGS. 3 and 4, the optical path adjustment layer 60 is formed on the surface of the insulating layer LE on which the wiring layer WE is formed. The optical path adjustment layer 60 is an element for individually setting the resonance wavelength (display color) of the resonance structure for each display color of the pixel P, and transmits light such as a silicon compound (typically silicon nitride or silicon oxide). Made of a conductive insulating material. Specifically, each optical path length (optical distance) between the first power supply conductor 41 and the second electrode E2 constituting the resonance structure is adjusted appropriately according to the film thickness of the optical path adjustment layer 60. The resonance wavelength of the light emitted from the pixel P is set for each display color.

  As illustrated in FIG. 3, on the surface of the optical path adjustment layer 60, the first electrode E1 for each pixel P in the display region 12 and the first conductor 63 in the peripheral region 14 are formed from the same layer. . The first electrode E1 and the first conductor 63 are made of a light-transmitting conductive material such as ITO (Indium Tin Oxide), for example. As described with reference to FIG. 2, the first electrode E1 is a substantially rectangular electrode (pixel electrode) that functions as an anode of the light emitting element 45, and is electrically connected to the optical path adjustment layer 60 as shown in FIG. It conducts to the relay electrode QE1 through the hole. That is, the first electrode E1 is electrically connected to the active region 10A (drain) of the light emission control transistor TEL via each relay electrode (QE1, QD1, QB2, QA4) of the multilayer wiring layer.

  The first conductor 63 is formed in an annular shape (rectangular frame shape) similar to the second conductor 58. As shown in part (C) of FIG. 11, the inner peripheral edge of the first conductor 63 is located on the inner side (periphery side of the substrate 10) of the second conductor 58, and the outer peripheral edge of the first conductor 63. Is located inside the outer peripheral edge of the second conductor 58. The first conductor 63 is electrically connected to the second conductor 58 through a conduction hole HF1 that penetrates the optical path adjustment layer 60, as shown in part (C) of FIGS. As shown in FIG. 13, the conduction hole HF1 is a through hole obtained by removing a rectangular frame-shaped region surrounding the display region 12 in plan view in the optical path adjustment layer 60. The conduction hole HF1 is located closer to the display area 12 than the conduction hole HE1. The first conductor 63 is electrically connected to the second conductor 58 over the entire circumference of the peripheral region 14 through the conduction hole HF1.

  On the surface of the optical path adjustment layer 60 on which the first electrode E1 and the first conductor 63 are formed, a pixel definition layer 65 is formed over the entire area of the substrate 10 as illustrated in FIG. The pixel definition layer 65 is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). As understood from FIG. 3, the pixel definition layer 65 is formed with openings 65 </ b> A corresponding to the first electrodes E <b> 1 in the display region 12.

  As illustrated in FIGS. 3 and 4, the light emitting functional layer 46 is formed on the surface of the optical path adjustment layer 60 on which the first electrode E 1, the first conductor 63, and the pixel definition layer 65 are formed. The light emitting functional layer 46 includes a light emitting layer formed of an organic EL material, and emits white light by supplying current. The light emitting layer is formed by a known film forming technique such as a printing technique or a vapor deposition technique. White light is light having a spectrum covering a blue wavelength range, a green wavelength range, and a red wavelength range, and at least two peaks are observed in the visible wavelength range. Note that the light emitting functional layer 46 may include an electron or hole transport layer or an injection layer supplied to the light emitting layer.

  As illustrated in FIG. 3, the light emitting functional layer 46 is continuous over a plurality of pixels P in the display region 12, and the peripheral edge 48 is located in the peripheral region 14 in plan view. Specifically, the peripheral edge 48 of the light emitting functional layer 46 is located in the second region S2, as shown in part (D) of FIG. The second region S2 is a rectangular frame region located on the display region 12 side of the first region S1 in plan view. A manufacturing error may occur at the position of the peripheral edge 48 of the light emitting functional layer 46. When a film forming technique such as a printing technique with relatively low manufacturing accuracy is employed for forming the light emitting functional layer 46, the error in the position of the peripheral edge 48 becomes particularly significant. The second region S2 is a region (manufacturing margin) secured so as to include an error range of the position of the peripheral edge 48. Specifically, the width of the second region S2 is set to about twice the width of the first region S1 (for example, 0.6 mm), and is preferably 1 to 3 times that of the first region S1.

  The peripheral edge 48 of the light emitting functional layer 46 overlaps with the second conductor 58 as shown in part (B) to part (D) of FIG. Specifically, the entire periphery of the peripheral edge 48 overlaps the second conductor 58 having a rectangular frame shape in plan view. In a configuration in which a part of the peripheral edge 48 of the light emitting functional layer 46 overlaps the second conductor 58 and the other part does not overlap the second conductor 58, the step reflecting the film thickness of the second conductor 58 is a light emitting function. It may appear on the surface of layer 46. In the present embodiment, since the entire circumference of the peripheral edge 48 overlaps with a single member (second conductor 58), there is an advantage that the step on the surface of the light emitting functional layer 46 is reduced.

  On the surface of the optical path adjustment layer 60 on which the light emitting functional layer 46 is formed, the second electrode E2 is formed over the entire display region 12. The second electrode E2 is electrically connected to the first conductor 63 through the conduction hole HG1 of the pixel defining layer 65 as shown in part (D) of FIG. As shown in FIG. 13, the conduction hole HG1 is a through-hole obtained by removing a rectangular frame-shaped region surrounding the display region 12 in the pixel definition layer 65 in plan view, and is in the first region S1 of the peripheral region 14. To position. The second electrode E2 is electrically connected to the first conductor 63 over the entire circumference of the peripheral region 14 through the conduction hole HG1. The conduction hole HG1 is located closer to the display area 12 than the conduction hole HF1.

  As understood from FIGS. 3 and 11, the second power source conductor 42 and the second conductor 58 are connected via the conduction hole HE1, and the second conductor 58 and the first conductor 63 are connected to the conduction hole HF1. The first conductor 63 and the second electrode E2 are connected via the conduction hole HG1. Therefore, the lower power supply potential (second potential) VCT supplied to the second power supply conductor 42 is supplied to the second electrode E2 via the second conductor 58 and the first conductor 63. Further, each conduction hole (HE1, HF1, HG1) used for connection between the second power supply conductor 42 and the second electrode E2 is formed in the first region S1 having a rectangular frame shape in plan view. In other words, as shown in FIG. 11, a region surrounded by the outer peripheral edge of the conduction hole HE1 and the inner peripheral edge of the conduction hole HG1 in plan view is defined as the first region S1. The wiring formed in the peripheral region 14 and connected to the second electrode E2 is referred to as “peripheral wiring D” in the following description. The peripheral wiring D of the first embodiment includes a second power supply conductor 42, a second conductor 58, and a first conductor 63, as illustrated in FIG.

  As illustrated in FIG. 3, a region (light emitting region) sandwiched between the first electrode E1 and the second electrode E2 inside each opening 65A of the pixel defining layer 65 in the light emitting functional layer 46 emits light. That is, a portion where the first electrode E1, the light emitting functional layer 46, and the second electrode E2 are stacked inside the opening 65A functions as the light emitting element 45. As understood from the above description, the pixel definition layer 65 defines the planar shape and size (area where light is actually emitted) of the light emitting element 45 of each pixel P. The light emitting device 100 of the first embodiment is a micro display in which the light emitting elements 45 are arranged with very high definition. For example, the area of one light emitting element 45 (the area of one opening 65A) is set to 40 μm 2 or less, and the interval between the light emitting elements 45 adjacent to each other in the X direction is set to 1.5 μm or less.

  The second electrode E2 functions as a semi-transmissive reflective layer having a property of transmitting part of the light reaching the surface and reflecting the rest (semi-transmissive reflective). For example, the transflective second electrode E2 is formed by forming a light-reflective conductive material such as an alloy containing silver or magnesium in a sufficiently thin film thickness. The radiated light from the light emitting functional layer 46 reciprocates between the first power supply conductor 41 and the second electrode E2, and a specific resonance wavelength component is selectively amplified and then transmitted through the second electrode E2. To the observation side (the side opposite to the substrate 10). That is, a resonance structure is formed that resonates the light emitted from the light emitting functional layer 46 between the first power supply conductor 41 functioning as a reflective layer and the second electrode E2 functioning as a semi-transmissive reflective layer.

  As described above, the conduction hole HG1 for conduction between the second electrode E2 and the first conductor 63 is formed in the first region S1 and emits light in the second region S2 located closer to the display region 12 than the first region S1. The peripheral edge 48 of the functional layer 46 is located. Therefore, as shown in FIGS. 3 and 11, the light emitting functional layer 46 and the conduction hole HG1 do not overlap each other in plan view.

  FIG. 14 is an explanatory diagram of a configuration in which the conduction hole HG1 and the light emitting functional layer 46 overlap in plan view (hereinafter referred to as “Comparison 2”). In contrast 2, the light emitting functional layer 46 is interposed between the second electrode E2 and the first conductor 63 in the region U in the conduction hole HG1. Therefore, in contrast 2, the conduction between the second electrode E2 and the first conductor 63 may be insufficient. As described above, a manufacturing error may occur at the position of the peripheral edge 48 of the light emitting functional layer 46. When the region U is enlarged due to a manufacturing error (when the contact area between the second electrode E2 and the first conductor 63 is reduced), the conduction between the second electrode E2 and the first conductor 63 is insufficient. Is particularly evident. On the other hand, in the first embodiment, since the light emitting functional layer 46 and the conduction hole HG1 do not overlap, the light emitting functional layer 46 and the first conductor 63 do not contact each other. Therefore, the light emitting functional layer 46 and the first conductor 63 are sufficiently connected via the conduction hole HG1.

  As described above, the conduction hole HG1 is located on the display area 12 side from the conduction hole HF1 in a plan view, and the conduction hole HF1 is located on the display area 12 side from the conduction hole HE1. That is, as shown in FIGS. 11 and 13, the conduction hole HE1, the conduction hole HF1, and the conduction hole HG1 are formed at positions shifted from each other in plan view. Part (A) of FIG. 15 is an enlarged cross-sectional view of the conduction hole HG1 and the conduction hole HF1 according to the present embodiment. On the other hand, the part (B) of FIG. 15 illustrates a configuration in which the conduction hole HG1 and the conduction hole HF1 overlap in plan view (hereinafter referred to as “comparative 3”). As shown in part (B) of FIG. 15, when the conduction hole HG1 and the conduction hole HF1 overlap in plan view, the surface of the second electrode E2 located outside the conduction hole HG1 and the conduction hole HG1. A step R having a height corresponding to the sum of the film thickness of the optical path adjusting layer 60 and the film thickness of the pixel defining layer 65 occurs between the surface of the region that has entered inside. Therefore, a step (unevenness) reflecting the step R on the surface of the second electrode E2 can occur in each layer covering the second electrode E2. On the other hand, in the first embodiment, as shown in the part (A) of FIG. 15, the conduction hole HG1 and the conduction hole HF1 do not overlap in plan view. Therefore, there is an advantage that the step on the surface of the second electrode E2 is reduced as compared with the comparative 3. Similarly, in the present embodiment, since the conduction hole HE1 and the conduction hole HF1 are formed at positions shifted in plan view, this corresponds to the sum of the film thickness of the pixel definition layer 65 and the film thickness of the insulating layer LE. No steps are generated. Therefore, the step on the surface of the first conductor 63 can be reduced.

  Considering only the conduction between the second electrode E2 and the second power supply conductor 42, it is sufficient that the second power supply conductor 42 exists only in the first region S1. However, in the first embodiment, as shown in the part (D) of FIG. 11, in addition to the first region S1, the second region S2 is provided so as to cover the second region S2 secured as the manufacturing margin of the light emitting functional layer 46. A power supply conductor 42 is formed. According to the above configuration, the second power supply conductor 42 has a sufficient area as compared with the configuration in which the second power supply conductor 42 is formed only in the first region S1. There is an advantage in that the resistance is reduced. Since the voltage drop in the second power supply conductor 42 is suppressed by the reduction in resistance, the potential VCT supplied to each pixel P in the display region 12 is made uniform, and display spots due to the error in the potential VCT are reduced. There is an advantage of being.

  As illustrated in FIG. 3, a sealing body 70 is formed on the entire surface of the substrate 10 on the surface of the second electrode E2. In FIG. 4, the sealing body 70 is not shown for convenience. The sealing body 70 is a light-transmitting film body that seals each element formed on the substrate 10 to prevent intrusion of outside air and moisture, and includes a first sealing layer 71 and a second sealing layer. 72 and a third sealing layer 73. A first sealing layer 71 is formed on the surface of the third sealing layer 73, and a second sealing layer 72 is formed on the surfaces of the first sealing layer 71 and the third sealing layer 73.

  The third sealing layer 73 of the sealing body 70 is formed on the surface of the second electrode E2, and directly contacts the surface of the second electrode E2. As understood from FIG. 3, the third sealing layer 73 is formed over the entire area of the substrate 10 including the display region 12 and the peripheral region 14. The third sealing layer 73 is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide), for example, with a film thickness of about 200 nm to 400 nm. The third sealing layer 73 is suitably formed to have a film thickness that is greater than or equal to the film thickness difference (for example, 120 nm) of the optical path adjustment layer 60. For the formation of the third sealing layer 73, a high-density plasma film forming technique such as a plasma CVD (Chemical Vapor Deposition) method, an ECR (Electron Cyclotron Resonance) plasma sputtering method, or an ion plating method is preferably used. It is also possible to form the third sealing layer 73 of silicon oxynitride by depositing silicon oxide in a nitrogen atmosphere. An inorganic oxide typified by a metal oxide such as titanium oxide can also be employed as the material for the third sealing layer 73.

  The 1st sealing layer 71 is an element which seals the light emitting element 45, and is comprised including the sealing surface 82 and the side end surface 84 as shown in FIG. The sealing surface 82 is a surface that overlaps the light emitting element 45 among the upper surface of the first sealing layer 71 (the surface opposite to the contact surface with the third sealing layer 73). The side end surface 84 is a surface continuous with the sealing surface 82 and is located outside the sealing surface 82 in a plan view and is inclined with respect to the sealing surface 82. The side end surface 84 includes an upper peripheral edge 86 on the sealing surface 82 side and a lower peripheral edge 88 on the substrate 10 side, and is formed so that the film thickness becomes smaller as it is closer to the lower peripheral edge 88. The lower peripheral edge 88 of the first sealing layer 71 is a third region on the peripheral side (opposite to the display region 12) of the substrate 10 in the first region S1 in plan view as shown in the part (D) of FIG. Located in S3. The third region S3 is a rectangular frame region having a predetermined width. A manufacturing error may occur at the position of the lower peripheral edge 88 of the first sealing layer 71. When a film forming technique such as a printing technique with relatively low manufacturing accuracy is employed for forming the first sealing layer 71, the error in the position of the lower peripheral edge 88 becomes particularly significant. The third region S3 is a region (manufacturing margin) secured so as to include an error range of the position of the lower peripheral edge 88. Specifically, the width of the third region S3 is set to about twice the width of the first region S1 (for example, 0.6 mm), and is preferably 1 to 3 times that of the first region S1.

  As shown in part (B) to part (D) of FIG. 11, the lower peripheral edge 88 overlaps the second conductor 58. Specifically, like the peripheral edge 48 of the light emitting functional layer 46, the lower peripheral edge 88 overlaps the second conductor 58 having a rectangular frame shape in plan view. Therefore, in the same manner as described above with respect to the light emitting functional layer 46, the lower peripheral edge 88 partially overlaps the second conductor 58, and the other part does not overlap the second conductor 58. It is possible to reduce a step on the surface of the one sealing layer 71 (lower peripheral edge 88).

  As described above, considering only the conduction between the second electrode E2 and the second power supply conductor 42, it is sufficient that the second power supply conductor 42 exists only in the first region S1. However, in the first embodiment, as shown in the part (D) of FIG. 11, in addition to the first region S1, the third region S3 secured as the manufacturing margin of the first sealing layer 71 is also covered. A second power supply conductor 42 is formed. According to the above configuration, the second power supply conductor 42 has a sufficient area as compared with the configuration in which the second power supply conductor 42 is formed only in the first region S1. There is an advantage in that the resistance is reduced. Since the voltage drop in the second power supply conductor 42 is suppressed by the reduction in resistance, the potential VCT supplied to each pixel P in the display region 12 is made uniform, and display spots due to the error in the potential VCT are reduced. There is an advantage of being.

  The first sealing layer 71 functions as a planarizing film that fills the steps on the surfaces of the second electrode E2 and the third sealing layer 73. That is, a step reflecting the shape of each element below (substrate 10 side) is formed on the surface of the second electrode E2 or the third sealing layer 73, but the sealing surface 82 of the first sealing layer 71 is , A substantially flat surface in which the level difference is sufficiently reduced. In other words, the sealing surface 82 of the first sealing layer 71 is flat compared to the lower surface (that is, the contact surface with the third sealing layer 73). For example, the first sealing layer 71 covers each conduction hole (HE1, HF1, HG1) formed in the first region S1, and on the surface of the first region S1 due to the conduction hole (second electrode E2 or The step generated in the third sealing layer 73) is flattened. The first sealing layer 71 has a sufficiently thick film thickness (for example, 1 μm to 5 μm, for example) compared to the second sealing layer 72 and the third sealing layer 73 so that the planarization function described above is realized. And particularly preferably 3 μm). The first sealing layer 71 is a heat treatment by applying a solution of a light transmissive organic material such as an epoxy resin to the surface of the second sealing layer 72 by a known coating technique (for example, a printing method or a spin coating method). It is formed by the process of hardening with. Note that the material of the first sealing layer 71 is not limited to an organic material. For example, the first sealing layer 71 having a film thickness sufficient for planarization can be formed by applying an inorganic material such as silicon oxide by a coating technique such as a printing method and drying it. The first sealing layer 71 is continuous over a wide area as compared with the area where the light emitting functional layer 46 is formed, and is formed so as to cover at least the light emitting functional layer 46. A configuration in which the first sealing layer 71 covers the second electrode E2 may also be employed.

  As understood from FIG. 3, the second sealing layer 72 is formed over the entire area of the substrate 10 including the display region 12 and the peripheral region 14. The second sealing layer 72 is formed of an inorganic material having excellent water resistance and heat resistance, for example, and has a thickness of about 300 nm to 700 nm (particularly preferably about 400 nm). For example, a nitrogen compound (silicon nitride, silicon oxide, silicon oxynitride) is suitable as the material of the third sealing layer 73. For the formation of the second sealing layer 72, a known film formation technique exemplified for the third sealing layer 73 is arbitrarily employed. The above is the specific configuration of the sealing body 70.

  A filter layer 90 is formed on the surface of the sealing body 70 (second sealing layer 72). Here, in FIG. 16, the filter layer 90 is laminated | stacked on the surface of the sealing body 70 (2nd sealing layer 72). 16 is a cross-sectional view of the sealing body 70 and the filter layer 90 (the insulating layer 92, the color filter 94, and the protection part 96), and FIG. 17 is a plan view. In FIG. 17, a part of the filter layer 90 (protection part 96) is illustrated by a solid line, and the other part of the outer shape is represented by a chain line. 3 and 4, the filter layer 90 is omitted for convenience.

  The filter layer 90 includes an insulating layer 92, a plurality of color filters 94, and a protection unit 96. The insulating layer 92 is an insulating member formed on the surface of the second sealing layer 72 and is formed over the entire area of the substrate 10. As shown in FIG. 16, an opening (first opening) 92A is formed for each pixel P in the insulating layer 92 in the display region 12, and an opening (second opening) 92B is formed in the insulating layer 92 in the peripheral region 14. Is formed. The opening 92B is formed in a rectangular frame-like region surrounding the display region 12 in plan view as shown in FIG.

  The color filter 94 and the protection unit 96 are formed from a colored layer K (KR, KG, KB) that transmits light of a specific wavelength. Specifically, each color filter 94 and the protection unit 96 of the first embodiment are configured by a plurality of colored layers K (KR, KG, KB) that transmit light having different wavelengths. The first colored layer KR transmits red light having a wavelength of about 610 nm, the second colored layer KG transmits green light having a wavelength of about 550 nm, and the third colored layer KB has blue light having a wavelength of about 470 nm. Permeate.

  The filter layer 90 of the first embodiment includes a plurality of color filters 94 (94R, 94G, 94B) that transmit monochromatic light having different wavelengths. The first color filter 94R is formed from the first colored layer KR. Similarly, the second color filter 94G is formed from the second colored layer KG, and the third color filter 94B is formed from the third colored layer KB. Each color filter 94 is arranged inside the opening 92A formed for each pixel P in the insulating layer 92 and overlaps the light emitting element 45 of each pixel P in plan view. Specifically, the first color filter 94R overlaps the light emitting element 45 of the red pixel P (the pixel P whose resonance wavelength is set to the wavelength of red light), and the second light emitting element 45 of the green pixel P has the second color. The color filter 94G overlaps, and the third color filter 94B overlaps the light emitting element 45 of the blue pixel P. As understood from FIG. 16, the insulating layer 92 functions as a partition wall of each color filter 94. Light emitted from each light emitting element 45 is colored by a color filter 94 overlapping the light emitting element 45 and then emitted to the outside of the light emitting device 100 to be visually recognized by an observer. Although FIG. 17 illustrates a stripe arrangement in which a plurality of pixels P of the same color are arranged in the Y direction, the arrangement of the pixels P of each display color is arbitrary.

  The protection unit 96 is an element that improves the sealing performance of the sealing body 70. As shown in FIGS. 16 and 17, the protection part 96 is formed in a rectangular frame shape in the peripheral region 14 so as to surround the display region 12 over the entire periphery in plan view. Therefore, the display area 12 is located inside the protection part 96 and the mounting area 16 is located outside the protection part 96. That is, the protection unit 96 exists between the display area 12 and the mounting area 16.

  The protection part 96 overlaps the lower peripheral edge 88 located on the substrate 10 side in the side end face 84 of the first sealing layer 71 in a plan view. In the configuration in which the surface of the sealing body 70 is exposed in the peripheral region 14, a boundary portion (lower peripheral edge 88) between the first sealing layer 71 and the lower ground (third sealing layer 73) of the first sealing layer 71. ) May reach the light emitting element 45 by moisture or outside air. In the present embodiment, since the protective portion 96 overlaps the lower peripheral edge 88 of the first sealing layer 71, moisture and outside air can be prevented from entering from the peripheral edge of the first sealing layer 71. That is, the sealing performance by the first sealing layer 71 can be improved.

  As understood from FIG. 16, the portion of the second sealing layer 72 that overlaps the upper peripheral edge 86 (hereinafter referred to as “corner portion”) is located on the surface of the sealing surface 82 of the second sealing layer 72. There is a problem that it is more susceptible to external force than a flat part and is easily damaged. The protection part 96 (first layer 96R) of this embodiment overlaps the upper peripheral edge 86 of the first sealing layer 71 on the surface of the second sealing layer 72 (that is, covers the corners of the second sealing layer 72). ). That is, the corner portion of the second sealing layer 72 that is easily damaged is protected by the protection portion 96. Therefore, there is an advantage that the possibility that the corner portion of the second sealing layer 72 is damaged is reduced (invasion of outside air and moisture from the damaged portion of the second sealing layer 72 is prevented).

  As shown in FIG. 16, the protection unit 96 of the first embodiment is configured by stacking a first layer 96R, a second layer 96G, and a third layer 96B. The first layer 96R is formed on the second sealing layer 72. The second layer 96G is formed over the first layer 96R, and the third layer 96B is formed over the second layer 96G. The first layer 96R is formed from the first colored layer KR. Similarly, the second layer 96G is formed from the second colored layer KG, and the third layer 96B is formed from the third colored layer KB.

  As described above, the first color filter 94R and the first layer 96R of the protection portion 96 are formed from the same layer (first colored layer KR). Similarly, the second color filter 94G and the second layer 96G are formed from the same layer (second colored layer KG), and the third color filter 94B and the third layer 96B are formed from the same layer (third colored layer KB). It is formed. According to the above configuration, the protection part 96 can be formed in the process of forming the color filter 94 of each color. That is, it is not necessary to execute the process of forming the protection unit 96 separately from the formation of the color filter 94. Therefore, there is an advantage that the manufacturing process of the light emitting device is simplified as compared with the configuration in which the protection unit 96 and the color filter 94 are separately formed.

  As shown in FIG. 16, the protection unit 96 overlaps the peripheral wiring D (second power supply conductor 42, second conductor 58, and first conductor 63) in the peripheral region 14 in plan view. FIG. 16 illustrates a configuration in which the protection unit 96 overlaps a part of the peripheral wiring D (the entire second power supply conductor 42 and the first conductor 63 and a part of the second conductor 58). When external light enters the peripheral region 14, the external light may be reflected by the peripheral wiring D and perceived by the observer. In the first embodiment, since the peripheral wiring D and the protection part 96 overlap in plan view, the light traveling from the observation side toward the peripheral wiring D and the reflected light on the surface of the peripheral wiring D are shielded by the protection part 96. Therefore, there is an advantage that the reflected light (reflection of the object on the observation side) on the surface of the peripheral wiring D is hardly perceived by the observer. In the first embodiment, in particular, since the protective portion 96 is formed by stacking the red first layer 96R, the green second layer 96G, and the blue third layer 96B, for example, the protective portion 96 may be a single layer or two layers. Compared to the configuration in which the protective layer 96 is formed, it is possible to impart sufficient light shielding performance to the protection portion 96. However, it is also possible to form the protection part 96 with a single layer or two layers.

  As illustrated in FIG. 16, the sealing substrate 20 is bonded to the surface of the filter layer 90 via the adhesive layer 21. The sealing substrate 20 is a light-transmitting plate member made of, for example, glass or quartz. The adhesive layer 21 is formed by curing an adhesive applied to the surface of the filter layer 90. A spin coat method is suitably employed for applying the adhesive. Specifically, the adhesive before curing is dropped on the substrate 10 (filter layer 90), and the substrate 10 is rotated to cause the adhesive to flow, so that the surface of the filter layer 90 (insulating layer 92, third layer 96B). , Uniformly applied to the entire surface of each color filter 94). If a step is formed on the surface of the filter layer 90, the flow of the adhesive on the surface of the filter layer 90 is hindered by this step, and the adhesive is not uniformly applied, and film formation failure of the adhesive layer 21 may occur. . In particular, film formation defects are more likely to occur as the level difference formed on the surface of the filter layer 90 increases. FIG. 18 is an explanatory diagram of a configuration in which a protective portion 96 is formed on the surface of the insulating layer 92 without forming the opening 92B in the insulating layer 92 (hereinafter referred to as “comparative 4”). In the comparative example 4, since the protective part 96 is formed on the surface of the insulating layer 92, the film thickness of the protective part 96 (the first layer 96R, the second layer 96G, the third layer 96B, and the like is formed on the surface of the filter layer 90. Level difference in accordance with the sum of the film thicknesses of the two. On the other hand, in the present embodiment, as shown in FIG. 16, the protective part 96 is located inside the opening 92B formed in the insulating layer 92 (on the surface of the second sealing layer 72 below the insulating layer 92). It is formed. Therefore, in the present embodiment, the step generated on the surface of the filter layer 90 has a size obtained by subtracting the film thickness of the insulating layer 92 from the film thickness of the protective part 96. That is, the step formed on the surface of the filter layer 90 is reduced as compared with the comparative 4 and the film formation failure of the adhesive layer 21 is reduced.

Second Embodiment
A second embodiment of the present invention will be described. In addition, about the element which an effect | action and function are the same as that of 1st Embodiment in each form illustrated below, the reference | standard referred by description of 1st Embodiment is diverted, and each detailed description is abbreviate | omitted suitably.

  FIG. 19 is an explanatory diagram of the filter layer 90 formed on the surface of the sealing body 70 of the second embodiment. As illustrated in FIG. 19, the opening 92 </ b> B described in the first embodiment is not formed in the insulating layer 92 of the second embodiment. The protection unit 96 according to the second embodiment is different from the first embodiment in the positional relationship of the peripheral edges of the respective layers (first layer 96R, second layer 96G, and third layer 96B). In the first embodiment, the peripheral edges of the layers of the protection unit 96 overlap in plan view (that is, the side surfaces of the layers are flush with each other), whereas in the second embodiment, the planar positions of the peripheral edges of the layers are flat. It is different visually.

  Specifically, as shown in FIG. 19, the inner periphery of the first layer 96R is positioned on the display region 12 side by a distance L1 from the inner periphery of the second layer 96G, and the outer periphery of the first layer 96R is It is located on the peripheral side of the substrate 10 (the side opposite to the display area 12) by a distance L3 from the outer peripheral edge of the two layers 96G. That is, the second layer 96G is formed in a smaller area than the first layer 96 so as to be included in a plan view within a range in which the first layer 96R immediately below is formed. Similarly, the inner peripheral edge of the second layer 96G is positioned on the display region 12 side by a distance L2 from the inner peripheral edge of the third layer 96B, and the outer peripheral edge of the second layer 96G is a distance L4 from the outer peripheral edge of the third layer 96B. Only on the peripheral side of the substrate 10. Therefore, the inner peripheral side surface and the outer peripheral side surface of the protection portion 96 are formed in a stepped shape with steps corresponding to the film thickness of each layer. The distance L1 to the distance L4 are set to an appropriate size, but it is preferable that the distance L1 to the thickness of the third layer 96B is greater than the thickness of the first layer 96R. For example, the distance L1 to the distance L4 can be formed to be about 5 μm with respect to the first layer 96R to the third layer 96B having a thickness of about 1 μm.

  In the second embodiment, the same effect as in the first embodiment is realized. In addition, for example, in the configuration in which the protective portion 96 having the side surfaces of the first layer 96R to the third layer 96B flush with each other is formed on the surface of the insulating layer 92 (for example, in contrast 4 shown in FIG. 18), A step corresponding to the sum of the film thicknesses of the layers (first layer 96R, second layer 96G, and third layer 96B) of the portion 96 occurs on the surface of the filter layer 90. In the second embodiment, as understood from FIG. 19, the level difference of one step on the surface of the filter layer 90 corresponds to the film thickness of each layer (96R, 96G, 96B) constituting the protection unit 96, It is smaller than the sum of the film thicknesses of the respective layers of the portion 96. As described above, according to the second embodiment, the surface of the filter layer 90 (insulating layer 92, first layer 96R, second layer 96G, third layer 96B, each color filter 94 is formed by forming the protective portion 96. Each step generated on the surface) (a step that can hinder the flow of the dropped adhesive) is smaller than that in the comparative example 4. Therefore, according to the present embodiment, when the adhesive is applied to the surface of the filter layer 90 by the spin coat method, the possibility that the flow of the adhesive is hindered by the step of the filter layer 90 is reduced. Film formation defects of the adhesive layer 21 are reduced.

<Modification>
The form illustrated above can be variously modified. Specific modifications are exemplified below. Two or more aspects arbitrarily selected from the following examples can be appropriately combined.

(1) From the viewpoint of reducing the level difference on the surface of the filter layer 90, as shown in FIG. 20, a protective portion 96 having the same thickness as that of the insulating layer 92 is provided on the opening 92 B formed in the insulating layer 92. You may form inside. According to the above configuration, as shown in FIG. 20, the surface of the insulating layer 92 and the surface of the protection portion 96 are located in substantially the same plane, so that the effect of reducing the step on the surface of the filter layer 90 is exceptional. It is remarkable.

  By the way, when the spin coat method is employed for forming the adhesive layer 21, there is a possibility that the adhesive dropped in the display area 12 flows and reaches the mounting area 16 from the display area 12 or the peripheral area 14. When the adhesive reaches the mounting region 16 and adheres to the surface of each mounting terminal 36, the mounting terminal 36 and the terminal of the external circuit may not be sufficiently conducted. In the first embodiment, the protection part 96 is located between the display area 12 and the mounting area 16, and a step corresponding to the film thickness of the protection part 96 appears on the surface of the filter layer 90. With the above configuration, since the flow of the adhesive with respect to the mounting region 16 is blocked by the level difference of the protective portion 96, it is possible to prevent a conduction failure between the mounting terminal 36 and the terminal of the external circuit due to the adhesion of the adhesive. Play.

(2) In each form mentioned above, the protection part 96 illustrated the structure which covers the side end surface 84 of the 1st sealing layer 71, and others, but the positional relationship of the 1st sealing layer 71 and the protection part 96 is the above-mentioned illustration. It is not limited to. For example, a configuration in which the protective portion 96 is formed in a region on the peripheral side (the side opposite to the display region 12) of the substrate 10 as viewed from the peripheral edge (lower peripheral edge 88) of the first sealing layer 71 (that is, the protective portion 96 is viewed in plan And a configuration that does not overlap the first sealing layer 71 is also employed. In addition, a configuration in which the protective portion 96 is formed on the sealing surface 82 of the first sealing layer 71 (a configuration in which the protective portion 96 is located in a region on the display region 12 side as viewed from the upper peripheral edge 86 of the first sealing layer 71). Is also adopted. As understood from the above description, whether or not the protective portion 96 overlaps the first sealing layer 71 (the side end face 84 of the first sealing layer 71) in a plan view is unquestioned in the present invention.

(3) Each element in the above embodiments can be omitted as appropriate. For example, in each of the above-described embodiments, the filter layer 90 includes the insulating layer 92, but the insulating layer 92 can be omitted from the filter layer 90. Moreover, although the sealing body 70 was comprised including the 1st sealing layer 71, the 2nd sealing layer 72, and the 3rd sealing layer 73, each layer is abbreviate | omitted suitably. For example, when the second sealing layer 72 is omitted, the protective part 96 is directly formed on the surface of the first sealing layer 71. In addition, the protection unit 96 includes three layers of the first layer 96R, the second layer 96G, and the third layer 96B. For example, any one or two layers of the first layer 96R to the third layer 96B are used. You may comprise.

(4) In each of the above embodiments, the protective part 96 that overlaps both the side end face 84 and the peripheral wiring D of the first sealing layer 71 is exemplified, but the protective part 96 is provided on either the side end face 84 or the peripheral wiring D. It is also possible to adopt a configuration in which these are stacked.

(5) In each of the embodiments described above, the protective part 96 is formed so as to overlap the periphery of the first sealing layer 71, but the protective part 96 may be formed so as to overlap the peripheral edge 48 of the light emitting functional layer 46. In the above configuration, as in the first embodiment, the entry of moisture and outside air into the gap between the peripheral edge 48 and the base layer is reduced.

(6) In each of the above embodiments, the protective part 96 is formed so as to overlap the entire periphery of the lower peripheral edge 88, but the protective part 96 may be overlapped on a part of the lower peripheral edge 88. Similarly, the protection part 96 may be overlapped with a part of the upper peripheral edge 86. In each of the above embodiments, the protection unit 96 is configured to overlap a part of the peripheral wiring D. However, a configuration in which the protection unit 96 is overlapped with the entire area of the peripheral wiring D in plan view may be employed.

(7) In each of the above embodiments, the protective part 96 is overlapped on both the upper peripheral edge 86 and the lower peripheral edge 88 of the first sealing layer 71. It may be superimposed on either side.

(8) The type of the colored layer K of the filter layer 90 is not limited to the examples in the above-described embodiments. For example, in addition to the first colored layer KR that transmits red light, the second colored layer KG that transmits green light, and the third colored layer KB that transmits blue light, the filter layer 90 has a wavelength of about You may comprise including the 4th colored layer which permeate | transmits 580 nm yellow light. In the above configuration, the pixel P whose display color is yellow is formed in the display region 12, and the fourth color filter that overlaps the light emitting element 45 of the pixel P and the fourth layer that overlaps the third layer 96B of the protection unit 96 are provided. The fourth colored layer is used to form the same layer.

(9) In each of the above-described embodiments, the light emitting element 45 using the organic EL material is exemplified. However, the present invention similarly applies to a configuration using a light emitting element in which a light emitting layer is formed of an inorganic EL material or a light emitting element such as an LED. Applied. Further, in each of the above-described embodiments, the top emission type light emitting device 100 that emits light to the side opposite to the substrate 10 is illustrated, but the present invention also applies to a bottom emission type light emitting device that emits light to the substrate 10 side. The same applies.

<Electronic equipment>
The light emitting device 100 exemplified in each of the above embodiments is suitably used as a display device for various electronic devices. FIG. 21 illustrates a head-mounted display device 1 (HMD: Head Mounted Display) using the light-emitting device 100 exemplified in each of the above-described embodiments as an electronic device.

  The display device 1 is an electronic device that can be worn on the user's head, and includes a transmission part (lens) 2L that overlaps the user's left eye, a transmission part 2R that overlaps the user's right eye, and a left-eye display. The light emitting device 100L and the half mirror 4L, and the right eye light emitting device 100R and the half mirror 4R are provided. The light emitting device 100L and the light emitting device 100R are arranged so that the emitted light travels in opposite directions. The half mirror 4L for the left eye transmits the transmitted light of the transmission part 2L to the left eye side of the user and reflects the emitted light from the light emitting device 100L to the left eye side of the user. Similarly, the right-eye half mirror 4R transmits the light transmitted through the transmissive portion 2R to the right eye side of the user and reflects the light emitted from the light emitting device 100R to the right eye side of the user. Therefore, the user perceives an image obtained by superimposing an image observed through the transmission unit 2L and the transmission unit 2R and a display image by each light emitting device 100. In addition, the stereoscopic image (the image for the left eye and the image for the right eye) with parallax added to each other is displayed on the light emitting device 100L and the light emitting device 100R, thereby allowing the user to perceive the stereoscopic effect of the display image. Is possible.

  Note that an electronic device to which the light emitting device 100 of each embodiment described above is applied is not limited to the display device 1 in FIG. For example, the light emitting device 100 of the present invention is also preferably used in an electronic view finder (EVF) used in an imaging device such as a video camera or a still camera. In addition, the light emitting device of the present invention can be used in various electronic devices such as mobile phones, personal digital assistants (smartphones), monitors such as televisions and personal computers, and car navigation devices.

DESCRIPTION OF SYMBOLS 10 ... Board | substrate, 100 ... Light-emitting device, 12 ... Display area, 14 ... Peripheral area, 16 ... Mounting area, 22 ... Scan line, 24 ... Control line, 26 ... Signal line, 30 ... Drive circuit 32... Scanning line drive circuit 34... Signal line drive circuit 36... Mounting terminal 41... First power supply conductor 42. E2 ... second electrode, 45 ... light emitting element, 46 ... light emitting functional layer, 48 ... peripheral edge, 58 ... second conductor, 60 ... optical path adjusting layer, 63 ... first conductor, 65 ... ... pixel definition layer, 70 ... sealing body, 71 ... first sealing layer, 82 ... sealing face, 84 ... side end face, 86 ... upper peripheral edge, 88 ... lower peripheral edge, 72 ... Second sealing layer 73... Third sealing layer 90... Filter layer 92. Insulating layer 94 R, 94 G, 94 B Color filter 96 96R... First layer 96G... Second layer 96B... Third layer 20... Sealing substrate 21. Adhesive layer C. Capacitance element D D. Peripheral wiring TDR. ... Drive transistor, TEL ... Light emission control transistor, TSL ... Select transistor, Q (QA1, QA2, QA3, QA4, QB1, QB2, QD1, QE1) ... Relay electrode, 1 ... Display device, 2L ... Transmission Part, 2R ... transmission part, 4L ... half mirror, 4R ... half mirror.

As illustrated in FIG. 16, the sealing substrate 20 is bonded to the surface of the filter layer 90 via the adhesive layer 21. The sealing substrate 20 is a light-transmitting plate member made of, for example, glass or quartz. The adhesive layer 21 is formed by curing an adhesive applied to the surface of the filter layer 90. A spin coat method is suitably employed for applying the adhesive. Specifically, the adhesive before curing is dropped on the substrate 10 (filter layer 90), and the substrate 10 is rotated to cause the adhesive to flow, so that the surface of the filter layer 90 (insulating layer 92, third layer 96B). , Uniformly applied to the entire surface of each color filter 94). If a step is formed on the surface of the filter layer 90, the flow of the adhesive on the surface of the filter layer 90 is hindered by this step, and the adhesive is not uniformly applied, and film formation failure of the adhesive layer 21 may occur. . In particular, film formation defects are more likely to occur as the level difference formed on the surface of the filter layer 90 increases. FIG. 18 is an explanatory diagram of a configuration in which a protective portion 96 is formed on the surface of the insulating layer 92 without forming the opening 92B in the insulating layer 92 (hereinafter referred to as “ Example A ”). In Example A , since the protective portion 96 is formed on the surface of the insulating layer 92, the thickness of the protective portion 96 (the first layer 96R, the second layer 96G, the third layer 96B, and the like) is formed on the surface of the filter layer 90. Level difference in accordance with the sum of the film thicknesses of the two. On the other hand, in the present embodiment, as shown in FIG. 16, the protective part 96 is located inside the opening 92B formed in the insulating layer 92 (on the surface of the second sealing layer 72 below the insulating layer 92). It is formed. Therefore, in the present embodiment, the step generated on the surface of the filter layer 90 has a size obtained by subtracting the film thickness of the insulating layer 92 from the film thickness of the protective part 96. That is, the step formed on the surface of the filter layer 90 is reduced as compared with Example A, and the film formation failure of the adhesive layer 21 is reduced.

In the second embodiment, the same effect as in the first embodiment is realized. Further, for example, in the configuration in which the protective portion 96 having the side surfaces of the first layer 96R to the third layer 96B flush with each other is formed on the surface of the insulating layer 92 (for example, the embodiment A shown in FIG. 18), the protection A step corresponding to the sum of the film thicknesses of the layers (first layer 96R, second layer 96G, and third layer 96B) of the portion 96 occurs on the surface of the filter layer 90. In the second embodiment, as understood from FIG. 19, the level difference of one step on the surface of the filter layer 90 corresponds to the film thickness of each layer (96R, 96G, 96B) constituting the protection unit 96, It is smaller than the sum of the film thicknesses of the respective layers of the portion 96. As described above, according to the second embodiment, the surface of the filter layer 90 (insulating layer 92, first layer 96R, second layer 96G, third layer 96B, each color filter 94 is formed by forming the protective portion 96. Each step generated on the surface) (steps that can hinder the flow of the dropped adhesive) is smaller than that in Example A. Therefore, according to the present embodiment, when the adhesive is applied to the surface of the filter layer 90 by the spin coat method, the possibility that the flow of the adhesive is hindered by the step of the filter layer 90 is reduced. Film formation defects of the adhesive layer 21 are reduced.

Claims (7)

A light emitting element that is disposed in the display region and includes a first electrode and a second electrode, and a light emitting functional layer that emits light in response to a current between the first electrode and the second electrode;
Peripheral wiring formed around the display region in plan view and conducting to the second electrode;
A filter layer including a first colored layer that transmits light of a first wavelength, the filter layer including the first colored layer formed on the first colored layer and overlapping the light emitting element, and the first colored layer formed on the first colored layer. And a filter layer including a first layer overlapping the peripheral wiring. The filter layer includes a second colored layer that transmits light having a second wavelength different from the first wavelength, the second color filter formed by the second colored layer and overlapping the light emitting element, and the second color filter. The light emitting device according to claim 1, further comprising: a second layer formed on the surface of the first layer by a colored layer and overlapping the peripheral wiring. The light emitting device according to claim 2, wherein a peripheral edge of the second layer is located inside the peripheral edge of the first layer in a plan view. The filter layer includes a third colored layer that transmits light having a third wavelength different from the first wavelength and the second wavelength, and is formed of the third colored layer and overlaps the light emitting element. The light emitting device according to claim 2, further comprising: a third layer formed on the surface of the second layer by the third colored layer and overlapping the peripheral wiring. The light emitting device according to claim 4, wherein a peripheral edge of the third layer is positioned inside a peripheral edge of the second layer in a plan view. The filter layer includes an insulating layer in which a plurality of first openings in the display region and a second opening overlapping the peripheral wiring are formed,
The first color filter, the second color filter, and the third color filter are formed inside the plurality of first openings,
The light emitting device according to claim 4, wherein the first layer, the second layer, and the third layer are formed inside the second opening. An electronic apparatus comprising the light-emitting device according to claim 1.

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