JP2018074115A - Temporary fixing material for semiconductor and method for manufacturing semiconductor device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to separate a support by a simple process after thermal history in a manufacture of a semiconductor device using the support and a temporary fixing material.SOLUTION: A temporary fixing material for semiconductors 101 includes: a peelable copper foil 10 having a carrier 11 and a copper foil 12 provided on the carrier 11; and thermosetting resin layers 21, 22 provided on the peelable copper foil 10.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a temporary fixing material for a semiconductor used for manufacturing a semiconductor and a method for manufacturing a semiconductor device using the same.

  For the purpose of increasing the density and performance of a semiconductor package, a mounting form in which semiconductor elements having different performances are mounted in one package has been proposed. Along with this, high-density interconnect technology between semiconductor elements, which is excellent in terms of cost, has become important (see, for example, Patent Document 1).

  A package-on-package in which an additional package is further stacked on the package by flip semiconductor element mounting is widely used in smartphones and tablet terminals (see, for example, Non-Patent Document 1 and Non-Patent Document 2). As a form for mounting a semiconductor element at a higher density, a packaging technique using an organic substrate having a high-density wiring, a fan-out type packaging technique (FO-POP) having a through mold via (TMV), silicon or glass A package technology using an interposer, a package technology using a through silicon via (TSV), a package technology using a semiconductor element embedded in a substrate for transmission between semiconductor elements, and the like have been proposed.

  The fan-out type package includes, for example, mounting a semiconductor element on a temporary fixing material laminated on a stainless steel plate as a support, forming a wiring layer after sealing the semiconductor element, and from the support It is produced by a method including peeling a sealing body including a semiconductor element.

  From such a background, a process using a silicon wafer or a glass plate as a support has been proposed. An adhesive as a temporary fixing material for adhering a semiconductor element and a silicon wafer or glass as a support in such a process has also been studied. With respect to this adhesive, it is important that the support can be separated without damaging the semiconductor element after thermal history. For this reason, a technique for improving the releasability by preliminarily releasing the semiconductor element or the support surface is generally adopted. However, due to an increase in the steps of applying and releasing the release component, the release is performed. Processing is one of the causes of increased manufacturing costs (see, for example, Patent Documents 2 and 3).

  In order to ensure the peelability of the pressure-sensitive adhesive after heat history, for example, a technique that utilizes dissolution of the pressure-sensitive adhesive with a solvent, a pressure-sensitive adhesive that decreases by heating, and a pressure-sensitive adhesive that is modified or disappeared by laser irradiation Proposed.

Special table 2012-529770 gazette Japanese Patent No. 4565804 Japanese Patent No. 4936667

Application of Through Mold Via (TMV) as PoP Base Package, Electronic Components and Technology Conference (ECTC), 2008 Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology, ECTC, 2012

  However, since it takes time to dissolve the pressure-sensitive adhesive in the solvent, the productivity tends to decrease. When reducing the adhesiveness of the adhesive by heating, there is a concern about the influence on the semiconductor element due to heating, so that the processes and materials that can be used are limited. Moreover, the adhesive which can be applied to these methods tends to have insufficient heat resistance. On the other hand, introduction of expensive laser equipment is indispensable for the method of modifying or eliminating the adhesive by laser irradiation.

  An object of one aspect of the present invention is to enable separation of a support in a simple process after a thermal history in the manufacture of a semiconductor device using the support and a temporary fixing material.

  One aspect of the present invention is for a semiconductor comprising (A) a peelable copper foil having a carrier and a copper foil provided on the carrier, and (B) a thermosetting resin layer provided on the peelable copper foil. Provide temporary fixing material.

  Another aspect of the present invention provides a method for manufacturing a semiconductor device using the semiconductor temporary fixing material. The manufacturing method according to one aspect includes a step of providing the temporary fixing material for a semiconductor on a support in a direction in which the thermosetting resin layer is in contact with the support, and the opposite side of the support for the temporary fixing material for a semiconductor. A step of mounting a semiconductor element on the surface, a step of forming a sealing resin layer for sealing the semiconductor element on a temporary fixing material for a semiconductor, and a wiring layer connected to the semiconductor element on the sealing resin layer And a step of separating the support from the sealing body having the semiconductor element, the sealing resin layer, and the wiring layer by peeling the carrier of the peelable copper foil and the copper foil.

  The manufacturing method according to another aspect of the present invention includes a step of providing the temporary fixing material for a semiconductor on a support in a direction in which the thermosetting resin layer is in contact with the support, and supporting the temporary fixing material for a semiconductor. Forming a wiring layer on a surface opposite to the body, mounting a semiconductor element connected to the wiring layer on the wiring layer, and forming a sealing resin layer for sealing the semiconductor element on the wiring layer And a step of separating the support from the sealing body having the semiconductor element, the sealing resin layer, and the wiring layer by peeling the carrier of the peelable copper foil and the copper foil.

  By using the temporary fixing material, by utilizing the peelability of the peelable copper foil while ensuring good heat resistance and appropriate adhesion to the support by the thermosetting resin layer in the manufacture of the semiconductor device. The support can be separated by a simple process after a heat history at a high temperature (for example, 260 ° C. or higher).

  According to one aspect of the present invention, in the manufacture of a semiconductor device using a support and a temporary fixing material, the support can be separated by a simple process after thermal history.

It is sectional drawing which shows typically one Embodiment of the heat-resistant temporary fixing material for semiconductors. It is sectional drawing which shows typically one Embodiment of the heat-resistant temporary fixing material for semiconductors. It is process drawing which shows typically one Embodiment of the manufacturing method of a semiconductor device. It is process drawing which shows typically one Embodiment of the manufacturing method of a semiconductor device.

  Hereinafter, several embodiments will be described with reference to the drawings. However, the present invention is not limited to the following embodiments. The same or corresponding parts are denoted by the same reference numerals, and redundant description may be omitted. The positional relationship such as up, down, left and right is based on the positional relationship shown in the drawings unless otherwise specified. The dimensional ratios in the drawings are not limited to the illustrated ratios.

  In this specification, terms such as “left”, “right”, “front”, “back”, “upper”, “lower”, “upper”, “lower”, “first”, “second” are used. If so, they are intended to be illustrative and do not necessarily mean that they are permanently in this relative position. The term “layer” includes a structure formed in a part in addition to a structure formed in the entire surface when observed as a plan view. The term “process” is not only an independent process, but is included in the term if the intended purpose of the process is achieved even if it is not clearly distinguishable from other processes. The numerical range indicated using “to” indicates a range including numerical values described before and after “to” as a minimum value and a maximum value, respectively. In the numerical ranges described stepwise in the present specification, the upper limit value or lower limit value of a numerical range of a certain step may be replaced with the upper limit value or lower limit value of the numerical range of another step.

  FIG.1 and FIG.2 is sectional drawing which shows one Embodiment of a temporary fixing material, respectively. A temporary fixing material 101 (temporary fixing material for a semiconductor) shown in FIG. 1 includes a peelable copper foil 10 and thermosetting resin layers 21 and 22 provided on both surfaces of the peelable copper foil 10. The temporary fixing material 102 (semiconductor temporary fixing material) shown in FIG. 2 has a peelable copper foil 10 and a thermosetting resin layer 21 provided on the surface of the peelable copper foil on the carrier 11 side. The peelable copper foil 10 includes a carrier 11, a copper foil 12 provided on the carrier 11, and a release layer 15 provided between the carrier 11 and the copper foil 12. Here, in this specification, “(semiconductor) temporary fixing material” is formed while fixing a semiconductor element, a wiring layer, and other various members (organic insulating material, conductive material, etc.) on a support. Means a member.

  FIG. 3 is a process diagram showing an embodiment of a method of manufacturing a semiconductor device using the temporary fixing material 101 of FIG. The method shown in FIG. 3 is opposite to the step (a) in which the temporary fixing material 101 is provided on the support 1 in the direction in which the thermosetting resin layer 21 is in contact with the support 1 and the support 1 of the temporary fixing material 101. A step (b) of mounting a plurality of semiconductor elements 3 on the side surface, a step (c) of forming a sealing resin layer 5 for sealing the semiconductor elements 3 on the temporary fixing material 101, and a sealing resin layer 5, forming the wiring layer 7 (rewiring layer) connected to the semiconductor element 3 on the semiconductor element 3, and peeling the carrier 11 and the copper foil 12 of the peelable copper foil 10, thereby sealing the semiconductor element 3. From the process (e) which isolate | separates the support body 1 from the sealing body 31 which has the resin layer 5, the wiring layer 7, and the thermosetting resin layer 22, and the process (f) which isolate | separates the copper foil 12 from the sealing body 31. Mainly composed. The obtained sealing body 31 can be used as a fan-out package with a rewiring layer.

  FIG. 4 is a process diagram showing an embodiment of a method of manufacturing a semiconductor device using the temporary fixing material 102 of FIG. The method shown in FIG. 4 includes a step similar to that shown in FIG. 3A in which the temporary fixing material 102 is provided on the support 1 in a direction in which the thermosetting resin layer 21 is in contact with the support 1. A step (a) of forming a wiring layer 7 (rewiring layer) on the surface opposite to the support 1, and a plurality of semiconductor elements 3 connected to the wiring layer 7 with the underfill 4 interposed therebetween A step (b) of mounting on the wiring layer 7, a step (c) of forming the sealing resin layer 5 for sealing the semiconductor element 3 on the wiring layer 7, and the carrier 11 and the copper foil 12 of the peelable copper foil 10. A step (e) of separating the support 1 from the sealing body 30 having the semiconductor element 3, the sealing resin layer 5 and the wiring layer 7 by peeling, and a step of separating the copper foil 12 from the sealing body 32 ( f). The obtained sealing body 32 can be used as a fan-out package with a rewiring layer.

  The thermosetting resin layers 21 and 22 are resin layers that are cured by heating and increase in elastic modulus. The storage elastic modulus at 25 ° C. of the thermosetting resin layers 21 and 22 after being heated at 180 ° C. for 1 hour is preferably 100 MPa or more from the viewpoint of heat resistance and void suppression, and from the viewpoint of peelability. The pressure is more preferably 500 MPa or more, and further preferably 1 GPa or more from the viewpoint of suppressing the displacement and deformation of the temporarily fixing material in the process.

  The storage elastic modulus at 180 ° C. of the thermosetting resin layers 21 and 22 after being heated at 180 ° C. for 1 hour is preferably 0.1 MPa or more in terms of suppressing voids at the time of thermal history. It is more preferable that it is 1 MPa or more from the point which can suppress position shift at the time of mounting etc., and it is further more preferable that it is 10 MPa or more from the point which can suppress a deformation | transformation of a temporarily fixed material.

  It is preferable that the storage elastic modulus at 260 ° C. of the thermosetting resin layers 21 and 22 after being heated at 180 ° C. for 1 hour is 0.1 MPa or more in terms of suppressing voids at the time of thermal history. It is more preferable that it is 1 MPa or more from the point which can suppress position shift at the time of mounting etc., and it is further more preferable that it is 10 MPa or more from the point which can suppress a deformation | transformation of a temporarily fixed material.

  The storage elastic modulus means a value measured according to the following procedure. The thermosetting resin layer is heated in an oven at 180 ° C. for 1 hour. About a strip-shaped test piece of 5 mm width and 30 mm length cut out from the thermosetting resin layer after heating, using a viscoelasticity analyzer (trade name: RSA-2, manufactured by Rheometrics Co., Ltd.), the heating rate is 5 ° C. / Min, frequency 1 Hz, measurement temperature −50 to 300 ° C., tensile mode dynamic viscoelasticity measurement is performed. From the measurement results, the storage elastic modulus at 25 ° C, 180 ° C or 260 ° C is obtained.

  The 5% weight reduction temperature of the thermosetting resin layers 21 and 22 after being heated at 180 ° C. for 1 hour can suppress blistering and peeling when receiving a thermal history for wiring formation on the temporary fixing material. In view of this, it is preferably 260 ° C. or higher, more preferably 280 ° C. or higher in terms of imparting heat resistance that can withstand the soldering process, and even more preferably 300 ° C. or higher in terms of suppressing minute voids. . The 5% mass reduction temperature refers to a differential thermothermal gravimetric simultaneous measurement device (trade name: TG / DTA6300, manufactured by SII NanoTechnology) for a sample obtained by heating a thermosetting resin layer at 180 ° C. for 1 hour. Is the temperature at which the weight of the sample was reduced by 5% when measured at a heating rate of 10 ° C./min and under a nitrogen flow (400 ml / min).

  From the viewpoint of handleability and film thickness uniformity, the thickness of the thermosetting resin layers 21 and 22 is preferably 2 to 50 μm. The thickness of the thermosetting resin layers 21 and 22 is more preferably 3 μm or more from the viewpoint that voids due to insufficient embedding during lamination can be suppressed. From the viewpoint of suppressing voids due to outgassing, the thickness of the thermosetting resin layers 21 and 22 is more preferably 30 μm or less.

  The thermosetting resin layers 21 and 22 can be layers formed from, for example, a thermosetting resin composition containing a (meth) acrylate compound and / or an epoxy compound.

The (meth) acrylate compound is preferably a bifunctional or higher (meth) acrylate. The bifunctional or higher functional (meth) acrylate is not particularly limited, but diethylene glycol diacrylate, triethylene glycol diacrylate, tetraethylene glycol diacrylate, diethylene glycol dimethacrylate, triethylene glycol dimethacrylate, tetraethylene glycol dimethacrylate, trimethylol. Propanediacrylate, trimethylolpropane triacrylate, trimethylolpropane dimethacrylate, trimethylolpropane trimethacrylate, 1,4-butanediol diacrylate, 1,6-hexanediol diacrylate, 1,4-butanediol dimethacrylate, 1 , 6-Hexanediol dimethacrylate, pentaerythritol triacrylate, pentaerythris Tall tetraacrylate, pentaerythritol trimethacrylate, pentaerythritol tetramethacrylate, dipentaerythritol hexaacrylate, dipentaerythritol hexamethacrylate, styrene, divinylbenzene, 4-vinyltoluene, 4-vinylpyridine, N-vinylpyrrolidone, 2-hydroxyethyl Acrylate, 2-hydroxyethyl methacrylate, 1,3-acryloyloxy-2-hydroxypropane, 1,2-methacryloyloxy-2-hydroxypropane, methylenebisacrylamide, N, N-dimethylacrylamide, N-methylolacrylamide, tris ( β-hydroxyethyl) isocyanurate triacrylate, compounds represented by the following general formula, urethane acrylate Examples thereof include urethane methacrylate and urea acrylate. In the following general formula, R ¹⁹ and R ²⁰ each independently represent a hydrogen atom or a methyl group, and g and h each independently represent an integer of 1 to 20.

  The 5% mass reduction temperature of the (meth) acrylate compound is preferably 150 ° C. or higher, more preferably 180 ° C. or higher, further preferably 200 ° C. or higher, and most preferably 260 ° C. or higher. . When the 5% mass reduction temperature is 150 ° C. or higher, the low outgassing property, the high temperature adhesion property, and the reflow resistance tend to be improved.

  As an epoxy compound, the compound which contains at least 2 or more epoxy group in a molecule | numerator from a viewpoint of high temperature adhesiveness and reflow resistance is preferable. From the viewpoint of pattern formability and thermocompression bonding, a glycidyl ether type epoxy resin that is liquid or semi-solid at room temperature (25 ° C.), specifically, has a softening temperature of 50 ° C. or less is more preferable. Such an epoxy compound is not particularly limited. For example, glycidyl ether of bisphenol A, AD, S or F, glycidyl ether of water-added bisphenol A, glycidyl ether of ethylene oxide-added bisphenol A, propylene oxide-added bisphenol A Examples include glycidyl ether, trifunctional or tetrafunctional glycidyl ether, glycidyl ester of dimer acid, and trifunctional or tetrafunctional glycidylamine. These can be used alone or in combination of two or more.

  The 5% mass reduction temperature of the epoxy compound is preferably 150 ° C. or higher, more preferably 180 ° C. or higher, further preferably 200 ° C. or higher, and most preferably 260 ° C. or higher. When the 5% mass reduction temperature is 150 ° C. or higher, the low outgassing property, the high temperature adhesion property, and the reflow resistance tend to be improved.

  It is preferable that the thermosetting resin layer and the thermosetting resin composition further contain a thermoplastic resin. Examples of the thermoplastic resin include acrylic resin, phenoxy resin, polyimide resin, polyamideimide resin, polyamide resin, polyurethane resin, polyurethaneimide resin, polyurea resin, polybenzoxazole resin, polysiloxane resin, polyester resin, polyether resin, A phenol resin, a phenol novolak resin, a cresol novolak resin, a polyketone resin, and the like can be given. These resins may have a glycidyl group, a phenolic hydroxyl group, a (meth) acrylate group, a carboxyl group or the like in the side chain.

  The peelable copper foil 10 has a carrier 11 and a copper foil 12. The carrier 11 may be a copper foil. In particular, it is easy to form a wiring layer having fine wiring by forming the wiring layer 7 on the peelable copper foil 10 as in the method of FIG. In order to particularly facilitate the formation of a thin film and fine wiring, the peelable copper foil has a peelable copper foil with a surface roughness Rz of preferably 3 μm or less, and more preferably 2 μm or less. The surface roughness Rz is measured by scanning a range of 100 μm × 100 μm using a laser microscope (“LEXT OLS3000” manufactured by Olympus Corporation). Commercially available products of peelable copper foil include FUTF-5DA-5, FUTF-5DA-3, FUTF-5DA-2, FUTF-5DA-1.5, Mitsui Kinzoku MT18Ex, MT18FL, JX Nippon Mining Co., Ltd. Nisseki Metals JXUT-I, JXUT-II, JXUT-III may be mentioned.

  The peel strength between the carrier of the peelable copper foil and the copper foil is preferably 0.001 to 0.050 kN / m. The peel strength is more preferably 0.003 kN / m or more, and even more preferably 0.005 kN / m or more, in that peeling during processing can be suppressed. The peel strength between the carrier and the copper foil is preferably 0.04 kN / m or less in order to reduce damage to the wiring at the time of peeling, and 0.03 kN in that damage at the peeling start point can be suppressed. Even more preferably, it is / m or less. Accordingly, the peel strength between the carrier and the copper foil is most preferably 0.005 to 0.03 kN / m. The peel strength between the carrier of the peelable copper foil and the copper foil is determined by cutting the peelable copper foil into a width of 10 mm and using a small tabletop testing machine EZ-S (manufactured by Shimadzu Corporation) at a feed rate of 50 mm / min. It can be an average value when measured.

  The peel strength between the peelable copper foil 10 and the thermosetting resin layers 21 and 22 after the temporary fixing material is heated at 180 ° C. for 1 hour is 0.050 kN from the viewpoint of easy peeling between the carrier and the copper foil. / M or more, and more preferably 0.1 kN / m or more from the viewpoint of suppressing voids at the interface between the peelable copper foil 10 and the thermosetting resin layers 21 and 22.

  From the viewpoint of handleability and film thickness uniformity, the peelable copper foil 10 preferably has a thickness of 2 to 30 μm. The thickness of the peelable copper foil here is the total thickness of the copper foil, the carrier, and the release layer. The thickness of the peelable copper foil is preferably 10 μm or less in terms of processing efficiency after etching and etching efficiency, and more preferably 5 μm or less in terms of forming a fine and thin-film wiring. The thickness of the peelable copper foil is more preferably 1 μm or more in that the copper foil can be easily peeled off. In view of the above, the thickness of the peelable copper foil is most preferably 1 to 5 μm.

  The support 1 is not particularly limited, but may be a panel-like support such as an organic substrate, a stainless steel plate, or a glass plate, or may be a wafer-like support such as glass or silicon.

  The wiring layer 7 is not particularly limited, but can be formed by a semi-additive method or a trench method. In the semi-additive method, a seed layer is formed, a resist having a desired pattern is formed on the seed layer, an exposed portion of the seed layer is thickened by an electrolytic plating method, and the resist is removed. In this method, a thin portion is removed by etching to obtain a desired wiring. The trench method is a method in which a seed layer is formed on an insulating layer in which a desired pattern is formed, the film is thickened by an electrolytic plating method or the like, and a desired wiring is obtained by polishing.

  When the wiring layer 7 is formed on the peelable copper foil 10 as in the method of FIG. 4, the copper foil is used as a seed layer, so that the wiring is performed by a semi-additive method without forming a seed layer by a method such as sputtering. A layer can be formed.

  Examples of the pattern forming method include laser ablation, photolithography, and imprint. From the viewpoint of miniaturization and cost, a photolithography process is preferable. Therefore, a photosensitive insulating material is preferably used as the insulating material. A plurality of sheet-like insulating materials can be used together.

  As an exposure method for the photosensitive insulating material, a normal projection exposure method, a contact exposure method, a direct drawing exposure method, or the like can be used. As a developing method, it is preferable to use an alkaline aqueous solution of sodium carbonate or TMAH.

  After forming the pattern, the insulating layer may be further heat-cured. The heating temperature may be 100 to 200 ° C., and the heating time may be 30 minutes to 3 hours.

  The thermal expansion coefficient of the insulating layer after curing is preferably 80 ppm / ° C. or less from the viewpoint of warpage suppression, and more preferably 70 ppm / ° C. or less from the viewpoint of obtaining high reliability. The linear expansion coefficient of the insulating layer after curing is preferably 20 ppm / ° C. or more from the viewpoint of stress relaxation of the insulating layer and ease of forming a high-definition pattern.

  The step of mounting the semiconductor element on the temporary fixing material 101 (thermosetting resin layer 22) or the wiring layer 7 is not particularly limited, but a method of injecting an underfill material by connecting the bumped semiconductor element by thermocompression bonding, A method of connecting the semiconductor elements to which the underfill has been attached by thermocompression bonding is mentioned.

  When the semiconductor element is mounted on the temporary fixing material as in the method of FIG. 3, it is preferable to use a temporary fixing material having thermosetting resin layers on both sides of the peelable copper foil. The side opposite to the temporary fixing material of the semiconductor element is preferably a circuit surface.

  The semiconductor element 3 is not particularly limited. For example, a volatile memory such as a graphics processing unit GPU, DRAM, or SRAM, a non-volatile memory such as a flash memory, an RF semiconductor element, or a semiconductor element or silicon having a combination thereof It can be a photonics semiconductor element, a MEMS, a sensor semiconductor element or the like. A semiconductor element having TSV can also be used. A plurality of semiconductor elements may be stacked using, for example, TSV.

  The thickness of the semiconductor element 3 is preferably 200 μm or less, and more preferably 100 μm or less in that the package can be further thinned. From the viewpoint of handleability, the thickness of the semiconductor element 3 is preferably 30 μm or more.

  The sealing resin for forming the sealing resin layer 5 is not particularly limited, but may be a liquid sealing material, a solid sealing material, or a sheet-like sealing material.

  The support is separated from the sealing body 31 or 32 by peeling the carrier of the peelable copper foil and the copper foil. The release layer is usually peeled from the copper foil together with the carrier. For example, a wiring layer can be stuck on adhesive tapes, such as a dicing tape, and a carrier and copper foil can be peeled using debonding apparatuses, such as DB-12T made from SUSS MicroTech.

  The copper foil remaining on the wiring layer after peeling can be removed by etching. A copper foil having a pattern formed by a method such as forming a resist on the copper foil can also be formed as a pad or a wiring.

  The combination of the thermosetting resin layer and the peelable copper foil contributes to a high level of heat resistance, adhesion and peelability. Further, the peelable copper foil enables easy peeling of the support even after receiving a thermal history at a high temperature during the process. Therefore, by using the temporary fixing material of this embodiment, it is possible to manufacture a semiconductor device having high-density wiring with good yield and low cost. In particular, a wiring layer having a high demand for thinning and miniaturization can be manufactured more efficiently.

  The semiconductor device manufacturing method according to the embodiment of the present disclosure has been described above. However, the present disclosure is not limited to the above-described embodiment, and may be changed as appropriate without departing from the spirit of the present disclosure.

  DESCRIPTION OF SYMBOLS 1 ... Support body, 3 ... Semiconductor element, 4 ... Underfill, 5 ... Sealing resin layer, 7 ... Wiring layer, 10 ... Peelable copper foil, 11 ... Carrier, 12 ... Copper foil, 15 ... Release layer, 21 and 22 ... thermosetting resin layer, 31, 32 ... sealing body, 101, 102 ... temporary fixing material.

Claims (8)

(A) a peelable copper foil having a carrier and a copper foil provided on the carrier;
(B) a thermosetting resin layer provided on the peelable copper foil;
Temporary fixing material for semiconductor comprising.   The temporary fixing material for a semiconductor according to claim 1, wherein a 5% weight reduction temperature of the thermosetting resin layer after being heated at 180 ° C. for 1 hour is 260 ° C. or more.   The temporary fixing material for semiconductors of Claim 1 or 2 whose peeling strength between the said carrier and the said copper foil is 0.001-0.050 kN / m.   The peel strength between the peelable copper foil and the thermosetting resin layer after heating the semiconductor temporary fixing material at 180 ° C. for 1 hour is 0.050 kN / m or more. The temporarily fixing material for semiconductors as described in any one.   The temporary fixing material for semiconductors as described in any one of Claims 1-4 whose thickness of the said peelable copper foil is 2-30 micrometers.   The temporarily fixing material for semiconductors as described in any one of Claims 1-5 whose thickness of the said thermosetting resin layer is 2-50 micrometers. On the support, the step of providing the temporary fixing material for semiconductor according to any one of claims 1 to 6 in a direction in which the thermosetting resin layer is in contact with the support;
Mounting a semiconductor element on a surface opposite to the support of the temporary fixing material for a semiconductor;
Forming a sealing resin layer for sealing the semiconductor element on the semiconductor temporary fixing material;
Forming a wiring layer connected to the semiconductor element on the sealing resin layer;
Separating the support from the sealing body having the semiconductor element, the sealing resin layer and the wiring layer by peeling the carrier of the peelable copper foil and the copper foil;
A method for manufacturing a semiconductor device, comprising: On the support, the step of providing the temporary fixing material for semiconductor according to any one of claims 1 to 6 in a direction in which the thermosetting resin layer is in contact with the support;
Forming a wiring layer on a surface opposite to the support of the temporary fixing material for semiconductor;
Mounting a semiconductor element connected to the wiring layer on the wiring layer;
Forming a sealing resin layer for sealing the semiconductor element on the wiring layer;
Separating the support from the sealing body having the semiconductor element, the sealing resin layer and the wiring layer by peeling the carrier of the peelable copper foil and the copper foil;
A method for manufacturing a semiconductor device, comprising:

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