JP2016178108A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method with high efficiency and at low cost of a three dimensional semiconductor device greatly required to achieve refinement and high density.SOLUTION: A semiconductor device manufacturing method comprises the steps of: (I) fixing a semiconductor element on an ultrathin metal foil of a peelable metal foil via an adhesive material; (II) encapsulating the semiconductor element with an encapsulation material; (III) exposing a rear face of the ultrathin metal foil; (IV) removing the ultrathin metal foil to form a seed layer; (V) forming a cured film pattern on the seed layer by using a photosensitive material; (VI) forming a wiring pattern by electrolytic plating, on the seed layer in a portion not coated with the cured film pattern and removing the cured film pattern; and (VII) forming a re-wiring insulation layer on the wiring pattern.SELECTED DRAWING: Figure 12

Description

  The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method of manufacturing a semiconductor device for manufacturing a three-dimensional semiconductor package that is highly demanded for miniaturization and high density sufficiently efficiently and at low cost.

  As a typical three-dimensional semiconductor package, there is a package-on-package in which a memory package is stacked on a logic package. Package-on-package is widely used in smartphones and tablet terminals because it can increase the mounting density in the surface direction by stacking the packages on the package, and is an essential item for increasing the speed and functionality.

  By the way, in the package-on-package structure, it is necessary to electrically connect the upper and lower packages. Conventionally, the lower semiconductor package has a simple structure in which a semiconductor element is flip-chip mounted on a substrate, and the upper package has only to be connected via a solder ball.

  However, due to the recent demand for lighter, thinner and smaller devices, warpage of the lower semiconductor package has increased, making it difficult to ensure connection with the upper package. Therefore, a structure in which the semiconductor element of the lower semiconductor package is sealed with a sealing material to suppress package warpage has been proposed and put into practical use (see, for example, Non-Patent Document 1). Furthermore, from the viewpoint of improving productivity, a package in which a redistribution insulating layer is formed by rearranging chips without using an organic substrate has been put into practical use (see, for example, Non-Patent Document 2).

Application of Through Mold Via (TMV) as PoP Base Package, Electronic Components and Technology Conference (ECTC), 2008 Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology, ECTC, 2012

  The lower semiconductor package disclosed in Non-Patent Documents 1 and 2 can be electrically connected to the upper and lower semiconductor packages through the vias by providing vias (openings) with a laser in the sealing portion.

FIG. 13 is a diagram showing an embodiment of a conventional method for manufacturing a lower semiconductor package. In the lower semiconductor package 100A, first, the wiring pattern 112 is formed on both surfaces of the core substrate 111 (FIG. 13A). Next, after forming an interlayer insulating layer 113 on both surfaces, a via 114 and a wiring pattern 115 are formed (FIG. 13B). The via opening 114 is made using a YAG laser or a carbon dioxide gas laser.
Next, a liquid or film solder resist 116 is formed on both sides, and predetermined portions are opened by exposure and development processing (see FIG. 13C). In this way, the printed wiring board 110 for the lower semiconductor package is manufactured.

Subsequently, the bumped semiconductor element 120 is mounted on the printed wiring board 110 obtained (see FIG. 13D). Next, the underfill material 130 is impregnated between the bumped semiconductor element 120 and the printed wiring board 110 (see FIG. 13E).
Next, the semiconductor element 120 is sealed with a sealing material 140 (see FIG. 13F). Thereafter, a sealing opening 141 is provided in the sealing material 140 using a carbon dioxide laser (see FIG. 13G). Next, a connection material 142 such as solder or a metal material is supplied to the sealing opening 141, and the lower semiconductor package 100A is manufactured (see FIG. 13H).

  Since the lower semiconductor package 100A thus obtained has the sealing opening 141 formed at a corresponding location, the upper package can be placed on the lower semiconductor package to ensure electrical connection. However, the lower semiconductor package 100A manufactured by such a method has a complicated manufacturing method and requires many constituent materials. In addition, it is necessary to introduce equipment such as a laser, and there is a problem that the residue tends to remain because the laser opens. In addition, when connecting to the upper package, a lot of flux materials and highly active flux materials are required to remove oxides. If the amount and type are not appropriate, there is a problem that poor connection is likely to occur and there is room for improvement. was there.

  An object of the present invention is to provide a method for efficiently and inexpensively manufacturing a three-dimensional semiconductor device that is highly demanded for miniaturization and high density.

According to the present invention, the following method for manufacturing a semiconductor device (semiconductor package) is provided.
1. (I) a step of fixing a semiconductor element on an ultrathin metal foil of a peelable metal foil via an adhesive material;
(II) sealing the semiconductor element with a sealing material;
(III) exposing the back surface of the ultrathin metal foil;
(IV) removing the ultrathin metal foil to form a seed layer;
(V) forming a cured film pattern on the seed layer using a photosensitive material;
(VI) forming a wiring pattern on the seed layer portion not covered with the cured film pattern by electrolytic plating, and removing the cured film pattern;
(VII) forming a rewiring insulating layer on the wiring pattern;
A method of manufacturing a semiconductor device including:
2. After the step (II) and before the step (III),
(IIa) forming an opening reaching the ultrathin metal foil in at least a part of the sealing portion formed in the step (II);
(IIb) The manufacturing method of the semiconductor device of 1 including the process of forming a metal plating part in the said opening part by electrolytic plating.
3. The manufacturing method of the semiconductor device of 1 or 2 with which the said peelable metal foil has the core base material containing glass cloth and resin, metal foil, and ultra-thin metal foil in this order.
4). 4. The method for manufacturing a semiconductor device according to 3, wherein the core substrate has a thickness of 0.2 mm to 2.0 mm.
5. The manufacturing method of the semiconductor device as described in any one of 1-4 whose thickness of the said ultra-thin metal foil is 0.5 micrometer-12 micrometers.
6). The manufacturing method of the semiconductor device as described in any one of 1-5 whose said ultra-thin metal foil is copper foil.
7). The manufacturing method of the semiconductor device as described in any one of 1-6 whose said adhesive material is an adhesive film which has photosensitivity.
8). 8. The method for producing a semiconductor device according to 7, wherein the photosensitive adhesive film has a thickness of 10 μm to 50 μm.
9. The method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein the sealing material is photosensitive and has a film shape.
10. 10. The method for manufacturing a semiconductor device according to 9, wherein the film-shaped sealing material has a thickness of 50 μm to 300 μm.

  ADVANTAGE OF THE INVENTION According to this invention, the method of manufacturing the three-dimensional-compatible semiconductor device with a high request | requirement of refinement | miniaturization and high density efficiently and at low cost can be provided.

It is a schematic sectional drawing of the peelable metal foil which has the ultra-thin metal foil used by this embodiment. It is a schematic sectional drawing of the semiconductor element used by this embodiment, and a schematic sectional drawing which shows the state which fixed the semiconductor element on the ultra-thin metal foil of peelable metal foil. It is a schematic sectional drawing which shows the state which sealed the semiconductor element with the sealing film. It is a schematic sectional drawing which shows the state which formed the opening part in the sealing film. It is a schematic sectional drawing which shows the state which formed the metal plating part in the opening part. It is a schematic sectional drawing which shows the state which exposed the back surface of ultra-thin metal foil. It is a schematic sectional drawing which shows the state which removed ultra-thin metal foil. It is a schematic sectional drawing which shows the state which formed the seed layer in the ultra-thin metal foil removal surface. It is a schematic sectional drawing which shows the state which formed the dry film resist patterned on the seed layer. FIG. 4 is a schematic cross-sectional view showing a state in which after forming a wiring pattern in an opening portion of a dry film resist pattern, the dry film resist pattern is removed, and a seed layer exposed by removing the dry film resist pattern is removed. It is a schematic sectional drawing which shows the state which formed the rewiring insulating layer so that the opening part of a wiring pattern and a part of said wiring pattern might be coat | covered. It is a schematic sectional drawing which shows the state which formed the solder ball on the wiring pattern. It is a figure which shows one Embodiment of the manufacturing method of the conventional lower stage semiconductor package.

The method for manufacturing a semiconductor device of the present invention includes the following steps (I) to (VII):
(I) A step of fixing a semiconductor element on an ultrathin metal foil of a peelable metal foil via an adhesive material (II) A step of sealing the semiconductor element with a sealing material (III) of the ultrathin metal foil Step of exposing the back surface (IV) Step of forming the seed layer by removing the ultrathin metal foil (V) Step of forming a cured resin film pattern using a photosensitive material on the seed layer (VI) Electroplating Step (VII) of forming a wiring pattern on the seed layer portion not covered with the cured resin film pattern and removing the cured resin film pattern (VII) A step of forming a rewiring insulating layer on the wiring pattern

In the manufacturing method of the present invention, conductors for electrical connection with the upper package are collectively formed by electrolytic plating using an ultrathin metal foil, and after removing the ultrathin metal foil, SAP (Semi-Additive Process) is performed. By using the fine metal wiring to form a semiconductor device (for example, a lower semiconductor package) can be efficiently manufactured.
Note that miniaturization is difficult when the ultrathin metal foil is used as a wiring layer without removing the ultrathin metal foil in order to simplify the process. It is more efficient to miniaturize by removing the ultrathin metal foil and forming the metal wiring.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same or corresponding parts are denoted by the same reference numerals, and redundant description is omitted. Further, the positional relationship such as up, down, left and right is based on the positional relationship shown in the drawings unless otherwise specified. In addition, the dimensional ratios in the drawings are not limited to the illustrated ratios.
Further, for convenience of explanation, the drawing shows one semiconductor element after separation, but the state before separation (a state in which a plurality of semiconductor elements are formed in a single area array) The present invention can also be applied to.

[Step (I)]
In the step (I), the semiconductor element is fixed on the ultrathin metal foil of the peelable metal foil via an adhesive material.
FIG. 1 is a schematic cross-sectional view of a peelable metal foil used in this embodiment. The peelable metal foil is composed of, for example, a carrier metal foil (core base material + metal foil), a release layer (release layer), and an ultrathin metal layer. Although there will be no restriction | limiting in particular if the thickness of carrier metal foil is thicker than the thickness of an ultra-thin metal layer, It is preferable that it is 10-30 micrometers, and it is more preferable that it is 10-20 micrometers.
The peelable metal foil 1 as the fixing member has, for example, metal foils 12 on both surfaces of the core base material 11, and the ultrathin metal foil 13 is disposed on one surface of the metal foil 12 via a release layer (not shown). It is the laminated body which has.

The core substrate 11 is a layer that can give rigidity to the peelable metal foil 1.
The core base material is not particularly limited, but includes a substrate made of glass cloth and resin (such as a glass cloth-impregnated glass cloth impregnated with resin), silicon wafer, glass, stainless steel (SUS) plate, etc. A highly rigid material is preferred.

The thickness of the core substrate is preferably in the range of 0.2 mm to 2.0 mm. If the thickness of the core substrate is within this range, the handling property is good and the material cost can be suppressed.
The thickness of the core base material is more preferably 0.3 mm to 1.2 mm, and further preferably 0.4 mm to 0.8 mm.

The average thermal expansion coefficient of the core substrate from room temperature to 150 ° C. is preferably in the range of 1 × 10 ⁻⁶ / ° C. to 15 × 10 ⁻⁶ / ° C. If the average coefficient of thermal expansion is in this range, it is easy to suppress the occurrence of warping after fixing the semiconductor element (chip) to the peelable metal foil, and the material cost can also be suppressed.
The average coefficient of thermal expansion of the core substrate can be measured with a TMA apparatus (TA2940, manufactured by TA Instruments). A core base material processed to have a width of 5.0 mm, a length of 50 mm, and a thickness of 0.2 mm is prepared, the measurement mode is tensile, the applied load is 0.05 N, the distance between chucks is 20 mm, and the heating rate is 10 ° C./min. It is preferable to measure the amount of displacement from 25 ° C. to 150 ° C. and calculate the average thermal expansion coefficient.

The room temperature elastic modulus of the core substrate is preferably in the range of 20 GPa to 40 GPa. If the room temperature elastic modulus is within this range, it is easy to suppress the occurrence of warping after the semiconductor element is fixed to the peelable metal foil, and the core substrate can be easily produced.
The room temperature elastic modulus of the core base material can be measured with a dynamic viscoelasticity measuring device (RSA-III, manufactured by T.A. Instruments Inc.). A core substrate processed to have a width of 2.0 mm, a length of 50 mm, and a thickness of 0.1 mm is prepared, and the elastic modulus in the tensile direction may be measured under the conditions of a measurement frequency of 1 Hz, a distance between chucks of 20 mm, and a measurement temperature of 25 ° C.

The metal foil 12 functions as a release layer for the ultrathin metal foil 13.
The metal foil is a metal foil made of, for example, copper, nickel, aluminum or the like, and is preferably a copper foil.
The thickness of the metal foil is preferably in the range of 3 μm to 20 μm.

The ultrathin metal foil 13 functions as a support layer for the semiconductor element 2 after the semiconductor element 2 is mounted.
The thickness of the ultrathin metal foil is preferably in the range of 0.5 μm to 12 μm. When the thickness of the ultrathin metal foil is within the above range, the ultrathin metal foil itself can be easily produced, and miniaturization is facilitated. The thickness of the ultrathin metal foil is more preferably 1 μm to 9 μm, and further preferably 3 μm to 7 μm.
The material of the ultrathin metal foil is not particularly limited, but general copper is suitable as the wiring material.

  The peelable metal foil 1 can use a commercial item, for example, MCLE-705 (LH) N3DX (made by Hitachi Chemical Co., Ltd.) is mentioned.

FIG. 2A is a schematic cross-sectional view of a semiconductor element used in this embodiment.
The semiconductor element 2 has an underfill film 16 that is an adhesive material on a connection surface with the peelable metal foil 1, and a metal post that is an opening of the underfill film and is formed on a connection terminal portion of the semiconductor element body 14. 15.

  Examples of the semiconductor element body 14 include logic semiconductor elements such as a microprocessor and a logic LSI, and memory semiconductors such as a DRAM and a flash memory.

  The metal posts 15 may be made of, for example, a copper material having a conical shape with a diameter of 40 μm and a height of 20 μm, and two peripherals may be arranged on the outer periphery of the semiconductor element at a pitch of 80 μm.

The underfill film 16 is an adhesive material for fixing the semiconductor element body 14 on the ultrathin metal foil 13 of a peelable metal foil.
As the underfill film, a film made of a thermosetting resin, a film made of a thermoplastic resin, a film made of a photosensitive resin, or the like can be used. Among these, a photosensitive adhesive film made of a photosensitive resin is preferable from the viewpoint of opening the metal post 15 in advance.
The underfill film 16 is preferably laminated in advance on the active surface (peelable metal foil connection surface) of the wafer-like semiconductor element body 14 before separation into individual pieces.

Hereinafter, the case where the underfill film 16 is an adhesive film having photosensitivity will be described.
An adhesive film 16 having photosensitivity is attached to the peelable metal foil connection surface of the semiconductor element body 14 including the metal posts 15 by lamination or the like. Next, a photosensitive adhesive film corresponding to the metal post 15 is opened to expose the metal post 15. The opening of the adhesive film having photosensitivity can be performed by exposure and development processing.

The photosensitive resin composition that can be used to form a photosensitive adhesive film preferably contains one or more selected from a polyimide resin, a phosphine oxide compound or an oxime ester compound, and an epoxy resin.
As the epoxy resin, a biphenol type epoxy resin, a biphenyl type epoxy resin, a cresol type epoxy resin, a novolac type epoxy resin, or the like can be used.

In the exposure process, a predetermined portion of the underfill film 16 is exposed and photocured by irradiating actinic rays through the mask pattern.
A known light source can be used as the active light source. For example, a lamp that effectively emits ultraviolet rays, such as a carbon arc lamp, a mercury vapor arc lamp, an ultrahigh pressure mercury lamp, a high pressure mercury lamp, or a xenon lamp, can be used. Further, direct drawing direct laser exposure may be used.

Although exposure amount varies depending on the composition of the device or a photosensitive resin composition to be ^{used, 10mJ / cm 2 ~600mJ / cm} 2 is preferred. When the exposure amount is within the range, photocuring becomes appropriate, and the opening shape can be obtained stably. The exposure amount is more preferably ^{20mJ / cm 2 ~400mJ / cm 2} .

Next, a portion other than the exposed portion (unexposed portion) is removed by development processing, thereby opening the metal post portion of the photosensitive resin film and exposing the metal post 15.
Examples of the developer used for the development treatment include an alkaline developer such as a dilute solution (1 to 5% by mass aqueous solution) of tetramethylammonium hydroxide (TMAH) at 20 ° C. to 50 ° C. Examples of the development treatment include known methods such as spraying, rocking immersion, brushing and scraping.

The thickness of the underfill film is preferably in the range of 10 μm to 50 μm. When the thickness of the underfill film is within the above range, the film can be easily manufactured, and the semiconductor package can be thinned.
Here, when the underfill film is an adhesive film having photosensitivity, the “thickness of the underfill film” refers to the thickness of the photosensitive layer of the underfill film.

The average coefficient of thermal expansion of the underfill film from room temperature to 150 ° C. is preferably in the range of 25 × 10 ⁻⁶ / ° C. to 100 × 10 ⁻⁶ / ° C. If the average coefficient of thermal expansion is 25 × 10 ⁻⁶ / ° C. or more, there is no need to increase the amount of filler, so there is little risk of lowering the resolution of the underfill film. On the other hand, if the average coefficient of thermal expansion is 100 × 10 ⁻⁶ / ° C. or less, the elastic modulus tends to be sufficient and the thermal shock resistance tends to be high.
For the same reason as described above, the room temperature elastic modulus of the underfill film 6 is preferably in the range of 1 GPa to 10 GPa.

It is preferable to use a mounting machine such as a flip chip bonder for fixing the semiconductor element 2 to the peelable metal foil 1. For example, the underfill film 16 can be fixed to the ultrathin metal foil 13 by a TCB (Thermal Compression Bonding) method. FIG. 2B is a schematic cross-sectional view showing a state in which the semiconductor element 2 is fixed on the ultrathin metal foil 13 of the peelable metal foil 1.
Thereafter, thermosetting may be performed at around 150 ° C. for about 1 hour, or thermosetting may be performed in combination with the sealing film 17 described later.

[Step (II)]
In step (II), the semiconductor element is sealed with a sealing material.
FIG. 3 is a schematic cross-sectional view showing a state in which the semiconductor element 2 is sealed with the sealing film 17.
In this embodiment, the sealing film 17 which covers the semiconductor element main body 14 is formed using a sealing material (see FIG. 3). The sealing material may be a thermosetting resin, a thermoplastic resin, or a photosensitive resin. Since a sealing film can provide a fine opening part, the sealing film which has photosensitivity is preferable.
The sealing with the sealing film 17 can employ a known method such as a laminate method or a compression method.

The photosensitive resin composition that can be used for forming a sealing film having photosensitivity preferably contains one or more selected from an acid-modified epoxy resin, a phosphine oxide compound, an oxime ester compound, and an epoxy resin.
As the acid-modified epoxy resin, biphenol type epoxy acrylate, biphenyl type epoxy acrylate, cresol novolac type epoxy acrylate and the like can be used, and cresol novolac type epoxy acrylate is preferable.
As the epoxy resin, a biphenol type epoxy resin, a biphenyl type epoxy resin, a cresol type epoxy resin, a novolac type epoxy resin, or the like can be used.

The thickness of the sealing film is preferably in the range of 50 μm to 300 μm.
If the thickness of the sealing film is 50 μm or more, the thickness is sufficient to seal the semiconductor element body 14. On the other hand, if the thickness of the sealing film is 300 μm or less, a fine opening can be easily formed in the sealing film.
Here, when the sealing film is a photosensitive sealing film, the “thickness of the sealing film” refers to the thickness of the photosensitive layer of the sealing film.

The average thermal expansion coefficient of the sealing film from room temperature to 150 ° C. is preferably in the range of 25 × 10 ⁻⁶ / ° C. to 100 × 10 ⁻⁶ / ° C. If the average coefficient of thermal expansion is 25 × 10 ⁻⁶ / ° C. or higher, it is not necessary to increase the amount of filler, and this is preferable because the resolution of the sealing film does not deteriorate. On the other hand, when the average coefficient of thermal expansion is 100 × 10 ⁻⁶ / ° C. or less, warpage of the resulting semiconductor package (semiconductor device) can be suppressed, and handling properties are also improved.
Similarly, the room temperature elastic modulus of the sealing film is preferably in the range of 1 GPa to 10 GPa for the same reason.

In this embodiment, after the step (II), a step (IIa) of forming an opening leading to the exposure of the ultrathin metal foil 13 in at least a part of the sealing film 17 formed in the step (II); It is preferable to perform the step (IIb) of forming a metal plating portion by electrolytic plating in the opening portion.
4 is a schematic cross-sectional view showing a state in which the opening 17a is formed in the sealing film 17, and FIG. 5 is a schematic cross-sectional view showing a state in which the metal plating portion 18 is formed in the opening 17a.

When a sealing film having photosensitivity is used as the sealing film 17, the opening 17a can be formed by exposure / development processing.
About an exposure process, the predetermined part of the sealing film 17 is exposed and irradiated by photoirradiation by irradiating actinic light through a mask pattern. As a light source of actinic light, a well-known light source can be used like an underfill film. Although exposure amount varies depending on the composition of the device or a photosensitive resin composition to be used, preferably ^{10mJ / cm 2 ~600mJ / cm 2} , more preferably ^{20mJ / cm 2 ~400mJ / cm 2} . Photocuring becomes sufficient exposure amount by a ^{10mJ / cm 2 ~600mJ / cm 2} , an opening can be formed stably.

After the exposure process, an opening 17a that exposes the ultrathin metal foil 13 is formed by removing the sealing film 17 other than the exposed part (unexposed part) by developing process.
As the developer used for the development treatment, for example, an alkaline developer such as a dilute solution (1 to 5% by mass aqueous solution) of sodium carbonate at 20 to 50 ° C. is used. As the development processing, known methods such as spraying, rocking immersion, brushing and scraping can be applied. Thereby, a predetermined opening 17a is formed.
After the opening 17a is provided, the sealing film 17 may be heat-cured at about 150 ° C. for about 1 hour.

Pickling treatment or plasma treatment may be performed for the purpose of removing an oxide film or residue on the ultrathin metal foil 13 after the opening portion 17a is formed and before the metal plating portion 18 is formed.
The metal plating part is preferably formed by an electrolytic plating method.
The metal plating part is preferably a metal plating part that is a copper foil.

[Step (III)]
In step (III), the back surface of the ultrathin metal foil (the back surface of the surface on which the semiconductor element of the ultrathin metal foil is fixed, the contact surface with the metal foil of the ultrathin metal foil) is exposed.
FIG. 6 is a schematic cross-sectional view showing a state where the back surface of the ultrathin metal foil 13 is exposed. The back surface of the ultrathin metal foil 13 can be exposed by peeling the ultrathin metal foil 13 from the metal foil 12.
There is no restriction | limiting in particular about the peeling method. For example, there is a method in which the surface opposite to the peelable metal foil 1 side of the sealing film 17 is vacuum-sucked to peel the core substrate 11 and the metal foil 12 simultaneously. At this time, mechanical peeling may be performed after a fixing plate such as a silicon wafer, a glass film, a SUS plate, or a core substrate is attached to the surface of the sealing film 17 via a temporary fixing material. The fixing plate such as the SUS plate may remain attached until it is separated into individual semiconductor packages. Affixing the fixing plate improves the rewiring insulation layer formation and handling properties when mounting solder balls, and is particularly effective for thin semiconductor packages.

[Step (IV)]
In step (IV), the ultrathin metal foil is removed to form a seed layer.
FIG. 7 is a schematic cross-sectional view showing a state where the ultrathin metal foil 13 is removed, and FIG. 8 is a schematic cross-sectional view showing a state where the seed layer 19 is formed on the ultrathin metal foil removal surface.

In the present embodiment, the ultrathin metal foil 13 can be removed by an etching process.
The etching solution used for the etching process is appropriately selected depending on the type of material constituting the ultrathin metal foil. For example, when the ultrathin metal foil is a copper foil, a mixed aqueous solution of iron chloride and hydrochloric acid or a mixed aqueous solution of copper chloride and hydrochloric acid is generally used. As the etching method, known methods such as spraying, rocking dipping, brushing and scraping can be employed. Thereby, the metal post 15 and the metal plating part 18 can be exposed (refer FIG. 7).

  A seed layer is formed on the surface from which the ultrathin metal foil has been removed (the exposed surface of the metal post and the metal plating portion). By forming the seed layer, a selective wiring pattern can be formed by electrolytic plating.

The formation method of the seed layer 19 is not particularly limited, but can be formed by electroless plating, sputtering treatment, or the like.
When the seed layer is formed by an electroless copper plating method, the thickness of the seed layer is not particularly limited, but is preferably 0.1 μm to 1.0 μm.
The seed layer can also be formed by a sputtering method. Although the target used for the said sputtering method can be selected suitably, it is a Ti / Cu target, for example. When the seed layer is formed by sputtering using a Ti / Cu target, the thickness of Ti or Cu is not particularly limited, but 20 nm to 100 nm for Ti and 100 nm to 500 nm for Cu are preferable. The outermost electrode can be plated using a commercially available electroless nickel / gold plating solution or the like.

[Step (V)]
In step (V), a cured resin film pattern is formed on the seed layer using a photosensitive material.
FIG. 9 is a schematic cross-sectional view showing a state where a patterned dry film resist 20 is formed on the seed layer 19, and the dry film resist corresponds to a photosensitive material. In this embodiment, a resin cured film pattern 20 of a dry film resist is formed on the seed layer 19.

  The dry film resist may be liquid or film-like. When the dry film resist is liquid, it can be formed by printing or a spin coater. On the other hand, when the dry film resist is a film, it can be formed by lamination. Next, a predetermined portion of the dry film resist is exposed and photocured by irradiating actinic rays through the mask pattern. Next, a pattern cured film 20 of a dry film resist is formed by removing portions other than the exposed portion by development (see FIG. 9).

[Process (VI)]
In step (VI), a wiring pattern is formed in the opening portion of the pattern made of a photosensitive material by electrolytic plating, and then the pattern made of the photosensitive material is removed. Thereby, a wiring pattern is formed in the seed layer portion not covered with the pattern made of the photosensitive material.
In FIG. 10, after forming a wiring pattern (metal wiring) 21 in the opening of the dry film resist pattern 20, the dry film resist pattern 20 is removed, and the seed layer 19 exposed by the removal of the dry film resist pattern 20 is removed. It is a schematic sectional drawing which shows the state removed.

In this embodiment, after the dry film resist pattern cured film 20 is formed, the wiring pattern 21 is formed in the pattern opening by electrolytic plating (see FIG. 10).
The thickness of the wiring pattern is preferably 1 to 20 μm. The wiring pattern is preferably a copper foil.

The dry film resist pattern 20 is removed by a peeling solution or the like, and the seed layer 19 exposed by the removal is removed (see FIG. 10).
Removal of the dry film resist pattern with a stripping solution can be performed by a known method.
The seed layer can be removed by etching using, for example, an etching solution, and can be performed by a known method.

[Step (VII)]
In step (VII), a rewiring insulating layer is formed on the wiring pattern.
FIG. 11 is a schematic cross-sectional view showing a state in which the rewiring insulating layer 22 is formed so as to cover the opening of the wiring pattern 21 and a part (both ends) of the wiring pattern 21.

In the present embodiment, the material for the rewiring insulating layer is not particularly limited, and a known photosensitive resin, a known thermosetting resin, or the like can be used. The material used may be liquid or film.
For example, when a liquid photosensitive resin is used to form the rewiring insulating layer, a film having a predetermined thickness is formed by a spin coater, and then a predetermined pattern is formed by exposure and development processing. The rewiring insulating layer can be formed by thermally curing the formed pattern in a nitrogen atmosphere (see FIG. 11).

After forming the rewiring insulating layer, a known process may be performed as necessary. For example, when multiple layers are required, the following process cycle may be repeated.
A seed layer is formed by electroless plating or sputtering (not shown). Thereafter, a wiring forming resist is formed, and a pattern is formed by exposure and development processing. Next, a wiring pattern is formed by electroplating (not shown). Next, the resist is peeled off and the seed layer is removed (not shown). Thereafter, a rewiring insulating layer is formed with a photosensitive material (not shown).

FIG. 12 is a schematic cross-sectional view showing a state in which solder balls 23 are formed on the wiring pattern 21. The wiring pattern 21 functions as an external connection terminal, and is connected to an external substrate or the like using a solder ball 23. Mounting of the solder balls 23 can be easily performed using a commercially available N ₂ reflow apparatus or the like. Finally, as shown in FIG. 12, the semiconductor device 100 can be obtained by dividing into individual pieces.

  The manufacturing method of the present embodiment is suitable for a semiconductor device that requires miniaturization and multi-pinning, and particularly suitable for a three-dimensional form of eWLB (embedded Wafer Level Ball Grid Array).

  The semiconductor package manufacturing method according to an embodiment of the present invention has been described above. However, the present invention is not necessarily limited to the above-described embodiment, and may be appropriately changed without departing from the spirit thereof. .

  EXAMPLES Hereinafter, although this invention is demonstrated in detail using an Example and a comparative example, this invention is not limited to these Examples.

Example 1
<Preparation of peelable metal foil>
A peelable metal foil (Hitachi Chemical Co., Ltd. MCLE-705), which is a core base material sandwiched between two copper foils and has a peelable copper foil as an ultrathin metal foil on one surface of the two copper foils. LH) N3DX) was prepared (see FIG. 1). At this time, the thickness of the core base material was 0.41 mm, the copper foil thickness was 18 μm on both sides, and the thickness of the peelable copper foil on the outermost layer on one side was 3 μm.
The peelable metal foil was processed into a size of 100 mm × 100 mm.
In addition to the 3 μm-thick peelable copper foil, which is an ultrathin metal foil, a total of three types of 2 μm and 5 μm were prepared. An ultrathin metal foil with a thickness of 2 μm was designated as N2DX (Example 2), a 3 μm thick with N3DX (Example 1), and a 5 μm thick with N5DX (Example 3).

<Preparation of semiconductor element>
An 8-inch wafer semiconductor device (Waltz WALTS-TEG CC80-0101JY_ (PI) _ModelI) was prepared. This semiconductor element was back-grinded to a thickness of 70 μm. A terminal in which a copper post having a height of 30 μm was formed was prepared (see FIG. 2).

<Synthesis of alkali-soluble resin P-1>
Alkali-soluble resin P-1 which is the material of the adhesive film which has the photosensitivity of a semiconductor element was prepared with the following method.
2,2-bis (3-amino-4-hydroxyphenyl), which is a diamine, in a 300 mL flask equipped with a stirrer, thermometer, nitrogen displacement device (nitrogen inlet tube), and reflux condenser with moisture receiver. Hexafluoropropane (manufactured by Central Glass Co., Ltd., trade name: BIS-AP-AF, molecular weight: 366) 14.64 g (0.04 mol), polyoxypropylene diamine (manufactured by BASF, trade name: D-400, molecular weight: 433) and 17.3 g (0.04 mol) and 3,3 ′-(1,1,3,3-tetramethyldisiloxane-1,3-diyl) bispropylamine (manufactured by Toray Dow Corning Co., Ltd.) 2. Product name: BY16-871EG, molecular weight: 248.5) 2.485 g (0.01 mol); m-aminophenol 2.183 g (0.02 mol); In addition, 80 g of N-methyl-2-pyrrolidone (hereinafter abbreviated as “NMP”) as a solvent was charged and stirred to dissolve the diamine in the solvent.
While cooling the flask in an ice bath, 31 g (0.1 mol) of 4,4′-oxydiphthalic dianhydride (hereinafter abbreviated as “ODPA”) was added little by little to the solution in the flask. After completion of the addition, the solution was heated to 180 ° C. while blowing nitrogen gas and kept for 5 hours to obtain polyimide resin P-1.

<Formation of photosensitive adhesive film>
Alkali-soluble resin P-1 as a base resin; M-313 (manufactured by Toa Gosei Co., Ltd., isocyanuric acid EO-modified diacrylate and isocyanuric acid EO-modified triacrylate) as a photocrosslinking agent, 80 parts by mass with respect to 100 parts by mass of the base resin; 3 parts by mass of I-819 (manufactured by Ciba Japan, bis (2,4,6-trimethylbenzoyl) -phenylphosphine oxide) as a photopolymerization initiator with respect to 100 parts by mass of the base resin; and a thermosetting agent component YDF-870GS (manufactured by Tohto Kasei Co., Ltd., bisphenol F-type bisglycidyl ether) was blended in an amount of 30 parts by mass with respect to 100 parts by mass of the base resin to prepare a photosensitive resin composition.

The obtained photosensitive resin composition was applied on a substrate (peeling agent-treated PET film) so that the film thickness after drying was 40 μm, and heated in an oven at 80 ° C. for 20 minutes, and then It heated at 120 degreeC for 20 minute (s), and the adhesive film which has the photosensitive property which consists of a photosensitive resin composition was formed on the base material.
Subsequently, a polyethylene film was bonded as a protective film on the surface opposite to the side in contact with the PET film, which is a substrate of the photosensitive adhesive film, to obtain an adhesive film member having photosensitivity.

The protective film of the adhesive film member having photosensitivity is peeled off, and the active surface including the copper metal post of the semiconductor element is made photosensitive using a press-type vacuum laminator (MVLP-500, manufactured by Meiki Seisakusho, trade name). The adhesive film which has was laminated | stacked. The pressing conditions were a press hot plate temperature of 60 ° C., a vacuuming time of 30 seconds, a laminating press time of 60 seconds, an atmospheric pressure of 4 kPa or less, and a pressing pressure of 0.5 MPa.
A phototool having a pattern formed thereon was brought into close contact with the formed adhesive film having photosensitivity, and exposure was performed with an energy amount of 500 mJ / cm ² using an EXM-1201 type exposure machine manufactured by Oak Manufacturing Co., Ltd. Next, heat treatment was performed at 80 ° C. for 30 seconds, and the PET film on the photosensitive adhesive film was peeled off. Next, spray development was performed in a 2.38 wt% TMAH aqueous solution at 30 ° C. for 90 seconds, the photosensitive adhesive film was opened, the metal post (electrode part) was exposed, and washed with pure water.
By the above procedure, a semiconductor element provided with a metal post and an adhesive film (underfill film) was manufactured.

<Mounting of semiconductor elements>
The obtained semiconductor element was processed to 7.3 mm × 7.3 mm and mounted so that the active surface (underfill film surface) was bonded to the peelable copper foil (ultra-thin metal foil) of the peelable metal foil (see FIG. 2). ).
For the mounting, a flip chip bonder was used, and the mounting was performed at a stage setting temperature of 80 ° C., a flip chip bonder head temperature of 140 ° C., and a pressure bonding time of 2 seconds. The load was 50N.

<Preparation of sealing film>
The photosensitive resin composition which is sealing film material was prepared with the following method.
As an alkali-developable resin containing a carboxyl group, acid-modified cresol novolac epoxy acrylate (CCR-1219H, Nippon Kayaku Co., Ltd., trade name) is used as a photoinitiator component, and 2,4,6-trimethylbenzoyl -Diphenyl-phosphine oxide (Darocur TPO, manufactured by Ciba Japan, trade name) and ethanone, 1- [9-ethyl-6- (2-methylbenzoyl) -9H-carbazol-3-yl]-, 1 -(O-acetyloxime) (Irgacure OXE-02, manufactured by Ciba Japan Co., Ltd., trade name) is used as a thermosetting agent component, and a biphenol type epoxy resin (YX-4000, manufactured by Japan Epoxy Resin Co., Ltd., trade name) is used. As an inorganic filler component, silica having an average particle size of 500 nm subjected to silane coupling treatment Filler was compounded respectively, to prepare a photosensitive resin composition. Here, the inorganic filler component was blended so as to be 40% by weight with respect to the resin content.

  The dispersion state of the obtained photosensitive resin composition was as follows: a dynamic light scattering nanotrack particle size distribution meter “UPA-EX150” (manufactured by Nikkiso Co., Ltd.), and a laser diffraction scattering type microtrack particle size distribution meter “MT-3100” ( It was confirmed that the maximum particle size of the inorganic filler component was 5 μm or less.

  The obtained photosensitive resin composition was uniformly applied on a 16 μm-thick polyethylene terephthalate film (G2-16, manufactured by Teijin Ltd., trade name) as a support layer to form a photosensitive resin composition coating layer. The formed photosensitive resin composition coating layer was dried at 100 ° C. for about 10 minutes using a hot air convection dryer to form a photosensitive resin composition layer having a thickness of 120 μm.

  On the surface of the photosensitive resin composition layer opposite to the side in contact with the support layer, a polyethylene film (NF-15, product name, manufactured by Tamapoly Co., Ltd.) is bonded as a protective film, and a photosensitive sealing film A member was manufactured.

<Formation of sealing film>
The protective film (polyethylene film) of the obtained sealing film member was peeled off, the exposed photosensitive resin layer was bonded to the semiconductor element mounting side of the peelable metal foil, and the sealing film was laminated on the semiconductor element ( (See FIG. 3). For the bonding, a press-type vacuum laminator (MVLP-500, manufactured by Meiki Seisakusho, trade name) was used. The pressing conditions were a press hot plate temperature of 80 ° C., a vacuuming time of 20 seconds, a laminating press time of 30 seconds, an atmospheric pressure of 4 kPa or less, and a pressing pressure of 0.5 MPa.

<Formation of opening>
A photo tool on which a pattern was formed was brought into close contact with the formed sealing film, and exposure was performed with an energy amount of 500 mJ / cm ² using an EXM-1201 type exposure machine manufactured by Oak Manufacturing Co., Ltd. Next, after standing at room temperature for 1 hour, the polyethylene terephthalate film of the sealing film is peeled off, and spray development is performed with a 1 wt% sodium carbonate aqueous solution at 30 ° C. for 180 seconds, and an opening is formed in the sealing film. Provided (see opening 17a in FIG. 4). Subsequently, the sealing film was irradiated with ultraviolet rays with an energy amount of 1.5 J / cm ² using an ultraviolet irradiation device (manufactured by Oak Manufacturing Co., Ltd.), and thermally cured in a clean oven at 175 ° C. for 2 hours (FIG. 4). reference).

<Formation of electrolytic copper plating>
The opening part of the sealing film was filled with a metal material (copper) by an electrolytic copper plating method to form a metal plating part (see the metal plating part 18 in FIG. 5).

<Removal of core substrate and copper foil>
Next, the surface of the sealing film of the laminate was vacuum-adsorbed, and the core substrate portion sandwiched between the two copper foils was mechanically peeled to expose the peelable copper foil (see FIG. 6).

<Removal of ultrathin metal foil>
Then, using an aqueous solution of ferric chloride (30% by weight), the peelable copper foil was etched by a spray method to expose the metal post and the metal plating part (see FIG. 7).

<Formation of seed layer>
On the exposed metal post and metal plating part side of the laminate, 100 nm of Ti was deposited by sputtering, and 300 nm of Cu was continuously deposited to form a seed layer (see seed layer 19 in FIG. 8).

<Formation of dry film resist>
A dry film resist (Hitachi Chemical Co., Ltd. Phototec RY-3525), which is a photosensitive resin composition, was laminated on the Cu seed layer by a roll laminator. Subsequently, the photo tool which formed the pattern was stuck, and it exposed by the energy amount of 100 mJ / cm < ² > using the exposure machine (EXM-1201 type | mold by Oak Manufacturing Co., Ltd.). Next, spray development was performed for 90 seconds with a 1% by mass aqueous sodium carbonate solution at 30 ° C., and the photosensitive resin composition was opened to form a dry film resist pattern (see dry film resist pattern 20 in FIG. 9).

<Formation of wiring pattern>
A wiring pattern was formed by electrolytic copper plating at the opening of the dry film resist pattern of the laminate (see wiring pattern 21 in FIG. 10).

<Removal of dry film resist>
Next, the dry film resist pattern was removed by a peeling solution (see FIG. 10).

<Removal of seed layer>
Subsequently, the exposed seed layer was removed by removing the dry film resist pattern with an etching solution (see FIG. 10).

<Formation of rewiring insulation layer>
A rewiring insulating layer was formed on the wiring pattern so as to cover the opening of the wiring pattern of the laminate (see the rewiring insulating layer 22 in FIG. 11).
Specifically, a photosensitive rewiring material (Hitachi Chemical Co., Ltd. AH-1170T) was applied with a spin coater, and exposure / development processing was performed. Next, thermosetting was performed for 1 hour at a predetermined temperature of 200 ° C. in a nitrogen atmosphere (oxygen concentration of 50 ppm or less) to form a rewiring insulating layer (see FIG. 11).

<Ball mounted>
Using a reflow apparatus, solder balls were mounted under a nitrogen atmosphere (oxygen concentration of 100 ppm or less), and finally, dicing was performed to obtain a semiconductor package having a package size of 14 mm × 14 mm (the solder balls 23 and FIG. 12). Semiconductor device 100).

Example 2
A semiconductor package was manufactured in the same manner as in Example 1 except that the thickness of the peelable copper foil of the peelable metal foil was 2 μm.

Example 3
A semiconductor package was manufactured in the same manner as in Example 1 except that the thickness of the peelable copper foil of the peelable metal foil was changed to 5 μm.

Example 4
A semiconductor package was manufactured in the same manner as in Example 1 except that the thickness of the sealing film was 100 μm.

Example 5
A semiconductor package was manufactured in the same manner as in Example 1 except that the thickness of the sealing film was 140 μm.

Example 6
A semiconductor package was manufactured in the same manner as in Example 1 except that the thickness of the adhesive film was 35 μm and the thickness of the sealing film was 100 μm.

Example 7
A semiconductor package was manufactured in the same manner as in Example 1 except that the thickness of the adhesive film was 45 μm and the thickness of the sealing film was 140 μm.

[Evaluation of semiconductor packages]
Table 1 shows the specifications of the semiconductor package manufactured in Example 1-3.
Moreover, the following evaluation was performed about the obtained semiconductor package. The results are shown in Table 2.

The wiring pattern formability of the obtained semiconductor device was evaluated based on the following criteria. (2μm, 3μm, 5μm)
A: Wiring pattern width / space width between wiring patterns is 10 μm / 10 μm or less ○: Wiring pattern width / space width between wiring patterns is 15 μm / 15 μm or less Δ: Wiring pattern width / space width between wiring patterns is 20 μm / 20 μm Less than

The openability of the sealing film was evaluated based on the following criteria. (100μm, 120μm, 140μm)
◎: Opening diameter of the opening is 80 μm or less ○: Opening diameter of the opening is 100 μm or less Δ: Opening diameter of the opening is 140 μm or less

The mountability of the semiconductor element was evaluated based on the following criteria.
○: The semiconductor element could be mounted on the peelable copper foil. ×: The semiconductor element could not be mounted on the peelable copper foil.

  The manufacturing method of the present invention is suitable as a method for manufacturing a semiconductor device that requires miniaturization and multi-pinning. In particular, it is suitable in a form in which eWLB is made three-dimensional. The manufacturing method of the present invention is suitable as a manufacturing method of various semiconductor devices, for example, lower semiconductor packages.

1 Peelable metal foil (fixing member)
2 Semiconductor element 11 Core substrate 12 Metal foil 13 Ultrathin metal foil 14 Semiconductor element body 15 Metal post 16 Underfill film 17 Sealing film 17a Opening 18 Metal plating part 19 Seed layer 20 Resin cured film pattern 21 Wiring pattern 22 Re Wiring insulating layer 23 Solder ball 100 Semiconductor package 111 Core base material 112 Wiring pattern 113 Interlayer insulating layer 114 Via opening 115 Wiring pattern 116 Solder resist 110 Printed wiring board for lower semiconductor package 120 Semiconductor device with bump 130 Underfill material 140 Sealing material 141 Sealing opening 142 Connecting material

Claims (10)

(I) a step of fixing a semiconductor element on an ultrathin metal foil of a peelable metal foil via an adhesive material;
(II) sealing the semiconductor element with a sealing material;
(III) exposing the back surface of the ultrathin metal foil;
(IV) removing the ultrathin metal foil to form a seed layer;
(V) forming a cured film pattern on the seed layer using a photosensitive material;
(VI) forming a wiring pattern on the seed layer portion not covered with the cured film pattern by electrolytic plating, and removing the cured film pattern;
(VII) forming a rewiring insulating layer on the wiring pattern;
A method of manufacturing a semiconductor device including: After the step (II) and before the step (III),
(IIa) forming an opening reaching the ultrathin metal foil in at least a part of the sealing portion formed in the step (II);
The method of manufacturing a semiconductor device according to claim 1, further comprising: (IIb) forming a metal plating portion in the opening by electrolytic plating.   The manufacturing method of the semiconductor device of Claim 1 or 2 with which the said peelable metal foil has the core base material containing glass cloth and resin, metal foil, and ultra-thin metal foil in this order.   The method for manufacturing a semiconductor device according to claim 3, wherein the core substrate has a thickness of 0.2 mm to 2.0 mm.   The method of manufacturing a semiconductor device according to claim 1, wherein the ultrathin metal foil has a thickness of 0.5 μm to 12 μm.   The said ultra-thin metal foil is copper foil, The manufacturing method of the semiconductor device as described in any one of Claims 1-5.   The method for manufacturing a semiconductor device according to claim 1, wherein the adhesive material is an adhesive film having photosensitivity.   The method of manufacturing a semiconductor device according to claim 7, wherein a thickness of the photosensitive adhesive film is 10 μm to 50 μm.   The method for manufacturing a semiconductor device according to claim 1, wherein the sealing material is photosensitive and has a film shape. The method for manufacturing a semiconductor device according to claim 9, wherein the film-shaped sealing material has a thickness of 50 μm to 300 μm.

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