JP2022097755A - Method for manufacturing wiring layer and method for forming seed layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method by which a wiring layer can be manufactured more efficiently in comparison to a conventional method.

SOLUTION: The disclosure hereof relates to a method for manufacturing a wiring layer. The manufacturing method comprises (A) forming an insulating material layer on a support substrate, (B) applying UV light to a surface of the insulating material layer in the presence of oxygen, (C) having a catalyst of 1×10^-5-100×10^-5 mol/m² adsorbed on the surface of the insulating material layer, (D) forming a seed layer on the surface of the insulating material layer by electroless plating, (E) forming a resist pattern on a surface of the seed layer, (F) forming, by electrolytic plating, a metal layer in a region of the surface of the seed layer, which is exposed from the resist pattern, (G) removing the resist pattern, and (H) removing the seed layer exposed as a result of removal of the resist pattern, and the catalyst between the seed layer and the insulating material layer in this order.

SELECTED DRAWING: Figure 2

COPYRIGHT: (C)2022,JPO&INPIT

Description

The present invention relates to a method for manufacturing a wiring layer, and more particularly to a method for manufacturing a wiring layer useful for efficiently manufacturing a semiconductor device at low cost, which is highly required for miniaturization and high density. The present invention also relates to a method for forming a seed layer in the process of manufacturing a wiring layer.

For the purpose of increasing the density and performance of semiconductor packages, mounting forms in which chips with different performances are mixedly mounted in one package have been proposed, and high-density interconnect technology between chips, which is excellent in terms of cost, has become important. (See, for example, Patent Document 1).

Package-on-packages, which connect different packages by stacking them on a package by flip-chip mounting, are widely used in smartphones and tablet terminals (see, for example, Non-Patent Documents 1 and 2). As a form for mounting at a higher density, a package technology (organic interposer) using an organic wiring board having a high density wiring, a fan-out type packaging technology (FO-WLP) having a through mold via (TMV), and silicon. Alternatively, a package technology using a glass interposer, a package technology using a through silicon via (TSV), a package technology using a chip embedded in a wiring board for chip-to-chip transmission, and the like have been proposed.

In particular, in an organic interposer and FO-WLP, when semiconductor chips are mounted in parallel, a fine wiring layer is required to conduct high-density conduction (see, for example, Patent Document 2).

Japanese Patent Publication No. 2012-528770 US Patent Application Publication No. 2001/0221071

Application of Through Mold Via (TMV) as PoP Base Package, Electronics Components and Technology Conference (ECTC), 2008 Advanced Low Profile PoP Solution with Embedded Wafer Level Level PoP (eWLB-PoP) Technology, ECTC, 2012

The formation of the fine wiring layer usually requires steps of seed layer formation by sputtering, resist formation, electroplating, resist removal, and seed layer removal, and this method has a problem of process cost. Therefore, a process capable of forming a fine wiring layer at low cost has been strongly desired.

As a method for forming a fine wiring layer at low cost, a method called a semi-additive method (SAP method) is known. This method usually involves forming a seed layer by electroless plating. However, the conventional semi-additive method has a problem that the adhesion of the seed layer to the insulating layer that is the base of the seed layer is insufficient. In order to improve this, it is known to carry out a step of roughening the surface of the insulating layer prior to the formation of the seed layer by electroless plating. For example, efforts have been made to roughen the surface of the insulating layer by using a liquid for desmear treatment, and to improve the adhesion between the insulating layer and the seed layer by the anchor effect thereof. For example, Japanese Patent No. 4552624 describes that a desmear treatment and an activation treatment are performed to form a plating base conductive layer (seed layer) by electroless copper plating. However, roughening treatment using a liquid for desmear treatment tends to make the surface of the insulating layer excessively rough, and is costly when forming fine wiring having a line width and a space width of 5 μm or less, for example. There was room for improvement in terms of yield.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for efficiently manufacturing a wiring layer as compared with the conventional one and a method for forming a seed layer in the process.

The method for manufacturing a wiring layer of the present invention includes the following steps in this order.
(A) A step of forming an insulating material layer on a support substrate.
(B) A step of irradiating the surface of the insulating material layer with ultraviolet rays in the presence of oxygen.
(C) A step of adsorbing a catalyst of 1 × 10 ^-5 to 100 × 10 ^-5 mol / m ² on the surface of the insulating material layer.
(D) A step of forming a seed layer on the surface of the insulating material layer by electroless plating.
(E) A step of forming a resist pattern having an opening for forming a wiring pattern on the surface of the seed layer.
(F) A step of forming a metal layer by electrolytic plating on the surface of the seed layer and exposed from the resist pattern.
(G) A step of removing a resist pattern.
(H) A step of removing the seed layer exposed by removing the resist pattern and the catalyst between the seed layer and the insulating material layer.

According to the above manufacturing method, ozone is generated by irradiation with ultraviolet rays in the presence of oxygen in step (B), and the surface of the insulating material layer can be treated with ultraviolet rays and ozone. This treatment (hereinafter, sometimes referred to as "ultraviolet-ozone treatment") finely roughens the surface of the insulating material layer and forms a site on the surface of the insulating material layer to which a catalyst (for example, a palladium catalyst) is adsorbed. do. The amount of catalyst adsorption in the step (C) can be controlled by the degree of the treatment in the step (B) (for example, the treatment time and the amount of ultraviolet irradiation). The amount of catalyst adsorbed (1 × ^10-5 to 100 × ^10-5 mol / m ² ) in the step (C) is an amount suitable for the insulating material layer after the ultraviolet-ozone treatment in the step (B) and is a conventional amount. This amount is smaller than the amount of catalyst adsorption in the semi-additive method. By setting the amount of catalyst adsorbed to an appropriate range, a seed layer can be sufficiently formed on the surface of the insulating material layer by electroless plating, and by carrying out step (H), the residual amount of catalyst in the insulating material layer can be sufficiently formed. Can be sufficiently reduced. By sufficiently reducing the residual amount of the catalyst, it is possible to sufficiently suppress the precipitation of metal in unnecessary portions in the subsequent steps. The residual amount of the catalyst in the region of the insulating material layer treated in the step (H) is preferably 1 × 10 ^-5 to 1 × 10 ^-8 mol / m ² . When the surface of the insulating material layer is roughened with the liquid used for the desmear treatment, the amount of catalyst adsorbed by the subsequent treatment is usually 1 × 10 ^{-2-1 × 10 -3 mol} / m. It is in the range of ² .

The ultraviolet-ozone treatment in the step (B) finely roughens the surface of the insulating material layer as compared with the roughening treatment using the liquid used in the conventional desmear treatment, so that a sufficient anchor effect can be obtained and a sufficient anchor effect can be obtained. Even if fine wiring is formed on the surface, problems such as the wiring falling down in the forming process can be sufficiently suppressed. For example, by forming a resist pattern having a groove having a line width of 0.5 to 20 μm on the surface of the insulating material layer as an opening for forming a wiring pattern, a wiring layer having wiring having a fine trench structure can be manufactured. Can be done.

A wiring layer having a multi-layer structure may be manufactured by the above manufacturing method. That is, after a new insulating material layer is formed so as to cover the wiring layer formed through the step (H), a series of steps from the step (B) to the step (H) is carried out once or a plurality of times. Thereby, a multi-layered wiring layer may be formed.

The present invention provides a method for forming a seed layer in the process of manufacturing a wiring layer. That is, in the method for forming the seed layer of the present invention, a step of irradiating the surface of the insulating material layer with ultraviolet rays in the presence of oxygen and a catalyst of 1 × 10 ^-5 to 100 × 10 ^-5 mol / m ² are used. It includes a step of adsorbing to the surface of the insulating material layer and a step of forming a seed layer on the surface of the insulating material layer by electroless plating.

In the present invention, the seed layer is, for example, an electroless plating layer selected from the group consisting of a copper layer, a nickel layer, a copper nickel alloy layer, a nickel phosphorus alloy layer, and a copper nickel phosphorus alloy layer. The thickness of the seed layer is preferably 0.1 to 500 nm.

In the present invention, the insulating material layer is preferably formed by using a resin composition having at least one of photosensitive and thermosetting properties. The resin composition preferably contains at least one resin selected from the group consisting of epoxy resins, phenol resins, polyamide-imide resins and photosensitive polyimide resins.

INDUSTRIAL APPLICABILITY According to the present invention, a method capable of efficiently producing a wiring layer as compared with the conventional method and a method for forming a seed layer in the process are provided.

FIG. 1A is a cross-sectional view schematically showing a state in which an insulating material layer is formed on a support substrate, and FIG. 1B is a cross-sectional view schematically showing a state in which an opening is provided in the insulating material layer. 1 (c) is a cross-sectional view schematically showing a state in which the surface of the insulating material has been activated, and FIG. 1 (d) is a cross-sectional view schematically showing a state in which the surface of the insulating material has been surface-treated. FIG. 1 (e) is a cross-sectional view schematically showing a state in which the catalyst is adsorbed on the surface of the insulating material. FIG. 2A is a cross-sectional view schematically showing a state in which a seed layer is formed by electroless plating on the surface of the insulating material and the opening, and FIG. 2B is a circuit on the seed layer formed by electroless plating. FIG. 2 (c) is a cross-sectional view schematically showing a state in which a resist pattern for formation is formed, FIG. 2 (c) is a cross-sectional view schematically showing a state in which a wiring pattern is formed by an electrolytic plating method, and FIG. 2 (d) is a cross-sectional view. It is sectional drawing which shows typically the state which the resist pattern was removed by the peeling process. FIG. 3A is a cross-sectional view schematically showing a state in which the seed layer and the catalyst are removed, and FIG. 3B is a cross-sectional view schematically showing a process of forming a wiring layer having a multilayer structure. 3 (c) is a cross-sectional view schematically showing a state in which UBM (underbarrier metal) is formed on the surface of the wiring formed in the via.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the same or corresponding parts will be designated by the same reference numerals, and duplicate description will be omitted. In addition, the positional relationship such as up, down, left, and right shall be based on the positional relationship shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios in the drawings are not limited to the ratios shown.

When terms such as "left", "right", "front", "back", "top", "bottom", "upper", "lower" are used in the description and claims of the present specification. These are intended for explanation and do not necessarily mean that they are in this relative position forever. Further, the term "layer" includes not only a structure having a shape formed on the entire surface but also a structure having a shape partially formed when observed as a plan view.

The outline of the method for manufacturing a wiring layer according to the present embodiment will be described with reference to FIGS. 1 to 3. The method for manufacturing a wiring layer according to this embodiment includes the following steps in this order.
(A) A step of forming the insulating material layer 2 on the support substrate 1 (see FIG. 1A).
(B) A step of irradiating the surface of the insulating material layer 2 with ultraviolet rays in the presence of oxygen.
(C) A step of adsorbing a catalyst of 1 × 10 ^-5 to 100 × 10 ^-5 mol / m ² on the surface of the insulating material layer 2 (see FIG. 1 (e)).
(D) A step of forming a seed layer 5 on the surface of the insulating material layer 2 by electroless plating (see FIG. 2A).
(E) A step of forming a resist pattern 6 having an opening 6a for forming a wiring pattern on the surface of the seed layer 5 (see FIG. 2B).
(F) A step of forming a wiring 7 (metal layer) by electrolytic plating on a region 5a on the surface of the seed layer 5 exposed from the resist pattern 6 (see FIG. 2C).
(G) A step of removing the resist pattern 6 (see FIG. 2D).
(H) A step of removing the seed layer 5b exposed by removing the resist pattern 6 and the catalyst between the seed layer 5b and the insulating material layer 2 (see FIG. 3A).

According to the above manufacturing method, ozone is generated by irradiation with ultraviolet rays in the presence of oxygen in step (B), and the surface of the insulating material layer 2 can be treated with ultraviolet rays and ozone. This ultraviolet-ozone treatment finely roughens the surface of the insulating material layer 2 and forms a site on the surface of the insulating material layer 2 to which a catalyst (for example, a palladium catalyst) is adsorbed. The amount of catalyst adsorption in the step (C) can be controlled by the degree of the treatment in the step (B) (for example, the treatment time and the amount of ultraviolet irradiation).

The amount of catalyst adsorbed (1 × ^10-5 to 100 × ^10-5 mol / m ² ) in the step (C) is an amount suitable for the insulating material layer after the ultraviolet-ozone treatment in the step (B) and is a conventional amount. This amount is smaller than the amount of catalyst adsorption in the semi-additive method. When the catalyst adsorption amount is 1 × 10 ^-5 mol / m ² or more, the seed layer 5 can be sufficiently formed on the surface of the insulating material layer 2 by electroless plating, and the catalyst adsorption amount is 100 × 10 ^-5 . When it is mol / m ² or less, the residual amount of the catalyst in the insulating material layer 2 can be sufficiently reduced by the catalyst removing treatment in the step (H). The amount of catalyst adsorbed on the insulating material layer 2 is preferably 1 × 10 ^-5 to 100 × 10 ^-5 mol / m ² , and preferably 1 × 10 ^-5 to 10 × 10 ^-5 mol / m ² . Is more preferable.

The ultraviolet-ozone treatment in the step (B) finely roughens the surface of the insulating material layer 2 as compared with the roughening treatment using the liquid used for the conventional desmear treatment, so that a sufficient anchor effect can be obtained. Even if fine wiring is formed on the surface thereof, problems such as the wiring falling down in the forming process can be sufficiently suppressed. For example, by forming a resist pattern 6 having a groove portion having a line width of 0.5 to 20 μm in the opening 6a for forming a wiring pattern on the surface of the insulating material layer 2, a wiring layer having wiring having a fine trench structure can be formed. Can be manufactured. The space width of the openings 6a (the distance between two adjacent openings 6a) is also preferably in the range of 0.5 to 20 μm.

Since the residual amount of the catalyst can be sufficiently reduced by the treatment in the step (H), it is possible to sufficiently suppress the precipitation of metal in unnecessary portions in the subsequent steps. The residual amount of catalyst in the region of the insulating material layer treated in the step (H) is preferably 1 × 10 ^-5 to 1 × 10 ^-8 mol / m ² , preferably 1 × 10 ^-6 to 1 × 10. It is more preferably ^-8 mol / m ² .

In the present embodiment, as shown in FIG. 3C, the wiring layer 50 having a multi-layer structure is manufactured. That is, after the insulating material layer 12 is newly formed so as to cover the wiring layer 10 formed through the step (H), a series of steps from the step (B) to the step (H) is performed once or a plurality of times. By doing so, a multi-layered wiring layer 50 is formed.

Hereinafter, embodiments of the present invention will be described in more detail. The manufacturing method described here is suitable for manufacturing a wiring layer that requires miniaturization and multi-pinning, and is particularly suitable for a package form that requires an interposer for mixedly mounting different types of chips.

<Step (I) of forming an insulating material layer on a wiring board>
This step is a step of forming the insulating material layer 2 on the surface of the support substrate 1 (FIG. 1A). The support substrate 1 shown in the figure has a copper layer 1a formed on its surface. The support substrate 1 may have wiring and / or a pad on the surface instead of the copper layer 1a.

The type of the support substrate 1 is not particularly limited, but is a silicon plate, a glass plate, a SUS plate, a wiring board containing a glass cloth, a sealing resin containing a semiconductor element, or the like, and a wiring board having high rigidity is suitable. The thickness of the support substrate 1 is preferably in the range of 0.2 to 2.0 mm. If the thickness is thinner than 0.2 mm, handling becomes difficult, while if the thickness is thicker than 2.0 mm, the material cost tends to be high. The support substrate 1 may be in the shape of a wafer or a panel. The size is not particularly limited, but a wafer having a diameter of 200 mm, a diameter of 300 mm or a diameter of 450 mm, or a rectangular panel having a side of 300 to 700 mm is preferable.

It is preferable to use a resin composition having at least one of photosensitive and thermosetting properties for forming the insulating material layer 2. The resin composition preferably contains at least one resin selected from the group consisting of epoxy resins, phenol resins, polyamide-imide resins and photosensitive polyimide resins. Examples of the material form used for forming the insulating material layer 2 include a liquid or a film. From the viewpoint of film thickness flatness and cost, it is preferable to use a film-like material. The resin composition may contain a filler (filler), and in this case, it is preferable to use a filler having an average particle size of 500 nm or less in that fine wiring can be formed.

When a film-shaped resin composition (hereinafter, simply referred to as "resin film" in some cases) is used, it is preferable that the temperature at which the resin film is laminated to the support substrate 1 is as low as possible. That is, it is preferable that the resin film can be laminated at 40 to 120 ° C. Resin films whose laminating temperature is below 40 ° C tend to have strong tack at room temperature (about 25 ° C) and deteriorate in handleability, while resin films above 120 ° C tend to have a large warp after laminating. ..

The coefficient of thermal expansion of the insulating material layer 2 after curing is preferably 80 × 10 ^-6 / K or less from the viewpoint of suppressing warpage, and 70 × 10 ^-6 / K or less in terms of obtaining high reliability. It is more preferable to have. Further, it is preferably 20 × 10 ^-6 / K or more in terms of stress relaxation property of the insulating material and high-definition pattern.

<Step of providing an opening in the insulating material layer (II)>
This step is a step of forming the opening 2a on the surface of the insulating material layer 2 (FIG. 1 (b)). In the present embodiment, the opening 2a is formed so as to penetrate the insulating material layer 2 in the thickness direction thereof, and is composed of a bottom surface (surface of the copper layer 1a) and side surfaces (insulating material layer 2). There is. In the present embodiment, the opening 2a is formed by a photolithography process (exposure and development) when the copper pad 8 of the finally manufactured wiring layer 30 is formed of the insulating material layer 2 with a photosensitive resin material. It is preferable to form the opening 2a. Instead of the photolithography process, the insulating material layer 2 having the opening 2a may be formed by laser ablation, imprinting, or the like.

As an exposure method for the photosensitive resin material, a normal projection exposure method, a contact exposure method, a direct drawing exposure method, or the like can be used. As a developing method, it is preferable to use an alkaline aqueous solution of sodium carbonate or TMAH (tetramethylammonium hydroxide). After forming the opening 2a, the insulating material layer 2 may be further heat-cured. For example, the heating temperature is 100 ° C. to 200 ° C., and the heating time is 30 minutes to 3 hours.

When the insulating material layer 2 is made of a thermosetting resin material, examples of the opening method include laser ablation, sandblasting, and waterblasting. Of these, laser ablation is preferable from the viewpoint that a fine opening 2a can be formed. As the opening method by laser ablation, it can be formed by a CO ₂ laser, a UV-YAG laser, or the like, but from the viewpoint of cost, the opening method using a CO ₂ laser is preferable.

<Step of activating the surface of the insulating material (III)>
This step is a step of activating the surface of the insulating material layer 2 (FIG. 1 (c)). The activation treatment carried out here is carried out in combination with the reforming treatment of the next step (IV) so that the palladium catalyst can be easily adsorbed on the surface of the insulating material layer 2 in the step (V). belongs to. In this embodiment, the case where a palladium catalyst is used as the catalyst is exemplified, but a copper catalyst or a silver catalyst may be used instead of the palladium catalyst.

In the present embodiment, as a method for activating treatment, ultraviolet irradiation is carried out in the presence of oxygen (for example, in the air). Ozone is generated by irradiation with ultraviolet rays in the presence of oxygen, and the surface of the insulating material layer 2 can be treated with ultraviolet rays and ozone. This ultraviolet-ozone treatment finely roughens the surface of the insulating material layer 2 and forms a site on the surface of the insulating material layer 2 to which the palladium catalyst is adsorbed. The amount of catalyst adsorption in the step (V) can be controlled by the degree of ultraviolet-ozone treatment (for example, the treatment time of ultraviolet rays and the amount of irradiation with ultraviolet rays).

The wavelength of the ultraviolet rays used for the activation treatment is preferably 150 nm to 400 nm, more preferably 150 nm to 350 nm, and even more preferably 150 nm to 300 nm. By shortening the wavelength of activation, the effect of the activation treatment is increased, and the treatment can be performed in a short time. The ultraviolet irradiation is preferably performed at 25 ° C to 80 ° C. In order to accelerate the reactivity, 40 ° C to 80 ° C is more preferable, and 60 ° C to 80 ° C is further preferable. The ultraviolet treatment is preferably carried out in 1 to 30 minutes, more preferably 3 to 30 minutes, still more preferably 5 to 30 minutes.

<Step of surface-treating the surface of the insulating material (IV)>
This step is a step of modifying the surface of the insulating material layer 2 and the side surface of the opening 2a (FIG. 1 (d)). The reforming treatment carried out here is a pretreatment for making the surface of the insulating material layer 2 after the activation transfer treatment of the step (III) more easily adsorbed by the palladium catalyst. In addition, this pretreatment may be carried out within one year from the activation treatment of step (III). Within one year, the effect of the above ultraviolet-ozone treatment can be effectively maintained.

As the liquid used for the surface treatment, a commercially available liquid may be used, and for example, an acidic pretreatment liquid (manufactured by Atotech Co., Ltd., trade name CC231) can be used. Further, a liquid containing a surfactant may be used for the purpose of improving the wettability of the surface of the insulating material layer 2. Alternatively, a commercially available liquid may be diluted with an organic solvent or water before use.

Examples of the surface treatment method include a spray method, a dip method, a spin coating method, a printing method and the like, and a dip method capable of efficient treatment is preferable. The surface treatment is preferably performed at 25 to 80 ° C. In order to accelerate the reactivity, 40 ° C to 80 ° C is more preferable, and 60 to 80 ° C is further preferable. The surface treatment is preferably performed in 5 to 30 minutes. 10 to 30 minutes is more preferable, and 15 to 30 minutes is even more preferable.

After performing the surface treatment, it may be washed with water or an organic solvent in order to remove excess liquid, and then it may be washed with an alkaline aqueous solution such as an aqueous solution of sodium hydroxide or an aqueous solution of potassium hydroxide, or a commercially available alkaline treatment. The surface may be treated with a liquid (manufactured by JCU Co., Ltd., trade name ES200). The concentration of the alkaline aqueous solution is preferably 1 to 30% by mass, more preferably 10 to 30% by mass. The surface treatment temperature with the alkaline aqueous solution is preferably 25 to 60 ° C, more preferably 30 to 60 ° C. The surface treatment time with the alkaline aqueous solution is preferably 1 to 30 minutes, more preferably 10 to 30 minutes.
<Step of adsorbing catalyst on the surface of insulating material (V)>
This step is a step of forming the palladium adsorption layer 4 on the surface including the opening 2a of the insulating material layer 2 that has undergone the above treatment (FIG. 1 (d)). The palladium adsorption layer 4 is composed of a palladium catalyst adsorbed on the surface including the opening 2a of the insulating material layer 2. This palladium catalyst serves as a catalyst for the electroless plating reaction in the step (VI) after undergoing an activation treatment for acting as a catalyst.

A commercially available palladium catalyst solution for electroless plating may be used for forming the palladium adsorption layer 4. By immersing the insulating material layer 2 in the palladium catalyst solution, the palladium catalyst can be adsorbed on the surface of the insulating material layer 2. The temperature of the palladium catalyst solution at this time is, for example, 25 to 80 ° C., and the immersion time is, for example, 1 minute to 60 minutes. After adsorbing the palladium catalyst, it may be washed with water or an organic solvent to remove the excess palladium catalyst.

After adsorbing the palladium catalyst, activation is performed so that palladium acts as a catalyst. A commercially available activator (activation treatment liquid) may be used for the activation treatment of palladium. By immersing the insulating material layer 2 in the activation treatment liquid, the palladium catalyst adsorbed on the surface of the insulating material layer 2 can be activated. The temperature of the activation treatment liquid at this time is, for example, 25 to 80 ° C., and the immersion time is, for example, 1 to 60 minutes. After activation of the palladium catalyst, it may be washed with water or an organic solvent in order to remove excess activation treatment liquid.

<Step of forming a seed layer (VI)>
This step is a step of forming the seed layer 5 by electroless plating on the surface including the opening 2a of the insulating material layer 2 on which the palladium adsorption layer 4 is formed (FIG. 2A). The seed layer 5 serves as a feeding layer for electrolytic copper plating performed to form the wiring 7 in the subsequent step (VII).

The seed layer 5 is an electroless plating layer selected from the group consisting of, for example, a copper layer, a nickel layer, a copper nickel alloy layer, a nickel phosphorus alloy layer, and a copper nickel phosphorus alloy layer. From the viewpoint of cost, the material of the seed layer 5 is preferably a nickel-phosphorus alloy or a copper nickel-phosphorus alloy.

When forming a layer made of a nickel-phosphorus alloy as the seed layer 5, a commercially available plating solution may be used as the electroless plating solution. For example, a medium phosphorus type (phosphorus content: 7 to 9% by mass) electroless. A nickel plating solution (manufactured by JCU Co., Ltd., trade name ELFSEED) can be used. The electroless nickel phosphorus plating is carried out in an electroless nickel phosphorus plating solution at 30 to 80 ° C.

When forming a layer made of a copper-nickel alloy as the seed layer 5, a commercially available plating solution may be used as the electroless plating solution. For example, an electroless copper nickel plating solution (manufactured by JCU Co., Ltd., trade name AISL) may be used. Can be used. Electroless copper nickel plating is performed in an electroless nickel phosphorus plating solution at 30 to 80 ° C.

The thickness of the seed layer 5 is preferably 0.1 to 500 nm, more preferably 0.1 to 400 nm, and even more preferably 0.1 to 300 nm. By setting the thickness of the seed layer to 0.1 nm or more, it is easy to form wiring with a uniform thickness in the subsequent electroplating, while by setting it to 500 nm or less, the wiring is connected to the wiring in the etching process of the seed layer 5. Excessive etching can be prevented, and fine wiring can be formed with good yield.

After electroless plating, it may be washed with water or an organic solvent in order to remove excess plating solution. After electroless plating, thermal curing (annealing: aging hardening treatment by heating) may be performed in order to enhance the adhesion between the seed layer 5 and the insulating material layer 2. The thermosetting temperature is preferably 80 to 200 ° C. In order to accelerate the reactivity, 120 to 200 ° C. is more preferable, and heating at 120 to 180 ° C. is further preferable. The thermosetting time is preferably 5 to 60 minutes, more preferably 10 to 60 minutes, still more preferably 20 to 60 minutes.

<Step of forming a resist pattern on the seed layer (VII)>
This step is a step of forming a resist pattern 6 for circuit formation on the seed layer 5 (FIG. 2 (b)).

The resist for circuit formation may be a commercially available resist, and for example, a negative film-like photosensitive resist (Phototec RY-5107 manufactured by Hitachi Kasei Co., Ltd.) can be used. First, a circuit-forming resist is formed so as to cover the seed layer 5 using a commercially available roll laminator. Next, the photo tool on which the pattern is formed is brought into close contact with the photo tool, exposed using an exposure machine, and then spray-developed with an aqueous sodium carbonate solution to form a resist pattern.

The opening 6a of the resist pattern 6 preferably corresponds to a trench structure having a groove having a line width of 0.5 to 20 μm. By forming such a resist pattern 6, a wiring board that realizes high density can be manufactured.

<Forming wiring by electroplating (VIII)>
This step is a step (VIII) of forming a wiring 7 (metal layer, for example, a copper layer) on the seed layer 5 by electrolytic plating (for example, electrolytic copper plating) (FIG. 2 (c)). By using the seed layer 5 as the feeding layer, the wiring 7 is formed in the opening 6a, and the metal layer 8a is formed in the opening 2a.

<Step of peeling off resist pattern (IX)>
This step is a step of peeling off the resist pattern 6 on the seed layer 5 (FIG. 2 (d)). As the peeling liquid, a commercially available one may be used, and for example, an amine-based etching liquid (manufactured by Mitsubishi Gas Chemical Company, R-100) or a 2.38% TMAH aqueous solution can be used.

<Step of removing the seed layer and the palladium catalyst (X)>
This step is a step of removing the seed layer 5b exposed by peeling of the resist pattern 6 and the palladium catalyst under the seed layer 5b (FIG. 3A). As the removing liquid for removing the seed layer 5b and the palladium catalyst, a commercially available one may be used, and examples thereof include an acidic etching liquid (BB-20, PJ-10, SAC-700W3C manufactured by JCU). ..

<Process of multi-layering wiring layer (XI)>
This step is a step of forming the wiring layers into multiple layers by further forming the wiring layers 20 and 30 on the surface of the wiring layer 10 formed through the above step (X) (FIG. 3B). In the present embodiment, after the insulating material layer 22 is newly formed so as to cover the wiring layer 10 formed through the step (X), a series of steps from the step (II) to the step (X) is performed in 2 steps. By repeating this process, a wiring layer having a three-layer structure is formed.

<Step of forming UBM on copper pad (XII)>
This step is a step of forming UBM 9 by performing gold plating with electroless nickel on the copper pad 8 formed through the step (XI) (FIG. 3 (c)). The plating thickness is not particularly limited, but the nickel plating thickness is preferably 1 to 10 μm, and the gold plating thickness is preferably about 0.1 μm.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments and may be appropriately modified without departing from the spirit of the present invention.

The present invention will be described in more detail with reference to the following examples, but the present invention is not limited to these examples.

<Manufacturing of resin film>
The following three types of photosensitive resin compositions were prepared as the resin compositions used for forming the insulating material layer.

(Photosensitive resin composition A)
The following ingredients were used.
-Photoreactive resin containing a carboxyl group and an ethylenically unsaturated group: Acid-modified cresol novolac type epoxy acrylate (CCR-1219H, manufactured by Nippon Kayaku Co., Ltd., trade name) 70 parts by mass-Photopolymerization initiator component : 2,4,6-trimethylbenzoyl-diphenyl-phosphinoxide (Darocure TPO, manufactured by Ciba Japan, trade name) and etanone, 1- [9-ethyl-6- (2-methylbenzoyl) -9H-carbazole -3-Il]-, 1- (o-Acetyloxym) (Irgacure OXE-02, manufactured by Ciba Japan, trade name) 5.6 parts by mass-heat-curing agent component: biphenol type epoxy resin (YX-4000, 20 parts by mass, inorganic filler component: silica filler (average particle size: 50 nm, silane coupling treated with vinyl silane)

The inorganic filler component was blended so as to be 10 parts by volume with respect to 100 parts by volume of the resin content. The particle size distribution was measured using a dynamic light scattering nanotrack particle size distribution meter "UPA-EX150" (manufactured by Nikkiso Co., Ltd.) and a laser diffraction scattering microtrack particle size distribution meter "MT-3100" (manufactured by Nikkiso Co., Ltd.). It was confirmed by measurement that the maximum particle size was 1 μm or less.

(Photosensitive resin composition B)
-Photoreactive resin containing a carboxyl group and an ethylenically unsaturated group: the same as the photosensitive resin composition A 70 parts by mass-Photopolymerization initiator component: the same as the photosensitive resin composition A 5. 6 parts by mass ・ Heat curing agent component: Same as the photosensitive resin composition A 20 parts by mass ・ Inorganic filler component: Barium sulfate having an average particle size of 300 nm is prepared with Star Mill LMZ (manufactured by Ashizawa Finetech Co., Ltd.) in diameter. Prepared by dispersing 1.0 mm zirconia beads at a peripheral speed of 12 m / s for 3 hours. The particle size distribution was measured using the same equipment as above, and it was confirmed that the maximum particle size was 2 μm. The inorganic filler component was blended so as to be 10 parts by volume with respect to 100 parts by volume of the resin content.

(Photosensitive resin composition C)
-Photoreactive resin containing a carboxyl group and an ethylenically unsaturated group: the same as the photosensitive resin composition A 70 parts by mass-Photopolymerization initiator component: the same as the photosensitive resin composition A 5. 6 parts by mass ・ Heat curing agent component: Same as photosensitive resin composition A ・ Inorganic filler component: Crystalline silica with an average particle size of 1 μm is prepared by Star Mill LMZ (manufactured by Ashizawa Finetech Co., Ltd.) with a diameter of 1. It was prepared by dispersing in 0 mm zirconia beads at a peripheral speed of 12 m / s for 3 hours. The particle size distribution was measured using the same equipment as above, and it was confirmed that the maximum particle size was 10 to 15 μm. The inorganic filler component was blended so as to be 10 parts by volume with respect to 100 parts by volume of the resin content.

Each solution of the photosensitive resin compositions A to C obtained as described above was applied onto the surface of a polyethylene terephthalate film (G2-16, manufactured by Teijin Limited, trade name, thickness: 16 μm). They were dried at 100 ° C. for about 10 minutes using a hot air convection dryer to obtain three types of resin films A to C. The thickness of each of these resin films was 15 μm.

<Manufacturing of wiring layer>
As a support substrate, a wiring board containing a glass cloth (size: 200 mm square, thickness: 1.5 mm) was prepared. A copper layer was formed on the surface of this wiring board, and the thickness thereof was 20 μm.

Resin films A to C were laminated on the surface of the copper layer of the wiring board. Specifically, first, the polyethylene terephthalate film was peeled off from the resin film, and the resin film was placed on the surface of the copper layer of the wiring board. Then, it was pressed using a press-type vacuum laminator (MVLP-500, manufactured by Meiki Co., Ltd.). The pressing conditions were a press hot plate temperature of 80 ° C., a vacuum drawing time of 20 seconds, a laminating press time of 60 seconds, an atmospheric pressure of 4 kPa or less, and a crimping pressure of 0.4 MPa.

Next, the resin film after pressing was subjected to an exposure treatment and a development treatment to provide an opening extending to the copper layer of the wiring board. The exposure was performed by adhering a photo tool with a pattern formed on a resin film and using a mask exposure machine (EXM-1201 type exposure machine, manufactured by ORC Manufacturing Co., Ltd.) with an energy amount of 300 mJ / cm ² . .. Next, spray development was performed for 90 seconds with a 1% by mass sodium carbonate aqueous solution at 30 ° C. to provide an opening 2a. Next, the surface of the insulating material layer after development was subjected to post-UV exposure with an energy amount of 2000 mJ / cm ² using a mask exposure machine (EXM-1201 type exposure machine, manufactured by ORC Manufacturing Co., Ltd.). Then, it was heat-cured at 180 ° C. for 1 hour in a clean oven.

The laminates (3 types) of the resin films (A to C) obtained as described above and the wiring board were cut into a size of 40 mm × 40 mm. Next, the surface of the resin film was subjected to ultraviolet treatment (activation treatment) using an ultraviolet irradiation device (SSP-16, manufactured by Sen Special Light Source Co., Ltd.). The distance from the ultraviolet lamp to the surface of the photosensitive insulating material was set to 40 mm. As shown in Tables 1 to 4, in the examples, the irradiation time of ultraviolet rays was set to 1 minute, 3 minutes or 5 minutes, and in the comparative examples, the irradiation time of ultraviolet rays was set to 0.1 minutes or 10 minutes.

Next, electroless nickel plating (modification of the surface of the resin film, adsorption of palladium catalyst, activation of palladium catalyst and electroless plating) was performed on the surface of the resin film as follows. First, it was immersed in a 40 mL / L aqueous solution of a cleaner (manufactured by JCU, trade name: ES-100) at 50 ° C. for 2 minutes, and then immersed in pure water for 1 minute. Next, it was immersed in a 70 mL / L aqueous solution of a modifier (manufactured by JCU, trade name: ES-200) at 50 ° C. for 2 minutes, and then immersed in pure water for 1 minute (reform treatment). Next, it was immersed in a 100 mL / L aqueous solution of an activator (manufactured by JCU, trade name: ES-300) at 50 ° C. for 2 minutes, and then immersed in pure water for 1 minute (palladium catalyst adsorption). Next, as an accelerator, it was immersed in a 10 mL / L aqueous solution of JCU's trade name: ES-400A at 40 ° C. for 2 minutes in an aqueous solution of JCU's trade name: ES-400B added at 14 g / L, and then in pure water. Soaked for 1 minute (activation of palladium catalyst). The Pd adsorption amount was calculated using an EDX measuring device (EDX-7000 manufactured by Shimadzu Corporation). The integration time was 6 minutes and the measurement temperature was room temperature. Next, as electroless nickel plating, JCU product name: ES-500M has a building bath concentration of 45 mL / L, JCU product name: ES-500C has a building bath concentration of 45 mL / L, and JCU product name: ES. -500B was added to a building bath concentration of 30 mL / L, ammonia water was added to 24 mL / L, and JCU's trade name: ES-500D was added to a building bath concentration of 40 mL / L in this order. Then, sulfuric acid was added so that the pH became 8.5. It was immersed in the obtained aqueous solution at 40 ° C. for 5 minutes, then immersed in pure water for 1 minute, and heated at 150 ° C. for 10 minutes in the air using an oven. The test example in which the film was formed by electroless plating was evaluated as "○", and the test example in which the film could not be formed was evaluated as "x".

Next, using a vacuum laminator (manufactured by Nikko Morton Co., Ltd., V-160), a resist for circuit formation (manufactured by Hitachi Kasei Co., Ltd., RY-5107UT) was placed on a resin film (40 mm × 40 mm) on which electroless nickel was formed. ) Was vacuum laminated. The laminating temperature was 110 ° C., the laminating time was 60 seconds, and the laminating pressure was 0.5 MPa. After vacuum laminating, it was left to stand for one day, and the resist for circuit formation was exposed using an i-line stepper (UPL-101, manufactured by Ushio, Inc.). The exposure amount was 140 mJ / cm ² , and the focus was -15 μm. After the exposure, the film was left to stand for one day, the protective film of the resist for circuit formation was peeled off, and the film was developed using a spray developing machine (AD-3000 manufactured by Mikasa). The developer was a 1.0% aqueous sodium carbonate solution, the development temperature was 30 ° C., and the spray pressure was 0.14 MPa.

Next, as a cleaner (manufactured by Okuno Pharmaceutical Industry Co., Ltd., trade name: ICP Clean S-135), it is immersed in a 100 mL / L aqueous solution at 50 ° C. for 1 minute, immersed in pure water at 50 ° C. for 1 minute, and immersed in pure water at 25 ° C. It was immersed for 1 minute and immersed in a 10% aqueous sulfuric acid solution at 25 ° C. for 1 minute. Next, in an aqueous solution of 120 g / L of copper sulfate pentahydrate and 220 g / L of 96% sulfuric acid, 0.25 mL of hydrochloric acid, 10 mL of the trade name of Okuno Pharmaceutical Co., Ltd .: Top Lucina GT-3, Okuno Pharmaceutical An industrial trade name: A seed layer was formed by electroplating an aqueous solution containing 1 mL of Toplucina GT-2 at 25 ° C. and a current density of 1.5 A / dm ² for 10 minutes. Then, it was immersed in pure water at 25 ° C. for 5 minutes and dried on a hot plate at 80 ° C. for 5 minutes.

Next, a circuit-forming resist was peeled off using a spray developer (AD-3000 manufactured by Mikasa). The peeling liquid was a 2.38% TMAH aqueous solution, the peeling temperature was 40 ° C., and the spray pressure was 0.2 MPa.

Next, the nickel and palladium catalysts, which are the seed layers, were removed. For nickel etching, use in ST-NI aqueous solution (manufactured by JCU, ST-NI A: 100 mL / L, ST-NI B: 10 mL / L, ST-40A: 75 mL / L, 35% hydrogen peroxide solution 60 mL / L). It was immersed at 35 ° C. for 1 minute. Next, as a removal of the palladium catalyst, it was immersed in an FL aqueous solution (manufactured by JCU, FL-A: 500 mL / L, FL-B: 40 mL / L) at 50 ° C. for 1 minute. The residual amount of Pd was calculated using an EDX measuring device (EDX-7000 manufactured by Shimadzu Corporation). The integration time was 6 minutes and the measurement temperature was room temperature.

Next, electroless nickel was applied to the surface of the wiring layer in which the copper wiring was formed. The substrate with copper wiring after removing palladium is immersed in a 200 mL / L aqueous solution (manufactured by World Metal Co., Ltd., trade name: Z-200) as an acidic degreasing solution at 50 ° C. for 1 minute, and then immersed in pure water at 50 ° C. for 1 minute. It was immersed in pure water at 25 ° C. for 1 minute, immersed in a 10% aqueous sulfuric acid solution at 25 ° C. for 1 minute, and immersed in pure water at 25 ° C. for 1 minute. Next, it was immersed in a 100 mL / L aqueous solution of a substituted palladium plating solution (Meltex, Inc., Meltex Activator 350) at 25 ° C. for 5 minutes, and then immersed in pure water at 25 ° C. for 1 minute. Next, it was immersed in an electroless nickel plating solution aqueous solution (ICP Nicolon-GM-SD-1: 50 mL / L, ICP Nicolon-GM-SD-M: 120 mL / L, manufactured by Okuno Pharmaceutical Industry Co., Ltd.) at 80 ° C. for 1 minute. .. A test example in which nickel was not deposited between the L / S 2 μm / 2 μm wiring was evaluated as “absent”, and a test example in which nickel was deposited was evaluated as “presence”.

Tables 1 and 2 show the results of Examples and Comparative Examples of the resin film A (photosensitive resin composition A).

Tables 3 and 4 show the results of Examples and Comparative Examples of the resin film B (photosensitive resin composition B).

Tables 5 and 6 show the results of Examples and Comparative Examples of the resin film C (photosensitive resin composition C).

1 ... Support substrate, 2 ... Insulation material layer, 4 ... Palladium adsorption layer, 5,5b ... Seed layer, 6 ... Resist pattern, 6a ... Opening for wiring pattern formation, 7 ... Wiring (metal layer), 10 ... Wiring Layer, 50 ... Multi-layered wiring layer

Claims (13)

(A) The process of forming the insulating material layer on the support substrate and
(B) A step of irradiating the surface of the insulating material layer with ultraviolet rays in the presence of oxygen,
(C) A step of adsorbing a catalyst of 1 × 10 ^-5 to 100 × 10 ^-5 mol / m ² on the surface of the insulating material layer, and
(D) A step of forming a seed layer on the surface of the insulating material layer by electroless plating, and
(E) A step of forming a resist pattern having an opening for forming a wiring pattern on the surface of the seed layer, and a step of forming the resist pattern.
(F) A step of forming a metal layer by electrolytic plating on the surface of the seed layer and exposed from the resist pattern.
(G) The step of removing the resist pattern and
(H) A step of removing the seed layer exposed by removing the resist pattern and the catalyst between the seed layer and the insulating material layer.
A method of manufacturing a wiring layer, including in this order. The method for manufacturing a wiring layer according to claim 1, wherein the resist pattern has a groove having a line width of 0.5 to 20 μm in the opening for forming the wiring pattern. The production of the wiring layer according to claim 1 or 2, wherein the seed layer is a electroless plating layer selected from the group consisting of a copper layer, a nickel layer, a copper nickel alloy layer, a nickel phosphorus alloy layer, and a copper nickel phosphorus alloy layer. Method. The method for manufacturing a wiring layer according to any one of claims 1 to 3, wherein the seed layer has a thickness of 0.1 to 500 nm. The method for manufacturing a wiring layer according to any one of claims 1 to 4, wherein the catalyst is a palladium catalyst. (H) According to any one of claims 1 to 5, the residual amount of catalyst in the region of the insulating material layer treated with the step (H) is 1 × 10 ^-5 to 1 × 10 ^-8 mol / m ² . The method for manufacturing the wiring layer described. The method for manufacturing a wiring layer according to any one of claims 1 to 6, wherein the insulating material layer is formed by using a resin composition having at least one of photosensitive and thermosetting properties. The method for producing a wiring layer according to claim 7, wherein the resin composition contains at least one resin selected from the group consisting of an epoxy resin, a phenol resin, a polyamide-imide resin, and a photosensitive polyimide resin. After a new insulating material layer is formed so as to cover the wiring layer formed through the step (H), a series of steps from the step (B) to the step (H) is carried out once or a plurality of times. The method for manufacturing a wiring layer according to any one of claims 1 to 8, wherein a multi-layered wiring layer is formed. The process of irradiating the surface of the insulating material layer with ultraviolet rays in the presence of oxygen,
A step of adsorbing a catalyst of 1 × 10 ^-5 to 100 × 10 ^-5 mol / m ² on the surface of the insulating material layer, and
A step of forming a seed layer on the surface of the insulating material layer by electroless plating, and
A method for forming a seed layer, including. The method for forming a seed layer according to claim 10, wherein the seed layer is a electroless plating layer selected from the group consisting of a copper layer, a nickel layer, a copper nickel alloy layer, a nickel phosphorus alloy layer, and a copper nickel phosphorus alloy layer. The method for forming a seed layer according to claim 10 or 11, wherein the thickness of the seed layer is 0.1 to 500 nm. The method for forming a seed layer according to any one of claims 10 to 12, wherein the catalyst is a palladium catalyst.

Images