JP2018073414A5 - - Google Patents

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JP2018073414A5
JP2018073414A5 JP2017204599A JP2017204599A JP2018073414A5 JP 2018073414 A5 JP2018073414 A5 JP 2018073414A5 JP 2017204599 A JP2017204599 A JP 2017204599A JP 2017204599 A JP2017204599 A JP 2017204599A JP 2018073414 A5 JP2018073414 A5 JP 2018073414A5
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Japan
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memory devices
memory
work
workflow
devices
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JP2017204599A
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Japanese (ja)
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JP2018073414A (ja
JP6920170B2 (ja
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Priority claimed from US15/595,887 external-priority patent/US10732866B2/en
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JP2017204599A 2016-10-27 2017-10-23 プロセッサ、及び複数のメモリ装置を含む分散計算システム内のワークフローを制御する方法 Active JP6920170B2 (ja)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US201662413977P 2016-10-27 2016-10-27
US201662413973P 2016-10-27 2016-10-27
US62/413,977 2016-10-27
US62/413,973 2016-10-27
US201662414426P 2016-10-28 2016-10-28
US62/414,426 2016-10-28
US201762485370P 2017-04-13 2017-04-13
US62/485,370 2017-04-13
US15/595,887 2017-05-15
US15/595,887 US10732866B2 (en) 2016-10-27 2017-05-15 Scaling out architecture for DRAM-based processing unit (DPU)

Publications (3)

Publication Number Publication Date
JP2018073414A JP2018073414A (ja) 2018-05-10
JP2018073414A5 true JP2018073414A5 (enExample) 2020-12-03
JP6920170B2 JP6920170B2 (ja) 2021-08-18

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JP2017204599A Active JP6920170B2 (ja) 2016-10-27 2017-10-23 プロセッサ、及び複数のメモリ装置を含む分散計算システム内のワークフローを制御する方法

Country Status (5)

Country Link
US (3) US10732866B2 (enExample)
JP (1) JP6920170B2 (enExample)
KR (1) KR102253582B1 (enExample)
CN (1) CN108009119B (enExample)
TW (1) TWI714803B (enExample)

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US10884664B2 (en) * 2019-03-14 2021-01-05 Western Digital Technologies, Inc. Executable memory cell
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