TWI714803B - 處理器及控制工作流的方法 - Google Patents

處理器及控制工作流的方法 Download PDF

Info

Publication number
TWI714803B
TWI714803B TW106130360A TW106130360A TWI714803B TW I714803 B TWI714803 B TW I714803B TW 106130360 A TW106130360 A TW 106130360A TW 106130360 A TW106130360 A TW 106130360A TW I714803 B TWI714803 B TW I714803B
Authority
TW
Taiwan
Prior art keywords
memory
dpu
workflow
task
host
Prior art date
Application number
TW106130360A
Other languages
English (en)
Chinese (zh)
Other versions
TW201816595A (zh
Inventor
牛迪民
李双辰
巴布 布瑞南
克里希納 Ｔ． 馬拉迪
郑宏忠
Original Assignee
南韓商三星電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南韓商三星電子股份有限公司 filed Critical 南韓商三星電子股份有限公司
Publication of TW201816595A publication Critical patent/TW201816595A/zh
Application granted granted Critical
Publication of TWI714803B publication Critical patent/TWI714803B/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/067—Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Human Computer Interaction (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Software Systems (AREA)
  • Databases & Information Systems (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
TW106130360A 2016-10-27 2017-09-06 處理器及控制工作流的方法 TWI714803B (zh)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US201662413977P 2016-10-27 2016-10-27
US201662413973P 2016-10-27 2016-10-27
US62/413,977 2016-10-27
US62/413,973 2016-10-27
US201662414426P 2016-10-28 2016-10-28
US62/414,426 2016-10-28
US201762485370P 2017-04-13 2017-04-13
US62/485,370 2017-04-13
US15/595,887 2017-05-15
US15/595,887 US10732866B2 (en) 2016-10-27 2017-05-15 Scaling out architecture for DRAM-based processing unit (DPU)

Publications (2)

Publication Number Publication Date
TW201816595A TW201816595A (zh) 2018-05-01
TWI714803B true TWI714803B (zh) 2021-01-01

Family

ID=62021367

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106130360A TWI714803B (zh) 2016-10-27 2017-09-06 處理器及控制工作流的方法

Country Status (5)

Country Link
US (3) US10732866B2 (enExample)
JP (1) JP6920170B2 (enExample)
KR (1) KR102253582B1 (enExample)
CN (1) CN108009119B (enExample)
TW (1) TWI714803B (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11163707B2 (en) * 2018-04-23 2021-11-02 International Business Machines Corporation Virtualization in hierarchical cortical emulation frameworks
EP3798850B1 (en) * 2018-06-27 2025-11-19 Shanghai Cambricon Information Technology Co., Ltd On-chip code breakpoint debugging method, on-chip processor, and chip breakpoint debugging system
US10915470B2 (en) * 2018-07-23 2021-02-09 SK Hynix Inc. Memory system
WO2020078470A1 (zh) * 2018-10-18 2020-04-23 上海寒武纪信息科技有限公司 片上网络数据处理方法及装置
US11327808B2 (en) * 2018-11-13 2022-05-10 Western Digital Technologies, Inc. Decentralized data processing architecture
US10884664B2 (en) * 2019-03-14 2021-01-05 Western Digital Technologies, Inc. Executable memory cell
US10884663B2 (en) 2019-03-14 2021-01-05 Western Digital Technologies, Inc. Executable memory cells
US11157692B2 (en) * 2019-03-29 2021-10-26 Western Digital Technologies, Inc. Neural networks using data processing units
CN111857061A (zh) * 2019-04-28 2020-10-30 北京国电智深控制技术有限公司 一种计算任务实现方法、装置及系统、存储介质
US12056382B2 (en) * 2020-05-26 2024-08-06 Qualcomm Incorporated Inference in memory
TWI742774B (zh) * 2020-07-22 2021-10-11 財團法人國家實驗研究院 運算系統及其主機資源分配方法
US11645111B2 (en) * 2020-10-23 2023-05-09 International Business Machines Corporation Managing task flow in edge computing environment
US12197601B2 (en) * 2020-12-26 2025-01-14 Intel Corporation Hardware offload circuitry
CN116204456A (zh) * 2021-11-30 2023-06-02 华为技术有限公司 数据访问方法及计算设备
CN114201421B (zh) * 2022-02-17 2022-05-10 苏州浪潮智能科技有限公司 一种数据流处理方法、存储控制节点及可读存储介质
US20230205500A1 (en) * 2023-03-07 2023-06-29 Lemon Inc. Computation architecture synthesis
CN116069480B (zh) * 2023-04-06 2023-06-13 杭州登临瀚海科技有限公司 一种处理器及计算设备

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4068305A (en) * 1975-05-12 1978-01-10 Plessey Handel Und Investments Ag Associative processors
US5752067A (en) * 1990-11-13 1998-05-12 International Business Machines Corporation Fully scalable parallel processing system having asynchronous SIMD processing
US20050027928A1 (en) * 2003-07-31 2005-02-03 M-Systems Flash Disk Pioneers, Ltd. SDRAM memory device with an embedded NAND flash controller
US7401261B1 (en) * 2003-12-19 2008-07-15 Unisys Corporation Automatic analysis of memory operations using panel dump file
US20090164789A1 (en) * 2007-12-21 2009-06-25 Spansion Llc Authenticated memory and controller slave
US20120017037A1 (en) * 2010-04-12 2012-01-19 Riddle Thomas A Cluster of processing nodes with distributed global flash memory using commodity server technology
US20160275017A1 (en) * 2015-03-20 2016-09-22 Kabushiki Kaisha Toshiba. Memory system

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5765011A (en) 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
EP0570729A3 (en) 1992-05-22 1994-07-20 Ibm Apap i/o programmable router
EP0689712A4 (en) 1993-03-17 1997-05-28 Zycad Corp CONFIGURABLE FIELDS WITH DIRECT ACCESS MEMORY ARRANGEMENT
US5847577A (en) 1995-02-24 1998-12-08 Xilinx, Inc. DRAM memory cell for programmable logic devices
US6760833B1 (en) * 1997-08-01 2004-07-06 Micron Technology, Inc. Split embedded DRAM processor
US6026478A (en) 1997-08-01 2000-02-15 Micron Technology, Inc. Split embedded DRAM processor
JPH11338767A (ja) 1998-05-22 1999-12-10 Mitsubishi Heavy Ind Ltd 画像処理用機能メモリ装置
US6424658B1 (en) 1999-01-29 2002-07-23 Neomagic Corp. Store-and-forward network switch using an embedded DRAM
AU5490200A (en) 1999-06-30 2001-01-31 Sun Microsystems, Inc. Active dynamic random access memory
US6555398B1 (en) * 1999-10-22 2003-04-29 Magic Corporation Software programmable multiple function integrated circuit module
US20030105799A1 (en) 2001-12-03 2003-06-05 Avaz Networks, Inc. Distributed processing architecture with scalable processing layers
EP1537486A1 (de) 2002-09-06 2005-06-08 PACT XPP Technologies AG Rekonfigurierbare sequenzerstruktur
US6947348B2 (en) 2003-07-15 2005-09-20 International Business Machines Corporation Gain cell memory having read cycle interlock
US20110026323A1 (en) 2009-07-30 2011-02-03 International Business Machines Corporation Gated Diode Memory Cells
US8478947B2 (en) * 2005-07-05 2013-07-02 Arm Limited Memory controller
US8301833B1 (en) 2007-06-01 2012-10-30 Netlist, Inc. Non-volatile memory module
US8341362B2 (en) 2008-04-02 2012-12-25 Zikbit Ltd. System, method and apparatus for memory with embedded associative section for computations
US8238173B2 (en) 2009-07-16 2012-08-07 Zikbit Ltd Using storage cells to perform computation
US8566669B2 (en) 2010-07-07 2013-10-22 Ocz Technology Group Inc. Memory system and method for generating and transferring parity information
US8379433B2 (en) 2010-09-15 2013-02-19 Texas Instruments Incorporated 3T DRAM cell with added capacitance on storage node
US20140247673A1 (en) 2011-10-28 2014-09-04 Naveen Muralimanohar Row shifting shiftable memory
JP6106043B2 (ja) 2013-07-25 2017-03-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US9921980B2 (en) * 2013-08-12 2018-03-20 Micron Technology, Inc. Apparatuses and methods for configuring I/Os of memory for hybrid memory modules
CN111274063B (zh) * 2013-11-07 2024-04-16 奈特力斯股份有限公司 混合内存模块以及操作混合内存模块的系统和方法
US9455020B2 (en) 2014-06-05 2016-09-27 Micron Technology, Inc. Apparatuses and methods for performing an exclusive or operation using sensing circuitry
GB2530261B (en) * 2014-09-16 2016-08-03 Ibm Memory and processor hierarchy to improve power efficiency
US9954533B2 (en) 2014-12-16 2018-04-24 Samsung Electronics Co., Ltd. DRAM-based reconfigurable logic
US9697877B2 (en) 2015-02-05 2017-07-04 The Board Of Trustees Of The University Of Illinois Compute memory
US10430618B2 (en) * 2015-10-09 2019-10-01 George Mason University Vanishable logic to enhance circuit security
CN105573959B (zh) * 2016-02-03 2018-10-19 清华大学 一种计算存储一体的分布式计算机

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4068305A (en) * 1975-05-12 1978-01-10 Plessey Handel Und Investments Ag Associative processors
US5752067A (en) * 1990-11-13 1998-05-12 International Business Machines Corporation Fully scalable parallel processing system having asynchronous SIMD processing
US20050027928A1 (en) * 2003-07-31 2005-02-03 M-Systems Flash Disk Pioneers, Ltd. SDRAM memory device with an embedded NAND flash controller
US7401261B1 (en) * 2003-12-19 2008-07-15 Unisys Corporation Automatic analysis of memory operations using panel dump file
US20090164789A1 (en) * 2007-12-21 2009-06-25 Spansion Llc Authenticated memory and controller slave
US20120017037A1 (en) * 2010-04-12 2012-01-19 Riddle Thomas A Cluster of processing nodes with distributed global flash memory using commodity server technology
US20160275017A1 (en) * 2015-03-20 2016-09-22 Kabushiki Kaisha Toshiba. Memory system

Also Published As

Publication number Publication date
KR20180046363A (ko) 2018-05-08
US12340101B2 (en) 2025-06-24
US11934669B2 (en) 2024-03-19
JP2018073414A (ja) 2018-05-10
KR102253582B1 (ko) 2021-05-18
TW201816595A (zh) 2018-05-01
CN108009119A (zh) 2018-05-08
US20180121120A1 (en) 2018-05-03
US20240211149A1 (en) 2024-06-27
JP6920170B2 (ja) 2021-08-18
US10732866B2 (en) 2020-08-04
US20200363966A1 (en) 2020-11-19
CN108009119B (zh) 2023-04-11

Similar Documents

Publication Publication Date Title
TWI714803B (zh) 處理器及控制工作流的方法
US11687763B2 (en) Method, apparatus and computer program to carry out a training procedure in a convolutional neural network
KR102860886B1 (ko) 스케줄러, 스케줄러의 동작 방법 및 이를 포함한 가속기 시스템
US8400458B2 (en) Method and system for blocking data on a GPU
US10719470B2 (en) Reconfigurable fabric direct memory access with multiple read or write elements
KR20210057184A (ko) 이종 cpu/gpu 시스템에서 데이터 흐름 신호 처리 애플리케이션 가속화
US20080059555A1 (en) Parallel application load balancing and distributed work management
US11409839B2 (en) Programmable and hierarchical control of execution of GEMM operation on accelerator
US20180181503A1 (en) Data flow computation using fifos
CN114968374B (zh) 一种基于新一代神威超级计算机的多层循环进程级和线程级协同自动优化方法
HeydariGorji et al. Stannis: Low-power acceleration of DNN training using computational storage devices
US20240370240A1 (en) Coarse-grained reconfigurable processor array with optimized buffers
JP2022068110A (ja) データ処理方法、データ処理装置及びデータ処理装置を含む電子装置
CN111656339A (zh) 存储器装置及其控制方法
US20240176759A1 (en) Machine learning parallelization method using host cpu with multi-socket structure and apparatus therefor
US12229078B2 (en) Neural processing unit synchronization systems and methods
Xiao et al. FCNNLib: An efficient and flexible convolution algorithm library on FPGAs
CN116484909A (zh) 面向人工智能芯片的矢量引擎处理方法和装置
TW202443390A (zh) 用於硬體積體電路之多集群架構
US12147381B2 (en) Cluster-based placement and routing of memory units and compute units in a reconfigurable computing grid
KR102722978B1 (ko) 뉴럴 프로세서, 뉴럴 프로세싱 장치 및 이의 클럭 게이팅 방법
KR20240095437A (ko) 가속기 상주 런타임 관리를 통한 높은 확장성의 hpc 애플리케이션들의 대기 시간 단축
KR20250118607A (ko) 분자동역학 시뮬레이션을 수행하는 전자 장치 및 그 동작 방법
CN118012623A (zh) 众核架构下的神经形态芯片的数据处理方法和处理器
Scionti et al. Future Challenges in Heterogeneity