JP2018067641A - Wiring board, semiconductor device, and method of manufacturing them - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board on which a semiconductor component that satisfies multi-layering, a high density, and a high speed is mounted.SOLUTION: A wiring board 10 having two or more insulating layers, comprises: a first insulating layer 100 that comprises first wiring 340 on its first surface; and a second insulating layer 400 arranged on its first surface. A second region where the first insulating layer is contacted with the second insulating layer has a surface roughness larger than that of a first region where the first insulating layer is contacted with the first wiring 340.SELECTED DRAWING: Figure 1

Description

Embodiments of the present disclosure relate to a wiring board, a semiconductor device, and a manufacturing method thereof.

With the downsizing and high functionality of electronic devices, the development of technology for multilayering, high density, and high speed has been promoted for semiconductor components that constitute electronic devices and also for wiring boards on which semiconductor components are mounted.

2. Description of the Related Art Conventionally, in the manufacture of multilayer electronic components including semiconductor devices, entire surface roughening treatment by liquid immersion has been performed as means for improving the adhesion of insulating materials constituting electric circuits. The roughening treatment by immersion is generally performed using an oxidizing agent, but it is difficult to study and control the roughening conditions, and a method for roughening the insulating material simply and precisely is required.

Patent Document 1 discloses a method of forming a roughened surface in a lump by sandwiching upper and lower insulating resin layers of a multilayer printed wiring board from above and below using a mold having a fine shape in a method for forming a roughened insulating resin surface. Has been. A method for improving the adhesion between the insulating resin layer and the metal wiring by changing the roughened shape according to the circuit pattern can be formed more easily by applying imprint technology. Yes.

On the other hand, with the recent increase in signal speed, it is more important to reduce transmission line loss in order to reliably propagate the signal. One cause of transmission line loss is loss due to conductor resistance (hereinafter referred to as conductor loss). In the conductor loss, particularly in the transmission of a high-frequency signal, the current concentrates on the surface of the transmission line, and the effective cross-sectional area through which the current flows decreases, so that the resistance increases and the signal attenuates (loss increases). For this reason, the roughening treatment on the surface of the transmission wiring may cause an increase in conductor resistance due to the skin effect when driven in a high frequency band, that is, an increase in conductor loss.

JP 2012-199380 A

However, in the conventional roughening method by immersion, it is difficult to change the roughened shape depending on the circuit pattern. Further, Patent Document 1 describes a method of selectively forming a roughened surface in a transmission line portion, and sufficient consideration is not given to the conductor loss of the transmission line.

An object of an embodiment of the present disclosure is to provide a wiring board and a semiconductor device that have improved reliability by a simple process.

According to an embodiment of the present disclosure, a wiring board having two or more insulating layers, the first insulating layer including the first wiring on the first surface, and the second disposed on the first surface. The second region where the first insulating layer is in contact with the second insulating layer has a larger surface roughness than the first region where the first insulating layer is in contact with the first wiring. A wiring board is provided.

The surface roughness of the second region may be an uneven structure having a height in the stacking direction of 0.01 μm or more and 3 μm or less.

As for the surface roughness of the second region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.5 or more and 1.5 or less, and the ten-point average roughness Rz _JIS is 1.5 or more and 2. It may be 5 or less.

As for the surface roughness of the first region measured based on JIS B0601-2001, the arithmetic average roughness Ra may be 0.1 or less, and the ten-point average roughness Rz _JIS may be 0.1 or less.

The wiring board further includes a first interlayer connection portion that penetrates the first insulating layer and is electrically connected to the first wiring. The first region includes a first insulating layer connected to the first interlayer connection. You may have surface roughness smaller than the 3rd area | region which touches a part.

The wiring board is further disposed on the second surface opposite to the first surface of the first insulating layer, and further includes a first electrode electrically connected to the first interlayer connection portion, and the third region has The first insulating layer may have a surface roughness smaller than that of the fourth region in contact with the first electrode.

In the first region, the bottom surface may have a surface roughness smaller than that of the side surface.

The first wiring is disposed on the first surface of the first insulating layer and extends in the first direction; the first insulating layer is disposed on the first surface; and A third wiring extending in a second direction perpendicular to the second wiring, the second wiring has a longer total extension than the third wiring, and a fifth region where the first insulating layer is in contact with the second wiring is The first insulating layer may have a surface roughness smaller than that of the sixth region in contact with the third wiring.

The first wiring is a transmission wiring, and is disposed on the first surface of the wiring board, and includes a fourth wiring that is electrically connected to a power source or a ground. The surface roughness may be smaller than the seventh region in contact with the fourth wiring.

A second interlayer connection portion that penetrates the second insulating layer and is electrically connected to the first wiring, and is disposed on a third surface of the second insulating layer opposite to the first insulating layer, A wiring board further including a fifth wiring electrically connected to the two interlayer connection portions and a second electrode electrically connected to the fifth wiring, and disposed on the third surface via a gap. A semiconductor device comprising: a semiconductor component having a third electrode electrically connected to the second electrode; and a first resin layer in contact with the third surface of the second insulating layer and embedding the semiconductor component. It may be.

A second resin layer disposed in the gap may be further provided.

The ninth region where the second insulating layer is in contact with the first resin layer has a larger surface roughness than the eighth region where the second insulating layer is in contact with the fifth wiring. The tenth region where the second insulating layer is in contact with the second resin layer may have a large surface roughness.

As for the surface roughness of the eighth region measured based on JIS B0601-2001, the arithmetic average roughness Ra may be 0.1 or less, and the ten-point average roughness Rz _JIS may be 0.1 or less.

The first insulating layer, the second insulating layer, and the first resin layer may include the same material.

The first insulating layer, the second insulating layer, and the first resin layer may include an epoxy resin.

The first resin layer may include a first filler.

The maximum particle size of the first filler may be 10 μm or more and 100 μm or less.

The first insulating layer, the second insulating layer, and the second resin layer may include the same material.

The first insulating layer, the second insulating layer, and the second resin layer may include an epoxy resin.

The second resin layer may include a second filler.

The maximum particle size of the second filler may be 1 μm or more and 10 μm or less.

The wiring substrate is disposed on a first interlayer connection portion that penetrates the first insulating layer and is electrically connected to the first wiring, and a second surface opposite to the first surface of the first insulating layer. And a first electrode that is electrically connected to the first interlayer connection portion, and may further include a solder ball that is electrically connected to the first electrode.

According to an embodiment of the present disclosure, a trench that is disposed on the first surface of the first insulating layer and has a first concavo-convex structure, and a second that is disposed on the first surface and is larger than the first concavo-convex structure. A concavo-convex structure and a through hole connected to the trench are formed, a first wiring disposed in the trench and an interlayer connection portion disposed in the through hole are formed, and a second insulating layer is formed on the first surface. A method of manufacturing a wiring board for stacking layers is provided.

A method of forming the trench, the second uneven structure, and the through-hole may be collectively formed by an imprint method.

The method of forming the trench, the second uneven structure, and the through hole may include removing the residue of the first insulating layer.

In the method of forming the first wiring and the interlayer connection portion, the first conductor is formed on the first surface so as to cover the trench, the second concavo-convex structure, and the through hole. The second conductor is formed so as to contact the body and fill the trench, the second concavo-convex structure, and the through hole, and the first conductor and the second conductor are exposed so that the second concavo-convex structure is exposed. And may be removed.

In the method of forming the first wiring and the interlayer connection portion, the first conductor is formed by a sputtering method, the second conductor is formed by an electrolytic plating method, and the second uneven structure is exposed. Thus, the first conductor and the second conductor may be removed by chemical mechanical polishing.

The second concavo-convex structure may be formed so that the height in the stacking direction is 0.01 μm or more and 3 μm or less.

As for the surface roughness of the second concavo-convex structure measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.5 or more and 1.5 or less, and the ten-point average roughness Rz _JIS is 1.5 or more and 2. You may form so that it may become 5 or less.

As for the surface roughness of the first uneven structure measured based on JIS B0601-2001, the arithmetic average roughness Ra may be 0.1 or less, and the ten-point average roughness Rz _JIS may be 0.1 or less.

Forming the first wiring includes a second wiring disposed on the first surface of the first insulating layer and extending in the first direction, and extending in a second direction orthogonal to the first direction. When the total extension of the second wiring is longer than the total extension of the third wiring, the fifth region where the first insulating layer is in contact with the second wiring is the first wiring. The insulating layer may be formed to have a surface roughness smaller than that of the sixth region in contact with the third wiring.

A wiring board is prepared, and a second interlayer connection portion that is electrically connected to the first wiring through the second insulating layer is opposite to the first insulating layer of the second insulating layer. Forming a fifth wiring electrically connected to the second interlayer connection portion and a second electrode electrically connected to the fifth wiring, the second electrode being disposed on the third surface on the side, A first resin that has a third electrode electrically connected to the first surface and is disposed on the third surface with a gap in contact with the third surface of the second insulating layer to embed the semiconductor component Forming a layer.

A second resin layer disposed in the gap may be further formed.

According to the embodiment of the present disclosure, it is possible to provide a wiring board and a semiconductor device with improved reliability by a simple process.

2A is a top view, FIG. 2B is a cross-sectional view, and FIG. 1C is an enlarged view illustrating an example of a wiring board according to an embodiment of the present disclosure. It is sectional drawing which shows an example of the manufacturing method of the wiring board which concerns on one Embodiment of this indication. 2A is a top view, FIG. 2B is a cross-sectional view, and FIG. 1C is an enlarged view illustrating an example of a wiring board according to an embodiment of the present disclosure. It is sectional drawing which shows an example of the manufacturing method of the wiring board which concerns on one Embodiment of this indication. It is (A) top view, (B) (C) sectional view, and (D) (E) enlarged view showing an example of a wiring board concerning one embodiment of this indication. It is sectional drawing which shows an example of the manufacturing method of the wiring board which concerns on one Embodiment of this indication. It is (A) top view, (B) (C) sectional view, and (D) (E) enlarged view showing an example of a wiring board concerning one embodiment of this indication. It is sectional drawing which shows an example of the manufacturing method of the wiring board which concerns on one Embodiment of this indication. It is (A) top view, (B) sectional view, and (C) (D) enlarged view showing an example of a wiring board concerning one embodiment of this indication. It is sectional drawing which shows an example of the manufacturing method of the wiring board which concerns on one Embodiment of this indication. 1A is a top view, FIG. 1B is a cross-sectional view, and FIG. 1C is an enlarged view illustrating an example of a semiconductor device according to an embodiment of the present disclosure. 6 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. (A) Scanning electron microscope (SEM) photograph on the upper surface of the insulating layer of the wiring board according to the reference example of the present disclosure, (B) Contour graph showing the uneven structure on the upper surface, and (C) Graph showing the uneven structure on the cross section It is. It is a SEM photograph in the (A) upper surface of the insulating layer of the wiring board concerning a reference example of this indication, (B) Contour graph showing the concavo-convex structure in the upper surface, and (C) Graph showing the concavo-convex structure in the section. 5A is an SEM on the upper surface of an insulating layer of a wiring board according to a reference example of the present disclosure; FIG. 5B is a contour graph showing a concavo-convex structure on the upper surface; and FIG.

Hereinafter, a wiring board, a semiconductor device, and a manufacturing method thereof according to an embodiment of the present disclosure will be described with reference to the drawings. However, the wiring board, the semiconductor device, and the manufacturing method thereof according to the embodiment of the present disclosure can be implemented in many different modes, and are limited to the description of the embodiment described below. is not. Note that in the drawings referred to in this embodiment, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted. In addition, for convenience of explanation, the description will be made using the terms “upper” or “lower”, but the vertical direction may be reversed.

<First Embodiment>
The configuration of the wiring board 10 and the method for manufacturing the wiring board 10 according to the first embodiment of the present disclosure will be described using FIG. 1 or FIG.

[Configuration of wiring board]
FIG. 1A is a top view, FIG. 1B is a cross-sectional view, and FIG. 1C is an enlarged view illustrating an example of a wiring board according to an embodiment of the present disclosure. 1B is a cross-sectional view taken along the line AA ′ in FIG. 1A, and FIG. 1C is an enlarged view in a region B in FIG. 1B. As shown in FIGS. 1A and 1B, the wiring board 10 includes a first insulating layer 100, a second insulating layer 400, and a conductor formed in each insulating layer.

The conductor of the first insulating layer 100 includes a first wiring 340, a first interlayer connection 360, and a first electrode 380. The first insulating layer 100 includes a first wiring 340 on the first surface. The first wiring 340 is electrically connected to the first interlayer connection 360 that penetrates the first insulating layer 100 at one end. In the present embodiment, the example in which one first wiring 340 is arranged on the first surface is shown, but the present invention is not limited to this. One or more first wirings 340 may be arranged on the first surface. In the present embodiment, the first wiring 340 is disposed only on the first surface of the first insulating layer 100, but the first wiring 340 is also disposed on the second surface opposite to the first surface. May be. The first interlayer connection 360 is electrically connected to the first electrode 380 on the second surface of the first insulating layer 100 opposite to the first surface.

A second insulating layer 400 is disposed on the first surface of the first insulating layer 100. The conductor of the second insulating layer 400 includes a second wiring 640, a second interlayer connection portion 660, and a second electrode 680. The second insulating layer 400 includes a second wiring 640 on the third surface opposite to the first insulating layer 100. The second wiring 640 is electrically connected to the second interlayer connection portion 660 that penetrates the second insulating layer 400. Second interlayer connection portion 660 is further electrically connected to the other end opposite to one end of first wiring 340. In the present embodiment, an example in which one second wiring 640 is arranged on the third surface is shown, but the present invention is not limited to this. One or more second wirings 640 may be arranged on the third surface. The second wiring 640 is electrically connected to the second electrode 680 on the third surface of the second insulating layer 400.

As shown in FIG. 1A, the planar shape of the first wiring 340 and the second wiring 640 is different from the first side 102 of the first insulating layer 100 and the second insulating layer 400 to the first side 102. Although the shape in which each line extends in the same direction toward the second side 104 on the opposite side is illustrated, it is not limited to this shape. For example, the planar shapes of the first wiring 340 and the second wiring 640 may extend in different directions. Further, in the case where the plurality of first wirings 340 or the second wirings 640 are arranged, some lines may intersect or some lines may be connected. In FIG. 1A, the first insulating layer 100 and the second insulating layer 400 are square, but the shape is not limited to this.

FIG. 1C is an enlarged view of a region B in FIG. As illustrated in FIG. 1C, the first insulating layer 100 is in contact with the first wiring 340, the first interlayer connection 360, and the second insulating layer 400.

In the first region where the first insulating layer 100 is in contact with the first wiring 340, the first uneven structure 140 is formed. As for the surface roughness in the first region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.1 or less, and the ten-point average roughness Rz _JIS is 0.1 or less. More preferably, the first region is substantially flat.

On the other hand, the second uneven structure 160 in the second region where the first insulating layer 100 is in contact with the second insulating layer 400 has a height in the stacking direction of 0.01 μm or more and 3 μm or less. As for the surface roughness in the second region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.5 or more and 1.5 or less, and the ten-point average roughness Rz _JIS is 1.5 or more and 2. 5 or less. The first insulating layer 100 is the second region from the first region where the first insulating layer 100 is in contact with the first wiring 340 and the third region where the first insulating layer 100 is in contact with the first interlayer connection 360. The second region in contact with the insulating layer 400 has a large surface roughness.

In the present embodiment, the first region in which the first insulating layer 100 is in contact with the first wiring 340 and the third region in which the first insulating layer 100 is in contact with the first interlayer connection 360 are small in surface roughness. Have Since the first region and the third region of the first insulating layer 100 have a small surface roughness, the first wiring 340 and the first interlayer connection portion 360 are separated from the first insulating layer 100. The contact area has a small surface roughness. The rough surface on the surface of the conductor can cause an increase in conductor resistance due to the skin effect when driven in a high frequency band, that is, an increase in conductor loss. Therefore, it is possible to provide a wiring board having improved transmission characteristics in a high frequency band by having a small surface roughness in a region where the first wiring 340 and the first interlayer connection 360 are in contact with the first insulating layer 100. Can do.

In the present embodiment, the second region where the first insulating layer 100 is in contact with the second insulating layer 400 has the second uneven structure 160. When the first insulating layer 100 has the second uneven structure 160 in the second region, the uneven structure is also formed in the region of the second insulating layer 400 in contact with the first insulating layer 100. The uneven structure of the second insulating layer 400 is formed so as to fit into the second uneven structure 160 of the first insulating layer 100. By adhering the second concavo-convex structure 160 of the first insulating layer 100 and the concavo-convex structure of the second insulating layer 400 so as to mesh with each other, the adhesion can be improved. As a result, a wiring board with improved reliability can be provided.

In the present embodiment, the wiring board 10 includes two insulating layers and a conductor formed on each insulating layer. The first insulating layer is in contact with the second insulating layer from the first region where the first insulating layer is in contact with the first wiring and the third region where the first insulating layer is in contact with the first interlayer connection portion. The second region has a large surface roughness. However, the present invention is not limited to this. For example, the wiring board may include m insulating layers and a conductor formed on each insulating layer. In this case, the region where the nth insulating layer is in contact with the (n + 1) th insulating layer is larger than the region where the nth insulating layer is in contact with the nth wiring and the region where the nth insulating layer is in contact with the nth interlayer connection portion. You may have surface roughness. (M is an arbitrary natural number of 3 or more, and n is an arbitrary natural number of 1 or more and m-1 or less.)

When the wiring board includes three or more insulating layers and a conductor formed on each insulating layer, the n-th insulating layer may be included in plural or a combination of arbitrary layers. A plurality of insulating layers have a larger surface roughness in a region where the insulating layers are in contact with each other than a region where the insulating layers are in contact with the wiring and a region where the insulating layer is in contact with the interlayer connection portion, thereby further improving the adhesion between the insulating layers. Can do. As a result, a wiring board with further improved reliability can be provided.

In the present embodiment, the second insulating layer, which is the uppermost layer, also includes the second insulating layer from the region where the second insulating layer is in contact with the second wiring and the region where the second insulating layer is in contact with the second interlayer connection portion. The region where the insulating layer is exposed on the uppermost surface has a large surface roughness. The uppermost insulating layer has a larger surface roughness than the region where the insulating layer is in contact with the wiring and the region where the insulating layer is in contact with the interlayer connection portion. Can be improved. As a result, a semiconductor device with further improved reliability can be provided.

In FIG. 1C, the second concavo-convex structure 160 in the second region is uniformly arranged as a quadrangular pyramid as an example. However, the present invention is not limited to this, and the second concavo-convex structure 160 in the second region may have any shape as long as it is within the range of the above conditions. The second concavo-convex structure 160 in the second region may be, for example, a polygonal pyramid shape, a polygonal frustum shape, a polygonal column shape, a conical shape, a frustoconical shape, a cylindrical shape, or a line shape, and a combination thereof. May be. The second uneven structure 160 in the second region may be a non-uniform uneven structure as long as it is within the range of the above conditions.

The width and height of the first wiring 340 and the second wiring 640 can be appropriately selected depending on the application. The width and height of the first wiring 340 and the second wiring 640 may be the same or different. The heights of the first wiring 340 and the second wiring 640 may be larger than those of the second uneven structure 160.

The material of the first insulating layer 100 and the second insulating layer 400 may be any material having electrical insulation. Examples of the material of the first insulating layer 100 and the second insulating layer 400 include, for example, an epoxy resin material, a silicone resin material, an acrylic resin material, a phenol resin material, a polyimide resin material, a polysulfone resin material, Polyester resin materials, polycarbonate resin materials, and the like can be used. The material of the first insulating layer 100 and the second insulating layer 400 is preferably an epoxy resin material. Note that the first insulating layer 100 and the second insulating layer 400 are illustrated as examples each including a single layer. However, the present invention is not limited to this, and a structure in which a plurality of base materials or layers are stacked. There may be. The material of the first insulating layer 100 and the second insulating layer 400 may be the same material or different materials.

The thickness of the 1st insulating layer 100 and the 2nd insulating layer 400 does not have a restriction | limiting in particular, According to a use, it can select suitably. If the thicknesses of the first insulating layer 100 and the second insulating layer 400 are too thin, the base material will bend, which makes handling difficult in the manufacturing process. On the other hand, if the thicknesses of the first insulating layer 100 and the second insulating layer 400 are too thick, the weight of the base material increases, and the burden on the apparatus for handling increases. Further, the thicker the first insulating layer 100 and the second insulating layer 400, the deeper the through holes for forming the interlayer connection portions that electrically connect the respective layers.

As shown in FIGS. 1B and 1C, each of the first wiring 340, the first interlayer connection 360, the second wiring 640, and the second interlayer connection 660 includes a first conductor. 200 and the second conductor 220 (hereinafter, when the first conductor 200 and the second conductor 220 are not distinguished from each other, the conductor or the first wiring 340, the first interlayer connection portion). 360, the second wiring 640, or the second interlayer connection portion 660). The first conductor 200 is disposed on the inner surface of the first trench 120. The second conductor 220 is disposed inside the first trench 120 and is in contact with the first conductor 200.

The material of the first conductor 200 and the material of the second conductor 220 may be any material having conductivity. For example, in the present embodiment, the first conductor 200 is copper formed by a sputtering method, and the second conductor 220 is copper formed by an electrolytic plating method, but is not limited thereto. As a material for the conductor, for example, gold, silver, copper, platinum, nickel, rhodium, ruthenium, iridium, or the like can be used. Further, the material of the first conductor 200 and the material of the second conductor 220 may be the same material or different materials. The materials of the first wiring 340, the first interlayer connection 360, the second wiring 640, and the second interlayer connection 660 may be the same material or different materials. Further, the material of the first wiring 340, the first interlayer connection 360, the second wiring 640, and the second interlayer connection 660 may be a single material or two or more different materials. A combination of these may be used.

The material of the first electrode 380 and the material of the second electrode 680 may be any material having conductivity. As a material for the conductor, for example, gold, silver, copper, aluminum, or the like can be used. The material of the first electrode 380 and the material of the second electrode 680 may be the same material or different materials. In the present embodiment, the first electrode 380 and the second electrode 680 are formed by stacking conductors and photolithography, but are not limited thereto.

[Method for Manufacturing Wiring Board 10]
A method of manufacturing a wiring board according to an embodiment of the present disclosure will be described using FIG. In FIG. 2, the same elements as those shown in FIG.

FIG. 2A illustrates a method for manufacturing a wiring board according to an embodiment of the present disclosure, in which a first trench 120, a second concavo-convex structure 160, and a first trench are formed in the first insulating layer 100 by imprinting. It is a figure which shows the process of forming the through-hole 180 of. First, the mold 110 for forming the first trench 120, the second uneven structure 160, and the first through hole 180 is formed in the first insulating layer 100. The mold 110 has protrusions corresponding to the first trench 120, the second concavo-convex structure 160, and the first through hole 180. The surfaces of the protrusions of the mold 110 corresponding to the first trench 120 and the first through hole 180 are formed to be substantially flat.

Next, using the mold 110, the first trench 120, the second uneven structure 160, and the first through hole 180 are imprinted on the first surface of the first insulating layer 100. Although not shown in FIG. 2, the first insulating layer 100 may be formed by coating on a substrate (not shown). In this case, the surface of the first insulating layer 100 opposite to the substrate is the first surface. The first insulating layer 100 is softened, and the mold 110 is pressed into the first surface. In this state, the first insulating layer 100 is cured, and the mold 110 is peeled from the first insulating layer 100, whereby the first insulating layer 100 having a cross-sectional structure shown in FIG. Insulating material residues may remain in the first trench 120, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100. For this reason, the residue of the insulating material is removed by performing a wet process using a permanganate solution or a dry process using oxygen plasma. By removing the residue of the insulating material, a good interlayer connection can be obtained, and a wiring board with improved reliability can be provided.

In this embodiment, the 1st trench 120, the 2nd uneven structure 160, and the 1st through-hole 180 are integrally formed by the imprint method. As a result, the manufacturing process can be simplified. In addition, the imprint method uses less chemical solution than a general photolithography method and is environmentally friendly.

A first concavo-convex structure 140 is formed on the inner surface (first region) of the first trench 120 formed in the first insulating layer 100 by an imprint method. As for the surface roughness in the first region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.1 or less, and the ten-point average roughness Rz _JIS is 0.1 or less. More preferably, the first region is substantially flat.

On the other hand, the second concavo-convex structure 160 formed on the first insulating layer 100 has a height in the stacking direction of 0.01 μm or more and 3 μm or less. When the height of the second uneven structure 160 in the stacking direction is 0.01 μm or less, it is difficult to form the mold 110 for forming the second uneven structure 160 by the imprint method. When the height of the second concavo-convex structure 160 in the stacking direction is 3 μm or more, depending on the thickness of the insulating layer, it is too deep and penetrates to the lower layer, resulting in unnecessary roughness. As for the surface roughness in the second uneven structure 160 measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.5 or more and 1.5 or less, and the ten-point average roughness Rz _JIS is 1.5 or more. 2.5 or less. The surface roughness in the second region is formed to be larger than the surface roughness in the first region and the third region.

The aspect ratio of the first trench 120 in which the first wiring 340 is disposed can be appropriately selected according to the application. Here, the aspect ratio of the first trench 120 is defined as the depth with respect to the opening width. If the aspect ratio of the first trench 120 in which the first wiring 340 is disposed is too small, it becomes difficult to form a fine pattern of the first wiring 340 on the wiring substrate 10. If the aspect ratio of the first trench 120 in which the first wiring 340 is disposed is too large, it is difficult to fill the first trench 120 with a conductor.

FIG. 2B is a diagram illustrating a process of forming the first conductor 200 on the first insulating layer 100 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. The first trench 120, the first concavo-convex structure 140, the second concavo-convex structure 160, and the first through-hole 180 of the first insulating layer 100 formed in FIG. A film is formed so as to be covered with 200. In this embodiment, copper was deposited using a sputtering method. However, the present invention is not limited to this, and the first conductor 200 may be a seed layer for filling metal by an electrolytic plating method in the next step. It may also be a seed layer and / or a barrier layer. The first conductor 200 includes the first trench 120, the first concavo-convex structure 140, the second concavo-convex structure 160, and the first through hole of the first insulating layer 100 formed in FIG. 180 is reflected. In other words, the first conductor 200 is formed along the first trench 120, the first uneven structure 140, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100. Is done. That is, the first conductor 200 has a concavo-convex structure formed in the first insulating layer 100. However, the present invention is not limited to this, and the uneven structure formed in the first insulating layer 100 may be at least partially filled with the first conductor 200.

FIG. 2C is a diagram illustrating a process of forming the second conductor 220 on the first conductor 200 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. The first trench 120, the first uneven structure 140, the second uneven structure 160, and the first through-hole 180 of the first insulating layer 100 formed in FIG. Fill with 220. In the present embodiment, the first trench 120, the first uneven structure 140, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100 are filled with copper by using an electrolytic plating method. To do. However, the present invention is not limited to this, and a method of filling the first trench 120, the first concavo-convex structure 140, the second concavo-convex structure 160, and the first through-hole 180 of the first insulating layer 100 with a metal is printing. The method can also be used.

FIG. 2D is a diagram illustrating a step of polishing the first insulating layer 100 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. As shown in FIG. 2D, the substantially entire surface of the first insulating layer 100 is polished. In the present embodiment, the surface of the first insulating layer 100 is polished using a chemical mechanical polishing method. By selectively polishing the first conductor 200 and the second conductor 220 on the first insulating layer 100, unnecessary first portions other than those in the first trench 120 and the first through-hole 180 are provided. The conductor 200 and the second conductor 220 can be removed. As a result, the second uneven structure 160 of the first insulating layer 100 is exposed. The first conductor 200 and the second conductor 220 in the first trench 120 are formed as the first wiring 340. The first conductor 200 and the second conductor 220 in the first through-hole 180 are formed as a first interlayer connection portion 360. In the present embodiment, the first wiring 340 and the first interlayer connection 360 are integrally formed, but the present invention is not limited to this. Each may be formed separately.

FIG. 2E is a diagram illustrating a process of laminating the second insulating layer 400 on the first insulating layer 100 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. In the present embodiment, the second insulating layer 400 is formed by applying on the first insulating layer 100. Here, the second insulating layer 400 is formed so as to fill the second uneven structure 160 of the first insulating layer 100 formed in FIG. That is, the second insulating layer 400 reflects the second uneven structure 160 of the first insulating layer 100. In other words, the second insulating layer 400 has an uneven structure in a region in contact with the first insulating layer 100. The second uneven structure 160 of the first insulating layer 100 and the uneven structure of the second insulating layer 400 are bonded so as to mesh with each other. By stacking the second insulating layer 400 on the first insulating layer 100, the first wiring 340 and the first interlayer connection 360 are embedded in the first insulating layer 100 and the second insulating layer 400. Is done.

FIG. 2F illustrates a method of manufacturing a wiring board according to an embodiment of the present disclosure, in which the second wiring 640 and the second wiring 640 are formed on the second insulating layer 400 by the steps of FIGS. It is a figure which shows the process of forming the interlayer connection part 660 of. Similar to the first insulating layer 100, an uneven structure, a second trench, and a second through hole are formed in the second insulating layer 400 by an imprint method, and the first conductor and the second conductor are formed. After filling with the body, polishing is performed, whereby the concavo-convex structure, the second wiring 640, and the second interlayer connection portion 660 are formed in the second insulating layer 400. In this embodiment, the manufacturing method of the wiring board provided with two insulating layers and the conductor formed in each insulating layer was shown. However, the present invention is not limited thereto, and a wiring board having two or more insulating layers can be appropriately prepared by preparing a mold having a trench having an arbitrary pattern in each layer, a through hole, and a protrusion corresponding to the concavo-convex structure. Can be formed.

FIG. 2G is a diagram illustrating a process of forming the first electrode 380 and the second electrode 680 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. In this embodiment, the second electrode 680 is formed using photolithography. However, the present invention is not limited to this. For example, the second electrode 680 may be formed integrally with the second wiring 640 and the second interlayer connection 660. In this embodiment mode, the first electrode 380 is formed by photolithography, but is not limited thereto. Although not shown in FIG. 2, the first insulating layer 100 may have a substrate (not shown) on the second surface opposite to the first surface. In this case, a step of first peeling the substrate may be included. On the second surface of the first insulating layer 100, a residue of the insulating material may remain in the first through hole 180. For this reason, the residue of the insulating material is removed by performing a wet process using a permanganate solution or a dry process using oxygen plasma. By removing the residue of the insulating material, a favorable electrode connection can be obtained, and a wiring board with improved reliability can be provided. Note that the first electrode 380 may be formed after a semiconductor component described later is disposed.

As described above, according to the method for manufacturing the wiring substrate 10 according to the present embodiment, the second concavo-convex structure 160 can be formed in the second region where the first insulating layer 100 is in contact with the second insulating layer 400. it can. In such a selective roughened surface forming method, by forming the second concavo-convex structure 160 in the first insulating layer 100, the region of the second insulating layer 400 that is in contact with the first insulating layer 100 is uneven. A structure is formed. The uneven structure of the second insulating layer 400 is formed so as to fit into the uneven structure of the first insulating layer 100. By bonding so that the concavo-convex structure of the first insulating layer 100 and the second insulating layer 400 is engaged with each other, the adhesion can be improved and peeling can be prevented. As a result, a wiring board with improved reliability can be provided.

According to the method for manufacturing the wiring substrate 10 according to this embodiment, the first region where the first insulating layer 100 is in contact with the first wiring 340 can be formed with a small surface roughness. The third region where the first insulating layer 100 is in contact with the first interlayer connection 360 can be formed with a small surface roughness. By forming the first region and the third region with a small surface roughness, the first wiring 340 and the first interlayer connection 360 have a small surface roughness where the region in contact with the first insulating layer 100 is small. Formed. The roughening treatment on the surface of the conductor can cause an increase in conductor resistance due to the skin effect when driven in a high frequency band, that is, an increase in conductor loss. Providing a wiring board with improved transmission characteristics in a high frequency band by forming a region of the first wiring 340 and the first interlayer connection 360 in contact with the first insulating layer 100 with a small surface roughness. Can do.

Second Embodiment
In the wiring substrate according to the second embodiment, the first region where the first insulating layer is in contact with the first wiring is smaller in surface roughness than the third region where the first insulating layer is in contact with the first interlayer connection portion. The third region has a smaller surface roughness than the fourth region where the first insulating layer is in contact with the first electrode, and the fourth region has the second insulating layer as the second insulating layer. It has a smaller surface roughness than the second region in contact with the layer.

The configuration of the wiring board 20 and the method for manufacturing the wiring board 20 according to the second embodiment of the present disclosure will be described with reference to FIG. 3 or FIG. Here, the detailed description of the same parts as those in the first embodiment is omitted.

[Configuration of wiring board]
3A is a top view, FIG. 3B is a cross-sectional view, and FIG. 3C is an enlarged view showing an example of a wiring board according to an embodiment of the present disclosure. 3B is a cross-sectional view taken along the line AA ′ in FIG. 3A, and FIG. 3C is an enlarged view in a region B in FIG. 3B. As shown in FIGS. 3A and 3B, the wiring board 20 includes a first insulating layer 100, a second insulating layer 400, and a conductor formed in each insulating layer.

The conductor of the first insulating layer 100 includes a first wiring 340, a first interlayer connection 360, and a first electrode 380. The first insulating layer 100 includes a first wiring 340 on the first surface. The first wiring 340 is electrically connected to the first interlayer connection 360 that penetrates the first insulating layer 100 at one end. In the present embodiment, the example in which one first wiring 340 is arranged on the first surface is shown, but the present invention is not limited to this. One or more first wirings 340 may be arranged on the first surface. In the present embodiment, the first wiring 340 is disposed only on the first surface of the first insulating layer 100, but the first wiring 340 is also disposed on the second surface opposite to the first surface. May be. The first interlayer connection 360 is electrically connected to the first electrode 380 on the second surface of the first insulating layer 100 opposite to the first surface.

A second insulating layer 400 is disposed on the first surface of the first insulating layer 100. The conductor of the second insulating layer 400 includes a second wiring 640, a second interlayer connection portion 660, and a second electrode 680. The second insulating layer 400 includes a second wiring 640 on the third surface opposite to the first insulating layer 100. The second wiring 640 is electrically connected to the second interlayer connection portion 660 that penetrates the second insulating layer 400. Second interlayer connection portion 660 is further electrically connected to the other end opposite to one end of first wiring 340. In the present embodiment, an example in which one second wiring 640 is arranged on the third surface is shown, but the present invention is not limited to this. One or more second wirings 640 may be arranged on the third surface. The second wiring 640 is electrically connected to the second electrode 680 on the third surface of the second insulating layer 400.

FIG. 3C is an enlarged view of a region B in FIG. As shown in FIG. 3C, the first insulating layer 100 is in contact with the first wiring 340, the first interlayer connection 360, the second insulating layer 400, and the first electrode 380.

In the first region where the first insulating layer 100 is in contact with the first wiring 340, the first uneven structure 140 is formed. As for the surface roughness in the first region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.1 or less, and the ten-point average roughness Rz _JIS is 0.1 or less. More preferably, the first region is substantially flat. Further, the surface roughness in the first region is smaller than the surface roughness in the third region where the first insulating layer 100 is in contact with the first interlayer connection 360. The surface roughness in the third region is smaller than the surface roughness in the fourth region where the first insulating layer 100 is in contact with the first electrode 380.

On the other hand, the second uneven structure 160 in the second region where the first insulating layer 100 is in contact with the second insulating layer 400 has a height in the stacking direction of 0.01 μm or more and 3 μm or less. As for the surface roughness in the second region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.5 or more and 1.5 or less, and the ten-point average roughness Rz _JIS is 1.5 or more and 2. 5 or less. The first region where the first insulating layer 100 is in contact with the first wiring 340, the third region where the first insulating layer 100 is in contact with the first interlayer connection 360, and the first insulating layer 100 are the first The second region in which the first insulating layer 100 is in contact with the second insulating layer 400 has a larger surface roughness than the fourth region in contact with the electrode 380.

In the present embodiment, the first region has a surface roughness smaller than that of the third region, and the third region has surface roughness smaller than that of the fourth region, so that the first wiring 340 has the first surface roughness. The first interlayer connection 360 has a surface roughness smaller than that of the first electrode 380. The rough surface of the wiring surface has a longer total extension than the rough surface of the interlayer connection portion, and has a large effect of increasing the conductor resistance due to the skin effect when driven in the high frequency band, that is, increasing the conductor loss. The rough surface of the interlayer connection portion has a longer total extension than the rough surface of the electrode, and has a large influence on the increase in conductor resistance due to the skin effect when driven in a high frequency band, that is, an increase in conductor loss. For this reason, the wiring board has improved transmission characteristics in the high frequency band by having a smaller surface roughness for a conductor that has a greater effect of causing an increase in conductor resistance due to the skin effect when driven in the high frequency band, that is, an increase in conductor loss. Can be provided.

The third region has a surface roughness larger than that of the first region, and the fourth region has surface roughness larger than that of the third region, whereby the first interlayer connection 360 is configured to have the first wiring 340. A larger surface roughness is formed, and the first electrode 380 has a surface roughness larger than that of the first interlayer connection 360. The concavo-convex structure of the first interlayer connection 360 is formed to fit into the concavo-convex structure of the third region. The uneven structure of the first electrode 380 is formed so as to fit into the uneven structure of the fourth region. Adhesion can be improved by adhering the concavo-convex structures so as to mesh with each other. By increasing the conductor resistance due to the skin effect when driven in a high frequency band, that is, the conductor having a smaller influence causing an increase in the conductor loss has a larger surface roughness, the conductor loss due to the skin effect is suppressed, and the first The adhesion between the insulating layer 100 and the conductor can be improved, and a wiring board with improved reliability can be provided.

In the present embodiment, the second region where the first insulating layer 100 is in contact with the second insulating layer 400 has the second uneven structure 160. When the first insulating layer 100 has the second uneven structure 160 in the second region, the uneven structure is also formed in the region of the second insulating layer 400 in contact with the first insulating layer 100. The uneven structure of the second insulating layer 400 is formed so as to fit into the second uneven structure 160 of the first insulating layer 100. By adhering the second concavo-convex structure 160 of the first insulating layer 100 and the concavo-convex structure of the second insulating layer 400 so as to mesh with each other, the adhesion can be improved. As a result, a wiring board with improved reliability can be provided.

In the present embodiment, the wiring board 20 includes two insulating layers and a conductor formed on each insulating layer. In the first insulating layer 100, the third region has a larger surface roughness than the first region, the fourth region has a larger surface roughness than the third region, and the second region has the fourth surface roughness. Surface roughness greater than However, the present invention is not limited to this. For example, the wiring board may include m insulating layers and a conductor formed on each insulating layer. Also in this case, in the first insulating layer 100, the third region has a surface roughness larger than the first region, the fourth region has a surface roughness larger than the third region, and the second region The region has a greater surface roughness than the fourth region. Further, in the nth insulating layer, a region where the nth insulating layer is in contact with the (n + 1) th insulating layer has a surface roughness larger than a region where the nth insulating layer is in contact with the nth interlayer connection portion, The region where the n insulating layer is in contact with the nth interlayer connection may have a surface roughness greater than the region where the nth insulating layer is in contact with the nth wiring. (M is an arbitrary natural number of 3 or more, and n is an arbitrary natural number of 2 or more and m-1 or less.)

When the wiring board includes three or more insulating layers and a conductor formed on each insulating layer, the n-th insulating layer may be included in plural or a combination of arbitrary layers. The region where the insulating layers are in contact with each other has a surface roughness greater than the region where the insulating layer is in contact with the interlayer connection, and the region where the insulating layer is in contact with the interlayer connection is a region where the insulating layer is in contact with the wiring By having a larger surface roughness, it is possible to further improve the respective adhesiveness. As a result, a wiring board with further improved reliability can be provided.

In the present embodiment, the second insulating layer that is the uppermost layer also has a surface in which the second insulating layer is in contact with the second interlayer connection portion and a surface that is larger than the region in which the second insulating layer is in contact with the second wiring. The region having the roughness and exposing the second insulating layer to the uppermost surface has a surface roughness larger than the region where the second insulating layer is in contact with the second interlayer connection portion. The uppermost insulating layer has a larger surface roughness than the region where the insulating layer is in contact with the wiring and the region where the insulating layer is in contact with the interlayer connection portion. Can be improved. As a result, a semiconductor device with further improved reliability can be provided.

[Method for Manufacturing Wiring Board 20]
A method of manufacturing a wiring board according to an embodiment of the present disclosure will be described using FIG. In FIG. 4, the same elements as those shown in FIG.

FIG. 4A illustrates a method for manufacturing a wiring board according to an embodiment of the present disclosure, in which a first trench 120, a second concavo-convex structure 160, and a first trench are formed in the first insulating layer 100 by imprinting. It is a figure which shows the process of forming the through-hole 180 of. First, the mold 110 for forming the first trench 120, the second uneven structure 160, and the first through hole 180 is formed in the first insulating layer 100. The mold 110 has protrusions corresponding to the first trench 120, the second concavo-convex structure 160, and the first through hole 180. The surfaces of the protrusions of the mold 110 corresponding to the first trench 120 and the first through hole 180 are formed to be substantially flat.

Next, using the mold 110, the first trench 120, the second uneven structure 160, and the first through hole 180 are imprinted on the first surface of the first insulating layer 100. Although not shown in FIG. 4, the first insulating layer 100 may be formed by coating on a substrate (not shown). In this case, the surface of the first insulating layer 100 opposite to the substrate is the first surface. The first insulating layer 100 is softened, and the mold 110 is pressed into the first surface. In this state, the first insulating layer 100 is cured, and the mold 110 is peeled from the first insulating layer 100, whereby the first insulating layer 100 having a cross-sectional structure illustrated in FIG. Insulating material residues may remain in the first trench 120, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100. For this reason, the residue of the insulating material is removed by performing a wet process using a permanganate solution or a dry process using oxygen plasma. By removing the residue of the insulating material, a good interlayer connection can be obtained, and a wiring board with improved reliability can be provided.

In this embodiment, the 1st trench 120, the 2nd uneven structure 160, and the 1st through-hole 180 are integrally formed by the imprint method. As a result, the manufacturing process can be simplified. In addition, the imprint method uses less chemical solution than a general photolithography method and is environmentally friendly.

A first concavo-convex structure 140 is formed on the inner surface (first region) of the first trench 120 formed in the first insulating layer 100 by an imprint method. As for the surface roughness in the first region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.1 or less, and the ten-point average roughness Rz _JIS is 0.1 or less. More preferably, the first region is substantially flat.

In the present embodiment, the surface roughness in the first region is formed smaller than the surface roughness in the third region. A third concavo-convex structure is formed on the inner surface (third region) of the first through-hole 180 formed in the first insulating layer 100 by an imprint method. The first through hole 180 is deeper in the stacking direction (perpendicular to the layer) than the first trench 120. For this reason, a concavo-convex structure is formed on the surface in the stacking direction (the direction perpendicular to the layer, the side surface) by friction when the mold 110 is peeled from the first insulating layer 100. The concavo-convex structure formed on the surface in the layer direction (layer and horizontal direction, bottom surface) is smaller than the concavo-convex structure formed on the surface in the stacking direction (layer and vertical direction, side surface). Therefore, the first region having many surfaces in the layer direction has a smaller surface roughness than the third region having many surfaces in the stacking direction.

On the other hand, the second concavo-convex structure 160 formed on the first insulating layer 100 has a height in the stacking direction of 0.01 μm or more and 3 μm or less. When the height of the second uneven structure 160 in the stacking direction is 0.01 μm or less, it is difficult to form the mold 110 for forming the second uneven structure 160 by the imprint method. When the height of the second concavo-convex structure 160 in the stacking direction is 3 μm or more, depending on the thickness of the insulating layer, it is too deep and penetrates to the lower layer, resulting in unnecessary roughness. As for the surface roughness in the second uneven structure 160 measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.5 or more and 1.5 or less, and the ten-point average roughness Rz _JIS is 1.5 or more. 2.5 or less. The surface roughness in the second region is formed to be larger than the surface roughness in the first region, the third region, and a fourth region described later.

FIG. 4B is a diagram illustrating a process of forming the first conductor 200 on the first insulating layer 100 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. The first trench 120, the first uneven structure 140, the second uneven structure 160, the third uneven structure, and the first through hole 180 of the first insulating layer 100 formed in FIG. Then, a film is formed so as to be covered with the first conductor 200. In this embodiment, copper was deposited using a sputtering method. However, the present invention is not limited to this, and the first conductor 200 may be a seed layer for filling metal by an electrolytic plating method in the next step. It may also be a seed layer and / or a barrier layer. The first conductor 200 includes the first trench 120, the first uneven structure 140, the second uneven structure 160, the third uneven structure, and the like of the first insulating layer 100 formed in FIG. And the 1st through-hole 180 is reflected. In other words, the first conductor 200 includes the first trench 120, the first uneven structure 140, the second uneven structure 160, the third uneven structure, and the first penetration of the first insulating layer 100. It is formed along the hole 180. That is, the first conductor 200 has a concavo-convex structure formed in the first insulating layer 100. However, the present invention is not limited to this, and the uneven structure formed in the first insulating layer 100 may be at least partially filled with the first conductor 200.

FIG. 4C is a diagram illustrating a process of forming the second conductor 220 on the first conductor 200 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. The first trench 120, the first uneven structure 140, the second uneven structure 160, the third uneven structure, and the first through hole 180 of the first insulating layer 100 formed in FIG. The second conductor 220 is filled. In the present embodiment, the first trench 120, the first concavo-convex structure 140, the second concavo-convex structure 160, the third concavo-convex structure, and the first through-hole 180 of the first insulating layer 100 are formed by electrolytic plating. To fill with copper. However, the present invention is not limited to this, and the first trench 120, the first uneven structure 140, the second uneven structure 160, the third uneven structure, and the first through hole 180 of the first insulating layer 100 are filled with metal. A printing method or the like can also be used as the method for performing the above.

FIG. 4D is a diagram illustrating a process of polishing the first insulating layer 100 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. As shown in FIG. 4D, substantially the entire surface of the first insulating layer 100 is polished. In the present embodiment, the surface of the first insulating layer 100 is polished using a chemical mechanical polishing method. By selectively polishing the first conductor 200 and the second conductor 220 on the first insulating layer 100, unnecessary first portions other than those in the first trench 120 and the first through-hole 180 are provided. The conductor 200 and the second conductor 220 can be removed. As a result, the second uneven structure 160 of the first insulating layer 100 is exposed. The first conductor 200 and the second conductor 220 in the first trench 120 are formed as the first wiring 340. The first conductor 200 and the second conductor 220 in the first through-hole 180 are formed as a first interlayer connection portion 360. In the present embodiment, the first wiring 340 and the first interlayer connection 360 are integrally formed, but the present invention is not limited to this. Each may be formed separately.

FIG. 4E is a diagram illustrating a process of laminating the second insulating layer 400 on the first insulating layer 100 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. In the present embodiment, the second insulating layer 400 is formed by applying on the first insulating layer 100. Here, the second insulating layer 400 is formed so as to fill the second uneven structure 160 of the first insulating layer 100 formed in FIG. That is, the second insulating layer 400 reflects the second uneven structure 160 of the first insulating layer 100. In other words, the second insulating layer 400 has an uneven structure in a region in contact with the first insulating layer 100. The second uneven structure 160 of the first insulating layer 100 and the uneven structure of the second insulating layer 400 are bonded so as to mesh with each other. By stacking the second insulating layer 400 on the first insulating layer 100, the first wiring 340 and the first interlayer connection 360 are embedded in the first insulating layer 100 and the second insulating layer 400. Is done.

FIG. 4F illustrates a method for manufacturing a wiring board according to an embodiment of the present disclosure, in which the second wiring 640 and the second wiring 640 are formed on the second insulating layer 400 by the steps of FIGS. It is a figure which shows the process of forming the interlayer connection part 660 of. Similar to the first insulating layer 100, an uneven structure, a second trench, and a second through hole are formed in the second insulating layer 400 by an imprint method, and the first conductor and the second conductor are formed. After filling with the body, polishing is performed, whereby the concavo-convex structure, the second wiring 640, and the second interlayer connection portion 660 are formed in the second insulating layer 400. In this embodiment, the manufacturing method of the wiring board provided with two insulating layers and the conductor formed in each insulating layer was shown. However, the present invention is not limited thereto, and a wiring board having two or more insulating layers can be appropriately prepared by preparing a mold having a trench having an arbitrary pattern in each layer, a through hole, and a protrusion corresponding to the concavo-convex structure. Can be formed.

FIG. 4G is a diagram illustrating a process of forming the first electrode 380 and the second electrode 680 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. In this embodiment, the second electrode 680 is formed using photolithography. However, the present invention is not limited to this. For example, the second electrode 680 may be formed integrally with the second wiring 640 and the second interlayer connection 660. In this embodiment mode, the first electrode 380 is formed by photolithography, but is not limited thereto. Although not shown in FIG. 4, the first insulating layer 100 may have a substrate (not shown) on the second surface opposite to the first surface. In this case, a step of first peeling the substrate may be included. On the second surface of the first insulating layer 100, a residue of the insulating material may remain in the first through hole 180. For this reason, the residue of the insulating material is removed by performing a wet process using a permanganate solution or a dry process using oxygen plasma. By removing the residue of the insulating material, a favorable electrode connection can be obtained, and a wiring board with improved reliability can be provided. Note that the first electrode 380 may be formed after a semiconductor component described later is disposed.

In the present embodiment, the surface roughness in the fourth region where the first insulating layer 100 is in contact with the first electrode 380 is formed to be larger than the surface roughness in the third region. A fourth uneven structure may be formed on the surface (fourth region) of the first insulating layer 100 in contact with the first electrode 380. Since the fourth region has the fourth uneven structure, the uneven structure is also formed on the surface of the first electrode 380 that is in contact with the first insulating layer 100. Adhesion can be improved by bonding so that the respective concavo-convex structures mesh with each other. Since the first electrode 380 is exposed to an external force, an adhesion force with the insulating material is required more strongly than other portions of the conductor. The adhesion between the first insulating layer 100 and the first electrode 380 can be improved, and a wiring board with improved reliability can be provided.

As described above, according to the method for manufacturing the wiring substrate 20 according to the present embodiment, the second concavo-convex structure 160 can be formed in the second region where the first insulating layer 100 is in contact with the second insulating layer 400. it can. In such a selective roughened surface forming method, by forming the second concavo-convex structure 160 in the first insulating layer 100, the region of the second insulating layer 400 that is in contact with the first insulating layer 100 is uneven. A structure is formed. The uneven structure of the second insulating layer 400 is formed so as to fit into the uneven structure of the first insulating layer 100. By bonding so that the concavo-convex structure of the first insulating layer 100 and the second insulating layer 400 is engaged with each other, the adhesion can be improved and peeling can be prevented. As a result, a wiring board with improved reliability can be provided.

According to the method for manufacturing the wiring board 20 according to the present embodiment, the first region has a surface roughness smaller than that of the third region, and the third region has surface roughness smaller than that of the fourth region. The first wiring 340 can be formed to have a surface roughness smaller than that of the first interlayer connection portion 360, and the first interlayer connection portion 360 can have a surface roughness smaller than that of the first electrode 380. . The rough surface on the wiring surface has a larger influence on the conductor resistance due to the skin effect when driven in the high frequency band, that is, the increase in the conductor loss than the rough surface on the interlayer connection portion. The rough surface in the interlayer connection portion has a larger influence on the increase in conductor resistance due to the skin effect when driven in the high frequency band, that is, the increase in conductor loss, than the rough surface in the electrode. For this reason, by increasing the conductor resistance due to the skin effect when driven in the high frequency band, that is, by forming the conductor having a large influence that causes an increase in the conductor loss to have a smaller surface roughness, the transmission characteristics in the high frequency band can be improved. An improved wiring board can be provided.

The third region has a surface roughness larger than that of the first region, and the fourth region has surface roughness larger than that of the third region, whereby the first interlayer connection 360 is configured to have the first wiring 340. A larger surface roughness is formed, and the first electrode 380 has a surface roughness larger than that of the first interlayer connection 360. The concavo-convex structure of the first interlayer connection 360 is formed so as to fit into the third concavo-convex structure. The uneven structure of the first electrode 380 is formed to fit into the fourth uneven structure. Adhesion can be improved by adhering the concavo-convex structures so as to mesh with each other. By increasing the conductor resistance due to the skin effect when driven in a high frequency band, that is, the conductor having a smaller influence causing an increase in the conductor loss has a larger surface roughness, the conductor loss due to the skin effect is suppressed, and the first The adhesion between the insulating layer 100 and the conductor can be improved, and a wiring board with improved reliability can be provided.

<Third Embodiment>
In the wiring substrate according to the third embodiment, the bottom surface is a side surface in the first region where the first insulating layer is in contact with the first wiring and the third region where the first insulating layer is in contact with the first interlayer connection portion. The first region has a smaller surface roughness and the second region has a larger surface roughness than the first region and the third region.

The configuration of the wiring board 30 and the method for manufacturing the wiring board 30 according to the third embodiment of the present disclosure will be described with reference to FIGS. Here, the detailed description of the same parts as those in the first embodiment is omitted.

[Configuration of wiring board]
FIG. 5 is a (A) top view, (B) (C) cross-sectional views, and (D) (E) enlarged views showing an example of a wiring board according to an embodiment of the present disclosure. 5B is a cross-sectional view taken along line AA ′ in FIG. 5A, and FIG. 5C is a cross-sectional view taken along line BB ′ in FIG. FIG. 5D is an enlarged view in a region C in FIG. 5B, and FIG. 5E is an enlarged view in a region D in FIG. 5C. As shown in FIGS. 5A, 5B, and 5C, the wiring board 30 includes a first insulating layer 100, a second insulating layer 400, and conductors formed in the respective insulating layers. With.

The conductor of the first insulating layer 100 includes a first wiring 340, a first interlayer connection 360, and a first electrode 380. The first insulating layer 100 includes a first wiring 340 on the first surface. The first wiring 340 is electrically connected to the first interlayer connection 360 that penetrates the first insulating layer 100 at one end. In the present embodiment, the example in which one first wiring 340 is arranged on the first surface is shown, but the present invention is not limited to this. One or more first wirings 340 may be arranged on the first surface. In the present embodiment, the first wiring 340 is disposed only on the first surface of the first insulating layer 100, but the first wiring 340 is also disposed on the second surface opposite to the first surface. May be. The first interlayer connection 360 is electrically connected to the first electrode 380 on the second surface of the first insulating layer 100 opposite to the first surface.

A second insulating layer 400 is disposed on the first surface of the first insulating layer 100. The conductor of the second insulating layer 400 includes a second wiring 640, a second interlayer connection portion 660, and a second electrode 680. The second insulating layer 400 includes a second wiring 640 on the third surface opposite to the first insulating layer 100. The second wiring 640 is electrically connected to the second interlayer connection portion 660 that penetrates the second insulating layer 400. Second interlayer connection portion 660 is further electrically connected to the other end opposite to one end of first wiring 340. In the present embodiment, an example in which one second wiring 640 is arranged on the third surface is shown, but the present invention is not limited to this. One or more second wirings 640 may be arranged on the third surface. The second wiring 640 is electrically connected to the second electrode 680 on the third surface of the second insulating layer 400.

FIG. 5D is an enlarged view of a region C in FIG. FIG. 5E is an enlarged view of a region D in FIG. As shown in FIGS. 5D and 5E, the first insulating layer 100 is in contact with the first wiring 340, the first interlayer connection 360, and the second insulating layer 400.

A first concavo-convex structure 140 is formed on the surface of the first region where the first insulating layer 100 is in contact with the first wiring 340 in the layer direction (the layer and the horizontal direction, the bottom surface). As for the surface roughness in the first region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.1 or less, and the ten-point average roughness Rz _JIS is 0.1 or less. More preferably, the surface of the first region in the layer direction (layer and horizontal direction, bottom surface) is substantially flat. Furthermore, the surface roughness on the surface in the layer direction (layer and horizontal direction, bottom surface) of the first region is smaller than the surface roughness on the surface in the stacking direction (layer and vertical direction, side surface) of the first region. The surface roughness of the surface of the first region in the layer direction (layer and horizontal direction, bottom surface) is the stacking direction (perpendicular to the layer) of the third region in which the first insulating layer 100 is in contact with the first interlayer connection 360. Smaller than the surface roughness of the surface in the direction, side).

On the other hand, the second uneven structure 160 in the second region where the first insulating layer 100 is in contact with the second insulating layer 400 has a height in the stacking direction of 0.01 μm or more and 3 μm or less. As for the surface roughness in the second region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.5 or more and 1.5 or less, and the ten-point average roughness Rz _JIS is 1.5 or more and 2. 5 or less. The first insulating layer 100 is the second region from the first region where the first insulating layer 100 is in contact with the first wiring 340 and the third region where the first insulating layer 100 is in contact with the first interlayer connection 360. The second region in contact with the insulating layer 400 has a large surface roughness.

In the present embodiment, the bottom surface of the first region has a surface roughness smaller than the side surface of the first region, and the bottom surface of the first region has a surface roughness smaller than the side surface of the third region, The bottom surface of the first wiring 340 has a smaller surface roughness than the side surface of the first wiring 340, and the bottom surface of the first wiring 340 has a smaller surface roughness than the side surface of the first interlayer connection portion 360. The rough surface of the wiring surface has a longer total extension than the rough surface of the interlayer connection portion, and has a large effect of increasing the conductor resistance due to the skin effect when driven in the high frequency band, that is, increasing the conductor loss. For this reason, a conductor having a greater effect of causing an increase in conductor resistance due to the skin effect when driven in a high frequency band, that is, an increase in conductor loss, has a smaller surface roughness, thereby improving transmission characteristics in the high frequency band. A wiring board can be provided.

The side surface of the first region has a surface roughness larger than that of the bottom surface of the first region, and the side surface of the third region has surface roughness larger than that of the bottom surface of the first region. The side surface of the first wiring 340 has a larger surface roughness than the bottom surface of the first wiring 340, and the side surface of the first interlayer connection 360 has a surface roughness larger than the bottom surface of the first wiring 340. The uneven structure of the first wiring 340 is formed so as to fit into the uneven structure of the first region. The concavo-convex structure of the first interlayer connection 360 is formed to fit into the concavo-convex structure of the third region. Adhesion can be improved by adhering the concavo-convex structures so as to mesh with each other. The conductor resistance due to the skin effect when driven in the high frequency band, that is, the conductor having a smaller influence causing the increase in the conductor loss has a larger surface roughness, thereby suppressing the conductor loss due to the skin effect, Therefore, it is possible to provide a wiring board with improved adhesion by improving the adhesion between the insulating layer 100 and the conductor.

In the present embodiment, the second region where the first insulating layer 100 is in contact with the second insulating layer 400 has the second uneven structure 160. When the first insulating layer 100 has the second uneven structure 160 in the second region, the uneven structure is also formed in the region of the second insulating layer 400 in contact with the first insulating layer 100. The uneven structure of the second insulating layer 400 is formed so as to fit into the second uneven structure 160 of the first insulating layer 100. By adhering the second concavo-convex structure 160 of the first insulating layer 100 and the concavo-convex structure of the second insulating layer 400 so as to mesh with each other, the adhesion can be improved. As a result, a wiring board with improved reliability can be provided.

In the present embodiment, the wiring board 30 includes two insulating layers and a conductor formed on each insulating layer. In the first insulating layer 100, the side surface of the first region and the side surface of the third region have a surface roughness larger than the bottom surface of the first region, and the second region has the first region and the third region. Has a surface roughness greater than the area. However, the present invention is not limited to this. For example, the wiring board may include m insulating layers and a conductor formed on each insulating layer. In this case, from the region where the nth insulating layer is in contact with the bottom surface of the nth wiring, the region in which the nth insulating layer is in contact with the side surface of the nth wiring and the nth insulating layer is the side surface of the nth interlayer connection portion. The region in contact with the n-th layer has a large surface roughness. The n-th insulating layer is in contact with the side surface of the n-th wiring, and the n-th insulating layer is in contact with the side surface of the n-th interlayer connection portion. A region where the insulating layer is in contact with the (n + 1) th insulating layer may have a large surface roughness. (M is an arbitrary natural number of 3 or more, and n is an arbitrary natural number of 1 or more and m-1 or less.)

When the wiring board includes three or more insulating layers and a conductor formed on each insulating layer, the n-th insulating layer may be included in plural or a combination of arbitrary layers. A plurality of insulating layers have a larger surface roughness in a region where the insulating layer is in contact with the side surface of the wiring and a region in which the insulating layer is in contact with the side surface of the interlayer connection portion than in a region where the insulating layer is in contact with the bottom surface of the wiring. Since the region where the insulating layers are in contact with each other and the region where the insulating layers are in contact with each other have a larger surface roughness than the region where the insulating layer and the insulating layer are in contact with the side surface of the interlayer connection portion, the adhesion can be further improved. As a result, a wiring board with further improved reliability can be provided.

In the present embodiment, the second insulating layer, which is the uppermost layer, is also a side region where the second insulating layer is in contact with the second wiring and a side region where the second insulating layer is in contact with the second interlayer connection portion. Has a larger surface roughness than the region of the bottom surface where the second insulating layer is in contact with the second wiring, and in the region where the second insulating layer is exposed on the uppermost surface, the second insulating layer is the second wiring. And the second insulating layer have a larger surface roughness than the region in contact with the second interlayer connection. The uppermost insulating layer has a larger surface roughness than the region where the insulating layer is in contact with the wiring and the region where the insulating layer is in contact with the interlayer connection portion. Can be improved. As a result, a semiconductor device with further improved reliability can be provided.

[Method for Manufacturing Wiring Board 30]
A method of manufacturing a wiring board according to an embodiment of the present disclosure will be described using FIG. In FIG. 6, the same elements as those shown in FIG.

FIG. 6A illustrates a method for manufacturing a wiring board according to an embodiment of the present disclosure, in which a first trench 120, a second concavo-convex structure 160, and a first trench are formed in the first insulating layer 100 by imprinting. It is a figure which shows the process of forming the through-hole 180 of. First, the mold 110 for forming the first trench 120, the second uneven structure 160, and the first through hole 180 is formed in the first insulating layer 100. The mold 110 has protrusions corresponding to the first trench 120, the second concavo-convex structure 160, and the first through hole 180. The surfaces of the protrusions of the mold 110 corresponding to the first trench 120 and the first through hole 180 are formed to be substantially flat.

Next, using the mold 110, the first trench 120, the second uneven structure 160, and the first through hole 180 are imprinted on the first surface of the first insulating layer 100. Although not shown in FIG. 6, the first insulating layer 100 may be formed by coating on a substrate (not shown). In this case, the surface of the first insulating layer 100 opposite to the substrate is the first surface. The first insulating layer 100 is softened, and the mold 110 is pressed into the first surface. In this state, the first insulating layer 100 is cured, and the mold 110 is peeled from the first insulating layer 100, whereby the first insulating layer 100 having a cross-sectional structure illustrated in FIG. 6A can be obtained. Insulating material residues may remain in the first trench 120, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100. For this reason, the residue of the insulating material is removed by performing a wet process using a permanganate solution or a dry process using oxygen plasma. By removing the residue of the insulating material, a good interlayer connection can be obtained, and a wiring board with improved reliability can be provided.

In this embodiment, the 1st trench 120, the 2nd uneven structure 160, and the 1st through-hole 180 are integrally formed by the imprint method. As a result, the manufacturing process can be simplified. In addition, the imprint method uses less chemical solution than a general photolithography method and is environmentally friendly.

A first concavo-convex structure 140 is formed on the surface (first region) in the inner layer direction (layer and horizontal direction, bottom surface) of the first trench 120 formed in the first insulating layer 100 by imprinting. Is done. As for the surface roughness in the first region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.1 or less, and the ten-point average roughness Rz _JIS is 0.1 or less. More preferably, the surface of the first region in the layer direction (layer and horizontal direction, bottom surface) is substantially flat.

In the present embodiment, the surface roughness on the bottom surface of the first region is formed smaller than the surface roughness on the side surface of the first region and the side surface of the third region. On the side surface of the first region and the side surface of the third region formed in the first insulating layer 100, a concavo-convex structure on the surface in the stacking direction (the direction perpendicular to the layer, the side surface) is formed by imprinting. Due to friction when the mold 110 is peeled from the first insulating layer 100 in the imprint method, a concavo-convex structure is formed on the surface in the stacking direction (direction perpendicular to the layer, side surface). The concavo-convex structure formed on the surface in the layer direction (layer and horizontal direction, bottom surface) is smaller than the concavo-convex structure formed on the surface in the stacking direction (layer and vertical direction, side surface). For this reason, the surface of the first region in the layer direction (the layer and the horizontal direction, the bottom surface) is the surface of the first region in the stacking direction (the direction perpendicular to the layer, the side surface) and the third region in the stacking direction (perpendicular to the layer). (Direction, side surface) surface roughness smaller than the surface.

On the other hand, the second concavo-convex structure 160 formed on the first insulating layer 100 has a height in the stacking direction of 0.01 μm or more and 3 μm or less. When the height of the second uneven structure 160 in the stacking direction is 0.01 μm or less, it is difficult to form the mold 110 for forming the second uneven structure 160 by the imprint method. When the height of the second concavo-convex structure 160 in the stacking direction is 3 μm or more, depending on the thickness of the insulating layer, it is too deep and penetrates to the lower layer, resulting in unnecessary roughness. As for the surface roughness in the second uneven structure 160 measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.5 or more and 1.5 or less, and the ten-point average roughness Rz _JIS is 1.5 or more. 2.5 or less. The surface roughness in the second region is formed to be larger than the surface roughness in the first region and the third region.

FIG. 6B is a diagram illustrating a process of forming the first conductor 200 on the first insulating layer 100 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. Formed on the surface of the first trench 120, the first uneven structure 140, the second uneven structure 160 of the first insulating layer 100 formed in FIG. The uneven structure to be formed and the first through-hole 180 are formed so as to be covered with the first conductor 200. In this embodiment, copper was deposited using a sputtering method. However, the present invention is not limited to this, and the first conductor 200 may be a seed layer for filling metal by an electrolytic plating method in the next step. It may also be a seed layer and / or a barrier layer. The first conductor 200 includes a first trench 120, a first uneven structure 140, a second uneven structure 160, and a stacking direction (perpendicular to the layer) of the first insulating layer 100 formed in FIG. The concavo-convex structure formed on the surface of the direction and the side surface and the first through-hole 180 are reflected. In other words, the first conductor 200 includes the first trench 120 of the first insulating layer 100, the first concavo-convex structure 140, the second concavo-convex structure 160, and the stacking direction (the direction perpendicular to the layer, the side surface). The concavo-convex structure formed on the surface and the first through hole 180 are formed. That is, the first conductor 200 has a concavo-convex structure formed in the first insulating layer 100. However, the present invention is not limited to this, and the uneven structure formed in the first insulating layer 100 may be at least partially filled with the first conductor 200.

FIG. 6C is a diagram illustrating a process of forming the second conductor 220 on the first conductor 200 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. Formed on the surface of the first trench 120, the first uneven structure 140, the second uneven structure 160 of the first insulating layer 100 formed in FIG. The uneven structure to be formed and the first through hole 180 are filled with the second conductor 220. In the present embodiment, the first trench 120 of the first insulating layer 100, the first concavo-convex structure 140, the second concavo-convex structure 160, and the concavo-convex structure formed on the surface in the stacking direction (direction perpendicular to the layer, side surface). , And the first through-hole 180 are filled with copper using an electrolytic plating method. However, the present invention is not limited to this, and the first trench 120, the first concavo-convex structure 140, the second concavo-convex structure 160 of the first insulating layer 100 are formed on the surface in the stacking direction (the direction perpendicular to the layer and the side surface). As a method for filling the uneven structure and the first through-hole 180 with metal, a printing method or the like can also be used.

FIG. 6D is a diagram illustrating a step of polishing the first insulating layer 100 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. As shown in FIG. 6D, the substantially entire surface of the first insulating layer 100 is polished. In the present embodiment, the surface of the first insulating layer 100 is polished using a chemical mechanical polishing method. By selectively polishing the first conductor 200 and the second conductor 220 on the first insulating layer 100, unnecessary first portions other than those in the first trench 120 and the first through-hole 180 are provided. The conductor 200 and the second conductor 220 can be removed. As a result, the second uneven structure 160 of the first insulating layer 100 is exposed. The first conductor 200 and the second conductor 220 in the first trench 120 are formed as the first wiring 340. The first conductor 200 and the second conductor 220 in the first through-hole 180 are formed as a first interlayer connection portion 360. In the present embodiment, the first wiring 340 and the first interlayer connection 360 are integrally formed, but the present invention is not limited to this. Each may be formed separately.

FIG. 6E is a diagram illustrating a process of laminating the second insulating layer 400 on the first insulating layer 100 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. In the present embodiment, the second insulating layer 400 is formed by applying on the first insulating layer 100. Here, the second insulating layer 400 is formed so as to fill the second uneven structure 160 of the first insulating layer 100 formed in FIG. That is, the second insulating layer 400 reflects the second uneven structure 160 of the first insulating layer 100. In other words, the second insulating layer 400 has an uneven structure in a region in contact with the first insulating layer 100. The second uneven structure 160 of the first insulating layer 100 and the uneven structure of the second insulating layer 400 are bonded so as to mesh with each other. By stacking the second insulating layer 400 on the first insulating layer 100, the first wiring 340 and the first interlayer connection 360 are embedded in the first insulating layer 100 and the second insulating layer 400. Is done.

FIG. 6F illustrates a method of manufacturing a wiring board according to an embodiment of the present disclosure, in which the second wiring 640 and the second wiring 640 are formed on the second insulating layer 400 by the steps of FIGS. It is a figure which shows the process of forming the interlayer connection part 660 of. Similar to the first insulating layer 100, an uneven structure, a second trench, and a second through hole are formed in the second insulating layer 400 by an imprint method, and the first conductor and the second conductor are formed. After filling with the body, polishing is performed, whereby the concavo-convex structure, the second wiring 640, and the second interlayer connection portion 660 are formed in the second insulating layer 400. In this embodiment, the manufacturing method of the wiring board provided with two insulating layers and the conductor formed in each insulating layer was shown. However, the present invention is not limited thereto, and a wiring board having two or more insulating layers can be appropriately prepared by preparing a mold having a trench having an arbitrary pattern in each layer, a through hole, and a protrusion corresponding to the concavo-convex structure. Can be formed.

FIG. 6G is a diagram illustrating a process of forming the first electrode 380 and the second electrode 680 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. In this embodiment, the second electrode 680 is formed using photolithography. However, the present invention is not limited to this. For example, the second electrode 680 may be formed integrally with the second wiring 640 and the second interlayer connection 660. In this embodiment mode, the first electrode 380 is formed by photolithography, but is not limited thereto. Although not shown in FIG. 6, the first insulating layer 100 may have a substrate (not shown) on the second surface opposite to the first surface. In this case, a step of first peeling the substrate may be included. On the second surface of the first insulating layer 100, a residue of the insulating material may remain in the first through hole 180. For this reason, the residue of the insulating material is removed by performing a wet process using a permanganate solution or a dry process using oxygen plasma. By removing the residue of the insulating material, a favorable electrode connection can be obtained, and a wiring board with improved reliability can be provided. Note that the first electrode 380 may be formed after a semiconductor component described later is disposed.

As described above, according to the method for manufacturing the wiring substrate 30 according to the present embodiment, the second concavo-convex structure 160 can be formed in the second region where the first insulating layer 100 is in contact with the second insulating layer 400. it can. In such a selective roughened surface forming method, by forming the second concavo-convex structure 160 in the first insulating layer 100, the region of the second insulating layer 400 that is in contact with the first insulating layer 100 is uneven. A structure is formed. The uneven structure of the second insulating layer 400 is formed so as to fit into the uneven structure of the first insulating layer 100. By bonding so that the concavo-convex structure of the first insulating layer 100 and the second insulating layer 400 is engaged with each other, the adhesion can be improved and peeling can be prevented. As a result, a wiring board with improved reliability can be provided.

According to the method for manufacturing the wiring board 30 according to the present embodiment, the bottom surface of the first region has a surface roughness smaller than the side surface of the first region, and the bottom surface of the first region is smaller than the side surface of the third region. By having a small surface roughness, the bottom surface of the first wiring 340 has a smaller surface roughness than the side surface of the first wiring 340, and the bottom surface of the first wiring 340 is the side surface of the first interlayer connection portion 360. It can be formed to have a smaller surface roughness. The rough surface on the wiring surface has a larger influence on the conductor resistance due to the skin effect when driven in the high frequency band, that is, the increase in the conductor loss than the rough surface on the interlayer connection portion. For this reason, by increasing the conductor resistance due to the skin effect when driven in the high frequency band, that is, by forming the conductor having a large influence that causes an increase in the conductor loss to have a smaller surface roughness, the transmission characteristics in the high frequency band can be improved. An improved wiring board can be provided.

The side surface of the first region has a surface roughness larger than that of the bottom surface of the first region, and the side surface of the third region has surface roughness larger than that of the bottom surface of the first region. The side surface of the first wiring 340 has a larger surface roughness than the bottom surface of the first wiring 340, and the side surface of the first interlayer connection 360 has a surface roughness larger than the bottom surface of the first wiring 340. The uneven structure on the side surface of the first wiring 340 is formed so as to fit the uneven structure on the side surface of the first region. The uneven structure on the side surface of the first interlayer connection 360 is formed so as to fit the uneven structure on the side surface of the third region. Adhesion can be improved by adhering the concavo-convex structures so as to mesh with each other. By increasing the conductor resistance due to the skin effect when driven in a high frequency band, that is, the conductor having a smaller influence causing an increase in the conductor loss has a larger surface roughness, the conductor loss due to the skin effect is suppressed, and the first The adhesion between the insulating layer 100 and the conductor can be improved, and a wiring board with improved reliability can be provided.

<Fourth embodiment>
In the wiring board according to the fourth embodiment, in the roll-type imprint method, the region where the first insulating layer is in contact with the wiring extending in the mold traveling direction is perpendicular to the mold traveling direction. The surface roughness is smaller than the area where the wiring extending in the direction contacts.

The configuration of the wiring board 40 and the method for manufacturing the wiring board 40 according to the fourth embodiment of the present disclosure will be described with reference to FIGS. Here, the detailed description of the same parts as those in the first embodiment is omitted.

[Configuration of wiring board]
FIG. 7 is an (A) top view, (B) (C) cross-sectional views, and (D) (E) enlarged views showing an example of a wiring board according to an embodiment of the present disclosure. 7B is a cross-sectional view taken along line AA ′ in FIG. 7A, and FIG. 7C is a cross-sectional view taken along line BB ′ in FIG. FIG. 7D is an enlarged view in a region C in FIG. 7C, and FIG. 7E is an enlarged view in a region D in FIG. 7C. As shown in FIGS. 7A, 7B, and 7C, the wiring board 40 includes a first insulating layer 100, a second insulating layer 400, and conductors formed in the respective insulating layers. With.

The conductor of the first insulating layer 100 includes two first wirings 340, first interlayer connection portions 360, and two first electrodes 380. The first insulating layer 100 includes a first wiring 340a and a first wiring 340b on a first surface. The first wiring 340 a extending from the first side 102 to the second side 104 (first direction) of the first insulating layer 100 is from the first side 102 to the third side 106 orthogonal to the first direction. It is longer than the first wiring 340b extending in the (second direction). The first wiring 340a is electrically connected to the first interlayer connection 360a penetrating the first insulating layer 100 at one end. The first interlayer connection 360a is electrically connected to the first electrode 380a on the second surface of the first insulating layer 100 opposite to the first surface. The first wiring 340b is electrically connected to the first interlayer connection 360b penetrating the first insulating layer 100 at one end. The first interlayer connection 360b is electrically connected to the first electrode 380b on the second surface of the first insulating layer 100. (Hereafter, the first wiring 340a and the first wiring 340b are referred to as the first wiring 340 when the first wiring 340a and the first wiring 340b are not distinguished. The first interlayer connection 360a and the first interlayer connection 360b are not distinguished from each other. This is referred to as a connection portion 360. The first electrode 380 is referred to when the first electrode 380a and the first electrode 380b are not distinguished from each other.) In this embodiment, two first wirings 340 are arranged on the first surface. However, the present invention is not limited to this. Two or more first wirings 340 may be arranged on the first surface. The total extension of the first wiring 340a extending in the first direction may be longer than the total extension of the first wiring 340b extending in the second direction orthogonal to the first direction. In the present embodiment, the first wiring 340 is disposed only on the first surface of the first insulating layer 100, but the first wiring 340 is also disposed on the second surface opposite to the first surface. May be.

A second insulating layer 400 is disposed on the first surface of the first insulating layer 100. The conductor of the second insulating layer 400 includes two second wirings 640, two second interlayer connection portions 660, and two second electrodes 680. The second insulating layer 400 includes a second wiring 640 a and a second wiring 640 b on the third surface opposite to the first insulating layer 100. The second wiring 640a extending from the first side 102 of the second insulating layer 400 toward the second side 104 (first direction) is from the first side 102 to the third side 106 orthogonal to the first direction. It is longer than the second wiring 640b extending in the (second direction). The second wiring 640 a is electrically connected to the second interlayer connection portion 660 a that penetrates the second insulating layer 400. Second interlayer connection portion 660a is further electrically connected to the other end opposite to one end of first wiring 340a. The second wiring 640 a is electrically connected to the second electrode 680 a on the third surface of the second insulating layer 400. The second wiring 640 b is electrically connected to the second interlayer connection portion 660 b that penetrates the second insulating layer 400. Second interlayer connection portion 660b is further electrically connected to the other end opposite to one end of first wiring 340b. The second wiring 640 b is electrically connected to the second electrode 680 b on the third surface of the second insulating layer 400. (Hereafter, when the second wiring 640a and the second wiring 640b are not distinguished from each other, the second wiring 640 is referred to. The second interlayer connection 660a and the second interlayer connection 660b are not distinguished from each other. It is referred to as a connection portion 660. When the second electrode 680a and the second electrode 680b are not distinguished from each other, it is referred to as a second electrode 680.) In this embodiment, two second wirings 640 are arranged on the third surface. However, the present invention is not limited to this. Two or more second wirings 640 may be arranged on the third surface. The total extension of the second wiring 640a extending in the first direction may be longer than the total extension of the second wiring 640b extending in the second direction orthogonal to the first direction.

FIG. 7D is an enlarged view of a region C in FIG. FIG. 7E is an enlarged view of a region D in FIG. As shown in FIGS. 7D and 7E, the first insulating layer 100 is in contact with the first wiring 340, the first interlayer connection 360, and the second insulating layer 400.

In a region where the first insulating layer 100 is in contact with the first wiring 340a, a first uneven structure 140a is formed. As for the surface roughness in the region in contact with the first wiring 340a measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.1 or less, and the ten-point average roughness Rz _JIS is 0.1 or less. . The region where the first insulating layer 100 is in contact with the first wiring 340a is more preferably substantially flat. Further, the surface roughness in the region where the first insulating layer 100 is in contact with the first wiring 340a is smaller than the surface roughness in the region where the first insulating layer 100 is in contact with the first wiring 340b.

On the other hand, the second uneven structure 160 in the second region where the first insulating layer 100 is in contact with the second insulating layer 400 has a height in the stacking direction of 0.01 μm or more and 3 μm or less. As for the surface roughness in the second region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.5 or more and 1.5 or less, and the ten-point average roughness Rz _JIS is 1.5 or more and 2. 5 or less. From the region where the first insulating layer 100 is in contact with the first wiring 340 a and the region where the first insulating layer 100 is in contact with the first wiring 340 b, the first insulating layer 100 is in contact with the second insulating layer 400. This region has a large surface roughness.

In this embodiment, the region where the first insulating layer 100 is in contact with the first wiring 340a has a smaller surface roughness than the region where the first insulating layer 100 is in contact with the first wiring 340b. 340a has a smaller surface roughness than the first wiring 340b. The rough surface of the wiring surface has a large effect of increasing the conductor resistance due to the skin effect when driven in a high frequency band, that is, increasing the conductor loss. For this reason, an increase in conductor resistance due to the skin effect when driven in a high frequency band, that is, a conductor with a long total extension that has a large effect on causing an increase in conductor loss has a smaller surface roughness, thereby reducing transmission characteristics in the high frequency band. An improved wiring board can be provided.

The region where the first insulating layer 100 is in contact with the first wiring 340b has a surface roughness larger than the region where the first insulating layer 100 is in contact with the first wiring 340a, so that the first wiring 340b is the first wiring 340b. A surface roughness larger than that of the wiring 340a is formed. The uneven structure of the first wiring 340b is formed so as to fit the first uneven structure 140b in a region where the first insulating layer 100 is in contact with the first wiring 340b. Adhesion can be improved by adhering the concavo-convex structures so as to mesh with each other. By increasing the conductor resistance due to the skin effect when driven in a high frequency band, that is, the conductor having a smaller influence causing an increase in the conductor loss has a larger surface roughness, the conductor loss due to the skin effect is suppressed, and the first The adhesion between the insulating layer 100 and the conductor can be improved, and a wiring board with improved reliability can be provided.

In the present embodiment, the second region where the first insulating layer 100 is in contact with the second insulating layer 400 has the second uneven structure 160. When the first insulating layer 100 has the second uneven structure 160 in the second region, the uneven structure is also formed in the region of the second insulating layer 400 in contact with the first insulating layer 100. The uneven structure of the second insulating layer 400 is formed so as to fit into the second uneven structure 160 of the first insulating layer 100. By adhering the second concavo-convex structure 160 of the first insulating layer 100 and the concavo-convex structure of the second insulating layer 400 so as to mesh with each other, the adhesion can be improved. As a result, a wiring board with improved reliability can be provided.

In the present embodiment, the wiring board 40 includes two insulating layers and a conductor formed on each insulating layer. In the first insulating layer 100, a region where the first insulating layer 100 is in contact with the first wiring 340b has a surface roughness larger than a region where the first insulating layer 100 is in contact with the first wiring 340a. The region 2 has a larger surface roughness than the region where the first insulating layer 100 is in contact with the first wiring 340b. However, the present invention is not limited to this. For example, the wiring board may include m insulating layers and a conductor formed on each insulating layer. In this case, the region where the nth insulating layer is in contact with the nb wiring has a larger surface roughness than the region where the nth insulating layer is in contact with the nath wiring, and the nth insulating layer is the nb wiring. The region where the nth insulating layer is in contact with the (n + 1) th insulating layer may have a larger surface roughness than the region in contact with. (M is an arbitrary natural number of 3 or more, and n is an arbitrary natural number of 1 or more and m-1 or less.)

When the wiring board includes three or more insulating layers and a conductor formed on each insulating layer, the n-th insulating layer may be included in plural or a combination of arbitrary layers. The region where the insulating layer is in contact with the wiring with a short total extension is larger than the region where the insulating layer is in contact with the wiring with a long total extension, and the region where the insulating layer is in contact with the wiring with a short total extension In addition, since the region where the insulating layers are in contact with each other has a large surface roughness, the adhesion can be further improved. As a result, a wiring board with further improved reliability can be provided.

In the present embodiment, the second insulating layer, which is the uppermost layer, is also in a region where the second insulating layer is in contact with the second wiring having a short total extension. The region where the second insulating layer is exposed on the uppermost surface has a surface roughness larger than the region where the second insulating layer is in contact with the second wiring. Since the uppermost insulating layer has a larger surface roughness in the region exposed on the uppermost surface than the region where the insulating layer is in contact with the wiring, the adhesion of the resin layer described later can be improved. As a result, a semiconductor device with further improved reliability can be provided.

[Method for Manufacturing Wiring Board 40]
A method of manufacturing a wiring board according to an embodiment of the present disclosure will be described using FIG. In FIG. 8, the same elements as those shown in FIG.

FIG. 8A illustrates a method for manufacturing a wiring board according to an embodiment of the present disclosure, in which a first trench 120a, a first trench 120b, and a second unevenness are formed on the first insulating layer 100 by imprinting. It is a figure which shows the process of forming the structure 160, the 1st through-hole 180a (not shown), and the 1st through-hole 180b (Hereafter, when not distinguishing the 1st trench 120a and the 1st trench 120b, it is 1st. 1 trench 120. The first through-hole 180a is referred to when the first through-hole 180a and the first through-hole 180b are not distinguished. First, the mold 110 for forming the first trench 120, the second uneven structure 160, and the first through hole 180 is formed in the first insulating layer 100. The mold 110 has protrusions corresponding to the first trench 120, the second concavo-convex structure 160, and the first through hole 180. The surfaces of the protrusions of the mold 110 corresponding to the first trench 120 and the first through hole 180 are formed to be substantially flat.

Next, using the mold 110, the first trench 120, the second uneven structure 160, and the first through hole 180 are imprinted on the first surface of the first insulating layer 100. Although not shown in FIG. 8, the first insulating layer 100 may be formed by coating on a substrate (not shown). In this case, the surface of the first insulating layer 100 opposite to the substrate is the first surface. The first insulating layer 100 is softened, and the mold 110 is pressed into the first surface. In this state, the first insulating layer 100 is cured, and the mold 110 is separated from the first insulating layer 100, whereby the first insulating layer 100 having a cross-sectional structure illustrated in FIG. 8A can be obtained. Insulating material residues may remain in the first trench 120, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100. For this reason, the residue of the insulating material is removed by performing a wet process using a permanganate solution or a dry process using oxygen plasma. By removing the residue of the insulating material, a good interlayer connection can be obtained, and a wiring board with improved reliability can be provided.

In this embodiment, the 1st trench 120, the 2nd uneven structure 160, and the 1st through-hole 180 are integrally formed by the imprint method. As a result, the manufacturing process can be simplified. In addition, the imprint method uses less chemical solution than a general photolithography method and is environmentally friendly.

A first uneven structure 140a is formed on the inner surface of the first trench 120a formed in the first insulating layer 100 by an imprint method. As for the surface roughness in the first region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.1 or less, and the ten-point average roughness Rz _JIS is 0.1 or less. More preferably, the inner surface of the first trench 120a is substantially flat.

In the present embodiment, the surface roughness on the inner surface of the first trench 120a is smaller than the surface roughness on the inner surface of the first trench 120b. A first concavo-convex structure 140b is formed on the inner surface of the first trench 120b formed in the first insulating layer 100 by an imprint method. For example, a second direction (the direction of FIG. 8A, FIG. 7A) perpendicular to the traveling direction of the roll mold 110 due to friction when the mold 110 is peeled from the first insulating layer 100 in the roll-type imprint method. The first concavo-convex structure 140b is formed on the inner surface of the first trench 120b extending in the direction from the first side 102 to the third side 106). The first uneven structure 140a formed on the inner surface of the first trench 120a extending in the traveling direction of the roll mold 110 is the first uneven structure 140b formed on the inner surface of the first trench 120b. Smaller than. For this reason, the area | region inside the 1st trench 120a has a surface roughness smaller than the area | region inside the 1st trench 120b.

On the other hand, the second concavo-convex structure 160 formed on the first insulating layer 100 has a height in the stacking direction of 0.01 μm or more and 3 μm or less. When the height of the second uneven structure 160 in the stacking direction is 0.01 μm or less, it is difficult to form the mold 110 for forming the second uneven structure 160 by the imprint method. When the height of the second concavo-convex structure 160 in the stacking direction is 3 μm or more, depending on the thickness of the insulating layer, it is too deep and penetrates to the lower layer, resulting in unnecessary roughness. As for the surface roughness in the second uneven structure 160 measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.5 or more and 1.5 or less, and the ten-point average roughness Rz _JIS is 1.5 or more. 2.5 or less. The surface roughness in the second region is formed larger than the surface roughness in the region in contact with the first wiring 340.

FIG. 8B is a diagram illustrating a process of forming the first conductor 200 on the first insulating layer 100 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. The first trench 120, the first uneven structure 140a, the first uneven structure 140b, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100 formed in FIG. 8A. Is formed so as to be covered with the first conductor 200. In this embodiment, copper was deposited using a sputtering method. However, the present invention is not limited to this, and the first conductor 200 may be a seed layer for filling metal by an electrolytic plating method in the next step. It may also be a seed layer and / or a barrier layer. The first conductor 200 includes the first trench 120, the first uneven structure 140a, the first uneven structure 140b, and the second uneven structure 160 of the first insulating layer 100 formed in FIG. , And the first through hole 180 is reflected. In other words, the first conductor 200 includes the first trench 120 of the first insulating layer 100, the first uneven structure 140a, the first uneven structure 140b, the second uneven structure 160, and the first It is formed along the through hole 180. That is, the first conductor 200 has a concavo-convex structure formed in the first insulating layer 100. However, the present invention is not limited to this, and the uneven structure formed in the first insulating layer 100 may be at least partially filled with the first conductor 200.

FIG. 8C is a diagram illustrating a process of forming the second conductor 220 on the first conductor 200 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. The first trench 120, the first uneven structure 140a, the first uneven structure 140b, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100 formed in FIG. 8A. Is filled with the second conductor 220. In the present embodiment, the first trench 120, the first uneven structure 140a, the first uneven structure 140b, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100 are electroplated. Fill with copper using the method. However, the present invention is not limited to this, and the first trench 120, the first uneven structure 140a, the first uneven structure 140b, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100 are made of metal. As a filling method, a printing method or the like can also be used.

FIG. 8D is a diagram illustrating a process of polishing the first insulating layer 100 in the method for manufacturing a wiring substrate according to an embodiment of the present disclosure. As shown in FIG. 8D, substantially the entire surface of the first insulating layer 100 is polished. In the present embodiment, the surface of the first insulating layer 100 is polished using a chemical mechanical polishing method. By selectively polishing the first conductor 200 and the second conductor 220 on the first insulating layer 100, unnecessary first portions other than those in the first trench 120 and the first through-hole 180 are provided. The conductor 200 and the second conductor 220 can be removed. As a result, the second uneven structure 160 of the first insulating layer 100 is exposed. The first conductor 200 and the second conductor 220 in the first trench 120a and the first trench 120b are formed as a first wiring 340a and a first wiring 340b. The first conductor 200 and the second conductor 220 in the first through-hole 180a (not shown) and the first through-hole 180b are connected to the first interlayer connection 360a (not shown) and the first conductor The interlayer connection 360b is formed. In the present embodiment, the first wiring 340 and the first interlayer connection 360 are integrally formed, but the present invention is not limited to this. Each may be formed separately.

FIG. 8E is a diagram illustrating a process of laminating the second insulating layer 400 on the first insulating layer 100 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. In the present embodiment, the second insulating layer 400 is formed by applying on the first insulating layer 100. Here, the second insulating layer 400 is formed so as to fill the second uneven structure 160 of the first insulating layer 100 formed in FIG. That is, the second insulating layer 400 reflects the second uneven structure 160 of the first insulating layer 100. In other words, the second insulating layer 400 has an uneven structure in a region in contact with the first insulating layer 100. The second uneven structure 160 of the first insulating layer 100 and the uneven structure of the second insulating layer 400 are bonded so as to mesh with each other. By stacking the second insulating layer 400 on the first insulating layer 100, the first wiring 340 and the first interlayer connection 360 are embedded in the first insulating layer 100 and the second insulating layer 400. Is done.

FIG. 8F illustrates a method of manufacturing a wiring board according to an embodiment of the present disclosure, in which the second wiring 640 and the second wiring 640 are formed on the second insulating layer 400 by the processes of FIGS. It is a figure which shows the process of forming the interlayer connection part 660 of. Similar to the first insulating layer 100, an uneven structure, a second trench, and a second through hole are formed in the second insulating layer 400 by an imprint method, and the first conductor and the second conductor are formed. After filling with the body, polishing is performed, whereby the concavo-convex structure, the second wiring 640, and the second interlayer connection portion 660 are formed in the second insulating layer 400. In this embodiment, the manufacturing method of the wiring board provided with two insulating layers and the conductor formed in each insulating layer was shown. However, the present invention is not limited thereto, and a wiring board having two or more insulating layers can be appropriately prepared by preparing a mold having a trench having an arbitrary pattern in each layer, a through hole, and a protrusion corresponding to the concavo-convex structure. Can be formed.

FIG. 8G is a diagram illustrating a process of forming the first electrode 380 and the second electrode 680 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. In this embodiment, the second electrode 680 is formed using photolithography. However, the present invention is not limited to this. For example, the second electrode 680 may be formed integrally with the second wiring 640 and the second interlayer connection 660. In this embodiment mode, the first electrode 380 is formed by photolithography, but is not limited thereto. Although not shown in FIG. 8, the first insulating layer 100 may have a substrate (not shown) on the second surface opposite to the first surface. In this case, a step of first peeling the substrate may be included. On the second surface of the first insulating layer 100, a residue of the insulating material may remain in the first through hole 180. For this reason, the residue of the insulating material is removed by performing a wet process using a permanganate solution or a dry process using oxygen plasma. By removing the residue of the insulating material, a favorable electrode connection can be obtained, and a wiring board with improved reliability can be provided. Note that the first electrode 380 may be formed after a semiconductor component described later is disposed.

As described above, according to the method for manufacturing the wiring substrate 40 according to the present embodiment, the second concavo-convex structure 160 can be formed in the second region where the first insulating layer 100 is in contact with the second insulating layer 400. it can. In such a selective roughened surface forming method, by forming the second concavo-convex structure 160 in the first insulating layer 100, the region of the second insulating layer 400 that is in contact with the first insulating layer 100 is uneven. A structure is formed. The uneven structure of the second insulating layer 400 is formed so as to fit into the uneven structure of the first insulating layer 100. By bonding so that the concavo-convex structure of the first insulating layer 100 and the second insulating layer 400 is engaged with each other, the adhesion can be improved and peeling can be prevented. As a result, a wiring board with improved reliability can be provided.

According to the method for manufacturing the wiring substrate 40 according to the present embodiment, the area where the first insulating layer 100 is in contact with the first wiring 340a has a smaller surface roughness than the area where the first insulating layer 100 is in contact with the first wiring 340b. Therefore, the first wiring 340a can be formed to have a surface roughness smaller than that of the first wiring 340b. The rough surface of the wiring surface has a large effect of increasing the conductor resistance due to the skin effect when driven in a high frequency band, that is, increasing the conductor loss. For this reason, by increasing the conductor resistance due to the skin effect when driven in the high frequency band, that is, by forming the conductor having a long total length that has a large influence on causing an increase in the conductor loss to have a smaller surface roughness, A wiring board with improved transmission characteristics can be provided.

The region where the first insulating layer 100 is in contact with the first wiring 340b has a surface roughness larger than the region where the first insulating layer 100 is in contact with the first wiring 340a, so that the first wiring 340b is the first wiring 340b. A surface roughness larger than that of the wiring 340a is formed. The uneven structure of the first wiring 340b is formed so that the first insulating layer 100 fits into the first uneven structure 140b in a region in contact with the first wiring 340b. Adhesion can be improved by adhering the concavo-convex structures so as to mesh with each other. By increasing the conductor resistance due to the skin effect when driven in a high frequency band, that is, the conductor having a smaller influence causing an increase in the conductor loss has a larger surface roughness, the conductor loss due to the skin effect is suppressed, and the first The adhesion between the insulating layer 100 and the conductor can be improved, and a wiring board with improved reliability can be provided.

<Fifth Embodiment>
The wiring board according to the fifth embodiment includes a first wiring that is a transmission wiring and a third wiring that is electrically connected to a power supply or a ground, and the first insulating layer is in contact with the first wiring. The first region has a smaller surface roughness than the fifth region where the first insulating layer is in contact with the third wiring.

The configuration of the wiring board 50 and the method for manufacturing the wiring board 50 according to the fifth embodiment of the present disclosure will be described with reference to FIG. 9 or FIG. Here, the detailed description of the same parts as those in the first embodiment is omitted.

[Configuration of wiring board]
9A is a top view, FIG. 9B is a cross-sectional view, and FIG. 9C is an enlarged view illustrating an example of a wiring board according to an embodiment of the present disclosure. FIG. 9B is a cross-sectional view taken along the line AA ′ of FIG. FIG. 9C is an enlarged view in a region B in FIG. 9B, and FIG. 9D is an enlarged view in a region C in FIG. 9B. As shown in FIGS. 9A and 9B, the wiring board 50 includes a first insulating layer 100, a second insulating layer 400, and a conductor formed in each insulating layer.

The conductor of the first insulating layer 100 includes a first wiring 340, a first interlayer connection 360 (not shown), a first electrode 380 (not shown), a third wiring 540, , A third interlayer connection (not shown), and a third electrode (not shown). The first insulating layer 100 includes a first wiring 340 and a third wiring 540 on the first surface. The first wiring 340 is electrically connected to a first interlayer connection 360 (not shown) penetrating the first insulating layer 100 at one end. First interlayer connecting portion 360 (not shown) is electrically connected to first electrode 380 (not shown) on the second surface opposite to the first surface of first insulating layer 100. . The third wiring 540 is electrically connected to a third interlayer connection portion (not shown) that penetrates the first insulating layer 100. The third interlayer connection portion (not shown) is electrically connected to the third electrode (not shown) on the second surface of the first insulating layer 100. In the present embodiment, the first wiring 340 is a transmission wiring, and the third wiring 540 is electrically connected to a power supply or a ground. Moreover, although the example which has arrange | positioned the 1st wiring 340 on the 1st surface was shown, it is not limited to this. One or more first wirings 340 may be arranged on the first surface. In the present embodiment, the first wiring 340 and the third wiring 540 are arranged only on the first surface of the first insulating layer 100. However, the first wiring 340 is the first wiring 340 on the opposite side of the first surface. It may be arranged on two sides.

A second insulating layer 400 is disposed on the first surface of the first insulating layer 100. The conductor of the second insulating layer 400 includes a second wiring 640, a second interlayer connection 660 (not shown), a second electrode 680 (not shown), a fourth wiring 740, , A fourth interlayer connection (not shown), and a fourth electrode (not shown). The second insulating layer 400 includes a second wiring 640 and a fourth wiring 740 on the third surface opposite to the first insulating layer 100. The second wiring 640 is electrically connected to a second interlayer connection portion 660 (not shown) that penetrates the second insulating layer 400. Second interlayer connection portion 660 (not shown) is further electrically connected to the other end opposite to one end of first wiring 340. The second wiring 640 is electrically connected to the second electrode 680 (not shown) on the third surface of the second insulating layer 400. The fourth wiring 740 is electrically connected to a fourth interlayer connection portion (not shown) that penetrates the first insulating layer 100. The fourth interlayer connection portion (not shown) is electrically connected to the fourth electrode (not shown) on the second surface of the first insulating layer 100. In the present embodiment, the second wiring 640 is a transmission wiring, and the fourth wiring 740 is electrically connected to a power supply or a ground. Moreover, although the example which has arrange | positioned one 2nd wiring 640 on the 3rd surface was shown, it is not limited to this. One or more second wirings 640 may be arranged on the third surface.

FIG. 9C is an enlarged view of region B in FIG. 9B. FIG. 9D is an enlarged view of a region C in FIG. 9B. As shown in FIGS. 9C and 9D, the first insulating layer 100 is in contact with the first wiring 340, the third wiring 540, and the second insulating layer 400.

In the first region where the first insulating layer 100 is in contact with the first wiring 340, the first uneven structure 140 is formed. As for the surface roughness in the first region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.1 or less, and the ten-point average roughness Rz _JIS is 0.1 or less. More preferably, the first region is substantially flat. Further, the surface roughness in the first region is smaller than the surface roughness in the fifth region where the first insulating layer 100 is in contact with the third wiring 540.

On the other hand, the second uneven structure 160 in the second region where the first insulating layer 100 is in contact with the second insulating layer 400 has a height in the stacking direction of 0.01 μm or more and 3 μm or less. As for the surface roughness in the second region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.5 or more and 1.5 or less, and the ten-point average roughness Rz _JIS is 1.5 or more and 2. 5 or less. From the first region where the first insulating layer 100 is in contact with the first wiring 340 and the fifth region where the first insulating layer 100 is in contact with the third wiring 540, the first insulating layer 100 is the second insulating layer. The second region in contact with layer 400 has a large surface roughness.

In the present embodiment, the first region has a surface roughness smaller than that of the fifth region, so that the first wiring 340 has a surface roughness smaller than that of the third wiring 540. The rough surface on the surface of the transmission wiring has a larger influence on the increase in the conductor resistance due to the skin effect when driven in the high frequency band, that is, the increase in the conductor loss, than the rough surface on the surface of the wiring electrically connected to the power source or the ground. For this reason, the wiring board has improved transmission characteristics in the high frequency band by having a smaller surface roughness for a conductor that has a greater effect of causing an increase in conductor resistance due to the skin effect when driven in the high frequency band, that is, an increase in conductor loss. Can be provided.

Since the fifth region has a surface roughness larger than that of the first region, the third wiring 540 has a surface roughness larger than that of the first wiring 340. The uneven structure of the third wiring 540 is formed so as to fit into the fifth uneven structure 140c in the fifth region. Adhesion can be improved by adhering the concavo-convex structures so as to mesh with each other. The rough surface on the surface of the transmission wiring has a larger influence on the increase in the conductor resistance due to the skin effect when driven in the high frequency band, that is, the increase in the conductor loss, than the rough surface on the surface of the wiring electrically connected to the power source or the ground. By increasing the conductor resistance due to the skin effect when driven in a high frequency band, that is, the conductor having a smaller influence causing an increase in the conductor loss has a larger surface roughness, the conductor loss due to the skin effect is suppressed, and the first The adhesion between the insulating layer 100 and the conductor can be improved, and a wiring board with improved reliability can be provided.

In the present embodiment, the second region where the first insulating layer 100 is in contact with the second insulating layer 400 has the second uneven structure 160. When the first insulating layer 100 has the second uneven structure 160 in the second region, the uneven structure is also formed in the region of the second insulating layer 400 in contact with the first insulating layer 100. The uneven structure of the second insulating layer 400 is formed so as to fit into the second uneven structure 160 of the first insulating layer 100. By adhering the second concavo-convex structure 160 of the first insulating layer 100 and the concavo-convex structure of the second insulating layer 400 so as to mesh with each other, the adhesion can be improved. As a result, a wiring board with improved reliability can be provided.

In the present embodiment, the wiring board 50 includes two insulating layers and a conductor formed on each insulating layer. In the first insulating layer 100, the fifth region has a surface roughness larger than that of the first region, and the second region has surface roughness larger than that of the fifth region. However, the present invention is not limited to this. For example, the wiring board may include m insulating layers and a conductor formed on each insulating layer. In this case, the region where the nth insulating layer is in contact with the wiring electrically connected to the power supply or the ground has a larger surface roughness than the region where the nth insulating layer is in contact with the transmission wiring. The region where the nth insulating layer is in contact with the (n + 1) th insulating layer may have a larger surface roughness than the region in contact with the wiring electrically connected to the power supply or the ground. (M is an arbitrary natural number of 3 or more, and n is an arbitrary natural number of 1 or more and m-1 or less.)

When the wiring board includes three or more insulating layers and a conductor formed on each insulating layer, the n-th insulating layer may be included in plural or a combination of arbitrary layers. The region where the insulating layer is in contact with the wiring electrically connected to the power supply or the ground has a larger surface roughness than the region where the insulating layer is in contact with the transmission wiring, and the insulating layer is electrically connected to the power supply or ground. Since the region where the insulating layers are in contact with each other has a larger surface roughness than the region where the wiring is connected to the wiring, the adhesion can be further improved. As a result, a wiring board with further improved reliability can be provided.

In the present embodiment, the second insulating layer that is the uppermost layer also has a surface roughness in which the region where the second insulating layer is in contact with the fourth wiring is larger than the region where the second insulating layer is in contact with the second wiring. The region where the second insulating layer is exposed on the uppermost surface is larger in surface roughness than the region where the second insulating layer is in contact with the second wiring and the region where the second insulating layer is in contact with the fourth wiring. Have Since the uppermost insulating layer has a larger surface roughness in the region exposed on the uppermost surface than the region where the insulating layer is in contact with the wiring, the adhesion of the resin layer described later can be improved. As a result, a semiconductor device with further improved reliability can be provided.

[Method for Manufacturing Wiring Board 50]
A method of manufacturing a wiring board according to an embodiment of the present disclosure will be described using FIG. In FIG. 10, the same elements as those shown in FIG.

FIG. 10A illustrates a method for manufacturing a wiring board according to an embodiment of the present disclosure, in which a first trench 120a, a first trench 120c, and a second unevenness are formed on the first insulating layer 100 by imprinting. It is a figure which shows the process of forming the structure 160, the 5th uneven structure 140c, the 1st through-hole 180a (not shown), and the 1st through-hole 180c (not shown) (henceforth, 1st trench 120a). When the first trench 120c is not distinguished, the first trench 120 is referred to as the first trench 120. When the first through hole 180a is not distinguished from the first through hole 180c, the first trench 120c is referred to as the first through hole 180. First, the mold 110 for forming the first trench 120, the second uneven structure 160, the fifth uneven structure 140 c, and the first through hole 180 is formed in the first insulating layer 100. The mold 110 has protrusions corresponding to the first trench 120, the second uneven structure 160, the fifth uneven structure 140 c, and the first through hole 180. The surfaces of the protrusions of the mold 110 corresponding to the first trenches 120a and the first through holes 180 are formed to be substantially flat.

Next, the first trench 120, the second concavo-convex structure 160, the fifth concavo-convex structure 140c, and the first through-hole 180 are imprinted on the first surface of the first insulating layer 100 using the mold 110. . Although not shown in FIG. 10, the first insulating layer 100 may be formed by coating on a substrate (not shown). In this case, the surface of the first insulating layer 100 opposite to the substrate is the first surface. The first insulating layer 100 is softened, and the mold 110 is pressed into the first surface. In this state, the first insulating layer 100 is cured, and the mold 110 is peeled from the first insulating layer 100, whereby the first insulating layer 100 having a cross-sectional structure illustrated in FIG. Insulating material residues may remain in the first trench 120, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100. For this reason, the residue of the insulating material is removed by performing a wet process using a permanganate solution or a dry process using oxygen plasma. By removing the residue of the insulating material, a good interlayer connection can be obtained, and a wiring board with improved reliability can be provided.

In this embodiment, the 1st trench 120, the 2nd uneven structure 160, the 5th uneven structure 140c, and the 1st through-hole 180 are integrally formed by the imprint method. As a result, the manufacturing process can be simplified. In addition, the imprint method uses less chemical solution than a general photolithography method and is environmentally friendly.

A first uneven structure 140a is formed on the inner surface of the first trench 120a formed in the first insulating layer 100 by an imprint method. As for the surface roughness in the first region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.1 or less, and the ten-point average roughness Rz _JIS is 0.1 or less. More preferably, the inner surface of the first trench 120a is substantially flat.

In the present embodiment, the surface roughness on the inner surface (first region) of the first trench 120a is formed to be smaller than the surface roughness on the inner surface (fifth region) of the first trench 120c. . In the fifth region formed in the first insulating layer 100, a fifth uneven structure 140c is formed by an imprint method. For this reason, the area | region inside the 1st trench 120a has surface roughness smaller than a 5th area | region.

On the other hand, the second concavo-convex structure 160 formed on the first insulating layer 100 has a height in the stacking direction of 0.01 μm or more and 3 μm or less. When the height of the second uneven structure 160 in the stacking direction is 0.01 μm or less, it is difficult to form the mold 110 for forming the second uneven structure 160 by the imprint method. When the height of the second concavo-convex structure 160 in the stacking direction is 3 μm or more, depending on the thickness of the insulating layer, it is too deep and penetrates to the lower layer, resulting in unnecessary roughness. As for the surface roughness in the second uneven structure 160 measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.5 or more and 1.5 or less, and the ten-point average roughness Rz _JIS is 1.5 or more. 2.5 or less. The surface roughness in the second region is formed to be larger than the surface roughness in the region inside the first trench 120a and the fifth region.

FIG. 10B is a diagram illustrating a process of forming the first conductor 200 on the first insulating layer 100 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. The first trench 120, the first uneven structure 140a, the fifth uneven structure 140c, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100 formed in FIG. Is formed so as to be covered with the first conductor 200. In this embodiment, copper was deposited using a sputtering method. However, the present invention is not limited to this, and the first conductor 200 may be a seed layer for filling metal by an electrolytic plating method in the next step. It may also be a seed layer and / or a barrier layer. The first conductor 200 includes the first trench 120, the first uneven structure 140a, the fifth uneven structure 140c, and the second uneven structure 160 of the first insulating layer 100 formed in FIG. , And the first through hole 180 is reflected. In other words, the first conductor 200 includes the first trench 120 of the first insulating layer 100, the first uneven structure 140a, the fifth uneven structure 140c, the second uneven structure 160, and the first It is formed along the through hole 180. That is, the first conductor 200 has a concavo-convex structure formed in the first insulating layer 100. However, the present invention is not limited to this, and the uneven structure formed in the first insulating layer 100 may be at least partially filled with the first conductor 200.

FIG. 10C is a diagram illustrating a process of forming the second conductor 220 on the first conductor 200 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. The first trench 120, the first uneven structure 140a, the fifth uneven structure 140c, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100 formed in FIG. Is filled with the second conductor 220. In the present embodiment, the first trench 120, the first uneven structure 140a, the fifth uneven structure 140c, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100 are electroplated. Fill with copper using the method. However, the present invention is not limited to this, and the first trench 120, the first uneven structure 140a, the fifth uneven structure 140c, the second uneven structure 160, and the first through hole 180 of the first insulating layer 100 are made of metal. As a filling method, a printing method or the like can also be used.

FIG. 10D is a diagram illustrating a process of polishing the first insulating layer 100 in the method for manufacturing a wiring substrate according to an embodiment of the present disclosure. As shown in FIG. 10D, the substantially entire surface of the first insulating layer 100 is polished. In the present embodiment, the surface of the first insulating layer 100 is polished using a chemical mechanical polishing method. By selectively polishing the first conductor 200 and the second conductor 220 on the first insulating layer 100, unnecessary first portions other than those in the first trench 120 and the first through-hole 180 are provided. The conductor 200 and the second conductor 220 can be removed. As a result, the second uneven structure 160 of the first insulating layer 100 is exposed. The first conductor 200 and the second conductor 220 in the first trench 120 a and the first trench 120 c are formed as a first wiring 340 and a third wiring 540. The first conductor 200 and the second conductor 220 in the first through hole 180a (not shown) and the first through hole 180c (not shown) are connected to a first interlayer connection 360a (not shown). And third interlayer connection 560 (not shown). In the present embodiment, the first wiring 340 and the first interlayer connection 360 are integrally formed, but the present invention is not limited to this. Each may be formed separately.

FIG. 10E is a diagram illustrating a process of laminating the second insulating layer 400 on the first insulating layer 100 in the method for manufacturing a wiring board according to an embodiment of the present disclosure. In the present embodiment, the second insulating layer 400 is formed by applying on the first insulating layer 100. Here, the second insulating layer 400 is formed so as to fill the second uneven structure 160 of the first insulating layer 100 formed in FIG. That is, the second insulating layer 400 reflects the second uneven structure 160 of the first insulating layer 100. In other words, the second insulating layer 400 has an uneven structure in a region in contact with the first insulating layer 100. The second uneven structure 160 of the first insulating layer 100 and the uneven structure of the second insulating layer 400 are bonded so as to mesh with each other. By stacking the second insulating layer 400 on the first insulating layer 100, the first wiring 340 and the first interlayer connection 360 are embedded in the first insulating layer 100 and the second insulating layer 400. Is done.

FIG. 10F illustrates a method for manufacturing a wiring board according to an embodiment of the present disclosure. In the method of FIGS. 10A to 10D, the second wiring 640 and the second wiring 640 are formed on the second insulating layer 400. It is a figure which shows the process of forming the 2nd interlayer connection part 660, the 4th wiring 740, and the 4th interlayer connection part 760. Similar to the first insulating layer 100, an uneven structure, a second trench, and a second through hole are formed in the second insulating layer 400 by an imprint method, and the first conductor and the second conductor are formed. After filling with a body, the second insulating layer 400 is polished to form an uneven structure, a second wiring 640, a second interlayer connection 660, a fourth wiring 740, and a fourth interlayer connection 760. Form. In this embodiment, the manufacturing method of the wiring board provided with two insulating layers and the conductor formed in each insulating layer was shown. However, the present invention is not limited thereto, and a wiring board having two or more insulating layers can be appropriately prepared by preparing a mold having a trench having an arbitrary pattern in each layer, a through hole, and a protrusion corresponding to the concavo-convex structure. Can be formed.

FIG. 10G shows a step of forming a first electrode 380 (not shown) and a second electrode 680 (not shown) in the method for manufacturing a wiring board according to an embodiment of the present disclosure. FIG. In this embodiment, the second electrode 680 is formed using photolithography. However, the present invention is not limited to this. For example, the second electrode 680 may be formed integrally with the second wiring 640 and the second interlayer connection 660. In this embodiment mode, the first electrode 380 is formed by photolithography, but is not limited thereto. Although not shown in FIG. 10, the first insulating layer 100 may have a substrate (not shown) on the second surface opposite to the first surface. In this case, a step of first peeling the substrate may be included. On the second surface of the first insulating layer 100, a residue of the insulating material may remain in the first through hole 180. For this reason, the residue of the insulating material is removed by performing a wet process using a permanganate solution or a dry process using oxygen plasma. By removing the residue of the insulating material, a favorable electrode connection can be obtained, and a wiring board with improved reliability can be provided. Note that the first electrode 380 may be formed after a semiconductor component described later is disposed.

As described above, according to the method for manufacturing the wiring substrate 50 according to the present embodiment, the second concavo-convex structure 160 can be formed in the second region where the first insulating layer 100 is in contact with the second insulating layer 400. it can. The fifth uneven structure 140 c can be formed in a fifth region where the first insulating layer 100 is in contact with the third wiring 540. In such a selective roughened surface forming method, by forming the second concavo-convex structure 160 in the first insulating layer 100, the region of the second insulating layer 400 that is in contact with the first insulating layer 100 is uneven. A structure is formed. The uneven structure of the second insulating layer 400 is formed so as to fit into the uneven structure of the first insulating layer 100. By bonding so that the concavo-convex structure of the first insulating layer 100 and the second insulating layer 400 is engaged with each other, the adhesion can be improved and peeling can be prevented. By forming the fifth concavo-convex structure 140 c in the fifth region of the first insulating layer 100, the concavo-convex structure is formed in the region in contact with the first insulating layer 100 of the third wiring 540. The uneven structure of the third wiring 540 is formed so as to fit into the uneven structure of the first insulating layer 100. By bonding so that the uneven structure of the first insulating layer 100 and the third wiring 540 is engaged with each other, the adhesion can be improved and peeling can be prevented. As a result, a wiring board with improved reliability can be provided.

According to the method for manufacturing the wiring substrate 50 according to the present embodiment, the first wiring 340 has a surface roughness smaller than that of the third wiring 540 because the first area has a surface roughness smaller than that of the fifth area. Can be formed. The rough surface on the surface of the transmission wiring has a great effect of increasing the conductor resistance due to the skin effect when driven in the high frequency band, that is, increasing the conductor loss. For this reason, by increasing the conductor resistance due to the skin effect when driven in the high frequency band, that is, by forming the conductor having a large influence that causes an increase in the conductor loss to have a smaller surface roughness, the transmission characteristics in the high frequency band can be improved. An improved wiring board can be provided.

Since the fifth region has a surface roughness larger than that of the first region, the third wiring 540 has a surface roughness larger than that of the first wiring 340. The uneven structure of the third wiring 540 is formed so as to fit into the fifth uneven structure 140c in the fifth region. Adhesion can be improved by adhering the concavo-convex structures so as to mesh with each other. By increasing the conductor resistance due to the skin effect when driven in a high frequency band, that is, the conductor having a smaller influence causing an increase in the conductor loss has a larger surface roughness, the conductor loss due to the skin effect is suppressed, and the first The adhesion between the insulating layer 100 and the conductor can be improved, and a wiring board with improved reliability can be provided.

<Sixth Embodiment>
In the present embodiment, an example of a semiconductor device in which a semiconductor component is mounted on the wiring board according to the first to fifth embodiments will be described. Here, the detailed description of the same parts as those of the wiring boards according to the first to fifth embodiments is omitted.

The configuration of the semiconductor device 1 and the method for manufacturing the semiconductor device 1 according to the sixth embodiment of the present disclosure will be described with reference to FIGS. Here, the detailed description of the same parts as those in the first embodiment is omitted.

[Configuration of semiconductor device]
11A is a top view, FIG. 11B is a cross-sectional view, and FIG. 11C is an enlarged view illustrating an example of a conductor device according to an embodiment of the present disclosure. FIG. 11B is a cross-sectional view taken along the line AA ′ of FIG. FIG. 11C is an enlarged view of a region B in FIG. As shown in FIGS. 11A and 11B, a semiconductor device 1 includes a wiring substrate 60 having a second electrode 680 and a semiconductor having a fifth electrode 820 electrically connected to the second electrode 680. A component 800, a first resin layer 840 that embeds the semiconductor component 800, and a second resin layer 860 disposed in a gap between the semiconductor component 800 and the wiring substrate 60 are provided. Further, the first electrode 380 of the wiring board 60 is provided with a solder ball 900.

As shown in the first to fifth embodiments, the wiring board 60 includes the second electrode 680 on the third surface of the second insulating layer 400 opposite to the first insulating layer 100. On the third surface of the second insulating layer 400, the semiconductor component 800 is disposed with a gap. The semiconductor component 800 includes a fifth electrode 820 for external power supply and signal input / output. The second electrode 680 of the wiring board 60 and the fifth electrode 820 of the semiconductor component 800 face each other and are electrically connected via the conductive member 880. The fifth electrode 820 is made of, for example, gold, silver, copper, aluminum, or the like, but is not limited thereto.

The semiconductor component 800 is embedded with the first resin layer 840. The first resin layer 840 is disposed so as to cover the non-circuit surface of the semiconductor component 800 and is in contact with the third surface of the second insulating layer 400 of the wiring board 60. A second resin layer 860 is disposed in the gap between the third surface of the second insulating layer 400 of the wiring substrate 60 and the semiconductor component 800. That is, the second resin layer 860 is in contact with the third surface of the second insulating layer 400 and the circuit surface of the semiconductor component 800, the second electrode 680 of the wiring substrate 60, and the fifth electrode of the semiconductor component 800. 820 and embedded.

In the present embodiment, the first insulating layer 100, the second insulating layer 400, the first resin layer 840, and the second resin layer 860 of the wiring board 60 include an epoxy resin. As the epoxy resin, for example, a liquid epoxy resin such as a bisphenol type epoxy resin or an alicyclic epoxy resin can be used. Moreover, you may use together semisolid epoxy resins, such as a phenol novolak type and a naphthalene type. However, the present invention is not limited to this, and the first insulating layer 100, the second insulating layer 400, the first resin layer 840, and the second resin layer 860 of the wiring board 60 have the same thermal expansion coefficient. Any material can be used. Since the first insulating layer 100, the second insulating layer 400, and the first resin layer 840 of the wiring board 60 are made of a material having the same thermal expansion coefficient, inconsistency in linear expansion coefficient particularly in the stacking direction. Therefore, the reliability of the semiconductor component 800 can be improved.

In the present embodiment, the first resin layer 840 and the second resin layer 860 may further include a filler. The filler may be, for example, a silica-based inorganic filler. Since the first resin layer 840 and the second resin layer 860 include a filler, a semiconductor device that can be configured with a low coefficient of thermal expansion and has improved reliability with suppressed thermal strain can be provided. . The maximum particle size of the first filler contained in the first resin layer 840 is preferably 10 μm or more and 100 μm or less. When the maximum particle size is 10 μm or less, the cost required for cutting the filler increases, such being undesirable. When the maximum particle size is 100 μm or more, fluidity is impaired in the molding process of the first resin layer 840, unfilling may occur, and productivity may be impaired. The maximum particle size of the second filler contained in the second resin layer 860 is preferably 1 μm or more and 10 μm or less. When the maximum particle size is 1 μm or less, the cost required for cutting the filler increases, such being undesirable. When the maximum particle size is 10 μm or more, fluidity is impaired in the filling step of the second resin layer 860, unfilling may occur, and productivity may be impaired.

Solder balls 900 for connecting the semiconductor device 1 to an external substrate are disposed on the first electrode 380 of the wiring substrate 60. By connecting the semiconductor device 1 to the external substrate with the solder balls 900, there is an effect that can be implemented at low cost.

FIG. 11C is an enlarged view of a region B in FIG. As shown in FIG. 11C, the second insulating layer 400 is in contact with the second wiring 640, the first resin layer 840, and the second resin layer 860.

In a sixth region where the second insulating layer 400 is in contact with the second wiring 640, a sixth uneven structure 440 is formed. As for the surface roughness in the sixth region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.1 or less, and the ten-point average roughness Rz _JIS is 0.1 or less. More preferably, the sixth region is substantially flat.

On the other hand, the seventh uneven structure 460 in the seventh region where the second insulating layer 400 is in contact with the first resin layer 840 and the second resin layer 860 has a height in the stacking direction of 0.01 μm or more and 3 μm or less. Range. As for the surface roughness in the second region measured based on JIS B0601-2001, the arithmetic average roughness Ra is 0.5 or more and 1.5 or less, and the ten-point average roughness Rz _JIS is 1.5 or more and 2. 5 or less. The seventh region where the second insulating layer 400 is in contact with the first resin layer 840 and the second resin layer 860 is larger than the sixth region where the second insulating layer 400 is in contact with the second wiring 640. Have

In the present embodiment, the sixth region where the second insulating layer 400 is in contact with the second wiring 640 has a small surface roughness. Since the sixth region of the first insulating layer 100 has a small surface roughness, the second wiring 640 has a small surface roughness in a region in contact with the second insulating layer 400. The rough surface on the surface of the conductor can cause an increase in conductor resistance due to the skin effect when driven in a high frequency band, that is, an increase in conductor loss. Therefore, since the region of the second wiring 640 in contact with the second insulating layer 400 has a small surface roughness, a semiconductor device with improved transmission characteristics in a high frequency band can be provided.

In the present embodiment, the seventh region where the second insulating layer 400 is in contact with the first resin layer 840 and the second resin layer 860 has a seventh uneven structure 460. Since the second insulating layer 400 has the seventh uneven structure 460 in the seventh region, the uneven structure is also formed in the regions of the first resin layer 840 and the second resin layer 860 that are in contact with the second insulating layer 400. Is formed. The uneven structure of the first resin layer 840 and the second resin layer 860 is formed so as to fit into the seventh uneven structure 460 of the second insulating layer 400. Adhesion can be improved by adhering the concavo-convex structures so as to mesh with each other. As a result, a semiconductor device with improved reliability can be provided. In the present embodiment, the region where the second insulating layer 400 is in contact with the first resin layer 840 and the region where the second insulating layer 400 is in contact with the second resin layer 860 are not distinguished as the seventh region. However, the size of the uneven structure 460a in the region in contact with the first resin layer 840 and the uneven structure 460b in the region in contact with the second resin layer 860 is appropriately determined depending on the material of each resin layer. Can be selected (hereinafter, when the concavo-convex structure 460a and the concavo-convex structure 460b are not distinguished, they are referred to as a seventh concavo-convex structure 460).

[Method of Manufacturing Semiconductor Device 1]
A method of manufacturing a semiconductor device according to an embodiment of the present disclosure will be described using FIG. In FIG. 12, the same elements as those shown in FIG.

FIG. 12A is a diagram illustrating a process of mounting the semiconductor component 800 on the third surface of the second insulating layer 400 of the wiring board 60 in the method for manufacturing a semiconductor device according to an embodiment of the present disclosure. is there. Before the semiconductor component 800 is placed on the wiring board 60, the second resin layer 860 is filled in advance. The third surface of the second insulating layer 400 of the wiring board 60 and the semiconductor component 800 are arranged with a gap therebetween. A gap between the third surface of the second insulating layer 400 of the wiring substrate 60 and the semiconductor component 800 is filled with the second resin layer 860. By filling the second resin layer 860 in advance, it is possible to provide a semiconductor device that can be satisfactorily filled without a bubble being formed therein and has improved reliability. The second electrode 680 of the wiring board 60 and the fifth electrode 820 of the semiconductor component 800 are electrically connected via the conductive member 880.

As shown in the first to fifth embodiments, the seventh region where the second resin layer 860 is in contact with the second insulating layer 400 has a seventh uneven structure 460. The uneven structure 460 b located in the gap between the third surface of the second insulating layer 400 and the semiconductor component 800 is filled with the second resin layer 860. That is, the second resin layer 860 reflects the uneven structure 460 b of the second insulating layer 400. In other words, the second resin layer 860 has an uneven structure in a region in contact with the second insulating layer 400. The uneven structure 460b of the second insulating layer 400 and the uneven structure of the second resin layer 860 are bonded so as to mesh with each other. By filling the gap between the second insulating layer 400 and the semiconductor component 800 with the second resin layer 860, the second electrode 680 of the wiring substrate 60 and the fifth electrode 820 of the semiconductor component 800 are Embedded in the second resin layer 860.

FIG. 12B is a diagram illustrating a process of embedding the semiconductor component 800 with the first resin layer 840 in the method for manufacturing a semiconductor device according to an embodiment of the present disclosure. The semiconductor component 800 is embedded with the first resin layer 840. The first resin layer 840 is formed so as to cover the non-circuit surface of the semiconductor component 800. The first resin layer 840 is also in contact with the third surface of the second insulating layer 400 of the wiring board 60. The seventh region where the first resin layer 840 is in contact with the second insulating layer 400 has a concavo-convex structure 460a. The uneven structure 460 a located on the third surface of the second insulating layer 400 is filled with the first resin layer 840. That is, the first resin layer 840 reflects the uneven structure 460 a of the second insulating layer 400. In other words, the first resin layer 840 has an uneven structure in a region in contact with the second insulating layer 400. The uneven structure 460a of the second insulating layer 400 and the uneven structure of the first resin layer 840 are bonded so as to mesh with each other.

FIG. 12C illustrates a process of placing solder balls on the semiconductor device in the method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Solder balls 900 for connecting the semiconductor device 1 to an external substrate are disposed on the first electrode 380 of the wiring substrate 60. By connecting the semiconductor device 1 to an external substrate with solder balls, there is an effect that can be implemented at low cost.

As described above, according to the method for manufacturing the semiconductor device 1 according to the present embodiment, the seventh unevenness in the seventh region where the second insulating layer 400 is in contact with the first resin layer 840 and the second resin layer 860. A structure 460 can be formed. In such a selective roughened surface forming method, by forming the seventh uneven structure 460 in the second insulating layer 400, the second insulation of the first resin layer 840 and the second resin layer 860 is achieved. An uneven structure is formed in a region in contact with the layer 400. The uneven structure of the first resin layer 840 and the second resin layer 860 is formed to fit into the uneven structure of the second insulating layer 400. By adhering the concave and convex structures of the second insulating layer 400, the first resin layer 840, and the second resin layer 860 to each other, the adhesion can be improved and peeling can be prevented. . As a result, a semiconductor device with improved reliability can be provided.

According to the manufacturing method of the semiconductor device 1 according to the present embodiment, the sixth region has a smaller surface roughness than the seventh region, and the second wiring 640 is formed to have a small surface roughness. Can do. The rough surface on the surface of the conductor can cause an increase in conductor resistance due to the skin effect when driven in a high frequency band, that is, an increase in conductor loss. By forming the region in contact with the second wiring 640 and the second insulating layer 400 with a small surface roughness, a semiconductor device with improved transmission characteristics in a high-frequency band can be provided.

The first concavo-convex structure and the second concavo-convex structure in the first insulating layer included in the wiring board according to the embodiment of the present disclosure described above will be described in more detail.

[Reference Example 1]
Since the concavo-convex structure according to Reference Example 1 of the present disclosure is the second concavo-convex structure according to one embodiment, detailed description thereof is omitted.

The parameters of the second uneven structure according to Reference Example 1 are as follows.
Shape of recess: Square column recess height: 2 μm
Recess width: 5 μm
Depth of recess: 5 μm
Recess pitch: 15 μm

[Reference Example 2]
Since the uneven structure according to Reference Example 2 of the present disclosure is the second uneven structure according to an embodiment, detailed description thereof is omitted.

The parameters of the second uneven structure according to Reference Example 2 are as follows.
Shape of recess: Square column recess height: 2 μm
Recess width: 5 μm
Depth of recess: 5 μm
Recess pitch: 10 μm

[Reference Example 3]
Since the uneven structure according to Reference Example 3 of the present disclosure is the first uneven structure according to an embodiment, detailed description thereof is omitted.

Each parameter of the first uneven structure according to Reference Example 3 is as follows.
Concave shape: None Concave height: 0 μm
Recess width: 0 μm
Depth of recess: 0 μm
Recessed pitch: 0 μm

The surface roughness of the 1st uneven structure in the 1st field with which the wiring board concerning one embodiment of this indication is provided, and the 2nd uneven structure in the 2nd field was measured. FIGS. 13 to 15 are an electron microscope (SEM) photograph on the upper surface (A) of the insulating layers of Reference Examples 1 to 3, (B) a contour graph showing the uneven structure on the upper surface, and (C) a graph showing the uneven structure on the cross section in FIGS. Show. Table 1 shows the arithmetic average roughness Ra and ten-point average roughness Rz _JIS of Reference Examples 1 to 3 measured based on JIS B0601-2001.

As shown in Table 1, in Reference Example 1 and Reference Example 2 as the second region, the surface roughness measured based on JIS B0601-2001 has an arithmetic average roughness Ra of 0.5 or more and 1.5 or less. The ten-point average roughness Rz _JIS was 1.5 or more and 2.5 or less. On the other hand, as for the surface roughness in the first region, the arithmetic average roughness Ra was 0.1 or less, and the ten-point average roughness Rz _JIS was 0.1 or less.

1: Semiconductor device 10, 20, 30, 40, 50, 60: Wiring substrate, 100: First insulating layer, 110: Mold, 120, 120a, 120b, 120c: First trench, 140, 140a, 140b : First uneven structure, 160: second uneven structure, 180, 180a, 180b, 180c: first through hole, 200: first conductor, 220: second conductor, 340, 340a, 340b : 1st wiring, 360, 360a, 360b: 1st interlayer connection part, 380, 380a, 380b: 1st electrode, 400: 2nd insulating layer, 460: 7th uneven structure, 540: 3rd 640, 640a, 640b: second wiring, 660, 660a, 660b: second interlayer connection, 680, 680a, 680b: second electrode, 740: fourth wiring, 800: semiconductor Goods, 820: fifth electrode, 840: first resin layer, 860: second resin layer, 880: conductive member, 900: solder ball,

Claims (33)

A wiring board having two or more insulating layers,
A first insulating layer comprising a first wiring on a first surface;
A second insulating layer disposed on the first surface,
A wiring substrate in which the second region where the first insulating layer is in contact with the second insulating layer has a larger surface roughness than the first region where the first insulating layer is in contact with the first wiring. The wiring board according to claim 1, wherein the surface roughness of the second region is an uneven structure having a height in the stacking direction of 0.01 μm or more and 3 μm or less. The surface roughness of the second region measured based on JIS B0601-2001 has an arithmetic average roughness Ra of 0.5 or more and 1.5 or less, and a ten-point average roughness Rz _JIS of 1.5 or more and 2 The wiring board according to claim 1, wherein the wiring board is 5 or less. 2. The surface roughness of the first region measured based on JIS B0601-2001 has an arithmetic average roughness Ra of 0.1 or less and a ten-point average roughness Rz _JIS of 0.1 or less. 4. The wiring board according to any one of items 1 to 3. The wiring board further includes a first interlayer connection portion that penetrates the first insulating layer and is electrically connected to the first wiring.
5. The wiring board according to claim 1, wherein the first region has a smaller surface roughness than the third region in which the first insulating layer is in contact with the first interlayer connection portion. 6. The wiring board further includes a first electrode disposed on a second surface opposite to the first surface of the first insulating layer and electrically connected to the first interlayer connection portion,
The wiring substrate according to claim 5, wherein the third region has a surface roughness smaller than that of a fourth region in which the first insulating layer is in contact with the first electrode. The wiring board according to claim 1, wherein in the first region, the bottom surface has a surface roughness smaller than that of the side surface. The first wiring is
A second wiring disposed on the first surface of the first insulating layer and extending in a first direction;
The first insulating layer is disposed on the first surface and includes a third wiring extending in a second direction orthogonal to the first direction;
The second wiring has a longer total extension than the third wiring,
The fifth region in which the first insulating layer is in contact with the second wiring has a smaller surface roughness than the sixth region in which the first insulating layer is in contact with the third wiring. The wiring board according to any one of the above. The first wiring is a transmission wiring,
A fourth wiring disposed on the first surface of the wiring board and electrically connected to a power source or a ground;
9. The wiring board according to claim 1, wherein the first region has a surface roughness smaller than that of a seventh region where the first insulating layer is in contact with the fourth wiring. A second interlayer connection portion that penetrates the second insulating layer and is electrically connected to the first wiring; and a third surface of the second insulating layer opposite to the first insulating layer. 10. The device according to claim 1, further comprising: a fifth wiring disposed and electrically connected to the second interlayer connection portion, and a second electrode electrically connected to the fifth wiring. The wiring board described in the section,
A semiconductor component having a third electrode disposed on the third surface via a gap and electrically connected to the second electrode;
A first resin layer in contact with the third surface of the second insulating layer and embedding the semiconductor component;
A semiconductor device comprising: The semiconductor device according to claim 10, further comprising a second resin layer disposed in the gap. The ninth region where the second insulating layer is in contact with the first resin layer has a larger surface roughness than the eighth region where the second insulating layer is in contact with the fifth wiring.
The semiconductor device according to claim 11, wherein the tenth region in which the second insulating layer is in contact with the second resin layer has a larger surface roughness than the eighth region. The surface roughness of the eighth region measured based on JIS B0601-2001 has an arithmetic average roughness Ra of 0.1 or less and a ten-point average roughness Rz _JIS of 0.1 or less. The semiconductor device described. The semiconductor device according to claim 10, wherein the first insulating layer, the second insulating layer, and the first resin layer contain the same material. The semiconductor device according to claim 14, wherein the first insulating layer, the second insulating layer, and the first resin layer include an epoxy resin. The semiconductor device according to claim 15, wherein the first resin layer includes a first filler. The semiconductor device according to claim 16, wherein a maximum particle size of the first filler is 10 μm or more and 100 μm or less. The semiconductor device according to claim 11, wherein the first insulating layer, the second insulating layer, and the second resin layer include the same material. The semiconductor device according to claim 18, wherein the first insulating layer, the second insulating layer, and the second resin layer include an epoxy resin. The semiconductor device according to claim 19, wherein the second resin layer includes a second filler. 21. The semiconductor device according to claim 20, wherein a maximum particle size of the second filler is 1 μm or more and 10 μm or less. The wiring board is
A first interlayer connection portion that penetrates the first insulating layer and is electrically connected to the first wiring;
A first electrode disposed on a second surface opposite to the first surface of the first insulating layer and electrically connected to the first interlayer connection;
The semiconductor device according to claim 10, further comprising a solder ball electrically connected to the first electrode. A trench disposed on the first surface of the first insulating layer and having a first uneven structure; a second uneven structure disposed on the first surface and larger than the first uneven structure; and the trench A through hole to be connected,
Forming a first wiring disposed in the trench and an interlayer connection disposed in the through hole;
A method of manufacturing a wiring board, wherein a second insulating layer is laminated on the first surface. 24. The method of manufacturing a wiring board according to claim 23, wherein a method of forming the trench, the second uneven structure, and the through hole is formed at a time by an imprint method. 25. The method of manufacturing a wiring board according to claim 24, wherein the method of forming the trench, the second uneven structure, and the through hole includes removing a residue of the first insulating layer. A method of forming the first wiring and the interlayer connection portion is as follows:
Forming a first conductor on the first surface so as to cover the trench, the second uneven structure, and the through hole;
Forming a second conductor in contact with the first conductor and filling the trench, the second uneven structure, and the through hole;
26. The method of manufacturing a wiring board according to claim 23, comprising removing the first conductor and the second conductor so that the second uneven structure is exposed. . A method of forming the first wiring and the interlayer connection portion is as follows:
Forming the first conductor by a sputtering method;
Forming the second conductor by electrolytic plating;
27. The method of manufacturing a wiring board according to claim 26, wherein the first conductor and the second conductor are removed by chemical mechanical polishing so that the second uneven structure is exposed. 28. The method for manufacturing a wiring board according to claim 23, wherein the second concavo-convex structure is formed so that a height in the stacking direction is 0.01 μm or more and 3 μm or less. The surface roughness of the second concavo-convex structure measured based on JIS B0601-2001 has an arithmetic average roughness Ra of 0.5 or more and 1.5 or less, and a ten-point average roughness Rz _JIS of 1.5 or more and 2 The method for manufacturing a wiring board according to any one of claims 23 to 28, wherein the wiring board is formed so as to be 5 or less. The first uneven structure is
The surface roughness of the first concavo-convex structure measured based on JIS B0601-2001 has an arithmetic average roughness Ra of 0.1 or less and a ten-point average roughness Rz _JIS of 0.1 or less. 30. The method for manufacturing a wiring board according to any one of items 29 to 29. Forming the first wiring includes
A second wiring disposed on the first surface of the first insulating layer and extending in a first direction;
A third wiring extending in a second direction orthogonal to the first direction;
Form the
When the total extension of the second wiring is longer than the total extension of the third wiring, the fifth region in which the first insulating layer is in contact with the second wiring has the first insulating layer 31. The method of manufacturing a wiring board according to claim 23, wherein the wiring board is formed to have a surface roughness smaller than that of a sixth region in contact with the third wiring. A wiring board according to any one of claims 1 to 9 is prepared,
A second interlayer connecting portion that penetrates the second insulating layer and is electrically connected to the first wiring on the wiring board; and a side of the second insulating layer opposite to the first insulating layer. Forming a fifth wiring electrically connected to the second interlayer connection portion and a second electrode electrically connected to the fifth wiring;
A semiconductor component having a third electrode electrically connected to the second electrode is disposed on the third surface with a gap;
Forming a first resin layer in contact with the third surface of the second insulating layer and embedding the semiconductor component;
A method of manufacturing a semiconductor device including: 33. The method of manufacturing a semiconductor device according to claim 32, further comprising forming a second resin layer disposed in the gap.