CN104780705B - The method of substrate and manufacture substrate - Google Patents
The method of substrate and manufacture substrate Download PDFInfo
- Publication number
- CN104780705B CN104780705B CN201410213857.1A CN201410213857A CN104780705B CN 104780705 B CN104780705 B CN 104780705B CN 201410213857 A CN201410213857 A CN 201410213857A CN 104780705 B CN104780705 B CN 104780705B
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- CN
- China
- Prior art keywords
- conductive layer
- hole
- layer
- substrate
- topmost
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09645—Patterning on via walls; Plural lands around one hole
Abstract
The invention discloses a kind of methods of substrate and manufacture substrate.Substrate according to the embodiment of the present invention includes：Dielectric layer, including via；First conductive layer, lamination is on the dielectric layer, wherein from the point of view of in vertical section figure when the first conductive layer, the edge for being adjacent to the downside vertex of via and being connect with downside vertex is formed as tilting and retreating along the direction far from via；And second conductive layer, second conductive layer filling in the vias and are laminated on the first conductive layer.
Description
The cross reference of related application
This application claims the South Korea patent application 10-2014- for submitting to Korean Intellectual Property Office on January 10th, 2014
Entire contents are hereby incorporated by by No. 0003536 equity by citation mode.
Technical field
The present invention relates to a kind of methods of substrate and manufacture substrate.
Background technology
With the progress of electronics industry, electronic device has gradually become lighter, thinner and smaller, and is used in these
Printed circuit board in electronic device needs lighter, thinner and smaller, and more functional.In order to meet this kind of demand, print
Printed circuit board is manufactured by carrying out internal via (IVH) technology.
In order to meet reliability, electrical property, heat dissipation, fine pattern etc., it is widely used that copper facing for carrying out IVH and fills out
Fill method.In plating copper filling-up method, the inside of micro- via is filled with copper, and via is formed in the upper layer of micro- via,
And then via is filled by using copper and via and micro- via are electrically connected to each other.
In order to improve the workmanship of IVH, has existed and ground for the various of deposit characteristics for improving plating copper filling-up method
Study carefully.
The relevant technologies of the present invention are disclosed in Korean Patent Publication No. 2008-0060902.
Invention content
The present invention provides a kind of methods of substrate and manufacture substrate, and the copper clad layers pressure of via can be formed with by undercutting
The conductive layer of plate and improve filling via deposit characteristics.
One aspect of the present invention provides a kind of substrate, which includes：Dielectric layer, including via；First conductive layer,
Lamination on the dielectric layer, wherein from the point of view of in vertical section figure when the first conductive layer, be adjacent to via downside vertex and
The edge being connect with downside vertex is formed as tilting and retreating along the direction far from via；And second conductive layer, this second
Conductive layer is filled in the vias and is laminated on the first conductive layer.
From the point of view of in vertical section figure when the first conductive layer, the first conductive layer may include an inclined-plane, and the inclined-plane is first
Being adjacent at the upper side end of via for conductive layer is retreated and is tilted along the direction far from via.
Substrate can further comprise arranging internal layer pad and supporting layer under a dielectric layer.
Internal layer pad can be made of the material of the material identical with the second conductive layer.
Dielectric layer and the first conductive layer are formed as copper clad laminate.
Another aspect provides a kind of method of manufacture substrate, this method includes：Including dielectric layer and
Via is formed in the copper clad laminate of one conductive layer；Undercut portions are formed by etching the first conductive layer；And it is filled by plating
Via.
When forming undercut portions, can the first conductive layer of wet etching the downside end for being adjacent to via, and when vertical
From the point of view of in sectional view when the first conductive layer, the edge for being adjacent to the downside vertex of via and being connect with downside vertex is formed as
It tilts and retreats along the direction far from via.
From the point of view of in vertical section figure when the first conductive layer, the first conductive layer may include an inclined-plane, and the inclined-plane is first
Being adjacent at the upper side end of via for conductive layer is retreated and is tilted along the direction far from via.
In the step of filling via, electroless copper and electricity copper facing can be used to fill via, and second can be led
Electric layer is laminated on the first conductive layer.
An additional aspect of the present invention provides a kind of substrate, which includes：Dielectric layer, including via；And first
Conductive layer is laminated on the dielectric layer, and first conductive layer has bottom in the end for being adjacent to via of the first conductive layer
Cut portion.
Substrate can further comprise the second conductive layer, which fills in the vias and be laminated to the first conduction
On layer.
Description of the drawings
Fig. 1 shows the structure of substrate according to the embodiment of the present invention.
Fig. 2 to Fig. 5 shows plating seam or gap are how to be generated in the vias according to the depth of via.
The method that Fig. 6 shows manufacture substrate according to the embodiment of the present invention.
Specific implementation mode
Because various modifications and the embodiment of the present invention may be present, it will be described with reference to the attached figures and describe specific
Embodiment.However, this limits the invention to specific embodiment by no means, and should be construed to include by this hair
All modifications, equivalent and the alternative that bright conception and scope is covered.Through description of the invention, when a certain skill of description
Art is confirmed as avoiding when putting of the present invention, it will omits relevant detailed description.
Such as term of " first " and " second " can be used for describing various elements, but said elements should not be limited by
State term.Above-mentioned term is only used for distinguishing an element and another element.
Term as used in this specification is only intended to describe specific embodiment, and will never limit the present invention.
Unless clearly additionally using, otherwise the expression way of singulative includes the meaning of plural form.In the present specification, all
As the expression way of " comprising " or "comprising" be intended to specified properties, quantity, step, operation, element, part or a combination thereof,
And be not construed as excluding other one or more characteristics, quantity, step, operation, element, part or a combination thereof it is any
There is a possibility that or.
Hereinafter, the particular implementation of the method for substrate and manufacture substrate will be described in detail with reference to the accompanying drawings.Joining
When examining attached drawing and describing only certain exemplary embodiments of this invention, it is identical with reference to mark that any identical or corresponding element will be assigned
Number, and the description to their redundancies will not be provided.
Fig. 1 shows the structure of substrate according to the embodiment of the present invention.
With reference to figure 1, substrate according to the embodiment of the present invention includes supporting layer 110, internal layer pad 120, dielectric layer
130, the first conductive layer 140 and the second conductive layer 160.
Supporting layer 110 supports internal layer pad 120.Here, supporting layer 110 can be made of dielectric material.
Internal layer pad 120 executes the function as the seed crystal (seed, crystal seed) for plating.Here, internal layer pad 120 can
It is made of the conductive material for plating.For example, internal layer pad 120 can be by the material substantially the same with the second conductive layer 160
It is made.
Dielectric layer 130 makes the first conductive layer 140 insulate.Here, dielectric layer 130 may include dielectric polymeric material.For example, being situated between
Electric layer 130 can be made of preimpregnation material (prepreg).
In addition, dielectric layer 130 may include the via 150 with predetermined diameter.Here, via 150 is formed as being used for base
The inside via (IVH) of the inner conductive of plate.In addition, via 150 can be filled for conductive conductive material.
First conductive layer 140 forms the circuit pattern for signal transfer.First conductive layer 140 can be on dielectric layer 130
It is made of an electrically conducting material.For example, the first conductive layer 140 can be made of copper.
First conductive layer 140 can be laminated on dielectric layer 130 and form copper clad laminate (CCL).Here, CCL is to use
It in the substrate plate for manufacturing printed circuit board and may be formed in such structure, the first conductive layer 140 is thin in this configuration
Ground is laminated on dielectric layer 130.For example, CCL may include the first conductive layer 140, it, should because wiring pattern becomes finer
First the conductive layer usually thickness with about 18um to 70um or the thickness with about 5um, 7um or 15um.
The shape of (under-cut) can be undercut and formed by being adjacent to the end of the first conductive layer 140 of via 150.Specifically
Ground from the point of view of in vertical section figure when the first conductive layer 140, is adjacent to the downside vertex of via 150 and connects with downside vertex
The edge connect is formed as tilting along the direction far from via 150 and retreats (recede) (tilting backwards).Here, first is conductive
Layer 140 may include inclined-plane 145, which becomes tilts on dielectric layer 130.It inclined-plane 145 can be by the first conductive layer 140
The upper end for being adjacent to via 150 far from via 150 retreat and form inclined-plane.
The undercut shape of first conductive layer 140 can reduce the actual grade being filled into for conductive material in via 150.Tool
Body, if the end for being adjacent to via 150 of the first conductive layer 140 is formed with vertical upright cross sectional shape, for waiting filling out
The depth of the conductive material filled by be dielectric layer 130 thickness and the first conductive layer 140 thickness summation.However, due to
The end for being adjacent to via 150 of one conductive layer 140 is formed with undercut shape, is accordingly used in the depth of conductive material to be filled
Can be the thickness of dielectric layer 130.For example, if the thickness of dielectric layer 130 is about 40um, and the thickness of the first conductive layer 140
Degree is about 9um, and if undercut shape is changed into the end of the first conductive layer 140 from vertical upright cross sectional shape, is used for
The depth of conductive material to be filled can change into about 40um from about 49um, which reduces about 20%.
Second conductive layer 160 is filled in via 150.Here, the second conductive layer 160 can be formed as being laminated to by plating
On first conductive layer 140 and it is filled in via 150.Here, the second conductive layer 160 can be by the material phase with internal layer pad 120
Same material is made.In addition, the second conductive layer 160 can be made of the material substantially the same with the material of the first conductive layer 140.
For example, in addition to the second conductive layer 160 be plated on the first conductive layer 140 and by the small interface by with the first conductive layer
140 the case where distinguishing, the second conductive layer 160 can be made of copper.
Therefore, because the undercut shape of the end for being adjacent to via of the first conductive layer, so implementation according to the present invention
The substrate of mode can prevent plating seam or gap.
Fig. 2 to Fig. 5 shows plating seam or gap are how to be generated in the vias according to the depth of via.
Fig. 2 to Fig. 5 shows via, each all has identical top width and bottom width but has different depth, and fills out
Filled with coating material.Each of via shown in Fig. 2 to Fig. 5 all has the bottom width of the top width and about 95um of about 100um.This
Outside, the via shown in Fig. 2 to Fig. 5 is respectively provided with the depth of about 50um, 65um, 80um and 95um.Fig. 2 to Fig. 5 is shown
When depth is smaller, then there is via lower appearance to stitch or the possibility in gap.
The method that Fig. 6 shows manufacture substrate according to the embodiment of the present invention.
With reference to figure 6, the method for manufacture substrate according to the embodiment of the present invention includes：It is led including dielectric layer and first
Via (S110) is formed in the copper clad laminate (CCL) of electric layer；Undercut portions (S120) are formed by etching the conductive layer of CCL；
And the via (S130) of CCL is filled by plating.
In step S110, the via with predetermined diameter is formed in CCL, in CCL, the first conductive layer is pressed in Jie
In electric layer.Here, via can be formed by laser technology or bore process.
In various embodiments, before via formation, CCL can be laminated on supporting layer or internal layer pad.Specifically
Internal layer pad is formed on supporting layer using conductive material, and dielectric layer and the first conductive layer (copper film) is laminated to by ground
On internal layer pad, to form the CCL being laminated on internal layer pad.
In step S120, can half-etching CCL the first conductive layer (copper film), to form the first conductive layer of undercut shape.
Here, half-etching can be executed by wet etching.For example, the etching solution between dielectric layer and the first conductive layer can be used
The lower end for being adjacent to via of the first conductive layer is etched to form undercut shape.Here, the from the point of view of in vertical section figure
When one conductive layer, the edge for being adjacent to the downside vertex of via and being connect with downside vertex is formed as inclining along the direction far from via
Tiltedly and retreat.
In step S130, via is filled to form the second conductive layer by plating.Here, electroless copper and electricity can be passed through
Copper facing and form the second conductive layer.Second conductive layer can be pressed on the first conductive layer.
After forming via, the method for manufacture substrate according to the embodiment of the present invention can be by using half-etching
The copper film of CCL generates undercut portions and prevents plating seam or gap.
Although it have been described that only certain exemplary embodiments of this invention, but for ordinary skill people of the art
For member it should be appreciated that without departing from the technical concept and range of the present invention, many changes of the present invention may be present
And modification, the scope of the present invention should be defined by the following claims.
It should also be understood that the right that many other embodiments in addition to the implementation described above are also included within the present invention is wanted
In asking.
Claims (9)
1. a kind of substrate, including：
Dielectric layer, including via；
First conductive layer, lamination on the dielectric layer, and are formed with the exposure via in first conductive layer
Hole；And
Second conductive layer, second conductive layer are filled in the via and the hole and are laminated to first conductive layer
On,
Wherein, the side surface in the hole of first conductive layer is inclined, and
Wherein, the hole of first conductive layer broadens from the topmost in the hole towards the via.
2. substrate according to claim 1, wherein the topmost in the hole of first conductive layer is than the mistake
The topmost in hole is wide.
3. substrate according to claim 1 further comprises internal layer pad and the support being arranged under the dielectric layer
Layer.
4. substrate according to claim 3, wherein the internal layer pad passes through the material identical with second conductive layer
Material be made.
5. substrate according to claim 1, wherein the dielectric layer and first conductive layer are formed as copper clad layers pressure
Plate.
6. a kind of method of manufacture substrate, including：
Include the copper clad laminate of dielectric layer and the first conductive layer by processing, forms via in the dielectric layer and in the first conduction
The hole of the exposure via is formed in layer；
Etch the downside end of the neighbouring via of first conductive layer so that the shape in the hole of first conductive layer changes
Become；
And the hole after the shape change of the via and first conductive layer is filled by plating,
Wherein, after etching the downside end of the neighbouring via of first conductive layer, first conductive layer
Hole become broadening towards the via from the topmost in the hole.
7. according to the method described in claim 6, wherein, the neighbouring via for etching first conductive layer it is described under
When side end, wet etching is used.
8. according to the method described in claim 6, wherein, the neighbouring via for etching first conductive layer it is described under
After side end, the topmost in the hole after the shape change of first conductive layer is wider than the topmost of the via.
9. according to the method described in claim 6, wherein, after the shape for filling the via and first conductive layer changes
Hole the step of in, filled using electroless copper and electricity copper facing the via and first conductive layer shape change after
Hole, and the second conductive layer is pressed on first conductive layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2014-0003536 | 2014-01-10 | ||
| KR1020140003536A KR102149797B1 (en) | 2014-01-10 | 2014-01-10 | Substrate and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104780705A CN104780705A (en) | 2015-07-15 |
| CN104780705B true CN104780705B (en) | 2018-08-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410213857.1A Active CN104780705B (en) | 2014-01-10 | 2014-05-20 | The method of substrate and manufacture substrate |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR102149797B1 (en) |
| CN (1) | CN104780705B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107072041B (en) * | 2017-04-25 | 2019-10-11 | 安徽宏鑫电子科技有限公司 | A kind of two-sided PCB |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2173945C1 (en) * | 2000-05-10 | 2001-09-20 | Сухолитко Валентин Афанасьевич | Volumetric printed circuit board |
| CN102404935A (en) * | 2010-09-13 | 2012-04-04 | 巨擘科技股份有限公司 | Multilayered through hole laminating structure |
| CN203181413U (en) * | 2013-01-28 | 2013-09-04 | 深圳华祥荣正电子有限公司 | Blind hole structure of printed circuit board, printed circuit board, and electronic product |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3198031B2 (en) * | 1995-05-16 | 2001-08-13 | シャープ株式会社 | Method for manufacturing build-up multilayer wiring board |
| US20020083586A1 (en) * | 1998-04-10 | 2002-07-04 | Takahiro Iijima | Process for producing multilayer circuit board |
| JP2000022337A (en) * | 1998-06-30 | 2000-01-21 | Matsushita Electric Works Ltd | Multilayer wiring board and its manufacture |
| KR20020066797A (en) * | 2001-02-13 | 2002-08-21 | 주식회사 심텍 | Blind via Hole on Build-up PCB |
| JP2003188533A (en) * | 2001-12-17 | 2003-07-04 | Fujikura Ltd | Circuit board, method of manufacturing the same and multilayer circuit board |
| KR100866688B1 (en) | 2006-12-27 | 2008-11-04 | 동부일렉트로닉스 주식회사 | Method for forming via hole of semiconductor device |
| JP6385635B2 (en) * | 2012-05-28 | 2018-09-05 | 新光電気工業株式会社 | Wiring board manufacturing method |
-
2014
- 2014-01-10 KR KR1020140003536A patent/KR102149797B1/en active IP Right Grant
- 2014-05-20 CN CN201410213857.1A patent/CN104780705B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2173945C1 (en) * | 2000-05-10 | 2001-09-20 | Сухолитко Валентин Афанасьевич | Volumetric printed circuit board |
| CN102404935A (en) * | 2010-09-13 | 2012-04-04 | 巨擘科技股份有限公司 | Multilayered through hole laminating structure |
| CN203181413U (en) * | 2013-01-28 | 2013-09-04 | 深圳华祥荣正电子有限公司 | Blind hole structure of printed circuit board, printed circuit board, and electronic product |
Also Published As
| Publication number | Publication date |
|---|---|
| KR102149797B1 (en) | 2020-08-31 |
| CN104780705A (en) | 2015-07-15 |
| KR20150083685A (en) | 2015-07-20 |
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