JP2018032881A - Wire bonding method, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wire bonding method and a semiconductor device capable of appropriately bonding wires.SOLUTION: A wire bonding method includes a wire bonding step of bonding a wire 8 to a portion located between a pair of press pieces 831 in a separation direction of the pair of press pieces 831, of an electrode 411, in a state in which the pair of press pieces 831 are pressed against two positions separated from each other, of a die pad part 11.SELECTED DRAWING: Figure 10

Description

  The present invention relates to a wire bonding method and a semiconductor device.

  Conventionally, as one of various semiconductor devices, there is a power supply control semiconductor device called IPM (Intelligent Power Module). Since such a semiconductor device often controls a large amount of electric power and easily generates heat, a plurality of semiconductor chips, a plurality of die pad portions, a metal layer serving as a heat sink, a bonding layer, and a sealing resin are provided. Prepare. The plurality of semiconductor chips are respectively disposed on the plurality of die pad portions. Each die pad portion is bonded to the metal layer via a bonding layer. The sealing resin covers the plurality of semiconductor chips, the plurality of die pad portions, the heat sink, and the bonding layer. A semiconductor device called IPM is described in Patent Document 1, for example.

  Such a semiconductor device is mounted on a substrate (circuit board). In a state where the semiconductor device is mounted on the substrate, the heat radiating plate is directly opposed to a relatively large heat radiating member outside the semiconductor device. If the bonding layer leaks to the outside of the sealing resin, a gap may be generated between the metal layer and the heat dissipation member. This hinders efficient transfer of heat from the semiconductor chip to the heat dissipation member.

  The heat dissipation layer and the sealing resin are different from each other. For this reason, there exists a possibility that the boundary of the outer edge of a thermal radiation layer and sealing resin may peel. If this peeling propagates to the inside of the sealing resin, there may be a problem that heat dissipation of the semiconductor chip is hindered or the semiconductor chip is corroded.

  When bonding a wire made of aluminum, pressure and vibration are applied to the wire. This pressure and vibration are also applied to the die pad part and the wire bonding part. If the die pad part or the wire bonding part is shaken or deformed, the wire cannot be properly bonded.

  Such a semiconductor device is mounted on a substrate (circuit board). In a state where the semiconductor device is mounted on the substrate, the heat radiating plate is directly opposed to a relatively large heat radiating member outside the semiconductor device. In addition, a plurality of semiconductor chips are mounted on the die pad portion via a solder paste, and each semiconductor chip and the lead are electrically connected using a thicker and harder wire such as aluminum so that a large current can flow. I have to.

  In the semiconductor device as described above, when a plurality of semiconductor chips are attached, solder paste between adjacent semiconductor chips may be connected. In addition, solder erosion may occur in which only part of the solder paste reaches the end of the die pad portion. Alternatively, the position of each semiconductor chip may shift from a desired position due to the surface tension of the solder paste or the like. If the mounting position of each semiconductor chip is shifted, bonding with a hard wire may be difficult. In addition, in order to avoid this problem, there is a problem that the outer shape of the semiconductor device is increased by increasing the distance between the semiconductor chips.

JP 2009-105389 A

  The present invention has been conceived under the circumstances described above, and the present invention has been conceived under the circumstances described above, and is capable of appropriately bonding wires. The main object is to provide a wire bonding method and a semiconductor device.

  The semiconductor device provided by the first aspect of the present invention includes a die pad portion having a main surface and a back surface facing in opposite directions, a semiconductor chip mounted on the main surface of the die pad portion, and the above-described die pad portion. A recess that exposes the back surface is formed, and includes a sealing resin portion that covers the die pad portion and the semiconductor chip, and a heat dissipation layer disposed in the recess. The groove has a portion located outside the die pad portion and located on the main surface side from the back surface, and the heat radiation layer is partially filled in the groove, and the die pad And a bonding layer in contact with the back surface of the portion.

  In a preferred embodiment of the present invention, the heat dissipation layer has a metal layer laminated on the opposite side of the die pad portion with respect to the bonding layer.

  In a preferred embodiment of the present invention, the metal layer is made of Cu.

  In a preferred embodiment of the present invention, the bonding layer is made of a resin.

  In a preferred embodiment of the present invention, a part of the metal layer protrudes from the recess in the thickness direction.

  In a preferred embodiment of the present invention, the groove is located outside the metal layer in the direction in which the back surface is widened.

  In a preferred embodiment of the present invention, the recess has a bottom surface having a portion located between the metal layer and the groove.

  In a preferred embodiment of the present invention, the groove is inclined so as to be positioned from the back surface side to the main surface side in the thickness direction of the die pad portion as the groove is separated from the die pad portion in the direction in which the back surface is expanded. doing.

  In a preferred embodiment of the present invention, the concave portion is located outside the die pad portion in the direction in which the back surface expands, and is connected to the first side surface connected to the bottom surface, the first side surface, and the back surface direction. And a second side surface located between the die pad portion and the first side surface in a direction in which the back surface expands, and the metal layer has the back surface widened. At least a part in the direction has an outer edge located between the first side surface and the second side surface, and overlaps the first side surface in the thickness direction of the die pad portion.

  In a preferred embodiment of the present invention, a part of the bonding layer is interposed between the support surface and the metal layer.

  A semiconductor device provided by the second aspect of the present invention includes a plurality of die pad portions having a main surface and a back surface facing in opposite directions, and a plurality of semiconductors mounted on the main surface of the plurality of die pad portions. A chip, a recess that exposes at least a part of each back surface of each die pad portion in common, and a sealing resin portion that covers each die pad portion and each semiconductor chip in common, and the recess A recess formed on the back surface side of the die pad portion and on the main surface side of the back surface. The heat dissipation layer has a bonding layer partially filled in the groove and in common contact with the back surface of each die pad portion.

  A semiconductor device provided by the third aspect of the present invention includes a die pad portion having a main surface and a back surface facing in opposite directions, a semiconductor chip mounted on the main surface of the die pad portion, and a recess from a resin bottom surface. And a recess that exposes the back surface of the die pad portion is formed, and includes a sealing resin portion that covers the die pad portion and the semiconductor chip, and a heat dissipation layer disposed in the recess. A first side surface that is located outside the die pad portion in a direction in which the back surface extends and is connected to the resin bottom surface, a support surface that is connected to the first side surface and that faces in a direction in which the back surface faces, and is connected to the support surface, and A second side surface located between the die pad portion and the first side surface in the direction in which the heat spreads, and the heat dissipation layer is in a direction in which the back surface is widened. At least a portion having an outer edge located between the first side surface and the second side surface, the heat dissipation layer overlapping the first side surface in the thickness direction of the die pad portion, and the heat dissipation layer and the die pad portion, And a bonding layer interposed therebetween.

  In a preferred embodiment of the present invention, the heat dissipation layer is made of metal.

  In a preferred embodiment of the present invention, the metal is Cu.

  In a preferred embodiment of the present invention, the bonding layer is made of a resin.

  In a preferred embodiment of the present invention, a part of the bonding layer is interposed between the support surface and the heat dissipation layer.

  In a preferred embodiment of the present invention, the recess has a groove that is located on the outer side of the die pad portion in the direction in which the back surface expands and that is located on the main surface side of the back surface. The bonding layer is partially filled in the groove.

  In a preferred embodiment of the present invention, a part of the heat dissipation layer protrudes from the recess in the thickness direction.

  In preferable embodiment of this invention, the said groove | channel is located outside with respect to the said heat radiating layer in the direction where the said back surface spreads.

  In preferable embodiment of this invention, the said recessed part has a recessed part bottom face which has a part located between the said thermal radiation layer and the said groove | channel.

  In a preferred embodiment of the present invention, the concave portion is inclined so as to be positioned from the back surface side to the main surface side in the thickness direction of the die pad portion as the back surface is separated from the die pad portion in a direction in which the back surface is widened. doing.

  A semiconductor device provided by a fourth aspect of the present invention includes a plurality of die pad portions having a main surface and a back surface facing in opposite directions, and a plurality of semiconductors mounted separately on the main surface of the plurality of die pad portions. A chip and a recess that is recessed from the resin bottom surface and that exposes at least a part of each back surface of the die pad portion in common, and covers the die pad portion and the semiconductor chip in common. A resin portion and a heat dissipation layer disposed in the recess, the recess being located outside the die pad portion on the back surface side, and connected to the resin bottom surface on the first side surface and the first side surface. A second side surface located between the die pad portion and the first side surface in the direction in which the back surface is connected and connected to the support surface and the back surface is widened; The heat dissipation layer has an outer edge located at least partially between the first side surface and the second side surface in the direction in which the back surface spreads, and the heat dissipation layer has the outer edge located in the thickness direction of the die pad portion. It has a heat dissipation layer that overlaps one side surface, and a bonding layer that is interposed between the heat dissipation layer and each of the die pad portions.

  The semiconductor device provided by the fifth aspect of the present invention has a die pad portion having a die pad main surface and a die pad back surface facing in opposite directions, a semiconductor chip mounted on the die pad main surface, and a recess recessed from the bottom surface. A recess that exposes the back surface of the die pad is formed, a sealing resin portion that covers the die pad portion and the semiconductor chip, a heat dissipation layer main surface that is disposed in the recess and faces the back surface of the die pad, and the heat dissipation layer main surface And a heat dissipation layer bonded to the die pad portion, the heat dissipation layer being located outside the die pad portion in the direction in which the die pad back surface expands. , A first side surface connected to the back surface of the heat dissipation layer, an intermediate surface connected to the first side surface and facing the direction in which the main surface of the heat dissipation layer faces, and the intermediate surface Rising, it is characterized by having a second side, which is located between the die pad portion and the first side in the direction in which the die pad rear surface spread.

  In a preferred embodiment of the present invention, the heat dissipation layer is made of ceramics.

  In a preferred embodiment of the present invention, the first side surface, the intermediate surface, and the second side surface are in contact with the sealing resin portion.

  In a preferred embodiment of the present invention, the back surface of the heat dissipation layer of the heat dissipation layer is flush with the bottom surface of the sealing resin portion.

  In a preferred embodiment of the present invention, the first side surface and the intermediate surface form a first corner.

  In a preferred embodiment of the present invention, the intermediate surface and the second side surface form a second corner.

  In a preferred embodiment of the present invention, at least one of the first corner and the second corner is a right angle.

  In a preferred embodiment of the present invention, the thickness direction dimension of the heat dissipation layer on the first side surface is larger than the thickness direction dimension of the heat dissipation layer on the second side surface.

  In a preferred embodiment of the present invention, the heat dissipation layer and the die pad portion are bonded via a bonding layer.

  In a preferred embodiment of the present invention, a plurality of grooves extending in a direction perpendicular to the thickness direction of the heat dissipation layer are formed in the heat dissipation layer main surface of the heat dissipation layer.

  In a preferred embodiment of the present invention, each of the grooves has a rectangular cross section.

  In a preferred embodiment of the present invention, any one of the plurality of grooves is in contact with the bonding layer.

  In a preferred embodiment of the present invention, any of the plurality of grooves is in contact with the sealing resin portion.

  A semiconductor device provided by a sixth aspect of the present invention includes a plurality of die pad portions having a die pad main surface and a die pad back surface facing in opposite directions, and a plurality of semiconductor chips mounted separately on the plurality of die pad main surfaces. And a recess that is recessed from the bottom and that exposes the back surface of each die pad in common, and is disposed in the recess, and a sealing resin portion that covers each die pad and each semiconductor chip in common, and A heat-dissipating layer main surface facing the back surface of the die pad and a heat-dissipating layer back surface opposite to the heat-dissipating layer main surface, and a heat-dissipating layer bonded in common to each of the die pad parts. Is located outside the respective die pad portions in the direction in which the back surface of the die pad spreads, and is connected to the first side surface connected to the back surface of the heat dissipation layer and the first side surface. An intermediate surface facing in the direction in which the main surface of the heat dissipation layer faces, a second side surface connected to the intermediate surface and positioned between the die pad portion and the first side surface in a direction in which the back surface of the die pad spreads. Yes.

  In the wire bonding method provided by the seventh aspect of the present invention, the pair of pressing pieces of the bonding target object is pressed in a state where the pair of pressing pieces are pressed at two spaced apart positions on the bonding target object. It has a wire bonding step of bonding a wire to a portion located between the pair of pressing pieces in the direction in which the pieces are separated.

  In a preferred embodiment of the present invention, in the wire bonding step, the wire is bonded to a portion of the bonding target that intersects a straight line connecting the pair of pressing pieces.

  In a preferred embodiment of the present invention, the bonding object includes a die pad portion made of a metal plate, and a semiconductor chip mounted on the die pad portion and having one or more electrodes. In the wire bonding step, Then, a wire is bonded to the electrode in a state where the pair of pressing pieces are pressed at a position sandwiching the semiconductor chip in the die pad portion.

  In a preferred embodiment of the present invention, the semiconductor chip has a plurality of electrodes, and in the wire bonding step, the pair of pressing pieces are pressed to a position sandwiching the plurality of electrodes. The wires are individually bonded to the plurality of electrodes.

  In a preferred embodiment of the present invention, the bonding object includes a wire bonding portion made of a metal plate, and in the wire bonding step, the pair of pressing pieces are pressed against the wire bonding portion. Then, a wire is bonded to the wire bonding portion.

  In a preferred embodiment of the present invention, the bonding object includes a die pad portion made of a metal plate, a semiconductor chip mounted on the die pad portion and having one or more electrodes, and a wire bonding portion separated from the die pad portion. In the wire bonding step, a wire is bonded to the electrode in a state where the pair of pressing pieces are pressed to a position where the semiconductor chip is sandwiched in the die pad portion, and the wire bonding step Thereafter, there is an additional wire bonding step of bonding a wire to the wire bonding portion in a state where an additional pair of pressing pieces are pressed against the wire bonding portion.

  In a preferred embodiment of the present invention, the semiconductor chip has a plurality of electrodes, and in the wire bonding step, the pair of pressing pieces are pressed to a position sandwiching the plurality of electrodes. The wires are individually bonded to the plurality of electrodes.

  In a preferred embodiment of the present invention, the wire is made of aluminum.

  In a preferred embodiment of the present invention, pressure and vibration are applied to the wire in the wire bonding step.

  A semiconductor device provided by an eighth aspect of the present invention includes a die pad portion having a main surface and a back surface facing in opposite directions, and a semiconductor mounted on the main surface of the die pad portion and having one or more electrodes. A chip, and a sealing resin portion that covers the die pad portion and the semiconductor chip, and the die pad portion is formed with a pair of pressing marks that are spaced apart from each other, and the pair of pressing members among the electrodes. One end of the wire is bonded to a portion located between the pair of pressing marks in the direction in which the marks are separated.

  In a preferred embodiment of the present invention, one end of the wire is bonded to a portion of the electrode that intersects a straight line that connects the pair of pressing marks.

  In a preferred embodiment of the present invention, it further comprises a wire bonding portion spaced from the die pad portion, and an additional pair of pressing marks spaced from each other is formed in the wire bonding portion, The other end of the wire is bonded to a portion located between the additional pair of pressing marks in the direction in which the additional pair of pressing marks is separated from the wire bonding portion.

  In a preferred embodiment of the present invention, the other end of the wire is bonded to a portion of the wire bonding portion that intersects a straight line connecting the additional pair of pressing marks.

  A semiconductor device provided by a ninth aspect of the present invention includes a die pad portion having a main surface and a back surface facing in opposite directions, and a semiconductor mounted on the main surface of the die pad portion and having one or more electrodes. A chip, a lead electrically connected to the semiconductor chip via a wire, and a sealing resin portion covering the die pad part, the semiconductor chip and a part of the lead, and the wire of the lead A pair of pressing marks that are spaced apart from each other are formed on the surface of the lead that sandwiches the connection part to which one end is bonded.

  In a preferred embodiment of the present invention, the lead having the pressing mark has a wider portion than the lead having no pressing mark.

  In a preferred embodiment of the present invention, the wires have different types of thickness, and the pressing marks are formed only near the connecting portion of the wire having a large thickness.

  In a preferred embodiment of the present invention, there are a plurality of the semiconductor chips, and the thick wires electrically connect only some of the semiconductor chips and the leads.

  In a preferred embodiment of the present invention, a pair of pressing marks that are spaced apart from each other with the semiconductor chip interposed therebetween are formed on the surface of the die pad that sandwiches the semiconductor chip.

  In a preferred embodiment of the present invention, the semiconductor chip includes a plurality of semiconductor chips and includes an output transistor and a semiconductor chip for controlling the output transistor. The lead pressing mark is formed on the lead connected to the output transistor. They are formed so as to be separated from each other with the connecting portion interposed therebetween.

  According to a tenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: an application step of applying a conductive bonding paste to a main surface of a die pad portion; The back surface of the semiconductor chip, which is larger than the region where the bonding paste is applied, is in contact with the conductive bonding paste so as to include the region where the conductive bonding paste is applied inward as viewed in the direction in which the main surface faces. And a bonding step of forming a conductive bonding material by softening and hardening the conductive bonding paste.

  In a preferred embodiment of the present invention, the conductive bonding paste is a solder paste.

  In a preferred embodiment of the present invention, in the coating step, after covering the main surface with a mask having an opening, the conductive bonding paste is filled in the opening.

  In a preferred embodiment of the present invention, the back surface of the semiconductor chip has higher wettability with respect to the conductive bonding paste than the main surface of the die pad portion.

  In a preferred embodiment of the present invention, the back surface of the semiconductor chip is made of Ag, Au, Ni or an alloy containing these metals, and the main surface of the die pad portion is any one of Cu, FeNi alloy, and Fe. It consists of

  A semiconductor device provided by an eleventh aspect of the present invention is interposed between a die pad portion having a main surface, a semiconductor chip having a back surface, the main surface of the die pad portion and the back surface of the semiconductor chip, A conductive bonding material for bonding the die pad portion and the semiconductor chip, and a bonding area between the back surface of the semiconductor chip and the conductive bonding material is determined by the main surface of the die pad portion and the conductive material. It is characterized by being larger than the bonding area with the adhesive bonding material.

  In a preferred embodiment of the present invention, the conductive bonding material is solder.

  In a preferred embodiment of the present invention, the back surface of the semiconductor chip has higher wettability with respect to the conductive bonding paste than the main surface of the die pad portion.

  In a preferred embodiment of the present invention, the back surface of the semiconductor chip is made of Ag, Au, Ni or an alloy containing these metals, and the main surface of the die pad portion is any one of Cu, FeNi alloy, and Fe. It consists of

  A semiconductor device provided by a twelfth aspect of the present invention includes a die pad portion having a main surface and a back surface facing in opposite directions, a plurality of semiconductor chips mounted on the main surface of the die pad portion, and the die pad portion. A conductive bonding material that is interposed between the main surface of the semiconductor chip and the back surfaces of the plurality of semiconductor chips, and bonds the die pad portion and the plurality of semiconductor chips. The bonding area between each back surface and the conductive bonding material is larger than the bonding area between the conductive bonding material formed on the main surface of the die pad portion corresponding to the semiconductor chip. It is said.

  In a preferred embodiment of the present invention, the semiconductor chip has a plurality of output transistors and a semiconductor chip for controlling the output transistors, and the plurality of output transistors have the relationship of the junction area.

  In a preferred embodiment of the present invention, the apparatus further includes a plurality of leads for taking out outputs of the plurality of output transistors to the outside, and a plurality of wires for connecting the output transistors and the leads, respectively. Is aluminum.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is sectional drawing which shows the mounting structure of the semiconductor device based on 1A embodiment of this invention. It is a top view (a part of composition is omitted) before bending a lead of a semiconductor device based on a 1A embodiment of the present invention. It is a bottom view before bending the lead | read | reed of the semiconductor device based on 1A embodiment of this invention. It is sectional drawing which follows the IV-IV line of FIG. It is a principal part expanded sectional view of FIG. It is a top view which shows 1 process of the manufacturing method of the semiconductor device based on 1A embodiment of this invention. FIG. 7 is a cross-sectional view showing a step subsequent to FIG. 6. FIG. 8 is a cross-sectional view showing a step subsequent to FIG. 7. FIG. 9 is a cross-sectional view showing a step subsequent to FIG. 8. It is a bottom view before bending the lead | read | reed of the semiconductor device based on 2A embodiment of this invention. It is a principal part expanded sectional view which follows the XI-XI line of FIG. It is sectional drawing which shows the mounting structure of the semiconductor device based on 1B Embodiment of this invention. It is a top view before bending the lead | read | reed of the semiconductor device based on 1B Embodiment of this invention (one part structure abbreviation). It is a bottom view before bending the lead | read | reed of the semiconductor device based on 1B Embodiment of this invention. It is sectional drawing which follows the XV-XV line | wire of FIG. It is a principal part expanded sectional view of FIG. It is a top view which shows 1 process of the manufacturing method of the semiconductor device based on 1B Embodiment of this invention. FIG. 18 is a cross-sectional view showing a step subsequent to FIG. 17. FIG. 19 is a cross-sectional view showing a step subsequent to FIG. 18. FIG. 20 is a cross-sectional view showing a step subsequent to FIG. 19. It is a bottom view before bending the lead | read | reed of the semiconductor device based on 2B Embodiment of this invention. It is a principal part expanded sectional view which follows the XXII-XXII line | wire of FIG. It is sectional drawing which shows the mounting structure of the semiconductor device based on 1C Embodiment of this invention. It is a top view (a part of composition omitted) before bending a lead of a semiconductor device based on 1C embodiment of the present invention. It is a bottom view before bending the lead | read | reed of the semiconductor device based on 1C Embodiment of this invention. It is sectional drawing which follows the XXVI-XXVI line of FIG. It is a principal part expanded sectional view of FIG. It is a top view which shows 1 process of the manufacturing method of the semiconductor device based on 1C Embodiment of this invention. FIG. 29 is a cross-sectional view showing a step subsequent to FIG. 28. It is sectional drawing which shows the semiconductor device based on 2C Embodiment of this invention. FIG. 31 is a plan view showing a heat dissipation layer of the semiconductor device shown in FIG. 30. It is sectional drawing which shows the mounting structure of the semiconductor device based on 1D Embodiment of this invention. FIG. 10 is a plan view (partially omitted) of a lead before bending a lead of a semiconductor device according to the first embodiment of the present invention; It is a principal part top view of the semiconductor device based on 1D Embodiment of this invention. It is a bottom view before bending the lead | read | reed of the semiconductor device based on 1D Embodiment of this invention. It is sectional drawing which follows the XXXVI-XXXVI line of FIG. It is a top view which shows 1 process of the manufacturing method of the semiconductor device based on 1D Embodiment of this invention. It is a side view which shows an example of the bonding apparatus used for the wire bonding method which concerns on this invention. It is a principal part perspective view which shows 1 process of the manufacturing method of the semiconductor device based on 1D Embodiment of this invention. It is a principal part perspective view which shows 1 process following FIG. It is a principal part perspective view which shows one process following FIG. It is a principal part perspective view which shows one process following FIG. FIG. 43 is a perspective view of relevant parts showing one process subsequent to FIG. 42. FIG. 43 is a plan view of relevant parts showing one process following FIG. 42. FIG. 43 is a plan view showing a process following FIG. 42. FIG. 46 is a cross-sectional view showing a process following FIG. 45. FIG. 47 is a cross-sectional view showing a process following FIG. 46. FIG. 48 is a cross-sectional view showing a process following FIG. 47. It is sectional drawing which shows the mounting structure of the semiconductor device based on 1E Embodiment of this invention. It is a top view (a part of composition omitted) before bending a lead of a semiconductor device based on a 1E embodiment of the present invention. It is a bottom view before bending the lead | read | reed of the semiconductor device based on 1E Embodiment of this invention. It is sectional drawing which follows the LII-LII line | wire of FIG. It is a principal part expanded sectional view of FIG. It is a top view which shows 1 process of the manufacturing method of the semiconductor device based on 1E Embodiment of this invention. FIG. 55 is an essential part enlarged cross-sectional view showing a process following FIG. 54. FIG. 56 is an essential part enlarged cross-sectional view showing a process following FIG. 55. FIG. 57 is an essential part enlarged cross-sectional view showing a process following FIG. 56; FIG. 58 is an essential part enlarged cross-sectional view showing a process following FIG. 57. FIG. 59 is an essential part enlarged cross-sectional view showing a process following FIG. 58. FIG. 60 is a plan view showing a process following FIG. 59. FIG. 61 is a plan view showing a process following FIG. 60. FIG. 62 is a cross-sectional view showing a process following FIG. 61. FIG. 63 is a cross-sectional view showing a process following FIG. 62. FIG. 64 is a cross-sectional view showing a process following FIG. 63.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a mounting structure in which a semiconductor device according to the first embodiment of the present invention is used.

  A semiconductor device mounting structure 801 illustrated in FIG. 1 includes a semiconductor device 101A, a substrate 807, and a heat dissipation member 808.

  The substrate 807 has a plurality of electronic components mounted thereon. The substrate 807 is made of an insulating material. A wiring pattern (not shown) is formed on the substrate 807. A plurality of holes 809 are formed in the substrate 807. The heat radiating member 808 is made of a material having a relatively large thermal conductivity, for example, a metal such as aluminum. The heat dissipation member 808 is fixed to the substrate 807 by a support member (not shown). The semiconductor device 101A is mounted on the substrate 807. In the present embodiment, the semiconductor device 101A is a product called IPM (Intelligent Power Module). The semiconductor device 101A is used for applications such as power control for air conditioners and motor control devices, for example.

  FIG. 2 is a plan view (partially omitted) of the lead before bending the lead of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a bottom view of the semiconductor device according to the first embodiment of the present invention before bending the leads. 4 is a cross-sectional view taken along line IV-IV in FIG. FIG. 5 is an enlarged cross-sectional view of a main part of FIG. 1 corresponds to a cross section taken along the line II in FIG. In FIG. 4, for convenience of understanding, each configuration is schematically shown.

  The semiconductor device 101A shown in these drawings includes a plurality of first electrode portions 1, a second electrode portion 2, a third electrode portion 3, a plurality of semiconductor chips 41 and 42, a passive component chip 43, and a heat dissipation layer. 6, a sealing resin portion 7, and a wire 8. In FIG. 2, the heat dissipation layer 6 is indicated by a dotted line, and the sealing resin portion 7 is indicated by a virtual line.

  The sealing resin part 7 covers the first electrode part 1, the second electrode part 2, the third electrode part 3, the semiconductor chips 41 and 42, and the passive component chip 43. The sealing resin portion 7 is made of, for example, a black epoxy resin. As shown in FIGS. 3 and 4, the sealing resin portion 7 has a resin main surface 71, a resin bottom surface 72, and a resin side surface 73.

  The resin main surface 71 is a flat surface that faces the direction z1 and extends along the xy plane. The resin bottom surface 72 is a flat surface that faces the direction z2 opposite to the direction z1 and extends along the xy plane. The resin side surface 73 has a shape surrounding the semiconductor chips 41 and 42 and the passive component chip 43 in the xy plan view. The resin side surface 73 is connected to the resin main surface 71 and the resin bottom surface 72.

  As clearly shown in FIG. 4, a recess 75 is formed in the sealing resin portion 7. The recess 75 is recessed from the resin bottom surface 72. The recess 75 has a recess bottom surface 751, a recess side surface 752, and a recess groove 753. The recess bottom surface 751 has a shape along the xy plane. The concave side surface 752 is connected to the resin bottom surface 72. The concave side surface 752 is generally along the direction z.

  The recess groove 753 is located between the recess bottom surface 751 and the recess side surface 752, and is arranged in a rectangular ring shape along the outer edge of the recess 75 as viewed in the z direction in this embodiment. As shown in FIG. 5, the recessed groove 753 is recessed from the recessed bottom surface 751 in the z1 direction. In the present embodiment, the recessed groove 753 is disposed outside the metal layer 65 when viewed in the z direction. Further, the concave groove 753 is inclined so as to be positioned in the z1 direction as it is separated from the concave bottom surface 751 in the x direction. The depth of the deepest portion of the recessed groove 753 is, for example, about 50 μm.

  As shown in FIG. 2, the semiconductor chips 41 and 42 and the passive component chip 43 have a rectangular shape in plan view. The semiconductor chip 41 is a power chip such as an IGBT, a MOS, or a diode, for example. The semiconductor chip 42 is an LSI chip such as a control IC. The passive component chip 43 is a passive component such as a resistor or a capacitor, for example.

  The first electrode part 1, the second electrode part 2, and the third electrode part 3 shown in FIGS. 2 to 4 are all made of a conductive material. An example of such a conductive material is copper. 2 is connected to the ground.

  A plurality (four in the present embodiment) of first electrode parts 1 are respectively a die pad part 11 (see FIGS. 1, 2, and 4), a connection part 12 (see FIGS. 1 and 2), and a wire bonding part. 13 (see FIGS. 1 and 2) and a lead 14 (see FIGS. 1 to 3). The plurality of first electrode portions 1 are separated from each other in the direction x.

  Each die pad portion 11 has a plate shape along the xy plane. A semiconductor chip 41 is disposed on the die pad portion 11. As shown in FIG. 4, a bonding layer 991 is interposed between the die pad portion 11 and the semiconductor chip 41. The bonding layer 991 is made of a conductive material. Such a conductive material is, for example, solder or silver paste. Solder has a relatively high thermal conductivity. When solder is used as the bonding layer 991, heat can be efficiently transferred from the semiconductor chip 41 to the die pad portion 11. All of the plurality of die pad portions 11 are exposed from the recess bottom surface 751.

  Each die pad portion 11 has a die pad main surface 111 and a die pad back surface 112. The die pad main surface 111 faces the direction z1, and the die pad back surface 112 faces the direction z2. That is, the die pad main surface 111 and the die pad back surface 112 face opposite to each other. A semiconductor chip 41 is arranged on the die pad main surface 111. A bonding layer 991 is interposed between the die pad main surface 111 and the semiconductor chip 41. The die pad back surface 112 is located at the same position in the thickness direction (direction z) of the die pad portion 11 with respect to the recess bottom surface 751. The die pad back surface 112 may be located closer to the direction in which the recess 75 opens than the recess bottom surface 751.

  As shown in FIG. 2, each connection portion 12 is located between the die pad portion 11 and the wire bonding portion 13 and is connected to the die pad portion 11 and the wire bonding portion 13. As shown in FIG. 1, the connection part 12 is a shape which follows the surface which inclines to xy plane. The connection portion 12 is inclined with respect to the xy plane so as to be directed in the direction z1 as it is separated from the die pad portion 11.

  Each wire bonding portion 13 shown in FIGS. 1 and 2 has a shape along the xy plane. Each wire bonding part 13 is located in the direction z1 side with respect to the die pad part 11 in the direction z. A wire 8 is bonded to one wire bonding portion 13 and one semiconductor chip 41. Thereby, one wire bonding part 13 and one semiconductor chip 41 are electrically connected. The lead 14 is connected to the wire bonding part 13. Each lead 14 extends along direction y. The lead 14 has a portion protruding from the resin side surface 73 of the sealing resin portion 7. In this embodiment, the lead 14 is for insertion mounting. As shown in FIG. 1, the lead 14 is bent and inserted into the hole 809 when the semiconductor device 101 </ b> A is mounted on the substrate 807. In order to fix the lead 14 to the substrate 807, the hole 809 is filled with a solder layer 810.

As shown in FIG. 2, the plurality (three in this embodiment) of second electrode portions 2 each include a wire bonding portion 23 and leads 24. The plurality of second electrode portions 2 are separated from each other in the direction x.

Each wire bonding portion 23 has a shape along the xy plane. Each wire bonding part 23 is located in the direction z1 side rather than the die pad part 11 in the direction z. A wire 8 is bonded to one wire bonding portion 23 and one semiconductor chip 41. Thereby, one wire bonding part 23 and one semiconductor chip 41 are electrically connected. The lead 24 is connected to the wire bonding part 23. Each lead 24 extends along direction y. The lead 24 has a portion protruding from the resin side surface 73 of the sealing resin portion 7. In this embodiment, the lead 24 is for insertion mounting. Although not shown, like the lead 14, the lead 24 is inserted into the hole 809 when the semiconductor device 101 </ b> A is mounted on the substrate 807.

  The third electrode portion 3 shown in FIGS. 1 and 2 includes a plurality of control die pad portions 31 and a plurality of leads 32. Both the control die pad portion 31 and the lead 32 are arranged at the same position in the direction z. In each control die pad portion 31, a semiconductor chip 42 or a passive component chip 43 is arranged. A bonding layer (not shown) is interposed between the control die pad portion 31 and the semiconductor chip 42 and between the control die pad portion 31 and the passive component chip 43. The back surface of the control die pad portion 31 may not face the heat dissipation layer 6 or may not be exposed.

  Each lead 32 has a portion protruding from the resin side surface 73 of the sealing resin portion 7. In this embodiment, the lead 32 is for insertion mounting. As shown in FIG. 1, the lead 32 is inserted into the hole 809 when the semiconductor device 101 </ b> A is mounted on the substrate 807. As described with respect to the lead 14, the hole 809 is filled with a solder layer 810 to secure the lead 32 to the substrate 807. A wire 8 is bonded to one lead 32 and one semiconductor chip 42. Thereby, one lead 32 and one semiconductor chip 42 are electrically connected. The wire 8 is also bonded to one semiconductor chip 42 and one passive component chip 43.

  As shown in FIG. 4, the heat dissipation layer 6 is disposed in the recess 75 in the sealing resin portion 7. The heat dissipation layer 6 is surrounded by the concave side surface 752. In the present embodiment, the heat dissipation layer 6 has a plate shape along the xy plane. In the present embodiment, the heat dissipation layer 6 includes a metal layer 65 and a bonding layer 66. The metal layer 65 is on the z2 direction side and is made of, for example, Cu, aluminum, or ceramics having a thickness of about 105 μm. The bonding layer 66 is on the z1 direction side with respect to the metal layer 65 and functions to bond the metal layer 65 to the die pad back surfaces 112 of the plurality of die pad portions 11. The bonding layer 66 is made of, for example, an insulating resin and has a thickness of about 250 μm, for example. This resin is a material that softens when pressure and vibration are applied in the manufacturing process of the semiconductor device 101A. The bonding layer 66 is in direct contact with any of the plurality of die pad portions 11 on which the semiconductor chip 41 is mounted. The metal layer 65 may have a portion that slightly protrudes from the resin bottom surface 72. As shown in FIG. 5, a part of the bonding layer 66 fills the concave groove 753. Further, the bonding layer 66 is in contact with the concave side surface 752.

  The heat dissipation layer 6 is provided to quickly release the heat generated in the semiconductor chip 41 to the outside of the semiconductor device 101A. In order to quickly release the heat generated in the semiconductor chip 41 to the outside of the semiconductor device 101A, the higher the thermal conductivity of the material constituting the heat dissipation layer 6, the better, but the sealing resin portion 7 and the thermal expansion coefficient If they are greatly different, there is a risk that the metal layer 65 may be easily peeled off. Preferably, the heat radiation layer 6 is made of a material having a thermal conductivity larger than that of the material constituting the sealing resin portion 7 and a thermal expansion coefficient close to that of the sealing resin portion 7. The heat dissipation layer 6 faces all of the plurality of die pad portions 11. As shown in FIG. 3, the heat dissipation layer 6 overlaps the entirety of each die pad portion 11 in the xy plan view (view in the thickness direction of the heat dissipation layer 6).

  As shown in FIGS. 3 and 4, the heat dissipation layer 6 has a heat dissipation layer main surface 61 and a heat dissipation layer back surface 62. The heat radiation layer main surface 61 faces the direction z1. The heat radiation layer main surface 61 overlaps the die pad back surface 112 of each die pad portion 11 and the recess bottom surface 751 in the xy plan view. The heat radiation layer main surface 61 is in direct contact with the die pad back surface 112 and the recess bottom surface 751. The heat radiation layer back surface 62 faces in the direction z <b> 2, which is the opposite direction to the direction in which the heat radiation layer main surface 61 faces. The heat radiation layer back surface 62 is not covered with the sealing resin portion 7 and is exposed from the sealing resin portion 7.

  Next, a method for manufacturing the semiconductor device 101A will be described. In the drawings used in the description of the manufacturing method, the same components as those described above are denoted by the same reference numerals.

  First, as shown in FIG. 6, a lead frame 300 including a plurality of die pad portions 11 and 31, a plurality of semiconductor chips 41 and 42, and a passive component chip 43 are prepared. Next, as shown in the figure, each semiconductor chip 41 is arranged on any one of the plurality of die pad portions 11 via a bonding layer (not shown). Similarly, each semiconductor chip 42 and the passive component chip 43 are arranged on any one of the plurality of control die pad portions 31 via a bonding layer (not shown). Next, as shown in the figure, the wire 8 is bonded to each of the semiconductor chips 41, 42 and the like.

  Next, as shown in FIGS. 7 and 8, a sealing resin portion 7 is formed. As shown in FIG. 7, the sealing resin portion 7 is formed by molding using a mold 881. As shown in the figure, a plurality of die pad portions 11 and the like are pressed with a mold 881. Next, a resin material is injected into the mold 881 to cure the resin material. When the resin material is cured, the mold 881 is removed from the plurality of die pad portions 11 and the like as shown in FIG. Thereby, the sealing resin part 7 can be formed. In the step of forming the sealing resin portion 7, the concave portions 75 that expose the plurality of die pad portions 11 are formed in the sealing resin portion 7.

  Next, as shown in FIG. 9, the heat dissipation layer 6 is fitted into the recess 75 of the sealing resin portion 7. Then, pressure and vibration are applied to the heat dissipation layer 6. Further, the heat dissipation layer 6 may be heated. By the pressurization, vibration, and heating, the bonding layer 66 of the heat dissipation layer 6 is softened. The softened bonding layer 66 moves in the recess 75, and a part thereof is filled in the recess groove 753. Further, the bonding layer 66 is in contact with the concave side surface 752.

  Next, the lead frame 300 shown in FIG. 6 is appropriately cut to manufacture the semiconductor device 101A shown in FIG.

  Next, the effect of this embodiment is demonstrated.

  In the semiconductor device 101 </ b> A, a part of the bonding layer 66 fills the concave groove 753. In the manufacturing process of the semiconductor device 101A, the bonding layer 66 can be prevented from overflowing from the recess 75 by the amount of filling. Therefore, it is possible to prevent the gap between the heat dissipation layer 6 and the heat dissipation member 808 due to the bonding layer 66 overflowing outside the metal layer 65, and efficiently dissipate heat from the semiconductor chips 41 and 42. can do.

  By disposing the recessed groove 753 outside the metal layer 65, it is possible to prevent an unintended gap from being generated between the metal layer 65 and the recessed groove 753. Excluding the air gap is suitable for further increasing heat dissipation and making it difficult for the metal layer 65 to peel off.

  By forming the concave groove 753 into a tapered shape, even if the position of the metal layer 65 in the x direction or the y direction is shifted, the volume of the concave groove 753 overlapping the metal layer 65 in the z direction can be reduced. This is preferable for eliminating the above-mentioned voids.

  10 and 11 show a semiconductor device according to the second embodiment of the present invention. In these drawings, the same or similar elements as those in the above embodiment are denoted by the same reference numerals as those in the above embodiment. In the semiconductor device 102A of the present embodiment, the configuration of the recess 75 is different from that of the semiconductor device 101A described above.

  In the present embodiment, the recess 75 includes a plurality of recess grooves 753, and further includes a plurality of recess first side surfaces 754, a recess second side surface 755, and a recess support surface 756. As shown in FIG. 10, a plurality of recess grooves 753 and a plurality of recess first side surfaces 754, recess second side surfaces 755, and recess support surfaces 756 are alternately arranged along the outer edge of the recess 75. In a portion corresponding to the four corners of the recess 75, a recess first side surface 754, a recess second side surface 755, and a recess support surface 756 are disposed.

  As shown in FIG. 11, the concave first side surface 754 is connected to the resin bottom surface 72 and is generally along the z direction. The concave first side surface 754 is located outside the die pad portion 11 when viewed in the z direction. The concave second side surface 755 is connected to the concave bottom surface 751 and is generally along the z direction. The concave second side surface 755 is located between the die pad portion 11 and the concave first side surface 754 when viewed in the z direction. The recessed portion support surface 756 connects the recessed portion first side surface 754 and the recessed portion second side surface 755 and generally faces the z2 direction.

  In the present embodiment, the region surrounded by the concave second side surface 755 is filled with the bonding layer 66. In addition, a part of the bonding layer 66 is interposed between the metal layer 65 and the concave support surface 756.

  In the semiconductor device 102A, in addition to the effect exhibited by the semiconductor device 101A, the metal layer 65 is at least indirectly supported by the concave support surface 756. For this reason, it is possible to prevent the metal layer 65 from being unduly inclined or recessed with respect to the resin bottom surface 72. Therefore, it is possible to suppress a gap from being formed between the heat dissipation member 808 attached so as to be in close contact with the metal layer 65, and heat dissipation from the semiconductor chips 41 and 42 can be enhanced.

  By interposing the bonding layer 66 between the metal layer 65 and the concave support surface 756, the metal layer 65 can be reliably fixed to the sealing resin portion 7. If the bonding layer 66 does not reach the end of the metal layer 65, the peeling of the metal layer 65 may propagate from that portion. In this embodiment, there is little such a possibility.

  The present invention is not limited to the embodiment described above. The specific configuration of each part of the present invention can be changed in various ways. For example, if it is a semiconductor device in which the metal layer is exposed from the back surface of the sealing resin, it can be similarly used in the case of a terminal for surface mounting instead of insertion mounting. In addition to the above-described IPM device, the present invention can also be applied to a semiconductor device that seals a drive element that has only one semiconductor chip and one island and the metal layer is exposed from the back surface of the sealing resin.

  FIG. 12 is a cross-sectional view showing a mounting structure in which the semiconductor device according to the first embodiment of the present invention is used.

  A semiconductor device mounting structure 801 illustrated in FIG. 12 includes a semiconductor device 101B, a substrate 807, and a heat dissipation member 808.

  The substrate 807 has a plurality of electronic components mounted thereon. The substrate 807 is made of an insulating material. A wiring pattern (not shown) is formed on the substrate 807. A plurality of holes 809 are formed in the substrate 807. The heat radiating member 808 is made of a material having a relatively large thermal conductivity, for example, a metal such as aluminum. The heat dissipation member 808 is fixed to the substrate 807 by a support member (not shown). The semiconductor device 101B is mounted on the substrate 807. In the present embodiment, the semiconductor device 101B is a product called IPM (Intelligent Power Module). The semiconductor device 101B is used for applications such as power control for air conditioners and motor control devices, for example.

  FIG. 13 is a plan view (partially omitted) of a lead before bending a lead of the semiconductor device according to the first embodiment of the present invention. FIG. 14 is a bottom view of the semiconductor device according to the first embodiment of the present invention before bending the leads. 15 is a cross-sectional view taken along line XV-XV in FIG. 16 is an enlarged cross-sectional view of a main part of FIG. 12 corresponds to a cross section taken along line XII-XII in FIG. In FIG. 15, for convenience of understanding, each configuration is schematically shown.

  The semiconductor device 101B shown in these drawings includes a plurality of first electrode portions 1, a second electrode portion 2, a third electrode portion 3, a plurality of semiconductor chips 41 and 42, a passive component chip 43, and a heat dissipation layer. 6, a sealing resin portion 7, and a wire 8. In FIG. 13, the heat radiation layer 6 is indicated by a dotted line, and the sealing resin portion 7 is indicated by a virtual line.

  The sealing resin part 7 covers the first electrode part 1, the second electrode part 2, the third electrode part 3, the semiconductor chips 41 and 42, and the passive component chip 43. The sealing resin portion 7 is made of, for example, a black epoxy resin. As shown in FIGS. 14 and 15, the sealing resin portion 7 has a resin main surface 71, a resin bottom surface 72, and a resin side surface 73.

  The resin main surface 71 is a flat surface that faces the direction z1 and extends along the xy plane. The resin bottom surface 72 is a flat surface that faces the direction z2 opposite to the direction z1 and extends along the xy plane. The resin side surface 73 has a shape surrounding the semiconductor chips 41 and 42 and the passive component chip 43 in the xy plan view. The resin side surface 73 is connected to the resin main surface 71 and the resin bottom surface 72.

  As clearly shown in FIG. 15, a recess 75 is formed in the sealing resin portion 7. The recess 75 is recessed from the resin bottom surface 72. The recess 75 has a recess bottom surface 751, a recess first side surface 754, a recess second side surface 755, and a recess support surface 756. The recess bottom surface 751 has a shape along the xy plane. The concave side surface 752 is connected to the resin bottom surface 72.

  As shown in FIG. 16, the concave first side surface 754 is connected to the resin bottom surface 72 and is generally along the z direction. The concave first side surface 754 is located outside the die pad portion 11 when viewed in the z direction. The concave second side surface 755 is connected to the concave bottom surface 751 and is generally along the z direction. The concave second side surface 755 is located between the die pad portion 11 and the concave first side surface 754 when viewed in the z direction. The recessed portion support surface 756 connects the recessed portion first side surface 754 and the recessed portion second side surface 755 and generally faces the z2 direction.

  As shown in FIG. 13, the semiconductor chips 41 and 42 and the passive component chip 43 have a rectangular shape in plan view. The semiconductor chip 41 is a power chip such as an IGBT, a MOS, or a diode, for example. The semiconductor chip 42 is an LSI chip such as a control IC. The passive component chip 43 is a passive component such as a resistor or a capacitor, for example.

  The first electrode part 1, the second electrode part 2, and the third electrode part 3 shown in FIGS. 13 to 4 are all made of a conductive material. An example of such a conductive material is copper. Note that the electrode portion shown in the lower right of FIG. 13 is grounded.

  The plurality of (four in this embodiment) first electrode portions 1 are respectively a die pad portion 11 (see FIGS. 12, 13, and 15), a connection portion 12 (see FIGS. 12 and 13), and a wire bonding portion. 13 (see FIGS. 12 and 13) and a lead 14 (see FIGS. 12 to 14). The plurality of first electrode portions 1 are separated from each other in the direction x.

  Each die pad portion 11 has a plate shape along the xy plane. A semiconductor chip 41 is disposed on the die pad portion 11. As shown in FIG. 15, a bonding layer 991 is interposed between the die pad portion 11 and the semiconductor chip 41. The bonding layer 991 is made of a conductive material. Such a conductive material is, for example, solder or silver paste. Solder has a relatively high thermal conductivity. When solder is used as the bonding layer 991, heat can be efficiently transferred from the semiconductor chip 41 to the die pad portion 11. All of the plurality of die pad portions 11 are exposed from the recess bottom surface 751.

  Each die pad portion 11 has a die pad main surface 111 and a die pad back surface 112. The die pad main surface 111 faces the direction z1, and the die pad back surface 112 faces the direction z2. That is, the die pad main surface 111 and the die pad back surface 112 face opposite to each other. A semiconductor chip 41 is arranged on the die pad main surface 111. A bonding layer 991 is interposed between the die pad main surface 111 and the semiconductor chip 41. The die pad back surface 112 is located at the same position in the thickness direction (direction z) of the die pad portion 11 with respect to the recess bottom surface 751. The die pad back surface 112 may be located closer to the direction in which the recess 75 opens than the recess bottom surface 751.

  As shown in FIG. 13, each connection portion 12 is located between the die pad portion 11 and the wire bonding portion 13 and is connected to the die pad portion 11 and the wire bonding portion 13. As shown in FIG. 12, the connection part 12 is a shape along the surface which inclines to xy plane. The connection portion 12 is inclined with respect to the xy plane so as to be directed in the direction z1 as it is separated from the die pad portion 11.

  Each wire bonding portion 13 shown in FIGS. 12 and 13 has a shape along the xy plane. Each wire bonding part 13 is located in the direction z1 side with respect to the die pad part 11 in the direction z. A wire 8 is bonded to one wire bonding portion 13 and one semiconductor chip 41. Thereby, one wire bonding part 13 and one semiconductor chip 41 are electrically connected. The lead 14 is connected to the wire bonding part 13. Each lead 14 extends along direction y. The lead 14 has a portion protruding from the resin side surface 73 of the sealing resin portion 7. In this embodiment, the lead 14 is for insertion mounting. As shown in FIG. 12, the lead 14 is bent and inserted into the hole 809 when the semiconductor device 101 </ b> B is mounted on the substrate 807. In order to fix the lead 14 to the substrate 807, the hole 809 is filled with a solder layer 810.

  As shown in FIG. 13, the plurality (three in this embodiment) of second electrode portions 2 each include a wire bonding portion 23 and leads 24. The plurality of second electrode portions 2 are separated from each other in the direction x.

  Each wire bonding portion 23 has a shape along the xy plane. Each wire bonding part 23 is located in the direction z1 side rather than the die pad part 11 in the direction z. A wire 8 is bonded to one wire bonding portion 23 and one semiconductor chip 41. Thereby, one wire bonding part 23 and one semiconductor chip 41 are electrically connected. The lead 24 is connected to the wire bonding part 23. Each lead 24 extends along direction y. The lead 24 has a portion protruding from the resin side surface 73 of the sealing resin portion 7. In this embodiment, the lead 24 is for insertion mounting. Although not shown, like the lead 14, the lead 24 is inserted into the hole 809 when the semiconductor device 101 </ b> B is mounted on the substrate 807.

  The third electrode unit 3 shown in FIGS. 12 and 13 includes a plurality of control die pad units 31 and a plurality of leads 32. Both the control die pad portion 31 and the lead 32 are arranged at the same position in the direction z. In each control die pad portion 31, a semiconductor chip 42 or a passive component chip 43 is arranged. A bonding layer (not shown) is interposed between the control die pad portion 31 and the semiconductor chip 42 and between the control die pad portion 31 and the passive component chip 43. The back surface of the control die pad portion 31 may not face the heat dissipation layer 6 or may not be exposed.

  Each lead 32 has a portion protruding from the resin side surface 73 of the sealing resin portion 7. In this embodiment, the lead 32 is for insertion mounting. As shown in FIG. 12, the lead 32 is inserted into the hole 809 when the semiconductor device 101 </ b> B is mounted on the substrate 807. As described with respect to the lead 14, the hole 809 is filled with a solder layer 810 to secure the lead 32 to the substrate 807. A wire 8 is bonded to one lead 32 and one semiconductor chip 42. Thereby, one lead 32 and one semiconductor chip 42 are electrically connected. The wire 8 is also bonded to one semiconductor chip 42 and one passive component chip 43.

  As shown in FIG. 15, the heat dissipation layer 6 is disposed in the recess 75 in the sealing resin portion 7. The heat dissipation layer 6 is surrounded by the concave first side surface 754 and the concave second side surface 755. In the present embodiment, the heat dissipation layer 6 has a plate shape along the xy plane. In the present embodiment, the heat dissipation layer 6 includes a metal layer 65 and a bonding layer 66. The metal layer 65 is on the z2 direction side and is made of, for example, Cu, aluminum, or ceramics having a thickness of about 105 μm. The metal layer 65 corresponds to an example of a heat dissipation sublayer in the present invention. The bonding layer 66 is on the z1 direction side with respect to the metal layer 65 and functions to bond the metal layer 65 to the die pad back surfaces 112 of the plurality of die pad portions 11. The bonding layer 66 is made of, for example, an insulating resin and has a thickness of about 250 μm, for example. This resin is a material that softens when pressure and vibration are applied in the manufacturing process of the semiconductor device 101B. The bonding layer 66 is in direct contact with any of the plurality of die pad portions 11 on which the semiconductor chip 41 is mounted. The metal layer 65 may have a portion that slightly protrudes from the resin bottom surface 72. As shown in FIG. 16, a part of the bonding layer 66 fills a region surrounded by the concave second side surface 755. In the present embodiment, a part of the bonding layer 66 is interposed between the concave support surface 756 and the metal layer 65.

  The heat dissipation layer 6 is provided in order to quickly release the heat generated in the semiconductor chip 41 to the outside of the semiconductor device 101B. In order to quickly release the heat generated in the semiconductor chip 41 to the outside of the semiconductor device 101B, the higher the thermal conductivity of the material constituting the heat dissipation layer 6, the better, but the sealing resin portion 7 and the thermal expansion coefficient If they are greatly different, there is a risk that the metal layer 65 may be easily peeled off. Preferably, the heat radiation layer 6 is made of a material having a thermal conductivity larger than that of the material constituting the sealing resin portion 7 and a thermal expansion coefficient close to that of the sealing resin portion 7. The heat dissipation layer 6 faces all of the plurality of die pad portions 11. As shown in FIG. 14, the heat radiation layer 6 overlaps the entirety of each die pad portion 11 in the xy plan view (view in the thickness direction of the heat radiation layer 6).

  As shown in FIGS. 14 and 15, the heat dissipation layer 6 has a heat dissipation layer main surface 61 and a heat dissipation layer back surface 62. The heat radiation layer main surface 61 faces the direction z1. The heat radiation layer main surface 61 overlaps the die pad back surface 112 of each die pad portion 11 and the recess bottom surface 751 in the xy plan view. The heat radiation layer main surface 61 is in direct contact with the die pad back surface 112 and the recess bottom surface 751. The heat radiation layer back surface 62 faces in the direction z <b> 2, which is the opposite direction to the direction in which the heat radiation layer main surface 61 faces. The heat radiation layer back surface 62 is not covered with the sealing resin portion 7 and is exposed from the sealing resin portion 7.

Next, a method for manufacturing the semiconductor device 101B will be described. In the drawings used in the description of the manufacturing method, the same components as those described above are denoted by the same reference numerals.

  First, as shown in FIG. 17, a lead frame 300 including a plurality of die pad portions 11 and 31, a plurality of semiconductor chips 41 and 42, and a passive component chip 43 are prepared. Next, as shown in the figure, each semiconductor chip 41 is arranged on any one of the plurality of die pad portions 11 via a bonding layer (not shown). Similarly, each semiconductor chip 42 and the passive component chip 43 are arranged on any one of the plurality of control die pad portions 31 via a bonding layer (not shown). Next, as shown in the figure, the wire 8 is bonded to each of the semiconductor chips 41, 42 and the like.

  Next, as shown in FIGS. 18 and 19, the sealing resin portion 7 is formed. As shown in FIG. 18, the sealing resin portion 7 is formed by molding using a mold 881. As shown in the figure, a plurality of die pad portions 11 and the like are pressed with a mold 881. Next, a resin material is injected into the mold 881 to cure the resin material. When the resin material is cured, the mold 881 is removed from the plurality of die pad portions 11 and the like as shown in FIG. Thereby, the sealing resin part 7 can be formed. In the step of forming the sealing resin portion 7, the concave portions 75 that expose the plurality of die pad portions 11 are formed in the sealing resin portion 7.

  Next, as shown in FIG. 20, the heat dissipation layer 6 is fitted into the recess 75 of the sealing resin portion 7. Then, pressure and vibration are applied to the heat dissipation layer 6. Further, the heat dissipation layer 6 may be heated. By the pressurization, vibration, and heating, the bonding layer 66 of the heat dissipation layer 6 is softened. The softened bonding layer 66 moves in the recess 75, and a part thereof is filled in the region surrounded by the recess second side surface 755. A part of the bonding layer 66 enters between the concave support surface 756 and the metal layer 65.

  Next, the lead frame 300 shown in FIG. 17 is appropriately cut to manufacture the semiconductor device 101B shown in FIG.

  Next, the effect of this embodiment is demonstrated.

  In the semiconductor device 101B, the metal layer 65 is at least indirectly supported by the concave support surface 756. For this reason, it is possible to prevent the metal layer 65 from being unduly inclined or recessed with respect to the resin bottom surface 72. Therefore, it is possible to suppress the gap between the metal layer 65 and the heat dissipation member 808 due to the bonding layer 66 overflowing outside the metal layer 65, and to increase heat dissipation from the semiconductor chips 41 and 42, and Further, peeling of the metal layer 65 can be made difficult to occur.

By interposing the bonding layer 66 between the metal layer 65 and the concave support surface 756, the metal layer 65 can be reliably fixed to the sealing resin portion 7. If the bonding layer 66 does not reach the end of the metal layer 65, the peeling of the metal layer 65 may propagate from that portion. In this embodiment, there is little such a possibility.

  21 and 22 show a semiconductor device according to the second embodiment of the present invention. In these drawings, the same or similar elements as those in the above embodiment are denoted by the same reference numerals as those in the above embodiment. In the semiconductor device 102B of the present embodiment, the configuration of the recess 75 is different from that of the semiconductor device 101B described above.

  In the present embodiment, the recess 75 has a plurality of recess first side surfaces 754, a recess second side surface 755, and a recess support surface 756, and further includes a plurality of recess side surfaces 752 and a recess groove 753. ing. As shown in FIG. 21, the plurality of recess grooves 753 and the plurality of recess first side surfaces 754, the recess second side surfaces 755, and the recess support surfaces 756 are alternately arranged along the outer edge of the recess 75. In a portion corresponding to the four corners of the recess 75, a recess first side surface 754, a recess second side surface 755, and a recess support surface 756 are disposed.

  As shown in FIG. 22, the recess groove 753 is located between the recess bottom surface 751 and the recess side surface 752. In this embodiment, the recess groove 753 is arranged in a rectangular ring shape along the outer edge of the recess 75 when viewed in the z direction. Yes. As shown in FIG. 22, the recessed groove 753 is recessed from the recessed bottom surface 751 in the z1 direction. In the present embodiment, the concave groove 753 is inclined so as to be positioned in the z1 direction as it is separated from the concave bottom surface 751 in the x direction. The depth of the deepest portion of the recessed groove 753 is, for example, about 50 μm.

  In the present embodiment, a part of the bonding layer 66 fills the concave groove 753. Further, the bonding layer 66 is in contact with the concave side surface 752.

  In the semiconductor device 102B, in addition to the effect exhibited by the semiconductor device 101B, a part of the bonding layer 66 fills the concave groove 753. By this filling, the bonding layer 66 can be prevented from overflowing from the recess 75 in the manufacturing process of the semiconductor device 101B. Therefore, it is possible to prevent a gap from being formed between the heat dissipation member 808 attached so as to be in close contact with the heat dissipation layer 6, and heat from the semiconductor chips 41 and 42 can be efficiently dissipated.

  By disposing the recessed groove 753 outside the metal layer 65, it is possible to prevent an unintended gap from being generated between the metal layer 65 and the recessed groove 753. Excluding the air gap is suitable for further increasing the heat dissipation.

  By forming the concave groove 753 into a tapered shape, even if the position of the metal layer 65 in the x direction or the y direction is shifted, the volume of the concave groove 753 overlapping the metal layer 65 in the z direction can be reduced. This is preferable for eliminating the above-mentioned voids.

  The present invention is not limited to the embodiment described above. The specific configuration of each part of the present invention can be changed in various ways. For example, if it is a semiconductor device in which the metal layer is exposed from the back surface of the sealing resin, it can be similarly used in the case of a terminal for surface mounting instead of insertion mounting. In addition to the above-described IPM device, the present invention can also be applied to a semiconductor device that seals a drive element that has only one semiconductor chip and one island and the metal layer is exposed from the back surface of the sealing resin.

[Appendix 1]
A die pad portion having a main surface and a back surface facing in opposite directions;
A semiconductor chip mounted on the main surface of the die pad portion;
A recessed portion that is recessed from the resin bottom surface and exposes the back surface of the die pad portion, and a sealing resin portion that covers the die pad portion and the semiconductor chip;
A heat dissipation layer disposed in the recess,
The concave portion is located outside the die pad portion in the direction in which the back surface is widened, and is connected to the first side surface connected to the resin bottom surface, connected to the first side surface, and the support surface facing in the direction in which the back surface faces. A second side surface located between the die pad portion and the first side surface in a direction in which the back surface is extended,
The heat dissipation layer has an outer edge located at least partially between the first side surface and the second side surface in a direction in which the back surface expands, and heat dissipation overlaps with the first side surface in the thickness direction of the die pad portion. And a bonding layer interposed between the heat dissipation layer and the die pad portion.
[Appendix 2]
The semiconductor device according to appendix 1, wherein the heat dissipation layer is made of metal.
[Appendix 3]
The semiconductor device according to attachment 2, wherein the metal is Cu.
[Appendix 4]
4. The semiconductor device according to appendix 2 or 3, wherein the bonding layer is made of a resin.
[Appendix 5]
The semiconductor device according to appendix 4, wherein a part of the bonding layer is interposed between the support surface and the heat dissipation layer.
[Appendix 6]
The concave portion has a groove that is located on the outer side of the die pad portion in the direction in which the back surface expands, and has a portion that is located on the main surface side of the back surface,
6. The semiconductor device according to any one of appendices 1 to 5, wherein the bonding layer is partially filled in the groove.
[Appendix 7]
The semiconductor device according to appendix 6, wherein a part of the heat dissipation layer protrudes from the recess in the thickness direction.
[Appendix 8]
The semiconductor device according to appendix 6 or 7, wherein the groove is located outside the heat dissipation layer in a direction in which the back surface is expanded.
[Appendix 9]
The semiconductor device according to appendix 8, wherein the recess has a recess bottom surface having a portion located between the heat dissipation layer and the groove.
[Appendix 10]
Any one of appendices 6 to 9, wherein the groove is inclined so as to be located from the back surface side to the main surface side in the thickness direction of the die pad portion as the groove is separated from the die pad portion in a direction in which the back surface is expanded. A semiconductor device according to claim 1.
[Appendix 11]
A plurality of die pad portions having a main surface and a back surface facing in opposite directions;
A plurality of semiconductor chips individually mounted on the main surface of the plurality of die pad portions;
A sealing resin portion that is recessed from the bottom surface of the resin and that has a recessed portion that exposes at least a part of each back surface of the die pad portion in common, and covers the die pad portion and the semiconductor chips in common. ,
A heat dissipation layer disposed in the recess,
The concave portion is located outside the die pad portions on the back surface side, connected to the first side surface connected to the resin bottom surface, connected to the first side surface, and a support surface facing in the direction in which the back surface faces, and connected to the support surface. A second side surface located between the die pad portion and the first side surface in a direction in which the back surface expands;
The heat dissipation layer has an outer edge located at least partially between the first side surface and the second side surface in a direction in which the back surface expands, and heat dissipation overlaps with the first side surface in the thickness direction of the die pad portion. A semiconductor device comprising: a layer; and a bonding layer interposed between the heat dissipation layer and each die pad portion.

  FIG. 23 is a cross-sectional view showing a mounting structure in which the semiconductor device according to the first embodiment of the present invention is used.

  A semiconductor device mounting structure 801 illustrated in FIG. 23 includes a semiconductor device 101C, a substrate 807, and a heat dissipation member 808.

  The substrate 807 has a plurality of electronic components mounted thereon. The substrate 807 is made of an insulating material. A wiring pattern (not shown) is formed on the substrate 807. A plurality of holes 809 are formed in the substrate 807. The heat radiating member 808 is made of a material having a relatively large thermal conductivity, for example, a metal such as aluminum. The heat dissipation member 808 is fixed to the substrate 807 by a support member (not shown). The semiconductor device 101C is mounted on the substrate 807. In the present embodiment, the semiconductor device 101C is a product called IPM (Intelligent Power Module). The semiconductor device 101C is used for applications such as power control for air conditioners and motor control devices, for example.

  FIG. 24 is a plan view (partially omitted) of the lead before bending the lead of the semiconductor device according to the first embodiment of the present invention. FIG. 25 is a bottom view of the semiconductor device according to the first embodiment of the present invention before bending the leads. 26 is a cross-sectional view taken along the line IIVI-IIVI of FIG. FIG. 27 is an enlarged cross-sectional view of a main part of FIG. FIG. 23 corresponds to a cross section taken along line XXIII-XXIII in FIG. In FIG. 26, each configuration is schematically shown for the sake of easy understanding.

  The semiconductor device 101C shown in these drawings includes a plurality of first electrode parts 1, a second electrode part 2, a third electrode part 3, a plurality of semiconductor chips 41 and 42, a passive component chip 43, and a heat dissipation layer. 6, a sealing resin portion 7, and a wire 8. In FIG. 24, the heat radiation layer 6 is indicated by a dotted line, and the sealing resin portion 7 is indicated by a virtual line.

  The sealing resin part 7 covers the first electrode part 1, the second electrode part 2, the third electrode part 3, the semiconductor chips 41 and 42, and the passive component chip 43. The sealing resin portion 7 is made of, for example, a black epoxy resin. As shown in FIGS. 25 and 26, the sealing resin portion 7 has a resin main surface 71, a resin bottom surface 72, and a resin side surface 73.

  The resin main surface 71 is a flat surface that faces the direction z1 and extends along the xy plane. The resin bottom surface 72 is a flat surface that faces the direction z2 opposite to the direction z1 and extends along the xy plane. The resin side surface 73 has a shape surrounding the semiconductor chips 41 and 42 and the passive component chip 43 in the xy plan view. The resin side surface 73 is connected to the resin main surface 71 and the resin bottom surface 72.

  As clearly shown in FIG. 26, a recess 75 is formed in the sealing resin portion 7. The recess 75 is recessed from the resin bottom surface 72. The recess 75 has a recess bottom surface 751. The recess bottom surface 751 has a shape along the xy plane.

  As shown in FIG. 24, the semiconductor chips 41 and 42 and the passive component chip 43 have a rectangular shape in plan view. The semiconductor chip 41 is a power chip such as an IGBT, a MOS, or a diode, for example. The semiconductor chip 42 is an LSI chip such as a control IC. The passive component chip 43 is a passive component such as a resistor or a capacitor, for example.

  The first electrode part 1, the second electrode part 2, and the third electrode part 3 shown in FIGS. 24 to 4 are all made of a conductive material. An example of such a conductive material is copper. Note that the electrode portion shown in the lower right of FIG. 24 is grounded.

  A plurality (four in this embodiment) of first electrode portions 1 are respectively a die pad portion 11 (see FIGS. 23, 24, and 26), a connection portion 12 (see FIGS. 23 and 24), and a wire bonding portion. 13 (see FIGS. 23 and 24) and a lead 14 (see FIGS. 23 to 25). The plurality of first electrode portions 1 are separated from each other in the direction x.

  Each die pad portion 11 has a plate shape along the xy plane. A semiconductor chip 41 is disposed on the die pad portion 11. As shown in FIG. 26, a bonding layer 991 is interposed between the die pad portion 11 and the semiconductor chip 41. The bonding layer 991 is made of a conductive material. Such a conductive material is, for example, solder or silver paste. Solder has a relatively high thermal conductivity. When solder is used as the bonding layer 991, heat can be efficiently transferred from the semiconductor chip 41 to the die pad portion 11. All of the plurality of die pad portions 11 are exposed from the recess bottom surface 751.

  Each die pad portion 11 has a die pad main surface 111 and a die pad back surface 112. The die pad main surface 111 faces the direction z1, and the die pad back surface 112 faces the direction z2. That is, the die pad main surface 111 and the die pad back surface 112 face opposite to each other. A semiconductor chip 41 is arranged on the die pad main surface 111. A bonding layer 991 is interposed between the die pad main surface 111 and the semiconductor chip 41. The die pad back surface 112 is located at the same position in the thickness direction (direction z) of the die pad portion 11 with respect to the recess bottom surface 751. The die pad back surface 112 may be located closer to the direction in which the recess 75 opens than the recess bottom surface 751.

  As shown in FIG. 24, each connection portion 12 is located between the die pad portion 11 and the wire bonding portion 13 and is connected to the die pad portion 11 and the wire bonding portion 13. As shown in FIG. 23, the connecting portion 12 has a shape along a surface inclined to the xy plane. The connection portion 12 is inclined with respect to the xy plane so as to be directed in the direction z1 as it is separated from the die pad portion 11.

  Each wire bonding portion 13 shown in FIGS. 23 and 24 has a shape along the xy plane. Each wire bonding part 13 is located in the direction z1 side with respect to the die pad part 11 in the direction z. A wire 8 is bonded to one wire bonding portion 13 and one semiconductor chip 41. Thereby, one wire bonding part 13 and one semiconductor chip 41 are electrically connected. The lead 14 is connected to the wire bonding part 13. Each lead 14 extends along direction y. The lead 14 has a portion protruding from the resin side surface 73 of the sealing resin portion 7. In this embodiment, the lead 14 is for insertion mounting. As shown in FIG. 23, when the semiconductor device 101C is mounted on the substrate 807, the lead 14 is bent and inserted into the hole 809. In order to fix the lead 14 to the substrate 807, the hole 809 is filled with a solder layer 810.

  As shown in FIG. 24, the plurality of (three in this embodiment) second electrode portions 2 each include a wire bonding portion 23 and a lead 24. The plurality of second electrode portions 2 are separated from each other in the direction x.

  Each wire bonding portion 23 has a shape along the xy plane. Each wire bonding part 23 is located in the direction z1 side rather than the die pad part 11 in the direction z. A wire 8 is bonded to one wire bonding portion 23 and one semiconductor chip 41. Thereby, one wire bonding part 23 and one semiconductor chip 41 are electrically connected. The lead 24 is connected to the wire bonding part 23. Each lead 24 extends along direction y. The lead 24 has a portion protruding from the resin side surface 73 of the sealing resin portion 7. In this embodiment, the lead 24 is for insertion mounting. Although not shown, like the lead 14, the lead 24 is inserted into the hole 809 when the semiconductor device 101 </ b> C is mounted on the substrate 807.

  The third electrode unit 3 shown in FIGS. 23 and 24 includes a plurality of control die pad units 31 and a plurality of leads 32. Both the control die pad portion 31 and the lead 32 are arranged at the same position in the direction z. In each control die pad portion 31, a semiconductor chip 42 or a passive component chip 43 is arranged. A bonding layer (not shown) is interposed between the control die pad portion 31 and the semiconductor chip 42 and between the control die pad portion 31 and the passive component chip 43. The back surface of the control die pad portion 31 may not face the heat dissipation layer 6 or may not be exposed.

  Each lead 32 has a portion protruding from the resin side surface 73 of the sealing resin portion 7. In this embodiment, the lead 32 is for insertion mounting. As shown in FIG. 23, the lead 32 is inserted into the hole 809 when the semiconductor device 101C is mounted on the substrate 807. As described with respect to the lead 14, the hole 809 is filled with a solder layer 810 to secure the lead 32 to the substrate 807. A wire 8 is bonded to one lead 32 and one semiconductor chip 42. Thereby, one lead 32 and one semiconductor chip 42 are electrically connected. The wire 8 is also bonded to one semiconductor chip 42 and one passive component chip 43. In many cases, the wires connected to the control semiconductor chip 42 and the passive component chip 43 are made of fine aluminum and gold wires that are thinner and softer than the wires 8.

  As shown in FIG. 26, the heat dissipation layer 6 is disposed in the recess 75 in the sealing resin portion 7. In the present embodiment, the heat dissipation layer 6 has a plate shape along the xy plane. In the present embodiment, the heat dissipation layer 6 is made of ceramics, Cu, or aluminum. The heat dissipation layer 6 has a heat dissipation layer main surface 61, a heat dissipation layer back surface 62, a first side surface 631, an intermediate surface 632, and a second side surface 633.

  The heat radiation layer main surface 61 faces the direction z1. The heat radiation layer main surface 61 overlaps the die pad back surface 112 of each die pad portion 11 and the recess bottom surface 751 in the xy plan view. The heat radiation layer back surface 62 faces the direction z <b> 2, which is the direction opposite to the direction in which the heat radiation layer main surface 61 faces. The heat radiation layer back surface 62 is not covered with the sealing resin portion 7 and is exposed from the sealing resin portion 7. The heat radiation layer main surface 61 of the heat radiation layer 6 is bonded to the die pad back surfaces 112 of the plurality of die pad portions 11 by the bonding layer 69. The bonding layer 69 is made of resin, for example.

  As shown in FIGS. 26 and 27, the first side surface 631 is connected to the heat radiation layer back surface 62 and is generally along the z direction. The first side surface 631 is located outside the die pad portion 11 when viewed in the z direction. The second side surface 633 is connected to the heat radiation layer main surface 61 and is generally along the z direction. The second side surface 633 is located between the die pad portion 11 and the first side surface 631 when viewed in the z direction. The intermediate surface 632 connects the first side surface 631 and the second side surface 633, and generally faces the z2 direction. In order to achieve the effect intended by the present application, the z-direction dimension of the first side surface 631 is preferably larger than the z-direction dimension of the second side surface 633.

  The first side surface 631, the intermediate surface 632, and the second side surface 633 are all in contact with the sealing resin portion 7. Further, the heat radiation layer back surface 62 is flush with the resin bottom surface 72 of the sealing resin portion 7. As shown in FIG. 27, the first side surface 631 and the intermediate surface 632 constitute a first corner portion 634. The intermediate surface 632 and the second side surface 633 constitute a second corner portion 645. In the present embodiment, each of the first corner portion 634 and the second corner portion 645 is a right angle, but may be chamfered.

  The heat dissipation layer 6 is provided to quickly release the heat generated in the semiconductor chip 41 to the outside of the semiconductor device 101C. For that purpose, the higher the thermal conductivity of the material constituting the heat radiation layer 6 is, the better. However, if the thermal expansion coefficient is significantly different from that of the sealing resin portion 7, there arises a problem that the heat radiation layer 6 is easily peeled off. There is a fear. Preferably, the heat radiation layer 6 is made of a material having a thermal conductivity larger than that of the material constituting the sealing resin portion 7 and a thermal expansion coefficient close to that of the sealing resin portion 7. The heat dissipation layer 6 faces all of the plurality of die pad portions 11. As shown in FIG. 25, the heat dissipation layer 6 overlaps the entire die pad portion 11 in the xy plan view (view in the thickness direction of the heat dissipation layer 6).

  Next, a method for manufacturing the semiconductor device 101C will be described. In the drawings used in the description of the manufacturing method, the same components as those described above are denoted by the same reference numerals.

  First, as shown in FIG. 28, a lead frame 300 including a plurality of die pad portions 11 and 31, a plurality of semiconductor chips 41 and 42, and a passive component chip 43 are prepared. Next, as shown in the figure, each semiconductor chip 41 is arranged on any one of the plurality of die pad portions 11 via a bonding layer (not shown). Similarly, each semiconductor chip 42 and the passive component chip 43 are arranged on any one of the plurality of control die pad portions 31 via a bonding layer (not shown). Next, as shown in the figure, the wire 8 is bonded to each of the semiconductor chips 41, 42 and the like.

  Next, as shown in FIG. 29, the sealing resin portion 7 is formed. Prior to the formation of the sealing resin portion 7, the heat dissipation layer 6 is bonded to the plurality of die pad portions 11 by the bonding layer 69. The heat radiation layer 6 is formed by forming a groove using a blade having a relatively wide width for a plate-like material made of ceramics, for example. Next, the plate-like material is cut so as to divide the center of the groove using a blade having a relatively narrow width. Thereby, the heat dissipation layer 6 having the first side surface 631, the intermediate surface 632, and the second side surface 633 can be formed.

  The sealing resin portion 7 is formed by molding using a mold 881. As shown in FIG. 29, the heat dissipation layer 6 and the like are pressed by a mold 881. Next, a resin material is injected into the mold 881 to cure the resin material. When the resin material is cured, the sealing resin portion 7 is obtained.

  Next, by appropriately cutting the lead frame 300 shown in FIG. 28, the semiconductor device 101C shown in FIG. 24 and the like is manufactured.

  Next, the effect of this embodiment is demonstrated.

  In the semiconductor device 101 </ b> C, even if separation occurs between the heat dissipation layer 6 and the resin bottom surface 72, the progress of the separation remains within the first side surface 631 and hardly progresses after the intermediate surface 632. For this reason, even after the occurrence of peeling, at least the second side surface 633 can contribute to the bonding between the heat dissipation layer 6 and the sealing resin portion 7. Therefore, it is possible to prevent an excessive gap from reaching the heat radiation layer main surface 61 between the heat radiation layer 6 and the sealing resin portion 7.

  The first corner portion 634 formed at a right angle is suitable for preventing the progress of peeling. Furthermore, by providing the second corner portion 645 formed at a right angle behind the first corner portion 634, the progress of peeling can be more reliably prevented.

  Setting the dimension (depth) in the z direction of the first side surface 631 to be larger than the dimension (depth) in the z direction of the second side surface 633 contributes to making the separation difficult to reach the intermediate surface 632, It is advantageous to prevent progress.

  30 and 31 show a semiconductor device according to the second embodiment of the present invention. In these drawings, the same or similar elements as those in the above embodiment are denoted by the same reference numerals as those in the above embodiment. In the semiconductor device 102C of the present embodiment, the configuration of the heat dissipation layer 6 is different from that of the semiconductor device 101C described above.

  In the present embodiment, the heat dissipation layer 6 has a plurality of grooves 611. The plurality of grooves 611 are formed in the heat dissipation layer main surface 61. The plurality of grooves 611 extend along the y direction and are arranged at an equal pitch. Each groove 611 has a rectangular cross section. A part of the bonding layer 69 enters any one of the plurality of grooves 611. In addition, a part of the sealing resin portion 7 enters any one of the plurality of grooves 611.

  The plurality of grooves 611 are formed in the process of forming the heat dissipation layer 6 described above. For example, before cutting the plate-like material, a plurality of parallel grooves are formed in the plate-like material using a plurality of parallel blades or lasers. These grooves become a plurality of grooves 611 of the heat dissipation layer 6.

  In the semiconductor device 102C, the effect exhibited by the semiconductor device 101C can be achieved. In addition, since the plurality of grooves 611 are formed, a part of the bonding layer 69 and a part of the sealing resin portion 7 enter the groove 611. This can be expected to have a so-called anchor effect that increases the bonding strength between the heat dissipation layer 6 and the bonding layer 69 and the bonding strength between the heat dissipation layer 6 and the sealing resin portion 7. Making the cross-sectional shape of the groove 611 rectangular is suitable for enhancing the anchor effect.

  The present invention is not limited to the embodiment described above. The specific configuration of each part of the present invention can be changed in various ways. For example, if it is a semiconductor device in which the heat dissipation layer is exposed from the back surface of the sealing resin, it can be used in the same way in the case of a terminal for surface mounting instead of insertion mounting. In addition to the above-described IPM device, the present invention can also be applied to a semiconductor device that seals a drive element having only one semiconductor chip and island and having a heat dissipation layer exposed from the back surface of the sealing resin.

[Appendix 1]
A die pad portion having a die pad main surface and a die pad back surface facing in opposite directions;
A semiconductor chip mounted on the main surface of the die pad;
A recessed portion that is recessed from the bottom surface and exposes the back surface of the die pad, and a sealing resin portion that covers the die pad portion and the semiconductor chip;
A heat dissipating layer main surface facing the die pad back surface and a heat dissipating layer back surface opposite to the heat dissipating layer main surface disposed in the recess, and a heat dissipating layer joined to the die pad part. ,
The heat dissipation layer is located outside the die pad portion in the direction in which the back surface of the die pad extends, and is connected to the first side surface connected to the back surface of the heat dissipation layer, the first side surface, and the middle facing the direction in which the main surface of the heat dissipation layer faces. And a second side surface located between the die pad portion and the first side surface in a direction in which the back surface of the die pad is widened.
[Appendix 2]
The semiconductor device according to appendix 1, wherein the heat dissipation layer is made of ceramics.
[Appendix 3]
The semiconductor device according to appendix 1 or 2, wherein the first side surface, the intermediate surface, and the second side surface are in contact with the sealing resin portion.
[Appendix 4]
The semiconductor device according to appendix 3, wherein the back surface of the heat dissipation layer is flush with the bottom surface of the sealing resin portion.
[Appendix 5]
The semiconductor device according to any one of appendices 1 to 4, wherein the first side surface and the intermediate surface form a first corner.
[Appendix 6]
The semiconductor device according to any one of appendices 1 to 5, wherein the intermediate surface and the second side surface form a second corner portion.
[Appendix 7]
The semiconductor device according to appendix 6, wherein at least one of the first corner and the second corner is a right angle.
[Appendix 8]
The semiconductor device according to any one of appendices 1 to 7, wherein a dimension in the thickness direction of the heat dissipation layer on the first side surface is larger than a dimension in the thickness direction of the heat dissipation layer on the second side surface.
[Appendix 9]
9. The semiconductor device according to any one of 1 to 8, wherein the heat dissipation layer and the die pad portion are bonded via a bonding layer.
[Appendix 10]
The semiconductor device according to appendix 9, wherein a plurality of grooves extending in a direction perpendicular to the thickness direction of the heat dissipation layer are formed in the heat dissipation layer main surface of the heat dissipation layer.
[Appendix 11]
The semiconductor device according to appendix 10, wherein each of the grooves has a rectangular cross section.
[Appendix 12]
12. The semiconductor device according to appendix 10 or 11, wherein any one of the plurality of grooves is in contact with the bonding layer.
[Appendix 13]
The semiconductor device according to any one of appendices 10 to 12, wherein any one of the plurality of grooves is in contact with the sealing resin portion.
[Appendix 14]
A plurality of die pad portions having a die pad main surface and a die pad back surface facing in opposite directions;
A plurality of semiconductor chips mounted on the principal surfaces of the plurality of die pads,
A recessed portion that is recessed from the bottom and that exposes the back surface of each die pad in common, and a sealing resin portion that covers each die pad portion and each semiconductor chip in common,
A heat dissipating layer main surface facing the back surface of the die pad, and a heat dissipating layer back surface opposite to the heat dissipating layer main surface; With
The heat dissipation layer is located outside the die pad portion in the direction in which the back surface of the die pad spreads, and is connected to the first side surface connected to the back surface of the heat dissipation layer, the first side surface, and the direction in which the main surface of the heat dissipation layer faces. A semiconductor device comprising: an intermediate surface; and a second side surface connected to the intermediate surface and positioned between the die pad portion and the first side surface in a direction in which the back surface of the die pad extends.

  FIG. 32 is a sectional view showing a mounting structure in which the semiconductor device according to the first embodiment of the present invention is used.

  A semiconductor device mounting structure 801 illustrated in FIG. 32 includes a semiconductor device 101D, a substrate 807, and a heat dissipation member 808.

  The substrate 807 has a plurality of electronic components mounted thereon. The substrate 807 is made of an insulating material. A wiring pattern (not shown) is formed on the substrate 807. A plurality of holes 809 are formed in the substrate 807. The heat radiating member 808 is made of a material having a relatively large thermal conductivity, for example, a metal such as aluminum. The heat dissipation member 808 is fixed to the substrate 807 by a support member (not shown). The semiconductor device 101D is mounted on the substrate 807. In the present embodiment, the semiconductor device 101D is a product called IPM (Intelligent Power Module). The semiconductor device 101D is used for applications such as power control for air conditioners and motor control devices, for example.

  33 and 34 are plan views (partially omitted) of the semiconductor device according to the first embodiment of the present invention before bending the leads. FIG. 35 is a bottom view of the semiconductor device according to the first embodiment of the present invention before bending the leads. 36 is a cross-sectional view taken along line XXXVI-XXXVI in FIG. 32 corresponds to a cross section taken along line XXXII-XXXII in FIG. In FIG. 36, each component is schematically shown for convenience of understanding.

  A semiconductor device 101D shown in these drawings includes a plurality of first electrode portions 1, a second electrode portion 2, a third electrode portion 3, a plurality of semiconductor chips 41 and 42, a passive component chip 43, and a heat dissipation layer. 6, a sealing resin portion 7, and a wire 8. In FIG. 33, the heat radiation layer 6 is indicated by a dotted line, and the sealing resin portion 7 is indicated by a virtual line.

  The sealing resin part 7 covers the first electrode part 1, the second electrode part 2, the third electrode part 3, the semiconductor chips 41 and 42, and the passive component chip 43. The sealing resin portion 7 is made of, for example, a black epoxy resin. As shown in FIGS. 35 and 36, the sealing resin portion 7 has a resin main surface 71, a resin bottom surface 72, and a resin side surface 73.

  The resin main surface 71 is a flat surface that faces the direction z1 and extends along the xy plane. The resin bottom surface 72 is a flat surface that faces the direction z2 opposite to the direction z1 and extends along the xy plane. The resin side surface 73 has a shape surrounding the semiconductor chips 41 and 42 and the passive component chip 43 in the xy plan view. The resin side surface 73 is connected to the resin main surface 71 and the resin bottom surface 72.

  As clearly shown in FIG. 36, a recess 75 is formed in the sealing resin portion 7. The recess 75 is recessed from the resin bottom surface 72. The recess 75 has a recess bottom surface 751 and a recess side surface 752. The recess bottom surface 751 has a shape along the xy plane. The concave side surface 752 is connected to the resin bottom surface 72. The concave side surface 752 is generally along the direction z.

  As shown in FIG. 33, the semiconductor chips 41 and 42 and the passive component chip 43 have a rectangular shape in plan view. The semiconductor chip 41 is, for example, a power chip such as IGBT, MOS, or diode, or an output transistor. The semiconductor chip 42 is an LSI chip such as a control IC, or controls the semiconductor chip 41. The passive component chip 43 is a passive component such as a resistor or a capacitor, for example. The semiconductor chip 41 has an electrode 411. The semiconductor chip 42 also has the same electrode as the electrode 411, and the description thereof is the same as the description of the electrode 411 below.

  The first electrode part 1, the second electrode part 2, and the third electrode part 3 shown in FIGS. 33 to 4 are all made of a conductive material. An example of such a conductive material is copper. Note that the electrode portion shown in the lower right of FIG. 33 is grounded.

  The plurality of (four in this embodiment) first electrode portions 1 are respectively a die pad portion 11 (see FIGS. 32 to 34 and 36), a connection portion 12 (see FIGS. 32 to 34), and a wire bonding portion. 13 (see FIGS. 32 to 34) and leads 14 (see FIGS. 32 to 35). The plurality of first electrode portions 1 are separated from each other in the direction x.

  Each die pad portion 11 has a plate shape along the xy plane. A semiconductor chip 41 is disposed on the die pad portion 11. As shown in FIG. 36, a bonding layer 991 is interposed between the die pad portion 11 and the semiconductor chip 41. The bonding layer 991 is made of a conductive material. Such a conductive material is, for example, solder or silver paste. Solder has a relatively high thermal conductivity. When solder is used as the bonding layer 991, heat can be efficiently transferred from the semiconductor chip 41 to the die pad portion 11. All of the plurality of die pad portions 11 are exposed from the recess bottom surface 751.

  Each die pad portion 11 has a die pad main surface 111 and a die pad back surface 112. The die pad main surface 111 faces the direction z1, and the die pad back surface 112 faces the direction z2. That is, the die pad main surface 111 and the die pad back surface 112 face opposite to each other. A semiconductor chip 41 is arranged on the die pad main surface 111. A bonding layer 991 is interposed between the die pad main surface 111 and the semiconductor chip 41. The die pad back surface 112 is located at the same position in the thickness direction (direction z) of the die pad portion 11 with respect to the recess bottom surface 751. The die pad back surface 112 may be located closer to the direction in which the recess 75 opens than the recess bottom surface 751.

  As shown in FIG. 33, each connection portion 12 is located between the die pad portion 11 and the wire bonding portion 13 and is connected to the die pad portion 11 and the wire bonding portion 13. As shown in FIG. 32, the connecting portion 12 has a shape along a surface inclined to the xy plane. The connection portion 12 is inclined with respect to the xy plane so as to be directed in the direction z1 as it is separated from the die pad portion 11.

  Each of the wire bonding portions 13 shown in FIGS. 32 to 34 has a shape along the xy plane. Each wire bonding part 13 is located in the direction z1 side with respect to the die pad part 11 in the direction z. A wire 8 is bonded to one wire bonding portion 13 and one semiconductor chip 41. Thereby, one wire bonding part 13 and one semiconductor chip 41 are electrically connected. The lead 14 is connected to the wire bonding part 13. Each lead 14 extends along direction y. The lead 14 has a portion protruding from the resin side surface 73 of the sealing resin portion 7. In this embodiment, the lead 14 is for insertion mounting. As shown in FIG. 32, when the semiconductor device 101D is mounted on the substrate 807, the lead 14 is bent and inserted into the hole 809. In order to fix the lead 14 to the substrate 807, the hole 809 is filled with a solder layer 810. The wire 8 connected to the semiconductor chip 41 and the wire bonding part 13 is made of aluminum.

  As shown in FIG. 34, a pair of pressing marks 113 are formed in the die pad portion 11. The pair of pressing marks 113 is formed in the bonding process of the wire 8 described later. The press mark 113 has a scratch-like shape slightly recessed from the die pad main surface 111 of the die pad portion 11. In the present embodiment, the pair of pressing marks 113 are separated from each other in the x direction and sandwich the semiconductor chip 41. The three electrodes 411 formed on the semiconductor chip 41 are arranged in the x direction and are arranged between a pair of pressing marks 113. The first bonding portion 81 of the wire 8 bonded to each electrode 411 intersects with a straight line connecting a pair of pressing marks 113.

  A pair of pressing marks 131 is formed in the wire bonding portion 13. The pair of pressing marks 131 is formed in the bonding process of the wire 8 described later. The press mark 131 has a scratch-like shape slightly recessed from the surface of the wire bonding portion 13. In the present embodiment, the pair of pressing marks 131 are separated from each other in the x direction. The second bonding portion 82 of the wire 8 bonded to the wire bonding portion 13 intersects with a straight line connecting the pair of pressing marks 131. Pressing marks similar to the pair of pressing marks 131 formed on the wire bonding part 13 are also formed on the wire bonding part 23 described later.

  As shown in FIG. 33, the plurality of (three in this embodiment) second electrode portions 2 each include a wire bonding portion 23 and a lead 24. The plurality of second electrode portions 2 are separated from each other in the direction x.

  Each wire bonding portion 23 has a shape along the xy plane. Each wire bonding part 23 is located in the direction z1 side rather than the die pad part 11 in the direction z. A wire 8 is bonded to one wire bonding portion 23 and one semiconductor chip 41. Thereby, one wire bonding part 23 and one semiconductor chip 41 are electrically connected. The lead 24 is connected to the wire bonding part 23. Each lead 24 extends along direction y. The lead 24 has a portion protruding from the resin side surface 73 of the sealing resin portion 7, is processed in the same manner as the lead 14, and is inserted into the hole 809 of the substrate 807. The wire 8 connected to the semiconductor chip 41 and the wire bonding part 23 is made of aluminum.

  The third electrode unit 3 shown in FIGS. 32 and 33 includes a plurality of control die pad units 31 and a plurality of leads 32. Both the control die pad portion 31 and the lead 32 are arranged at the same position in the direction z. In each control die pad portion 31, a semiconductor chip 42 or a passive component chip 43 is arranged. A bonding layer (not shown) is interposed between the control die pad portion 31 and the semiconductor chip 42 and between the control die pad portion 31 and the passive component chip 43. The back surface of the control die pad portion 31 may not face the heat dissipation layer 6 or may not be exposed.

  Each lead 32 has a portion protruding from the resin side surface 73 of the sealing resin portion 7, is processed in the same manner as the lead 14, and is inserted into the hole 809 of the substrate 807. A wire 8 is bonded between one lead 32 and a predetermined electrode of one semiconductor chip 42. Thereby, one lead 32 and one semiconductor chip 42 are electrically connected. The wire 8 is also bonded to a predetermined electrode of one semiconductor chip 42 and one passive component chip 43. In many cases, the wires connected to the control semiconductor chip 42 and the passive component chip 43 are made of fine aluminum and gold wires that are thinner and softer than the wires 8.

  The heat dissipation layer 6 is made of ceramics, Cu, or aluminum, and is disposed in the recess 75 in the sealing resin portion 7 as shown in FIG. The heat dissipation layer 6 is surrounded by the concave side surface 752. In the present embodiment, the heat dissipation layer 6 has a plate shape along the xy plane. In the present embodiment, the heat dissipation layer 6 includes a metal layer 65 and a bonding layer 66. The metal layer 65 is on the z2 direction side and is made of, for example, Cu having a thickness of about 105 μm. The bonding layer 66 is on the z1 direction side with respect to the metal layer 65 and functions to bond the metal layer 65 to the die pad back surfaces 112 of the plurality of die pad portions 11. The bonding layer 66 is made of, for example, an insulating resin and has a thickness of about 250 μm, for example. This resin is a material that softens when pressure and vibration are applied in the manufacturing process of the semiconductor device 101D. It directly contacts any of the plurality of die pad portions 11 on which the semiconductor chip 41 is mounted. The metal layer 65 may have a portion that slightly protrudes from the resin bottom surface 72. The bonding layer 66 is in contact with the concave side surface 752.

  The heat dissipation layer 6 is provided to quickly release the heat generated in the semiconductor chip 41 to the outside of the semiconductor device 101D. For this purpose, the higher the thermal conductivity of the material constituting the heat dissipation layer 6 is, the better. However, if the thermal expansion coefficient is significantly different from that of the sealing resin portion 7, problems such as easy peeling of the metal layer 65 occur. There is a fear. Preferably, the heat radiation layer 6 is made of a material having a thermal conductivity larger than that of the material constituting the sealing resin portion 7 and a thermal expansion coefficient close to that of the sealing resin portion 7. The heat dissipation layer 6 faces all of the plurality of die pad portions 11. As shown in FIG. 35, the heat dissipation layer 6 overlaps the entire die pad portion 11 in the xy plan view (view in the thickness direction of the heat dissipation layer 6).

  As shown in FIGS. 35 and 36, the heat dissipation layer 6 has a heat dissipation layer main surface 61 and a heat dissipation layer back surface 62. The heat radiation layer main surface 61 faces the direction z1. The heat radiation layer main surface 61 overlaps the die pad back surface 112 of each die pad portion 11 and the recess bottom surface 751 in the xy plan view. The heat radiation layer main surface 61 is in direct contact with the die pad back surface 112 and the recess bottom surface 751. The heat radiation layer back surface 62 faces in the direction z <b> 2, which is the opposite direction to the direction in which the heat radiation layer main surface 61 faces. The heat radiation layer back surface 62 is not covered with the sealing resin portion 7 and is exposed from the sealing resin portion 7.

  Next, a method for manufacturing the semiconductor device 101D will be described. In the drawings used in the description of the manufacturing method, the same components as those described above are denoted by the same reference numerals.

First, as shown in FIG. 37, a lead frame 300 including a plurality of die pad portions 11 and 31, a plurality of semiconductor chips 41 and 42, and a passive component chip 43 are prepared. Next, as shown in the figure, each semiconductor chip 41 is arranged on any one of the plurality of die pad portions 11 via a bonding layer (not shown). Similarly, each semiconductor chip 42 and the passive component chip 43 are arranged on any one of the plurality of control die pad portions 31 via a bonding layer (not shown).

Next, the wire 8 is bonded. FIG. 38 shows an example of a bonding apparatus for bonding the wire 8 made of aluminum. The illustrated bonding apparatus 85 includes a capillary 851, a guide 852, a cutter 853, a base 854, an arm 855, and a wire reel 856. A wire 8 is wound around the wire reel 856. The arm 855 is attached to the base 854 via a mechanism that generates vibration such as an ultrasonic generation mechanism. The wire 8 sent out from the wire reel 856 is sent to the tip of the capillary 851 by the guide 852. The capillary 851 is used to press the wire 8 against a bonding target while applying vibration (referred to as “wedge bonding”). The cutter 853 functions to cut the bonded wire.

  As shown in FIG. 39, the process of bonding the wire 8 to the semiconductor chip 41 mounted on the die pad part 11 and the wire bonding part 13 connected to the die pad part 11 located adjacent to the die pad part 11 will be described as an example. The bonding process of the wire 8 made of other aluminum is the same. Prior to the wire 8 bonding step, the lead frame 300 is set on a jig 860, for example. The jig 860 is formed in accordance with the shape of the lead frame 300 and has support surfaces 861 and 862. The support surface 861 supports the die pad unit 11, and the support surface 862 supports the wire bonding unit 13.

  Next, as shown in FIG. 40, a pair of pressing pieces 831 and a pair of pressing pieces 832 are prepared. The pair of pressing pieces 831 and the pair of pressing pieces 832 are constituted by, for example, thin metal bars that are paired with each other. A pair of pressing pieces 831 is pressed against the die pad unit 11. At this time, the pair of pressing pieces 831 are separated from each other in the x direction, and the three electrodes 411 of the semiconductor chip 41 are positioned between the pair of pressing pieces 831. Further, the pair of pressing pieces 832 are pressed against the wire bonding portion 13 shown in the figure. The pair of pressing pieces 832 are separated from each other in the x direction.

  Next, as shown in FIG. 41, a first bonding process of the wire 8 is performed. The tip of the capillary 851 to which the wire 8 is attached is brought into contact with the electrode 411 of the semiconductor chip 41. The wire 8 is bonded to the electrode 411 by applying pressure and ultrasonic vibration from the capillary 851 to the wire 8.

  Next, as shown in FIG. 42, a second bonding step of the wire 8 is performed. The tip of the capillary 851 is moved from the electrode 411 of the semiconductor chip 41 to the wire bonding unit 13. The wire 8 is bonded to the wire bonding portion 13 by applying pressure and ultrasonic vibration to the wire 8 from the capillary 851. Further, after this joining, the wire 8 is cut by the cutter 853 shown in FIG.

  Through the first bonding step and the second bonding step, the first bonding portion 81 is bonded to the electrode 411 of the semiconductor chip 41 and the second bonding portion 82 is bonded to the wire bonding portion 13 as shown in FIGS. The obtained wire 8 is obtained. As shown in FIG. 44, a pair of pressing marks 113 is formed in a portion of the die pad portion 11 where the pair of pressing pieces 831 are pressed. Further, a pair of pressing marks 131 is formed in the portion of the wire bonding portion 13 where the pair of pressing pieces 832 are pressed. The first bonding portion 81 intersects with a straight line connecting the pair of pressing marks 113. Further, the second bonding portion 82 intersects with a straight line connecting the pair of pressing marks 131. By repeating the same bonding operation, as shown in FIG. 45, a lead frame 300 in which a plurality of wires 8 are bonded to the semiconductor chips 41, 42, etc. is obtained. The wire 8 ′ for connecting the semiconductor chip 42 and the third electrode portion 3 may use a pressing piece 831 as in the above-described method, but uses ball bonding and does not use the holding piece 831. May be.

  Next, as shown in FIGS. 46 and 47, the sealing resin portion 7 is formed. As shown in FIG. 46, the sealing resin portion 7 is formed by molding using a mold 881. As shown in the figure, a plurality of die pad portions 11 and the like are pressed with a mold 881. Next, a resin material is injected into the mold 881 to cure the resin material. When the resin material is cured, the mold 881 is removed from the plurality of die pad portions 11 and the like as shown in FIG. Thereby, the sealing resin part 7 can be formed. In the step of forming the sealing resin portion 7, the concave portions 75 that expose the plurality of die pad portions 11 are formed in the sealing resin portion 7.

  Next, as shown in FIG. 48, the heat dissipation layer 6 is fitted into the recess 75 of the sealing resin portion 7. Then, pressure and vibration are applied to the heat dissipation layer 6. Further, the heat dissipation layer 6 may be heated. By the pressurization, vibration, and heating, the bonding layer 66 of the heat dissipation layer 6 is softened. The softened bonding layer 66 is filled in the recess 75. Further, the bonding layer 66 is in contact with the concave side surface 752.

  Next, the lead frame 300 is appropriately cut to manufacture the semiconductor device 101D shown in FIG.

  Next, the effect of this embodiment is demonstrated.

  By pressing a position sandwiching the electrode 411 or the wire bonding portion 13 where the wire 8 is bonded by the pair of pressing pieces 831 and 832, the die pad portion 11 or the It is possible to prevent the wire bonding portion 13 from being unduly shaken or deformed. Therefore, the wire 8 can be appropriately bonded.

  By positioning the first bonding portion 81 between the straight lines connecting the pair of pressing marks 113 (tips of the pair of pressing pieces 831), the die pad portion 11 is shaken by pressure and vibration applied from the capillary 851 in the first bonding step. Or deformation can be suitably prevented.

  By positioning the second bonding portion 82 between the straight lines connecting the pair of pressing marks 131 (tips of the pair of pressing pieces 832), the wire bonding portion 13 is caused by pressure and vibration applied from the capillary 851 in the second bonding step. It is possible to suitably prevent shaking and deformation.

  The first bonding process is performed in a posture in which all of the plurality of electrodes 411 formed on the semiconductor chip 41 are sandwiched between a pair of pressing pieces 831. Accordingly, it is not necessary to move the pair of pressing pieces 831 while performing the first bonding process on the plurality of electrodes 411. Therefore, the bonding process can be performed efficiently.

  The present invention is not limited to the embodiment described above. The specific configuration of each part of the present invention can be changed in various ways. For example, if it is a semiconductor device in which the metal layer is exposed from the back surface of the sealing resin, it can be similarly used in the case of a terminal for surface mounting instead of insertion mounting. In addition to the above-described IPM device, the present invention can also be applied to a semiconductor device that seals a drive element that has only one semiconductor chip and one island and the metal layer is exposed from the back surface of the sealing resin.

[Appendix 1]
In a state where the pair of pressing pieces are pressed at two spaced apart positions on the bonding target object, the bonding target object is positioned between the pair of pressing pieces in the direction in which the pair of pressing pieces are separated from each other. A wire bonding method comprising a wire bonding step of bonding a wire to a portion to be performed.
[Appendix 2]
The wire bonding method according to appendix 1, wherein, in the wire bonding step, the wire is bonded to a portion of the bonding target that intersects a straight line connecting the pair of pressing pieces.
[Appendix 3]
The bonding object includes a die pad portion made of a metal plate, and a semiconductor chip mounted on the die pad portion and having one or more electrodes,
The wire bonding according to appendix 1 or 2, wherein, in the wire bonding step, a wire is bonded to the electrode in a state where the pair of pressing pieces are pressed at a position sandwiching the semiconductor chip in the die pad portion. Method.
[Appendix 4]
The semiconductor chip has a plurality of electrodes,
4. The wire bonding method according to appendix 3, wherein, in the wire bonding step, wires are individually bonded to the plurality of electrodes in a state where the pair of pressing pieces are pressed at positions sandwiching the plurality of electrodes.
[Appendix 5]
The bonding object includes a wire bonding portion made of a metal plate,
The wire bonding method according to appendix 1 or 2, wherein, in the wire bonding step, a wire is bonded to the wire bonding portion in a state where the pair of pressing pieces are pressed against the wire bonding portion.
[Appendix 6]
The bonding object includes a die pad portion made of a metal plate, a semiconductor chip mounted on the die pad portion and having one or more electrodes, and a wire bonding portion spaced from the die pad portion,
In the wire bonding step, a wire is bonded to the electrode in a state where the pair of pressing pieces are pressed at a position sandwiching the semiconductor chip in the die pad portion,
The supplementary note 1 or 2, further comprising an additional wire bonding step of bonding a wire to the wire bonding portion in a state where an additional pair of pressing pieces are pressed against the wire bonding portion after the wire bonding step. Wire bonding method. [Appendix 7]
The semiconductor chip has a plurality of electrodes,
The wire bonding method according to appendix 6, wherein, in the wire bonding step, wires are individually bonded to the plurality of electrodes in a state where the pair of pressing pieces are pressed at positions sandwiching the plurality of electrodes.
[Appendix 8]
The wire bonding method according to any one of appendices 1 to 7, wherein the wire is made of aluminum.
[Appendix 9]
In the wire bonding step, pressure and vibration are applied to the wire.
The wire bonding method according to appendix 8.
[Appendix 10]
A die pad portion having a main surface and a back surface facing in opposite directions;
A semiconductor chip mounted on the main surface of the die pad portion and having one or more electrodes;
A sealing resin part covering the die pad part and the semiconductor chip,
The die pad part is formed with a pair of press marks that are separated from each other,
One end of a wire is bonded to a portion of the electrode located between the pair of pressing marks in a direction in which the pair of pressing marks are separated from each other. [Appendix 11]
The semiconductor device according to appendix 10, wherein one end of the wire is bonded to a portion of the electrode that intersects a straight line connecting the pair of pressing marks.
[Appendix 12]
A wire bonding part spaced apart from the die pad part;
In the wire bonding portion, an additional pair of pressing marks that are separated from each other is formed,
Appendices 10 or 11 wherein the other end of the wire is bonded to a portion located between the additional pair of pressing marks in the direction in which the additional pair of pressing marks is separated from the wire bonding portion. The semiconductor device described.
[Appendix 13]
The semiconductor device according to appendix 12, wherein the other end of the wire is bonded to a portion of the wire bonding portion that intersects a straight line connecting the additional pair of pressing marks.
[Appendix 14]
A die pad portion having a main surface and a back surface facing in opposite directions;
A semiconductor chip mounted on the main surface of the die pad portion and having one or more electrodes;
A lead electrically connected to the semiconductor chip via a wire;
A sealing resin portion covering a part of the die pad portion, the semiconductor chip and the lead,
A semiconductor device, wherein a pair of pressing marks that are separated from each other are formed on a surface of the lead that sandwiches a connecting portion to which one end of the wire of the lead is bonded.
[Appendix 15]
The semiconductor device according to appendix 11, wherein the lead having the pressing mark has a wider portion than the lead having no pressing mark.
[Appendix 16]
The wires have different thicknesses,
13. The semiconductor device according to appendix 11 or 12, wherein the pressing mark is formed only near a connection portion of the thick wire.
[Appendix 17]
There are multiple semiconductor chips,
14. The semiconductor device according to appendix 13, wherein the thick wire electrically connects only a part of the semiconductor chip and the leads.
[Appendix 18]
15. The semiconductor device according to any one of appendices 11 to 14, wherein a pair of pressing marks that are spaced apart from each other with the semiconductor chip interposed therebetween are formed on a surface of the die pad that sandwiches the semiconductor chip.
[Appendix 19]
The semiconductor chip includes a plurality of output transistors and a semiconductor chip for controlling the output transistors,
16. The semiconductor device according to any one of appendices 11 to 15, wherein the lead pressing marks are formed so as to be separated from each other across a lead connecting portion connected to the output transistor.

  FIG. 49 is a cross-sectional view showing a mounting structure in which the semiconductor device according to the first embodiment of the present invention is used.

  A semiconductor device mounting structure 801 illustrated in FIG. 49 includes a semiconductor device 101E, a substrate 807, and a heat dissipation member 808.

  The substrate 807 has a plurality of electronic components mounted thereon. The substrate 807 is made of an insulating material. A wiring pattern (not shown) is formed on the substrate 807. A plurality of holes 809 are formed in the substrate 807. The heat radiating member 808 is made of a material having a relatively large thermal conductivity, for example, a metal such as aluminum. The heat dissipation member 808 is fixed to the substrate 807 by a support member (not shown). The semiconductor device 101E is mounted on the substrate 807. In the present embodiment, the semiconductor device 101E is a product called IPM (Intelligent Power Module). The semiconductor device 101E is used for applications such as power control for air conditioners and motor control devices, for example.

  FIG. 50 is a plan view (partially omitted) of the lead before bending the lead of the semiconductor device according to the first embodiment of the present invention. FIG. 51 is a bottom view of the semiconductor device according to the first embodiment of the present invention before the leads are bent. 52 is a cross-sectional view taken along line LII-LII in FIG. 53 is an enlarged cross-sectional view of a main part of FIG. 49 corresponds to a cross section taken along line ILIX-ILIX in FIG. In FIG. 52, each component is schematically shown for convenience of understanding.

  The semiconductor device 101E shown in these drawings includes a plurality of first electrode portions 1, a second electrode portion 2, a third electrode portion 3, a plurality of semiconductor chips 41 and 42, a passive component chip 43, and a heat dissipation layer. 6, a sealing resin portion 7, and a wire 8. In FIG. 50, the heat radiation layer 6 is indicated by a dotted line, and the sealing resin portion 7 is indicated by a virtual line.

  The sealing resin part 7 covers the first electrode part 1, the second electrode part 2, the third electrode part 3, the semiconductor chips 41 and 42, and the passive component chip 43. The sealing resin portion 7 is made of, for example, a black epoxy resin. As shown in FIGS. 51 and 52, the sealing resin portion 7 has a resin main surface 71, a resin bottom surface 72, and a resin side surface 73.

  The resin main surface 71 is a flat surface that faces the direction z1 and extends along the xy plane. The resin bottom surface 72 is a flat surface that faces the direction z2 opposite to the direction z1 and extends along the xy plane. The resin side surface 73 has a shape surrounding the semiconductor chips 41 and 42 and the passive component chip 43 in the xy plan view. The resin side surface 73 is connected to the resin main surface 71 and the resin bottom surface 72.

  As clearly shown in FIG. 52, a recess 75 is formed in the sealing resin portion 7. The recess 75 is recessed from the resin bottom surface 72. The recess 75 has a recess bottom surface 751 and a recess side surface 752. The recess bottom surface 751 has a shape along the xy plane. The concave side surface 752 is connected to the resin bottom surface 72. The concave side surface 752 is generally along the direction z.

  As shown in FIG. 50, the semiconductor chips 41 and 42 and the passive component chip 43 have a rectangular shape in plan view. The semiconductor chip 41 is, for example, a power chip such as IGBT, MOS, or diode, or an output transistor. The semiconductor chip 42 is an LSI chip such as a control IC or for controlling the semiconductor chip 41. The passive component chip 43 is a passive component such as a resistor or a capacitor, for example.

  The first electrode part 1, the second electrode part 2, and the third electrode part 3 shown in FIGS. 50 to 4 are all made of a conductive material. An example of such a conductive material is copper. Note that the electrode portion shown in the lower right of FIG. 50 is grounded.

  The plurality of (four in this embodiment) first electrode portions 1 are respectively a die pad portion 11 (see FIGS. 49, 50, and 52), a connection portion 12 (see FIGS. 49 and 50), and a wire bonding portion. 13 (see FIGS. 49 and 50) and leads 14 (see FIGS. 49 to 51). The plurality of first electrode portions 1 are separated from each other in the direction x.

  Each die pad portion 11 has a plate shape along the xy plane. A semiconductor chip 41 is disposed on the die pad portion 11. As shown in FIG. 52, solder 991 is interposed between the die pad portion 11 and the semiconductor chip 41. The solder 991 is an example of the conductive bonding material referred to in the present invention, and an Ag paste may be used instead of the solder 991. Solder has a relatively high thermal conductivity. The solder 991 can efficiently transfer heat from the semiconductor chip 41 to the die pad portion 11. All of the plurality of die pad portions 11 are exposed from the recess bottom surface 751.

  As shown in FIG. 53, a back surface electrode 413 is formed on the semiconductor chip 41. The back electrode 413 is made of a material having relatively high solder wettability such as Ag, Au, Ni, or an alloy containing these metals. In the present embodiment, the back surface 412 of the semiconductor chip 41 is constituted by the back surface electrode 413.

  Each die pad portion 11 has a die pad main surface 111 and a die pad back surface 112. The die pad main surface 111 faces the direction z1, and the die pad back surface 112 faces the direction z2. That is, the die pad main surface 111 and the die pad back surface 112 face opposite to each other. A semiconductor chip 41 is arranged on the die pad main surface 111. Solder 991 is interposed between the die pad main surface 111 and the semiconductor chip 41. The die pad back surface 112 is located at the same position in the thickness direction (direction z) of the die pad portion 11 with respect to the recess bottom surface 751. The die pad back surface 112 may be located closer to the direction in which the recess 75 opens than the recess bottom surface 751.

  The die pad portion 11 is made of, for example, any one of Cu, FeNi alloy, and Fe, and the die pad main surface 111 is a surface having relatively low solder wettability. In the present embodiment, the bonding area between the solder 991 and the back surface 412 of the semiconductor chip 41 is larger than the bonding area between the solder 991 and the die pad main surface 111.

  As shown in FIG. 50, each connection portion 12 is located between the die pad portion 11 and the wire bonding portion 13 and is connected to the die pad portion 11 and the wire bonding portion 13. As shown in FIG. 49, the connecting portion 12 has a shape along a surface inclined to the xy plane. The connection portion 12 is inclined with respect to the xy plane so as to be directed in the direction z1 as it is separated from the die pad portion 11.

  Each wire bonding portion 13 shown in FIGS. 49 and 50 has a shape along the xy plane. Each wire bonding part 13 is located in the direction z1 side with respect to the die pad part 11 in the direction z. A wire 8 is bonded to one wire bonding portion 13 and one semiconductor chip 41. Thereby, one wire bonding part 13 and one semiconductor chip 41 are electrically connected. The lead 14 is connected to the wire bonding part 13. Each lead 14 extends along direction y. The lead 14 has a portion protruding from the resin side surface 73 of the sealing resin portion 7. In this embodiment, the lead 14 is for insertion mounting. As shown in FIG. 49, when the semiconductor device 101E is mounted on the substrate 807, the lead 14 is bent and inserted into the hole 809. In order to fix the lead 14 to the substrate 807, the hole 809 is filled with a solder layer 810.

  As shown in FIG. 50, the plurality of (three in the present embodiment) second electrode portions 2 each include a wire bonding portion 23 and a lead 24. The plurality of second electrode portions 2 are separated from each other in the direction x.

  Each wire bonding portion 23 has a shape along the xy plane. Each wire bonding part 23 is located in the direction z1 side rather than the die pad part 11 in the direction z. A wire 8 is bonded to one wire bonding portion 23 and one semiconductor chip 41. Thereby, one wire bonding part 23 and one semiconductor chip 41 are electrically connected. The lead 24 is connected to the wire bonding part 23. Each lead 24 extends along direction y. The lead 24 has a portion protruding from the resin side surface 73 of the sealing resin portion 7. In this embodiment, the lead 24 is for insertion mounting. Although not shown, like the lead 14, the lead 24 is inserted into the hole 809 when the semiconductor device 101E is mounted on the substrate 807.

  The third electrode unit 3 shown in FIGS. 49 and 50 includes a plurality of control die pad units 31 and a plurality of leads 32. Both the control die pad portion 31 and the lead 32 are arranged at the same position in the direction z. In each control die pad portion 31, a semiconductor chip 42 or a passive component chip 43 is arranged. A bonding layer (not shown) is interposed between the control die pad portion 31 and the semiconductor chip 42 and between the control die pad portion 31 and the passive component chip 43. The back surface of the control die pad portion 31 may not face the heat dissipation layer 6 or may not be exposed.

  Each lead 32 has a portion protruding from the resin side surface 73 of the sealing resin portion 7. In this embodiment, the lead 32 is for insertion mounting. As shown in FIG. 49, the lead 32 is inserted into the hole 809 when the semiconductor device 101E is mounted on the substrate 807. As described with respect to the lead 14, the hole 809 is filled with the solder layer 810 to fix the lead 32 to the substrate 807. A wire 8 is bonded to one lead 32 and one semiconductor chip 42. Thereby, one lead 32 and one semiconductor chip 42 are electrically connected. The wire 8 is also bonded to one semiconductor chip 42 and one passive component chip 43.

  As shown in FIG. 52, the heat dissipation layer 6 is disposed in the recess 75 in the sealing resin portion 7. The heat dissipation layer 6 is surrounded by the concave side surface 752. In the present embodiment, the heat dissipation layer 6 has a plate shape along the xy plane. In the present embodiment, the heat dissipation layer 6 includes a metal layer 65 and a bonding layer 66. The metal layer 65 is on the z2 direction side and is made of, for example, Cu, aluminum, or ceramics having a thickness of about 105 μm. The bonding layer 66 is on the z1 direction side with respect to the metal layer 65 and functions to bond the metal layer 65 to the die pad back surfaces 112 of the plurality of die pad portions 11. The bonding layer 66 is made of, for example, an insulating resin and has a thickness of about 250 μm, for example. This resin is a material that softens when pressure and vibration are applied in the manufacturing process of the semiconductor device 101E. It directly contacts any of the plurality of die pad portions 11 on which the semiconductor chip 41 is mounted. The metal layer 65 may have a portion that slightly protrudes from the resin bottom surface 72. The bonding layer 66 is in contact with the concave side surface 752.

  The heat dissipation layer 6 is provided to quickly release the heat generated in the semiconductor chip 41 to the outside of the semiconductor device 101E. In order to quickly release the heat generated in the semiconductor chip 41 to the outside of the semiconductor device 101E, the higher the thermal conductivity of the material constituting the heat dissipation layer 6, the better, but the sealing resin portion 7 and the thermal expansion coefficient If they are greatly different, there is a risk that the metal layer 65 may be easily peeled off. Preferably, the heat radiation layer 6 is made of a material having a thermal conductivity larger than that of the material constituting the sealing resin portion 7 and a thermal expansion coefficient close to that of the sealing resin portion 7. The heat dissipation layer 6 faces all of the plurality of die pad portions 11. As shown in FIG. 51, the heat dissipation layer 6 overlaps the entire die pad portion 11 in the xy plan view (view in the thickness direction of the heat dissipation layer 6).

  As shown in FIGS. 51 and 52, the heat dissipation layer 6 has a heat dissipation layer main surface 61 and a heat dissipation layer back surface 62. The heat radiation layer main surface 61 faces the direction z1. The heat radiation layer main surface 61 overlaps the die pad back surface 112 of each die pad portion 11 and the recess bottom surface 751 in the xy plan view. The heat radiation layer main surface 61 is in direct contact with the die pad back surface 112 and the recess bottom surface 751. The heat radiation layer back surface 62 faces in the direction z <b> 2, which is the opposite direction to the direction in which the heat radiation layer main surface 61 faces. The heat radiation layer back surface 62 is not covered with the sealing resin portion 7 and is exposed from the sealing resin portion 7.

  Next, a method for manufacturing the semiconductor device 101E will be described. In the drawings used in the description of the manufacturing method, the same components as those described above are denoted by the same reference numerals.

  First, as shown in FIG. 54, a lead frame 300 including a plurality of die pad portions 11 and 31 is prepared. Then, a solder paste 991 'is applied by the procedure described below. The solder paste 991 'is an example of the conductive bonding paste referred to in the present invention, and instead of the solder paste 991', an Ag paste or a paste made of another metal and an organic solvent may be used. As shown in the figure, the region to which the solder paste 991 ′ is applied is smaller than the plan view dimensions of the semiconductor chips 41 and 42 and the passive component chip 43, and is included in the inside thereof. Yes. In FIGS. 55 to 59, description will be given by taking as an example the application of solder paste 991 'to the die pad portion 11 and the joining of the semiconductor chip 41. In order to improve heat dissipation, the following method is used only for a portion where a plurality of semiconductor chips 41 are mounted on one of the die pad portions 11, and the conductive bonding paste for other portions is the same as the conventional one. Various methods may be used.

  First, as shown in FIG. 55, a mask 992 is prepared. A plurality of openings 993 are formed in the mask 992. These openings 993 correspond to the application area of the solder paste 991 'shown in FIG. The lead frame 300 is covered with the mask 992.

Next, as shown in FIG. 56, a solder paste 991 'is applied. This application is performed by filling the opening 993 of the mask 992 with a solder paste 991 '. Next, as shown in FIG. 57, when the mask 992 is removed, the solder paste 991 'is applied to a desired region.

  Next, the semiconductor chip 41 is placed on the solder paste 991 '. The area where the solder paste 991 ′ is applied is smaller than the size in plan view of the semiconductor chip 41. The semiconductor chip 41 is placed so as to cover the solder paste 991 '. At this time, the semiconductor chip 42 and the passive component chip 43 described above are also placed.

  Next, for example, the lead frame 300 is inserted into a reflow furnace and heated to melt the solder paste 991 '. Since the back surface 412 (back surface electrode 413) of the semiconductor chip 41 is made of, for example, Ag or Au having relatively high solder wettability, the molten solder paste 991 'spreads over the entire surface. On the other hand, since the main surface 111 of the die pad portion 11 is made of Cu, FeNi alloy, or Fe, which has relatively low solder wettability, the molten solder paste 991 'is difficult to spread. As a result, after heating by the reflow furnace, the solder 991 having the form shown in FIG. 59 is obtained. The solder 991 has a larger bonding area with the back surface 412 of the semiconductor chip 41 than a bonding area with the main surface 111 of the die pad portion 11. FIG. 60 shows the lead frame 300 taken out from the reflow furnace.

  Next, as shown in FIG. 61, the wire 8 is bonded between each semiconductor chip 41, 42 and the corresponding lead.

  Next, as shown in FIGS. 62 and 63, the sealing resin portion 7 is formed. As shown in FIG. 62, the sealing resin portion 7 is formed by molding using a mold 881. As shown in the figure, a plurality of die pad portions 11 and the like are pressed with a mold 881. Next, a resin material is injected into the mold 881 to cure the resin material. When the resin material is cured, the mold 881 is removed from the plurality of die pad portions 11 and the like as shown in FIG. Thereby, the sealing resin part 7 can be formed. In the step of forming the sealing resin portion 7, a recess 75 that exposes the back side of the plurality of die pad portions 11 is formed in the sealing resin portion 7.

  Next, as shown in FIG. 64, the heat dissipation layer 6 is fitted into the recess 75 of the sealing resin portion 7. Then, pressure and vibration are applied to the heat dissipation layer 6. Further, the heat dissipation layer 6 may be heated. By the pressurization, vibration, and heating, the bonding layer 66 of the heat dissipation layer 6 is softened. The softened bonding layer 66 is filled in the recess 75. Further, the bonding layer 66 is in contact with the concave side surface 752.

  Next, the lead frame 300 is appropriately cut to manufacture the semiconductor device 101E shown in FIG.

  Next, the effect of this embodiment is demonstrated.

  According to the present embodiment, the solder paste 991 ′ is applied to an area smaller than the planar size of the semiconductor chip 41, and the semiconductor chip 41 is placed so as to cover it. When the solder paste 991 ′ is heated in this state, the solder 991 tends to stay in the semiconductor chip 41 in a plan view. Therefore, it is possible to prevent the solders 991 for joining adjacent semiconductor chips 41 to the die pad main surface 111 from coming into contact with each other or only a part of the solder paste reaching the end of the die pad. . As a result, the position of each semiconductor chip is not shifted from the predetermined position due to solder erosion, the surface tension of the solder, etc., and the semiconductor chip can be arranged at the predetermined position, so that the wire work can be facilitated. become. In addition, since the distance between adjacent chips can be reduced, the outer shape of the semiconductor device can be further reduced.

  The back surface 412 of the semiconductor chip 41 is configured to have relatively high solder wettability, while the main surface 111 of the die pad portion 11 is configured to have relatively low solder wettability, thereby preventing the solder 991 from protruding. Can be aimed at.

  The application of the solder paste 991 'using the mask 992 is suitable for more accurately applying the solder paste 991' to the intended region. As a method for applying the solder paste 991 ′, in addition to the method using the mask 992, for example, the solder paste 991 ′ filled in a syringe may be dropped.

  The present invention is not limited to the embodiment described above. The specific configuration of each part of the present invention can be changed in various ways. For example, if the semiconductor device uses a thick and hard wire such as aluminum, it is applicable not only to the semiconductor device for IPM described above but also to a semiconductor device such as a power transistor having only one semiconductor chip and one island. Applicable. Furthermore, it can be used not only for insertion mounting but also for a semiconductor device having a terminal for surface mounting.

[Appendix 1]
An application step of applying a conductive bonding paste to the main surface of the die pad part;
The conductive bonding paste is applied to the back surface of the semiconductor chip whose size in the direction of the main surface is larger than the region where the conductive bonding paste is applied. A placing step of contacting the conductive bonding paste so as to include a region inside;
A bonding step of forming a conductive bonding material by curing after softening the conductive bonding paste;
A method for manufacturing a semiconductor device, comprising:
[Appendix 2]
The method for manufacturing a semiconductor device according to attachment 1, wherein the conductive bonding paste is a solder paste.
[Appendix 3]
3. The method of manufacturing a semiconductor device according to appendix 2, wherein, in the application step, the main surface is covered with a mask having an opening, and then the conductive bonding paste is buried in the opening.
[Appendix 4]
The method for manufacturing a semiconductor device according to any one of appendices 1 to 3, wherein the back surface of the semiconductor chip has higher wettability to the conductive bonding paste than the main surface of the die pad portion.
[Appendix 5]
The back surface of the semiconductor chip is made of Ag, Au, Ni or an alloy containing these metals,
The semiconductor device manufacturing method according to appendix 4, wherein the main surface of the die pad portion is made of any one of Cu, FeNi alloy, and Fe.
[Appendix 6]
A die pad portion having a main surface;
A semiconductor chip having a back surface;
A conductive bonding material interposed between the main surface of the die pad portion and the back surface of the semiconductor chip, and bonding the die pad portion and the semiconductor chip;
The semiconductor device according to claim 1, wherein a bonding area between the back surface of the semiconductor chip and the conductive bonding material is larger than a bonding area between the main surface of the die pad portion and the conductive bonding material.
[Appendix 7]
The semiconductor device according to appendix 6, wherein the conductive bonding material is solder.
[Appendix 8]
The semiconductor device according to appendix 6, wherein the back surface of the semiconductor chip has higher wettability with respect to the conductive bonding paste than the main surface of the die pad portion.
[Appendix 9]
The back surface of the semiconductor chip is made of Ag, Au, Ni or an alloy containing these metals,
The semiconductor device according to appendix 8, wherein the main surface of the die pad portion is made of any one of Cu, FeNi alloy, and Fe.
[Appendix 10]
A die pad portion having a main surface and a back surface facing in opposite directions;
A plurality of semiconductor chips mounted on the main surface of the die pad portion;
A conductive bonding material that is interposed between the main surface of the die pad portion and the back surfaces of the plurality of semiconductor chips, and bonds the die pad portion and the plurality of semiconductor chips. The bonding area between each back surface of the semiconductor chip and the conductive bonding material is larger than the bonding area between the conductive bonding material formed on the main surface of the die pad portion corresponding to the semiconductor chip. A semiconductor device.
[Appendix 11]
The semiconductor chip has a plurality of output transistors and a control semiconductor chip,
The semiconductor device according to appendix 9, wherein the plurality of output transistors have the relationship of the junction area.
[Appendix 12]
A plurality of leads for taking out the outputs of the plurality of output transistors to the outside; and a plurality of wires for connecting the output transistors and the leads, respectively.
The semiconductor device according to appendix 10, wherein the wire is aluminum.

101A to 101E, 102A to 102C Semiconductor device 1 First electrode portion 11 Die pad portion 111 Main surface 111 Die pad main surface 112 Die pad back surface 113 Press mark 12 Connection portion 13 Wire bonding portion 131 (Additional) press mark 14 Lead 2 Second electrode Section 23 Wire bonding section 24 Lead 3 Third electrode section 31 Control die pad section 32 Lead 300 Lead frame 41 Semiconductor chip 411 Electrode 412 Back surface 413 Back surface electrode 42 Semiconductor chip 43 Passive component chip 6 Heat radiation layer 61 Heat radiation layer main surface 611 Groove 62 Heat dissipation layer back surface 631 First side surface 632 Intermediate surface 633 Second side surface 634 First corner portion 645 Second corner portion 65 Metal layer 66 Bonding layer 69 Bonding layer 7 Sealing resin portion 71 Resin main surface 72 Resin bottom surface 73 Resin side surface 75 Recess 751 Concave bottom surface 752 Concave side surface 753 Concave Groove 754 Concave first side 755 Concave second side 756 Concave support surface 8 Wire 81 First bonding unit 82 Second bonding unit 85 Bonding device 801 Mounting structure 807 Substrate 808 Heat radiation member 809 Hole 810 Solder layer 810 Solder layer 831 Holding piece 832 (Addition) Presser piece 851 Capillary 852 Guide 853 Cutter 854 Base 855 Arm 856 Wire reel 860 Jig 861 Support surface 862 Support surface 881 Mold 991 Solder (conductive bonding material)
991 Bonding layer 991 ′ Solder paste (conductive bonding paste)
992 Mask 993 Opening

Claims (19)

  In a state where the pair of pressing pieces are pressed at two spaced apart positions on the bonding target object, the bonding target object is positioned between the pair of pressing pieces in the direction in which the pair of pressing pieces are separated from each other. A wire bonding method comprising a wire bonding step of bonding a wire to a portion to be performed.   The wire bonding method according to claim 1, wherein in the wire bonding step, the wire is bonded to a portion of the bonding target that intersects a straight line connecting the pair of pressing pieces. The bonding object includes a die pad portion made of a metal plate, and a semiconductor chip mounted on the die pad portion and having one or more electrodes,
3. The wire according to claim 1, wherein in the wire bonding step, the wire is bonded to the electrode in a state where the pair of pressing pieces are pressed at a position sandwiching the semiconductor chip in the die pad portion. Bonding method. The semiconductor chip has a plurality of electrodes,
The wire bonding method according to claim 3, wherein in the wire bonding step, wires are individually bonded to the plurality of electrodes in a state where the pair of pressing pieces are pressed at a position sandwiching the plurality of electrodes. . The bonding object includes a wire bonding portion made of a metal plate,
The wire bonding method according to claim 1 or 2, wherein, in the wire bonding step, a wire is bonded to the wire bonding portion in a state where the pair of pressing pieces are pressed against the wire bonding portion. The bonding object includes a die pad portion made of a metal plate, a semiconductor chip mounted on the die pad portion and having one or more electrodes, and a wire bonding portion spaced from the die pad portion,
In the wire bonding step, a wire is bonded to the electrode in a state where the pair of pressing pieces are pressed at a position sandwiching the semiconductor chip in the die pad portion,
3. The method according to claim 1, further comprising an additional wire bonding step of bonding a wire to the wire bonding portion in a state where an additional pair of pressing pieces are pressed against the wire bonding portion after the wire bonding step. The wire bonding method as described. The semiconductor chip has a plurality of electrodes,
The wire bonding method according to claim 6, wherein in the wire bonding step, wires are individually bonded to the plurality of electrodes in a state where the pair of pressing pieces are pressed at positions sandwiching the plurality of electrodes. .   The wire bonding method according to claim 1, wherein the wire is made of aluminum. In the wire bonding step, pressure and vibration are applied to the wire.
The wire bonding method according to claim 8. A die pad portion having a main surface and a back surface facing in opposite directions;
A semiconductor chip mounted on the main surface of the die pad portion and having one or more electrodes;
A sealing resin part covering the die pad part and the semiconductor chip,
The die pad part is formed with a pair of press marks that are separated from each other,
One end of a wire is bonded to a portion of the electrode located between the pair of pressing marks in a direction in which the pair of pressing marks are separated from each other.   The semiconductor device according to claim 10, wherein one end of the wire is bonded to a portion of the electrode that intersects a straight line connecting the pair of pressing marks. A wire bonding part spaced apart from the die pad part;
In the wire bonding portion, an additional pair of pressing marks that are separated from each other is formed,
The other end of the wire is bonded to a portion located between the additional pair of pressing marks in a direction in which the additional pair of pressing marks is separated from the wire bonding portion. A semiconductor device according to 1.   The semiconductor device according to claim 12, wherein the other end of the wire is bonded to a portion of the wire bonding portion that intersects with a straight line connecting the additional pair of pressing marks. A die pad portion having a main surface and a back surface facing in opposite directions;
A semiconductor chip mounted on the main surface of the die pad portion and having one or more electrodes;
A lead electrically connected to the semiconductor chip via a wire;
A sealing resin portion covering a part of the die pad portion, the semiconductor chip and the lead,
A semiconductor device, wherein a pair of pressing marks that are separated from each other are formed on a surface of the lead that sandwiches a connecting portion to which one end of the wire of the lead is bonded.   The semiconductor device according to claim 11, wherein the lead having the pressing mark has a wider portion than the lead having no pressing mark. The wires have different thicknesses,
The semiconductor device according to claim 11, wherein the pressing mark is formed only near a connection portion of the thick wire. There are multiple semiconductor chips,
The semiconductor device according to claim 13, wherein the thick wire electrically connects only a part of the semiconductor chip and the lead.   The semiconductor device according to claim 11, wherein a pair of pressing marks that are spaced apart from each other with the semiconductor chip interposed therebetween are formed on a surface of the die pad that sandwiches the semiconductor chip. The semiconductor chip includes a plurality of output transistors and a semiconductor chip for controlling the output transistors,
16. The semiconductor device according to claim 11, wherein the lead pressing marks are formed so as to be spaced apart from each other with the lead connecting portion connected to the output transistor interposed therebetween.

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