JP2018026498A - Method of masking semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of masking semiconductor package capable of masking the part other than a predetermined region precisely, in order to perform specific processing, e.g., electromagnetic shielding, precisely for a predetermined region in a semiconductor package.SOLUTION: A holding jig J including recesses 61 sectioned by bulkhead 63 is suction held on a porous table 11, and each semiconductor package P is arranged in each recess 61 of the semiconductor package P. For the semiconductor package P held stably in the recess 61, a masking tape T is pasted to cover a bump 59 completely. By performing electromagnetic shielding for the semiconductor package P where a predetermined region is covered, various processing, e.g., electromagnetic shielding, laser marking, and the like, can be executed precisely for the region excepting the part coated with the masking tape.SELECTED DRAWING: Figure 9

Description

  The present invention relates to a masking method of a semiconductor device, in particular, a masking method of a semiconductor package for masking a predetermined part of a sealed semiconductor package.

  In wireless communication devices such as smartphones, reception performance may be adversely affected by electromagnetic waves generated from built-in semiconductor elements interfering with an antenna or the like. Conventionally, as a method for preventing such an adverse effect due to electromagnetic waves, a method of suppressing the generation of electromagnetic waves by covering a circuit or device with a sheet metal shield has been the mainstream.

  However, in recent years, there has been a strong demand for thinner communication devices, and sheet metal shields with a large mounting area are an obstacle to reducing the size and thickness of devices. Therefore, a method for suppressing the generation of electromagnetic waves at the semiconductor element level, that is, the component level, is being sought as an alternative to the suppression method using the sheet metal shield.

  A semiconductor element protects a semiconductor chip by sealing a small semiconductor chip with an insulating resin or the like to form a semiconductor package (for example, Patent Document 1). A semiconductor package is manufactured by arranging a large number of small semiconductor chips on a support tape, sealing the semiconductor chip with an insulating material, forming bumps and circuits, and then dicing again with a dicing process. . As a method for suppressing electromagnetic waves at the semiconductor element level, a method is proposed in which each of the semiconductor packages is covered with a shielding material (electromagnetic shield) that blocks electromagnetic waves by processes such as sputtering, plating, and spraying ( For example, Patent Document 2).

JP2012-49502 JP2012-39104A

However, the conventional method has the following problems.
That is, when the semiconductor package is covered with an electromagnetic shield, it is difficult to precisely cover the target area of the semiconductor package with the electromagnetic shield, and there is a concern that it is difficult to improve the electromagnetic wave reduction performance at the semiconductor element level. .

  Here, the problem of the conventional method will be described with reference to the drawings. As shown in FIG. 20A, the semiconductor package 101 has a structure in which a substrate layer 103 and a sealing resin layer 105 formed by covering a semiconductor chip that has been fragmented with an insulating resin are laminated. . A circuit 107 is formed on the surface of the substrate layer 103 and further includes bumps 109.

  When each of the semiconductor packages 101 is covered with a shield layer 111 made of an electromagnetic shield material, as shown in FIG. 20B, the shield layer 111 does not come into contact with the bump 109, and the sealing resin layer 105 and the substrate layer 103. It is necessary to be formed so as to sufficiently cover the side surface. However, if the shield layer 111 is excessively formed, the shield layer 111 made of a conductor is formed so as to be in contact with the bump 109 as shown in FIG.

  Since the size of the semiconductor package is very small, it is difficult to realize electromagnetic shielding processing with the required accuracy in each semiconductor package. As described above, in the semiconductor package, the problem relating to the feasibility of the precision processing limited to the required range occurs not only in the electromagnetic shield processing but also in various processing steps such as laser marking processing.

  The present invention has been made in view of such circumstances, and in order to precisely perform a specific process, such as an electromagnetic shield process, on a predetermined area in a semiconductor package, a part other than the predetermined area The main object of the present invention is to provide a method for masking a semiconductor package capable of precisely masking the mask.

In order to achieve such an object, the present invention has the following configuration.
That is, the semiconductor package masking method according to the present invention is a semiconductor in which a substrate layer having bumps formed on its surface and a sealing layer in which a semiconductor element that has been cut into pieces is covered with an insulating material and sealed. A holding step for holding the package;
A masking step of covering at least the bumps by applying a masking tape to the held semiconductor package;
It is characterized by providing.

  (Operation / Effect) According to this method, the semiconductor package is held in the holding step, and in the masking step, the masking tape is applied so as to cover at least the bumps. Since the bump portion of the semiconductor package is covered by the masking process, it is possible to reliably avoid the occurrence of a product defect due to the treatment being performed on the bump portion when a treatment such as an electromagnetic shielding process is subsequently performed on the semiconductor package.

Further, in the above-described invention, a holding part installation step of installing a holding part having a cell part having the same shape as the semiconductor package and a partition wall partitioning the cell parts,
In the holding step, each of the semiconductor packages is preferably held inside each of the cell portions with respect to the holding portion installed in the holding portion installing step.

  (Operation / Effect) According to this configuration, each of the semiconductor packages is attached with the masking tape while being held inside the cell section partitioned by the partition walls. The cell portion has the same shape as the semiconductor package, and the positional deviation of the semiconductor package is prevented by the partition walls. Therefore, each of the semiconductor packages is held more stably inside the cell portion, so that the masking process can be executed more precisely.

  Further, in the above-described invention, in the holding step, each of the semiconductor packages is arranged such that the height of the upper surface of the partition wall is lower than the height of the top of the bump and higher than the height of the surface of the substrate layer. It is preferable to hold.

  (Operation / Effect) According to this configuration, in the holding step, the height of the upper surface of the partition wall is lower than the height of the top of the bump and higher than the height of the surface of the substrate layer. Therefore, the bump can be reliably covered with the masking tape in the masking step. On the other hand, since it is possible to avoid the masking tape covering the lower position of the substrate layer, the masked portion does not become excessively wide. As a result, the target range of the masking process can be precisely limited, so that a specific process such as an electromagnetic shield process can be performed on a wider part of the semiconductor package.

  In the above-described invention, it is preferable that the cell portion has a tapered shape that tapers from the top toward the bottom.

  (Operation / Effect) According to this configuration, since the cell portion is tapered from the top toward the bottom, the gap with the semiconductor package is narrowed at the bottom. Therefore, it is possible to more reliably avoid the occurrence of positional deviation in the semiconductor package held in the cell portion.

  On the other hand, since the gap with the semiconductor package is widened at the upper part of the cell portion, the adhesive constituting the masking tape easily enters the gap in the masking step. As a result, a portion requiring masking, such as a bump or the surface of a substrate layer, can be more reliably covered with a masking tape. Therefore, both the stability of the semiconductor package and the certainty of masking can be enjoyed.

  In the above-described invention, the outer shape of the holding portion is preferably circular.

  (Function / Effect) According to this configuration, since the outer shape of the holding portion is circular, the holding portion can be handled in the same manner as a disk-like configuration such as a semiconductor wafer regardless of the position where the cell portion is provided. Can do. Therefore, it is possible to more easily and surely perform treatment such as conveyance and arrangement on the holding unit.

  In the above-described invention, it is preferable that in the masking step, the masking tape is attached to the semiconductor package by rolling an attaching roller in a predetermined direction.

  (Operation / Effect) According to this configuration, since the masking tape is attached to the semiconductor package by the rolling of the attaching roller, the masking of the semiconductor package can be executed more suitably and reliably.

  In the above-described invention, it is preferable that the pressing force of the sticking roller is controlled by the rolling position of the sticking roller in the masking step.

  (Operation / Effect) According to this configuration, since the pressing force of the affixing roller is controlled by the rolling position of the affixing roller, it is possible to more reliably avoid the occurrence of masking variations depending on the arrangement positions of the semiconductor packages.

  In the above-described invention, it is preferable that in the masking step, the pressure in the chamber is reduced and the masking tape is attached to the semiconductor package by a differential pressure.

  (Operation / Effect) According to this configuration, the inside of the chamber is decompressed and the masking tape is attached to the semiconductor package by the differential pressure, so that the semiconductor package can be masked more suitably and reliably. Further, the masking variation due to the arrangement position of the semiconductor package can be further reduced.

It is a perspective view which shows the basic composition of the masking tape sticking apparatus which concerns on an Example. It is a side view which shows the structure of the sticking unit which concerns on an Example. It is a side view explaining the structure of the semiconductor package which concerns on an Example. It is a figure explaining the structure of the holding jig which concerns on an Example. (A) is a top view of the holding jig, (b) is an AA cross-sectional view of the holding jig J shown in (a). It is a figure explaining the structure of the holding jig and semiconductor package which concern on an Example. (A) is sectional drawing which shows the state of the semiconductor package arrange | positioned at the jig | tool for holding | maintenance, (b) is sectional drawing which shows the correlation with the recessed part of a jig | tool for holding | maintenance, and the size of a semiconductor package. It is a flowchart explaining operation | movement of the masking tape sticking apparatus which concerns on an Example. It is a figure explaining the state in which the holding jig is mounted in step S1. It is a figure explaining the state by which a semiconductor package is arrange | positioned in a recessed part in step S2. It is a figure which shows the structure in step S3. (A) is a figure which shows the state by which a masking tape is affixed, (b) is an enlarged view of the area | region shown by A in (a). It is a figure which shows the structure in step S4. It is a figure which shows the structure in step S6. (A) is a figure which shows the state in which a tape conveyance apparatus adsorbs and holds a masking tape, (b) is a figure which shows the state in which a tape conveyance apparatus conveys a semiconductor package with a masking tape after adsorption holding. It is a figure which shows the structure of a comparative example. (A) It is a top view which shows the position where a semiconductor package is arrange | positioned in the comparative example which does not partition with a partition, (b) is a figure which shows the relationship between the pressing force of a sticking roller, and the arrangement position of a semiconductor package in a comparative example. (C) is a diagram showing a state in which masking is performed more than the required range due to excessive pressing force, and (d) is a required range due to insufficient pressing force. It is a figure which shows the state which was not masked. It is a figure which shows the structure of a modification (1). (A) is a figure which shows the state before depressurizing the inside of a chamber, (b) is a figure which shows the state which depressurizes the inside of a chamber and affixes a tape on a semiconductor package. It is a figure which shows the structure of a modification (2). (A) is a figure which shows the structure of the apparatus in step S3, (b) is a figure which shows the state which conveys a semiconductor package and a masking tape by gripping a ring frame in step S6. It is a figure which shows the structure of a modification. (A) is a figure which shows the structure of a modification (3), (b) is a figure which shows the structure of a modification (4). It is a figure which shows the structure of the porous table which concerns on a modification (6). It is a figure which shows the structure of a modification (7). (A) is a figure which shows the structure which deform | transforms a masking tape and separates a semiconductor package from a recessed part, (b) is a figure which shows the structure which deform | transforms a holding jig and separates a semiconductor package from a recessed part. It is sectional drawing which shows the structure of the recessed part which concerns on a modification (8). It is a figure which shows the jig | tool structure for holding | maintenance concerning a modification (9). It is a figure explaining the conventional problem which concerns on the process with respect to a semiconductor package. (A) is sectional drawing which shows the structure of a semiconductor package, (b) is a figure which shows an example of the state processed correctly with respect to the requested | required range, (c) is a figure which shows the requested | required range. It is a figure which shows an example of the state in which the process was made exceeding.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view illustrating an overall configuration of a masking tape attaching apparatus 1 according to an embodiment.

<Description of overall configuration>
The masking tape attaching apparatus 1 according to the embodiment includes a jig supply / recovery unit 3 in which a cassette C1 containing a disk-shaped holding jig J is loaded, a jig transport mechanism 7 including a robot arm 5, an alignment stage. 9. A porous table 11 on which the holding jig J and the semiconductor package P are placed and sucked and held, and a package collection unit 12 in which a cassette C2 for storing the masking tape T applied to the semiconductor package P is loaded. ing.

  As a configuration not shown, the masking tape attaching device 1 includes a package storage unit that stores the semiconductor package P and a package transfer unit that transfers the semiconductor package P to the porous table 11. Examples of the package transport unit include a pick and place robot and a die bonder. The masking tape T has a configuration in which an adhesive layer and a base material layer are laminated as an example. The adhesive layer contains an adhesive and covers the portion to be masked.

  A tape supply unit 13 that supplies a masking tape T for masking toward a semiconductor package P placed on the porous table 11, and a separator that peels and collects the separator s from the masking tape T with a separator supplied from the tape supply unit 13. A collecting unit 15, a sticking unit 17 for sticking the masking tape T to the semiconductor package P placed on the porous table 11 and held by suction, and a tape cutting device for cutting the masking tape T attached to the semiconductor package P into a predetermined shape 19. A peeling unit 21 that peels off an unnecessary masking tape T after being attached to the semiconductor package P and cut, a tape recovery unit 23 that winds and collects the masking tape T peeled off by the peeling unit 21, and the like are provided. Yes.

  The cassette C1 constituting the jig supply / recovery unit 3 can store the disk-shaped holding jig J in multiple stages in a horizontal posture. The robot arm 5 provided in the jig transport mechanism 7 is configured to be capable of moving forward and backward horizontally, and is capable of driving and turning as a whole. The tip of the robot arm 5 is provided with a horseshoe-shaped vacuum suction-type jig holding portion 5a.

  The jig holding portion 5a is inserted into the gap between the holding jigs J housed in multiple stages in the cassette C to suck and hold the holding jig J from the back surface, and the holding jig J sucked and held from the cassette C. The alignment stage 9, the porous table 11, and the jig supply / collection unit 3 are transported in this order. The alignment stage 9 is configured to align the holding jig J carried in and placed by the jig transport mechanism 7 based on the notch N formed on the outer periphery thereof.

  As will be described later, the porous table 11 includes a plurality of suction holes, and vacuum-holds the holding jig J transferred from the jig transport mechanism 7 and placed in a predetermined alignment posture. Yes. The porous table 11 is configured to vacuum-suck each of the semiconductor packages P installed in the recesses of the holding jig J. Instead of the porous table 11, a table made of metal, resin, or the like and having a plurality of relatively large (for example, a diameter of about 1 mm) suction holes may be used.

  As shown in FIG. 2, the tape supply unit 13 guides the masking tape T with the separator s delivered from the supply bobbin 29 by winding it around one or more guide rollers 31, and removes the masking tape T from which the separator s has been peeled off. It is configured to lead to the pasting unit 17. The supply bobbin 29 is configured so as to be given an appropriate rotational resistance so that excessive tape feeding is not performed.

  In the separator collection unit 15, the collection bobbin 33 that winds up the separator s peeled from the masking tape T is rotationally driven in the winding direction. The affixing unit 17 is provided with an affixing roller 35 that faces forward and is horizontally reciprocated by a slide guide mechanism 37 shown in FIG. 2 and a screw feed type drive mechanism (not shown).

  The peeling unit 21 is provided with a peeling roller 39 that faces forward and horizontally. The peeling roller 39 is configured to be reciprocated horizontally by a slide guide mechanism 37 and a screw feed type drive mechanism (not shown).

  The tape collecting unit 23 is configured such that a masking tape T that is no longer needed, that is, a collecting bobbin 41 that winds up the unnecessary tape T ′ is rotated in the winding direction. Examples of the unnecessary tape T ′ include the remaining masking tape pieces cut out along the outer shape of the wafer W.

  As shown in FIG. 1, the tape cutting device 19 includes a movable table 43, a rotating shaft 44, and a pair of support arms 45. The movable table 43 is configured to be movable up and down (z direction). The rotation shaft 44 is provided at the free end of the movable base 43 and can be rotated around an axis in the vertical direction (z direction). The support arm 45 is provided at a lower end portion of a support member that extends downward from the rotation shaft 44 and is supported so as to be slidable in the horizontal direction.

  A cutter unit 47 is provided on the free end side of the support arm 45, and a cutter blade 25 with a cutting edge facing downward is attached to the cutter unit 47. That is, as the pivot shaft 44 pivots about the longitudinal axis P, the support arm 45 also pivots about the z-direction axis. The cutter blade 25 is moved along the outer periphery of the holding jig J by the turning movement of the support arm 45 to cut out the masking tape T.

  Further, by adjusting the slide of the support arm 45, the distance from the vertical axis P, which is the turning center of the cutter blade 25, is adjusted. With such a configuration, the turning radius of the cutter blade 25 can be changed and adjusted in accordance with the diameter of the holding jig J.

  Here, the configurations of the semiconductor package P and the holding jig J will be described. The semiconductor package P according to the embodiment has a substantially rectangular parallelepiped configuration as a whole, and as shown in FIG. 3, a first substrate layer 51, an earth layer 53 having a grounding ground, a second substrate layer 55, And a sealing layer 57 are sequentially laminated. The first substrate layer 51 has bumps 59 on the surface. A circuit (not shown) is formed on the surface of the first substrate layer 51. The sealing layer 57 has a configuration in which a small semiconductor chip (not shown) is sealed with an insulating material. The semiconductor chip is electrically connected to the second substrate layer 55 by a bump or the like (not shown).

  As shown in FIG. 4A, the holding jig J has a disk-like outer shape, and a notch N for positioning is formed. The outer shape of the holding jig J is not limited to a circle, and is preferably the same shape as the outer shape of the wafer defined by the SEMI standard or the Japan Semiconductor Manufacturing Equipment Association. As an example of a preferable outer shape of the holding jig J, a substantially rectangular shape or the like can be given.

  A number of recesses 61 are formed on the surface of the holding jig J. Each of the recesses 61 is arranged in a two-dimensional matrix as an example, and each of the recesses 61 is partitioned by a partition wall 63. The shape of the recess 61 is substantially the same as the outer shape of the semiconductor package P. In other words, each semiconductor package P is disposed in each of the recesses 61 so that the semiconductor package P can be stably held inside the recesses 61 defined by the partition walls 63.

  The material constituting the holding jig J is preferably a material having flexibility and flexibility such as resin, and particularly preferably made of elastic rubber or the like. Further, as shown in FIG. 4B, suction holes 65 are provided in the bottom portions 61 a of the recesses 61. The holding jig J corresponds to the holding portion in the present invention. The recess 61 corresponds to a cell portion in the present invention.

  FIG. 5A shows a state in which each of the semiconductor packages P is arranged in the recess 61 of the holding jig J held by suction on the porous table 11. The porous table 11 includes a plurality of suction holes 12, and each of the suction holes 12 is connected to a suction device 14. When the positioned holding jig J is placed on the porous table 11, each of the suction holes 65 provided in the holding jig J is connected to the suction hole 12 of the porous table 11. Is done.

  In the semiconductor package P, the height from the bottom surface of the sealing layer 57 to the surface of the first substrate layer 51 is H1, and the height from the bottom surface of the sealing layer 57 to the top of the bump 59 is H2. In the holding jig J according to the embodiment, the height R from the bottom surface of the recess 61 to the upper surface 63a of the partition wall 63 is higher than the height H1 in the semiconductor package P as shown in FIG. It is preferable to be configured to be lower.

  Further, the upper surface 63a of the partition wall 63 is preferably subjected to non-adhesive treatment. As an example of the non-adhesive treatment, there may be mentioned a configuration in which the upper surface 63a made of aluminum is coated with Teflon (registered trademark). The height R from the bottom surface of the recess 61 to the upper surface 63a of the partition wall 63 may be changed as appropriate according to the range in which the masking tape T is required to be covered (masking). In the embodiment, the range where masking is required is the entire bump 59 and the entire surface of the first substrate layer 51, and therefore the height R is adjusted to the extent shown in FIG.

<Explanation of device operation>
Next, a series of operations for attaching the masking tape T to each of the semiconductor packages P using the masking tape attaching apparatus 1 according to the embodiment will be described. FIG. 6 is a flowchart for explaining a process of attaching the protective masking tape T to the semiconductor package P.

Step S1 (placement of holding jig)
When a sticking command is issued, first, the robot arm 5 in the jig transport mechanism 7 is moved toward the cassette C1 placed and loaded on the cassette base. The robot arm 5 inserts the jig holding portion 5a into the gap between the holding jigs housed in the cassette C, and sucks the disc-shaped holding jig J from the back surface (lower surface) with the jig holding portion 5a. The holding jig J held and taken out is transferred to the alignment stage 9.

  The holding jig J placed on the alignment stage 9 is aligned using a notch N formed on the outer periphery of the holding jig J. The holding jig J for which the alignment has been completed is carried out again by the robot arm 5 and placed on the porous table 11 as shown in FIG. The holding jig J placed on the porous table 11 is turned and aligned so that the center of the holding jig J is above the center of the porous table 11. At this time, each of the suction holes 65 provided on the bottom surface of the recess 61 is aligned so as to be connected to the suction hole 12.

  The holding jig J aligned on the porous table 11 is sucked and held on the porous table 11 by the suction device 14. That is, the suction device 14 sucks the holding jig J through the suction hole 12. The process according to step S1 corresponds to the holding part installation process in the present invention.

  In addition, as shown in FIG. 2, the affixing unit 17 and the peeling unit 21 are in the left initial position. Moreover, the cutter blade 25 of the tape cutting device 19 is each waiting in the upper initial position.

Step S2 (Semiconductor package supply)
After the holding jig J is sucked and held on the porous table 11, the semiconductor package P is supplied. The package transport unit supplies and transports the semiconductor package P stored in the package storage unit toward the porous table 11. Then, as shown in FIG. 8, one semiconductor package P is arranged in each of the recesses 61 of the holding jig J held by suction on the porous table 11.

  Since each of the suction holes 65 is connected in communication with the suction hole 12, each of the semiconductor packages P arranged inside the recess 61 is attached to the porous table 11 by the suction device 14 via the suction hole 65 and the suction hole 12. Adsorbed and held. Further, each of the recesses 61 is partitioned by a partition wall 63, and the inner shape of the recess 61 is substantially the same as the outer shape of the semiconductor package P. Therefore, by disposing in the concave portion 61 of the holding jig J, it is possible to avoid the positional deviation of the semiconductor package P on the porous table 11. Accordingly, each of the semiconductor packages P is stably held in the recess 61 of the holding jig J. The semiconductor package P is disposed in each of the recesses 61, and the semiconductor package P is stably held on the porous table 11 via the holding jig J, thereby completing the step S2. Step S2 corresponds to the holding step in the present invention.

Step S3 (tape attaching process)
Next, as shown by a virtual line (two-dot chain line) in FIG. 2, the affixing roller 35 of the affixing unit 17 is lowered, and the masking tape T is pressed downward by the affixing roller 35 while moving forward on the wafer W. Roll in the right direction in FIG. As a result, the masking tape T is attached to the entire surface of the semiconductor package P as shown in FIG.

  As shown in FIG. 5B, the height R of the partition wall 63 is adjusted to be lower than the height H2 in the semiconductor package P and higher than the height H1. Therefore, in a state where the semiconductor package P is stably held inside the recess 61, the upper surface 63 a of the partition wall 63 is located between the top of the bump 59 and the upper surface of the first substrate unit 51 in the height direction (z direction).

  Accordingly, as shown in FIG. 9B, the adhesive layer of the masking tape T that has been affixed is at least the entire surface of the semiconductor package P (the entire bump 59 and the first substrate 51) by the pressing force of the affixing roller 35. Cover the entire top surface). On the other hand, the ground layer 53 provided with the ground is not covered with the adhesive layer of the masking tape T. Therefore, it is possible to completely cover (mask) the upper surfaces of the bumps 59 and the first substrate unit 51, which are portions other than the target region of the electromagnetic shielding process, with the adhesive layer of the masking tape T. By masking the entire surface of each semiconductor package P with the masking tape T, the tape attaching process according to step S3 is completed. The process according to step S3 corresponds to the masking process in the present invention.

Step S4 (tape cutting process)
After the tape sticking process is completed, the tape cutting process according to step S4 is started. That is, when the affixing roller 35 rolls and the affixing unit 17 reaches the end position, the cutter blade 25 waiting upward is lowered and pierced by the masking tape T as shown in FIG. Then, the support arm 45 is turned by turning the turning shaft 44 around the axis in the z direction. Along with this, the cutter blade 25 pivots while sliding on the outer peripheral edge of the holding jig J, so that the masking tape T is cut along the outer periphery of the holding jig J.

Step S5 (collection of unnecessary tape)
When the tape cutting along the outer periphery of the holding jig J is completed, the cutter blade 25 is raised to the original standby position. Next, the unnecessary tape T ′ cut and cut on the wafer W is wound up and peeled off while the peeling unit 21 moves forward. When the peeling unit 21 reaches the end position of the peeling operation, the peeling unit 21 and the pasting unit 17 move in the opposite directions and return to the initial position. At this time, the unnecessary tape T ′ is wound around the recovery bobbin 41 and a certain amount of masking tape T is fed out from the tape supply unit 13.

Step S6 (collection of processed packages)
When each process up to step S5 is completed, the semiconductor package subjected to the tape pasting process is collected. First, the suction device 14 is controlled to release the suction holding of the semiconductor package P on the porous table 11. Thereafter, as shown in FIG. 11A, the tape transport device G adsorbs the upper surface of the masking tape Tp cut out along the outer periphery of the holding jig J.

  The masking tape Tp is affixed so as to cover the entire surface of each semiconductor package P. Further, since the upper surface 63a of the partition wall 63 is subjected to non-adhesion processing, the masking tape T is easily peeled off from the holding jig J. Therefore, as shown in FIG. 11B, when the tape transport device G holding the masking tape Tp is moved upward, each of the semiconductor packages P is separated from the recess 61 of the holding jig J, and the masking tape Tp. And move upward.

  At this time, it is preferable that the holding of the holding jig J on the porous table 11 is maintained. That is, the suction hole 12 that sucks and holds the holding jig J and the suction hole 12 that is connected to the suction hole 65 and sucks and holds the semiconductor package P are connected to different suction devices 14, respectively. More preferably, the suction holding of J and the suction holding of the semiconductor package P are controlled independently.

  The masking tape Tp moved upward is transferred to the tape transport device G together with each of the semiconductor packages P, and collected in the cassette C2 of the package collection unit 12 shown in FIG. The holding jig J remaining on the porous table 11 is collected by the robot arm 5 to the jig supply / collection unit 3 as necessary. Thus, one masking tape application process is completed, and thereafter the above operations are sequentially repeated.

  The semiconductor package P recovered by the package recovery unit 12 is in a state where the entire bump 59 and the entire surface of the first substrate layer 51 are covered. On the other hand, the ground layer 53 and the second substrate layer 55 are configured not to be covered with the masking tape T by appropriately adjusting the height of the partition wall 63 and the pressing force of the sticking roller.

  For this reason, the semiconductor package P collected by the masking process is subsequently subjected to the electromagnetic shield process, thereby reliably avoiding the formation of the electromagnetic shield layer on the surface of the bump 59 or the first substrate layer 51. However, the ground layer 53 and the sealing layer 57 can be reliably covered with the electromagnetic shielding material. That is, contact between the electromagnetic shield layer and the bump 59 can be reliably avoided, and the electromagnetic shield layer is reliably grounded by the earth layer 53. Accordingly, it is possible to manufacture a device that can reliably prevent the generation of electromagnetic waves at the semiconductor component level while avoiding the occurrence of a short circuit.

  In addition, since the semiconductor package P to be masked is fragmented, the surfaces of the ground layer 53 and the sealing layer 57 to be shielded are already exposed, and the distance between the semiconductor packages P can be increased. . Therefore, the process of forming the electromagnetic shield layer after masking can be executed more easily and suitably.

  Note that various processes that are not limited to the electromagnetic shielding process can be performed on the semiconductor package P after the masking process. An example is a laser marking process. That is, a laser marking process may be performed on a portion other than the protected portion while reliably protecting the desired portion, such as the bump 59 or the circuit formed on the upper surface of the first substrate layer 51, with masking. it can.

  Another example of the process is a mounting process by a package on package method (PoP). That is, when performing the mounting process by stacking the separated semiconductor packages P, the bumps 59 and the like of the lower layer side semiconductor package P are masked in advance so that the bumps 59 of the lower layer side package are covered by the upper layer side semiconductor package P. It is possible to suitably avoid the problem of being stressed.

<Effects of Configuration of Example>
Thus, masking tape sticking device 1 concerning the present invention sticks a masking tape on the surface of a semiconductor package in the state of being fragmented. By applying the masking tape, the entire bumps 59 formed on the surface of each semiconductor package are suitably covered with the adhesive layer of the masking tape. Therefore, it is possible to precisely perform a specific process such as an electromagnetic shielding process on a part other than the predetermined part (such as the sealing layer 57 and the earth layer 53) while reliably protecting the predetermined part such as the bump 59 with the masking tape. it can. In addition, since the masking process is performed on each of the semiconductor packages after the fragmentation, the specific process can be more easily performed on the unmasked part.

  In the embodiment, the semiconductor package P can be more stably held on the porous table 11 by using the holding jig J when applying the masking tape. That is, each individual semiconductor package P is disposed in each of the recesses 61 defined by the partition walls 63. Since the shape of the recess 61 is the same shape as the outer shape of the semiconductor package P, each position of the semiconductor package P on the porous table 11 is more precisely held by the partition wall 63. Therefore, when the masking tape T is affixed, it is possible to preferably avoid the occurrence of masking failure due to the positional deviation of the semiconductor package P.

  The partition wall 63 is disposed so as to extend in the height direction of the semiconductor package P. The height of the upper surface of the partition wall 63 is adjusted to an appropriate position so as to be between the top of the bump 59 and the surface of the first substrate layer 51. Therefore, it can be avoided that the pressing force of the sticking roller 35 acts on the semiconductor package P in a direction other than the height direction (z direction). That is, the partition 63 of the holding jig J reliably prevents the semiconductor package P from being overturned or deformed due to the pressing force acting on the semiconductor package P in a direction other than the height direction. it can. Accordingly, since the masking process can be completed suitably and reliably with a smaller number of steps with respect to a large number of semiconductor packages P after being fragmented, the efficiency of the masking process can be greatly improved.

  Further, by disposing the semiconductor package P inside the recess 61 partitioned by the partition wall 63, it is possible to further obtain an effect of preventing masking variations with respect to each semiconductor package P. As an example, when the semiconductor package P is arranged on the table D without being partitioned by the partition wall 63 as shown in FIG. 12A, more semiconductor packages P are present in the central portion M than in the left and right end portions E. Be placed.

  In this case, as shown in FIG. 12 (b), the pressing force C acting on the semiconductor package P from the sticking roller 35 varies depending on the rolling position of the sticking roller 35, so that the masking of the semiconductor package P is not uniform. We are concerned about the problem. That is, since a relatively excessive pressing force C acts on the semiconductor package P arranged at the end E, there is a concern that the ground layer 53 may be covered with the adhesive layer of the masking tape T (FIG. 12). (C)). If an electromagnetic shield process is subsequently performed on the semiconductor package P with the ground layer 53 masked, the formed electromagnetic shield layer is not in contact with the ground, and thus troubles due to poor grounding occur.

  On the other hand, in the semiconductor package arranged in the central portion M of the holding jig J, there is a concern that the bump 59 is not completely covered at the time of masking due to the lack of the pressing force C (FIG. 12D). . If the subsequent electromagnetic shielding process is performed with the bump 59 masked incompletely, the electromagnetic shield layer contacts the bump 59, causing a short circuit (see FIG. 20C). Thus, when masking is non-uniform | heterogenous, it will become difficult to perform the process after a masking process with respect to each of many semiconductor packages P precisely.

  In the embodiment, the semiconductor packages are partitioned by partition walls 63, and the height of the partition walls 63 is higher than the surface of the semiconductor package P (the surface of the first substrate layer 51). In this case, the variation in the pressing force of the affixing roller 35 is preferably reduced by the upper surface 63a of the partition wall 63 adjusted to an appropriate height, so that non-uniform masking due to the arrangement position of the semiconductor package P occurs. It can be avoided more reliably.

  Further, the outer shape of the holding jig J is circular, similar to the outer shape of the semiconductor wafer. Specifically, it has the same shape as the wafer defined by the SEMI Standard, Japan Semiconductor Manufacturing Equipment Association, etc. For this reason, when carrying out processing such as transportation, arrangement, and alignment with respect to the holding jig J, a configuration of an apparatus that performs the same processing on the semiconductor wafer can be applied. The operation of the tool J can be optimized more easily.

  The present invention is not limited to the above embodiment, and can be modified as follows.

  (1) In the embodiment, the masking tape application device 1 has been described by taking as an example a roller-type configuration in which the application roller 35 is rolled to apply the masking tape T. You may apply the structure which affixes the masking tape T by a differential pressure.

  In the chamber-type configuration according to the modification (1), as shown in FIG. 13A, the masking tape T is sandwiched between the upper housing 71a and the lower housing 71b to form the chamber 71. Then, in a state where the semiconductor package P held on the porous table 11 is housed in the chamber 71, pressure reduction of both the upper housing 71a and the lower housing 71b is started using a vacuum device (not shown).

  At this time, by controlling the air pressure in the space of the lower housing 71b to be lower than the air pressure in the space of the upper housing 71a, the masking tape T is attached to the semiconductor package P by the differential pressure Sp as shown in FIG. Each surface is coated. By applying such a configuration in which the masking tape is applied while reducing the pressure in the chamber, a large number of semiconductor packages P are suitably covered with the masking tape T without being affected by variations in the pressing force of the application roller. be able to.

  (2) In each of the embodiments and modifications, a ring frame f may be further disposed around the porous table 11. That is, as shown in FIG. 14A, a configuration in which the upper surface of the ring frame f and the entire surface of the semiconductor package P are covered with the masking tape T may be applied.

  In such a modification (2), the masking tape T is cut along the ring frame f in step S5. Then, as shown in FIG. 14B, in step S6, the ring frame f is gripped and moved upward using the transfer arm H or the like, so that the entire upper surface of the masking tape Tp is not attracted and held. Each of P can be conveyed. That is, it is possible to prevent unnecessary force from acting on the masking tape Tp and the semiconductor package P during the conveyance, and thus it is possible to prevent the tape and the semiconductor package from being damaged.

  (3) In each of the examples and the modified examples, the depth of each of the recesses 61 is the same, but is not limited thereto. That is, you may apply the structure which changes the height of the bottom part 61a of the recessed part 61 with the position of the recessed part 61. FIG. Although the masking variation can be reduced by the partition wall 63 of the holding jig J, there may be a case where the variation is not zero.

  As an example, in the configuration in which the masking tape is applied by a roller type, the application is applied when the rolling position of the application roller 35 is on the end E of the holding jig J as shown in FIG. The pressing force C is larger than when the rolling position of the roller 35 is the central portion M of the holding jig J. Therefore, the semiconductor package P arranged at the end E tends to cover the masking tape T to the lower side of the semiconductor package P as compared with the semiconductor package P arranged at the center M.

  Therefore, as shown in FIG. 15, the height of the bottom 61a of the recess 61 is configured to be relatively low at the end E of the holding jig J in accordance with the variation of the pressing force C acting on the semiconductor package P. In the central part M of the jig J, the height of the bottom 61a is made relatively high.

  In this way, by changing the height of the bottom 61a depending on the position of the recess 61, the height of the position where the semiconductor package P is sucked and held can be adjusted as appropriate. Therefore, even when the pressing force C varies, it is possible to reliably avoid the problem of masking variation depending on the arrangement position of the semiconductor package P.

  (4) The structure for adjusting the height of the semiconductor package P is not limited to the structure for changing the thickness of the bottom 61a of the holding jig J. As shown in FIG. At least a part of the bottom 61a of the tool J may be omitted, and in the porous table 11, the pins 75 that move up and down in the z direction may be disposed at the lower portions of the recesses 61. By controlling the height of the pin 75 in accordance with the position where the semiconductor package P is disposed, the height of the position where the semiconductor package P is sucked and held can be adjusted as appropriate. Further, the pin 75 may be provided so as to penetrate the porous table 11 in the vertical direction.

(5) In the embodiment and each modification, a configuration for controlling the operation of the affixing roller 35 may be applied so that the pressing force of the affixing roller 35 is changed depending on the rolling position of the affixing roller 35.

  As an example, when the sticking roller 35 is rolling on the end E of the holding jig J in step S3, the pressing force C of the sticking roller 35 against the masking tape T is controlled to be relatively large. On the other hand, when the affixing roller 35 rolls on the center portion M of the holding jig J, the pressing force C is controlled to be relatively small.

  By controlling the magnitude of the pressing force C according to the rolling position of the sticking roller 35 in this way, even if the height of the bottom 61a of the holding jig J is constant, it depends on the arrangement position of the semiconductor package P. The occurrence of masking variations can be suitably avoided.

  (6) In the embodiment and each modification, the recess 61 and the partition wall 63 may be formed integrally with the porous table 11 as shown in FIG.

  (7) The configuration in which the semiconductor package P is separated from the holding jig J in step S6 is for holding the entire masking tape Tp as a whole by sucking and holding the tape transport device G as shown in FIG. The configuration is not limited to moving away from the jig J. That is, as shown in FIG. 17A, the semiconductor package P may be separated from the holding jig J by applying a force to the end portion of the masking tape Tp that has been cut out and deforming it.

  As shown in FIG. 17B, the semiconductor package P may be separated from the holding jig J by bending and deforming the holding jig J. In such a configuration, since the masking tape T is not deformed, it is possible to suitably avoid the problem that stress is applied to the semiconductor package P and the problem that the masking tape Tp is peeled off from the semiconductor package. In particular, when the holding jig J is a material having flexibility and elasticity (such as rubber), the bending deformation of the holding jig J shown in FIG.

  (8) In the example and each modification, as shown in FIG. 18, the recess 61 may have a tapered shape that tapers toward the bottom 61a. In this case, since the width W1 of the bottom 61a is relatively small, the gap between the semiconductor package P and the partition wall 63 is reduced. Therefore, it is possible to more suitably avoid the occurrence of positional deviation of the semiconductor package P in the state where it is disposed in the recess 61. Therefore, in the modification (8), it is more preferable that the width W1 of the bottom 61a is substantially the same as the width of the bottom of the semiconductor package P.

  And in the upper part 61b of the recessed part 61, the width W2 becomes comparatively wide. Therefore, the adhesive layer constituting the masking tape T tends to enter the gap Ga between the semiconductor package P and the upper portion 61b. Therefore, in the tape applying process according to step S3, at least the entire bump 59 and the entire surface of the first substrate layer 51 can be reliably covered with the adhesive layer of the masking tape T.

  (9) In the embodiment and each modification, the holding jig J has been described as a disk-shaped configuration as shown in FIG. 4, but the outer shape of the holding jig J is not limited to a circular shape. As shown, the outer shape may be changed as appropriate according to the position and number of the recesses 61.

  (10) In the examples and the modifications, the batch-type pasting apparatus has been described as an example, but the configuration according to the present invention can also be applied to a continuous-type apparatus.

  (11) In the example and each modification, the porous table 11 is configured to hold the semiconductor package P by adsorbing the semiconductor package P, but is not limited thereto. That is, a configuration in which the holding jig J or the semiconductor package P is held using a table that does not have a suction function instead of the porous table 11 may be applied.

  (12) Although the holding jig J has been described using the configuration including the suction holes 65 in the examples and the modifications, a configuration without the suction holes 65 may be applied to the holding jig J.

  (13) In each of the examples and modifications, the holding jig J was placed on the porous table 11 and then the semiconductor package P was placed and held in the recess 61 of the holding jig J. It is not restricted to the structure which arrange | positions J and the semiconductor package P separately. That is, the holding jig J in which the semiconductor package P is disposed in each of the recesses 61 is loaded in the cassette C1, and the masking tape T is pasted after the holding jig J is placed on the porous table 11. It may be a configuration.

  In such a modification, a holding jig J (for example, a tray or the like) that holds a large number of individual semiconductor packages P is transported to the porous table 11. Therefore, the time and process required for the masking process can be shortened, so that the yield can be greatly improved.

DESCRIPTION OF SYMBOLS 1 ... Masking tape sticking device 3 ... Jig supply / collection part 5 ... Robot arm 9 ... Alignment stage 11 ... Porous table 12 ... Suction hole 14 ... Suction device 17 ... Sticking unit 19 ... Tape cutting device 21 ... Peeling unit 25 ... Cutter Blade 35 ... Pasting roller 51 ... First substrate layer 53 ... Earth layer 57 ... Sealing layer 59 ... Bump 61 ... Recess 63 ... Partition 65 ... Suction hole T ... Masking tape J ... Holding jig P ... Semiconductor package N ... Notch

Claims (8)

A holding step for holding a semiconductor package in which a substrate layer having bumps formed on the surface and a sealing layer in which a semiconductor element that has been fragmented is covered with an insulating material and sealed;
A masking step of covering at least the bumps by applying a masking tape to the held semiconductor package;
A method for masking a semiconductor package, comprising: The method of masking a semiconductor package according to claim 1,
A holding part installation step of installing a holding part having a cell part having the same shape as the semiconductor package and a partition wall partitioning the cell parts;
In the holding step, each of the semiconductor packages is held inside each of the cell portions with respect to the holding portion installed in the holding portion installation step. The semiconductor package masking method according to claim 2,
In the holding step, each of the semiconductor packages is held such that the height of the upper surface of the partition wall is lower than the height of the top of the bump and higher than the height of the surface of the substrate layer. Semiconductor package masking method. In the masking method of the semiconductor package of Claim 2 or Claim 3,
A masking method for a semiconductor package, wherein the cell portion is tapered from the top toward the bottom. In the semiconductor package masking method according to any one of claims 2 to 4,
A method of masking a semiconductor package, wherein the outer shape of the holding portion is circular. In the masking method of the semiconductor package in any one of Claims 1 thru | or 5,
In the masking step, the masking tape is attached to the semiconductor package by rolling a sticking roller in a predetermined direction. The masking method for a semiconductor package according to claim 6,
In the masking step, the pressing force of the sticking roller is controlled by the rolling position of the sticking roller. In the masking method of the semiconductor package in any one of Claims 1 thru | or 5,
In the masking step, the interior of the chamber is depressurized, and the masking tape is attached to the semiconductor package by a differential pressure.

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