JP2017539128A5 - - Google Patents

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JP2017539128A5
JP2017539128A5 JP2017523318A JP2017523318A JP2017539128A5 JP 2017539128 A5 JP2017539128 A5 JP 2017539128A5 JP 2017523318 A JP2017523318 A JP 2017523318A JP 2017523318 A JP2017523318 A JP 2017523318A JP 2017539128 A5 JP2017539128 A5 JP 2017539128A5
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control channel
channel message
tti
bandwidth
format
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JP2017539128A (ja
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JP2017523318A 2014-10-31 2015-10-14 Dciフラグとdciフォーマットサイズインジケータとを有する2段階pdcch Active JP6837964B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201462073700P 2014-10-31 2014-10-31
US62/073,700 2014-10-31
US201462096412P 2014-12-23 2014-12-23
US62/096,412 2014-12-23
US14/882,165 2015-10-13
US14/882,165 US10021677B2 (en) 2014-10-31 2015-10-13 Two-stage PDCCH with DCI flag and DCI format size indicator
PCT/US2015/055602 WO2016069270A1 (en) 2014-10-31 2015-10-14 Two-stage pdcch with dci flag and dci format size indicator

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JP2017539128A JP2017539128A (ja) 2017-12-28
JP2017539128A5 true JP2017539128A5 (enExample) 2018-11-08
JP6837964B2 JP6837964B2 (ja) 2021-03-03

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US (1) US10021677B2 (enExample)
EP (1) EP3213446B1 (enExample)
JP (1) JP6837964B2 (enExample)
KR (1) KR102586638B1 (enExample)
CN (1) CN107113136B (enExample)
AU (1) AU2015339822B2 (enExample)
ES (1) ES2869885T3 (enExample)
WO (1) WO2016069270A1 (enExample)

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