JP2017526208A - 電流コーディングとサイズコーディングとを組み合わせることによって位相補間器の線形性を改善すること - Google Patents

電流コーディングとサイズコーディングとを組み合わせることによって位相補間器の線形性を改善すること Download PDF

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Publication number
JP2017526208A
JP2017526208A JP2016571694A JP2016571694A JP2017526208A JP 2017526208 A JP2017526208 A JP 2017526208A JP 2016571694 A JP2016571694 A JP 2016571694A JP 2016571694 A JP2016571694 A JP 2016571694A JP 2017526208 A JP2017526208 A JP 2017526208A
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JP
Japan
Prior art keywords
branches
differential
transistors
phase
switches
Prior art date
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Ceased
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JP2016571694A
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English (en)
Japanese (ja)
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JP2017526208A5 (enExample
Inventor
スン、リ
ジュ、ジ
コン、シャオファ
アークディア、ケネース・ルイス
チェン、ジキン
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Qualcomm Inc
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Qualcomm Inc
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Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2017526208A publication Critical patent/JP2017526208A/ja
Publication of JP2017526208A5 publication Critical patent/JP2017526208A5/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00065—Variable delay controlled by a digital setting by current control, e.g. by parallel current control transistors

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)
  • Analogue/Digital Conversion (AREA)
  • Networks Using Active Elements (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2016571694A 2014-06-09 2015-05-13 電流コーディングとサイズコーディングとを組み合わせることによって位相補間器の線形性を改善すること Ceased JP2017526208A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/300,127 US9485084B2 (en) 2014-06-09 2014-06-09 Linearity of phase interpolators by combining current coding and size coding
US14/300,127 2014-06-09
PCT/US2015/030644 WO2015191214A1 (en) 2014-06-09 2015-05-13 Improving linearity of phase interpolators by combining current coding and size coding

Publications (2)

Publication Number Publication Date
JP2017526208A true JP2017526208A (ja) 2017-09-07
JP2017526208A5 JP2017526208A5 (enExample) 2018-05-31

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JP2016571694A Ceased JP2017526208A (ja) 2014-06-09 2015-05-13 電流コーディングとサイズコーディングとを組み合わせることによって位相補間器の線形性を改善すること

Country Status (5)

Country Link
US (1) US9485084B2 (enExample)
EP (1) EP3152834A1 (enExample)
JP (1) JP2017526208A (enExample)
CN (1) CN106464240A (enExample)
WO (1) WO2015191214A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI638522B (zh) * 2016-11-02 2018-10-11 瑞昱半導體股份有限公司 相位調整電路與控制方法
CN113014252B (zh) * 2016-11-11 2024-09-03 瑞昱半导体股份有限公司 相位调整电路、控制方法与测量方法
CN107689792B (zh) * 2017-09-15 2020-04-07 北京华大九天软件有限公司 一种高线性低电压相位内插电路
US11558045B1 (en) * 2021-06-29 2023-01-17 International Business Machines Corporation Phase rotator
KR20230047824A (ko) 2021-10-01 2023-04-10 삼성전자주식회사 클록 데이터 복원 회로 및 이를 포함하는 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6133773A (en) * 1997-10-10 2000-10-17 Rambus Inc Variable delay element
JP2007312394A (ja) * 2006-05-19 2007-11-29 National Semiconductor Germany Ag 制御可能な位相を具備する周期的電気信号を発生する方法及び回路装置
JP2013201693A (ja) * 2012-03-26 2013-10-03 Toshiba Corp 位相補間器および位相補間方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7180352B2 (en) 2001-06-28 2007-02-20 Intel Corporation Clock recovery using clock phase interpolator
US6922109B2 (en) 2002-04-01 2005-07-26 Broadcom Corporation Multiple synthesized clocks with fractional PPM control from a single clock source
US7266169B2 (en) 2002-09-13 2007-09-04 Broadcom Corporation Phase interpolater and applications thereof
GB0413071D0 (en) * 2004-06-12 2004-07-14 Texas Instruments Ltd Triangulating phase interpolator
US7135905B2 (en) * 2004-10-12 2006-11-14 Broadcom Corporation High speed clock and data recovery system
US7298195B2 (en) 2005-03-31 2007-11-20 Agere Systems Inc. Methods and apparatus for improved phase switching and linearity in an analog phase interpolator
US7961025B2 (en) 2008-01-31 2011-06-14 International Business Machines Corporation Current-mode phase rotator with partial phase switching
US7750707B2 (en) 2008-03-17 2010-07-06 Broadcom Corporation High-resolution low-interconnect phase rotator
US7928788B2 (en) 2008-07-31 2011-04-19 Freescale Semiconductor, Inc. Double-balanced sinusoidal mixing phase interpolator circuit and method
US7994837B1 (en) 2009-08-07 2011-08-09 Altera Corporation Techniques for phase interpolation
TW201315155A (zh) 2011-09-20 2013-04-01 Sunplus Technology Co Ltd 相位內插電路
US8786346B2 (en) * 2012-02-15 2014-07-22 Megachips Corporation Phase interpolator and method of phase interpolation with reduced phase error
CN103795404B (zh) * 2012-10-31 2017-10-31 中兴通讯股份有限公司 一种相位插值器电路及相位插值信号处理方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6133773A (en) * 1997-10-10 2000-10-17 Rambus Inc Variable delay element
JP2007312394A (ja) * 2006-05-19 2007-11-29 National Semiconductor Germany Ag 制御可能な位相を具備する周期的電気信号を発生する方法及び回路装置
JP2013201693A (ja) * 2012-03-26 2013-10-03 Toshiba Corp 位相補間器および位相補間方法

Also Published As

Publication number Publication date
EP3152834A1 (en) 2017-04-12
US9485084B2 (en) 2016-11-01
US20150358148A1 (en) 2015-12-10
WO2015191214A1 (en) 2015-12-17
CN106464240A (zh) 2017-02-22

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